From: Anitha Chrisanthus <anitha.chrisanthus@intel.com> To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com Subject: [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Date: Tue, 30 Jun 2020 14:27:25 -0700 [thread overview] Message-ID: <1593552491-23698-14-git-send-email-anitha.chrisanthus@intel.com> (raw) In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> This initializes the mipi high speed transmitter CTRL and SYNC configuration registers. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 55 ++++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 29 +++++++++++++++++++++- 2 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 92a62e5..886a8ac 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -553,6 +553,55 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); } +static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) +{ + u32 sync_cfg = 0, ctrl = 0, fg_en; + u32 ctrl_no = MIPI_CTRL6; + + /*MIPI_TX_HS_SYNC_CFG*/ + if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) + sync_cfg |= LINE_SYNC_PKT_ENABLE; + if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) + sync_cfg |= FRAME_COUNTER_ACTIVE; + if (ctrl_cfg->tx_ctrl_cfg.line_counter_active) + sync_cfg |= LINE_COUNTER_ACTIVE; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking) + sync_cfg |= DSI_V_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) + sync_cfg |= DSI_HSA_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) + sync_cfg |= DSI_HBP_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) + sync_cfg |= DSI_HFP_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn) + sync_cfg |= DSI_SYNC_PULSE_EVENTN; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line) + sync_cfg |= DSI_LPM_FIRST_VSA_LINE; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) + sync_cfg |= DSI_LPM_LAST_VFP_LINE; + /* enable frame generator */ + fg_en = 1 << fg_id; + sync_cfg |= FRAME_GEN_EN(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) + sync_cfg |= ALWAYS_USE_HACT(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) + sync_cfg |= HACT_WAIT_STOP(fg_en); + + /* MIPI_TX_HS_CTRL*/ + ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) + ctrl |= DSI_EOTP_EN; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) + ctrl |= DSI_CMD_HFP_EN; + ctrl |= LCD_VC(fg_id); + ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); + /*67 ns stop time*/ + ctrl |= HSEXIT_CNT(0x43); + + kmb_write_mipi(MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); + kmb_write_mipi(MIPI_TXm_HS_CTRL(ctrl_no), ctrl); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -596,8 +645,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, bits_per_pclk, - word_count, - ctrl_cfg->lane_rate_mbps, + word_count, ctrl_cfg->lane_rate_mbps, ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; @@ -612,6 +660,9 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, return -EINVAL; /*Multi-Channel FIFO Configuration*/ mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); + + /*Frame Generator Enable */ + mipi_tx_ctrl_cfg(frame_id, ctrl_cfg); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index d6fcead..9a5f371 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -398,7 +398,35 @@ #define MIPI_CTRL_HS_BASE_ADDR (0x400) #define MIPI_TX_HS_CTRL (0x0) +#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M)) +#define HS_CTRL_EN (1 << 0) +#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ +#define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/ +#define ACTIVE_LANES(n) ((n) << 4) +#define LCD_VC(ch) ((ch) << 8) +#define DSI_EOTP_EN (1 << 11) +#define DSI_CMD_HFP_EN (1 << 12) +#define CRC_EN (1 << 14) +#define HSEXIT_CNT(n) ((n) << 16) +#define HSCLKIDLE_CNT (1 << 24) #define MIPI_TX_HS_SYNC_CFG (0x8) +#define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ + + (0x400*M)) +#define LINE_SYNC_PKT_ENABLE (1 << 0) +#define FRAME_COUNTER_ACTIVE (1 << 1) +#define LINE_COUNTER_ACTIVE (1 << 2) +#define DSI_V_BLANKING (1 << 4) +#define DSI_HSA_BLANKING (1 << 5) +#define DSI_HBP_BLANKING (1 << 6) +#define DSI_HFP_BLANKING (1 << 7) +#define DSI_SYNC_PULSE_EVENTN (1 << 8) +#define DSI_LPM_FIRST_VSA_LINE (1 << 9) +#define DSI_LPM_LAST_VFP_LINE (1 << 10) +#define WAIT_ALL_SECT (1 << 11) +#define WAIT_TRIG_POS (1 << 15) +#define ALWAYS_USE_HACT(f) ((f) << 19) +#define FRAME_GEN_EN(f) ((f) << 23) +#define HACT_WAIT_STOP(f) ((f) << 28) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ (0x400*M) + (0x2C*N) + (8*O)) @@ -454,7 +482,6 @@ #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + (0x400*M) + (0x4*N)) - #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ + (0x400*M)) -- 2.7.4 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Anitha Chrisanthus <anitha.chrisanthus@intel.com> To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Date: Tue, 30 Jun 2020 14:27:25 -0700 [thread overview] Message-ID: <1593552491-23698-14-git-send-email-anitha.chrisanthus@intel.com> (raw) In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> This initializes the mipi high speed transmitter CTRL and SYNC configuration registers. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 55 ++++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 29 +++++++++++++++++++++- 2 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 92a62e5..886a8ac 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -553,6 +553,55 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); } +static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) +{ + u32 sync_cfg = 0, ctrl = 0, fg_en; + u32 ctrl_no = MIPI_CTRL6; + + /*MIPI_TX_HS_SYNC_CFG*/ + if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) + sync_cfg |= LINE_SYNC_PKT_ENABLE; + if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) + sync_cfg |= FRAME_COUNTER_ACTIVE; + if (ctrl_cfg->tx_ctrl_cfg.line_counter_active) + sync_cfg |= LINE_COUNTER_ACTIVE; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking) + sync_cfg |= DSI_V_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) + sync_cfg |= DSI_HSA_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) + sync_cfg |= DSI_HBP_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) + sync_cfg |= DSI_HFP_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn) + sync_cfg |= DSI_SYNC_PULSE_EVENTN; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line) + sync_cfg |= DSI_LPM_FIRST_VSA_LINE; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) + sync_cfg |= DSI_LPM_LAST_VFP_LINE; + /* enable frame generator */ + fg_en = 1 << fg_id; + sync_cfg |= FRAME_GEN_EN(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) + sync_cfg |= ALWAYS_USE_HACT(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) + sync_cfg |= HACT_WAIT_STOP(fg_en); + + /* MIPI_TX_HS_CTRL*/ + ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) + ctrl |= DSI_EOTP_EN; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) + ctrl |= DSI_CMD_HFP_EN; + ctrl |= LCD_VC(fg_id); + ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); + /*67 ns stop time*/ + ctrl |= HSEXIT_CNT(0x43); + + kmb_write_mipi(MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); + kmb_write_mipi(MIPI_TXm_HS_CTRL(ctrl_no), ctrl); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -596,8 +645,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, bits_per_pclk, - word_count, - ctrl_cfg->lane_rate_mbps, + word_count, ctrl_cfg->lane_rate_mbps, ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; @@ -612,6 +660,9 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, return -EINVAL; /*Multi-Channel FIFO Configuration*/ mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); + + /*Frame Generator Enable */ + mipi_tx_ctrl_cfg(frame_id, ctrl_cfg); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index d6fcead..9a5f371 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -398,7 +398,35 @@ #define MIPI_CTRL_HS_BASE_ADDR (0x400) #define MIPI_TX_HS_CTRL (0x0) +#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M)) +#define HS_CTRL_EN (1 << 0) +#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ +#define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/ +#define ACTIVE_LANES(n) ((n) << 4) +#define LCD_VC(ch) ((ch) << 8) +#define DSI_EOTP_EN (1 << 11) +#define DSI_CMD_HFP_EN (1 << 12) +#define CRC_EN (1 << 14) +#define HSEXIT_CNT(n) ((n) << 16) +#define HSCLKIDLE_CNT (1 << 24) #define MIPI_TX_HS_SYNC_CFG (0x8) +#define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ + + (0x400*M)) +#define LINE_SYNC_PKT_ENABLE (1 << 0) +#define FRAME_COUNTER_ACTIVE (1 << 1) +#define LINE_COUNTER_ACTIVE (1 << 2) +#define DSI_V_BLANKING (1 << 4) +#define DSI_HSA_BLANKING (1 << 5) +#define DSI_HBP_BLANKING (1 << 6) +#define DSI_HFP_BLANKING (1 << 7) +#define DSI_SYNC_PULSE_EVENTN (1 << 8) +#define DSI_LPM_FIRST_VSA_LINE (1 << 9) +#define DSI_LPM_LAST_VFP_LINE (1 << 10) +#define WAIT_ALL_SECT (1 << 11) +#define WAIT_TRIG_POS (1 << 15) +#define ALWAYS_USE_HACT(f) ((f) << 19) +#define FRAME_GEN_EN(f) ((f) << 23) +#define HACT_WAIT_STOP(f) ((f) << 28) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ (0x400*M) + (0x2C*N) + (8*O)) @@ -454,7 +482,6 @@ #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + (0x400*M) + (0x4*N)) - #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ + (0x400*M)) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-06-30 21:29 UTC|newest] Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-06-30 21:27 [PATCH 00/59] Add support for Keem Bay DRM driver Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 01/59] drm/kmb: Add support for KeemBay Display Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 02/59] drm/kmb: Added id to kmb_plane Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 04/59] drm/kmb: Use biwise operators for register definitions Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 10/59] drm/kmb: Part 2 " Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 11/59] drm/kmb: Use correct mmio offset from data book Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` Anitha Chrisanthus [this message] 2020-06-30 21:27 ` [Intel-gfx] [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 17/59] drm/kmb: Part7 " Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 18/59] drm/kmb: Part8 " Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 20/59] drm/kmb: Register IRQ for LCD Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 23/59] drm/kmb: Additional register programming to update_plane Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 24/59] drm/kmb: Add ADV7535 bridge Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 25/59] drm/kmb: Display clock enable/disable Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 26/59] drm/kmb: rebase to newer kernel version Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 27/59] drm/kmb: minor name change to match device tree Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 28/59] drm/kmb: Changed MMIO size Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 29/59] drm/kmb: Defer Probe Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 30/59] drm/kmb: call bridge init in the very beginning Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 31/59] drm/kmb: Cleanup probe functions Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 38/59] drm/kmb: Mipi DPHY initialization changes Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 39/59] drm/kmb: Fixed driver unload Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 40/59] drm/kmb: Added LCD_TEST config Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 41/59] drm/kmb: Changes for LCD to Mipi Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 42/59] drm/kmb: Update LCD programming to match MIPI Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 44/59] drm/kmb: Mipi settings from input timings Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 45/59] drm/kmb: Enable LCD interrupts Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:27 ` [PATCH 47/59] drm/kmb: Don’t inadvertantly disable LCD controller Anitha Chrisanthus 2020-06-30 21:27 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 49/59] drm/kmb: Disable ping pong mode Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 50/59] drm/kmb: Do the layer initializations only once Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG " Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 52/59] drm/kmb: Cleaned up code Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 54/59] drm/kmb: Initialize uninitialized variables Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 55/59] drm/kmb: Added useful messages in LCD ISR Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 56/59] kmb/drm: Prune unsupported modes Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 57/59] drm/kmb: workaround for dma undeflow issue Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 58/59] drm/kmb: Get System Clock from SCMI Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 21:28 ` [PATCH 59/59] drm/kmb: work around for planar formats Anitha Chrisanthus 2020-06-30 21:28 ` [Intel-gfx] " Anitha Chrisanthus 2020-06-30 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for Keem Bay DRM driver Patchwork 2020-07-01 3:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-07-01 6:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2020-07-01 7:01 ` [PATCH 00/59] " Sam Ravnborg 2020-07-01 7:01 ` [Intel-gfx] " Sam Ravnborg 2020-07-01 21:53 ` Chrisanthus, Anitha 2020-07-01 21:53 ` [Intel-gfx] " Chrisanthus, Anitha 2020-07-02 10:19 ` Neil Armstrong 2020-07-02 10:19 ` [Intel-gfx] " Neil Armstrong
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