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From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Ben Dooks <ben.dooks@sifive.com>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Hal Feng <hal.feng@starfivetech.com>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
Date: Tue, 21 Feb 2023 10:46:33 +0800	[thread overview]
Message-ID: <20230221024645.127922-8-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20230221024645.127922-1-hal.feng@starfivetech.com>

From: Emil Renner Berthing <kernel@esmil.dk>

For the common code will be shared with the StarFive JH7110 SoC.

Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../reset/starfive/reset-starfive-jh7100.c    |  2 +-
 .../reset/starfive/reset-starfive-jh71x0.c    | 50 +++++++++----------
 .../reset/starfive/reset-starfive-jh71x0.h    |  2 +-
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 9d7cb4ed8869..5f06e5ae3346 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
-	return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
+	return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
 					      base + JH7100_RESET_ASSERT0,
 					      base + JH7100_RESET_STATUS0,
 					      jh7100_reset_asserted,
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
index 3577444a89c6..a689f4730ed7 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Reset driver for the StarFive JH7100 SoC
+ * Reset driver for the StarFive JH71X0 SoCs
  *
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
  */
@@ -15,7 +15,7 @@
 
 #include "reset-starfive-jh71x0.h"
 
-struct jh7100_reset {
+struct jh71x0_reset {
 	struct reset_controller_dev rcdev;
 	/* protect registers against concurrent read-modify-write */
 	spinlock_t lock;
@@ -24,16 +24,16 @@ struct jh7100_reset {
 	const u64 *asserted;
 };
 
-static inline struct jh7100_reset *
-jh7100_reset_from(struct reset_controller_dev *rcdev)
+static inline struct jh71x0_reset *
+jh71x0_reset_from(struct reset_controller_dev *rcdev)
 {
-	return container_of(rcdev, struct jh7100_reset, rcdev);
+	return container_of(rcdev, struct jh71x0_reset, rcdev);
 }
 
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
 			       unsigned long id, bool assert)
 {
-	struct jh7100_reset *data = jh7100_reset_from(rcdev);
+	struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
 	unsigned long offset = BIT_ULL_WORD(id);
 	u64 mask = BIT_ULL_MASK(id);
 	void __iomem *reg_assert = data->assert + offset * sizeof(u64);
@@ -62,34 +62,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 	return ret;
 }
 
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, true);
+	return jh71x0_reset_update(rcdev, id, true);
 }
 
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
 				 unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, false);
+	return jh71x0_reset_update(rcdev, id, false);
 }
 
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
 	int ret;
 
-	ret = jh7100_reset_assert(rcdev, id);
+	ret = jh71x0_reset_assert(rcdev, id);
 	if (ret)
 		return ret;
 
-	return jh7100_reset_deassert(rcdev, id);
+	return jh71x0_reset_deassert(rcdev, id);
 }
 
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
-	struct jh7100_reset *data = jh7100_reset_from(rcdev);
+	struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
 	unsigned long offset = BIT_ULL_WORD(id);
 	u64 mask = BIT_ULL_MASK(id);
 	void __iomem *reg_status = data->status + offset * sizeof(u64);
@@ -98,25 +98,25 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 	return !((value ^ data->asserted[offset]) & mask);
 }
 
-static const struct reset_control_ops jh7100_reset_ops = {
-	.assert		= jh7100_reset_assert,
-	.deassert	= jh7100_reset_deassert,
-	.reset		= jh7100_reset_reset,
-	.status		= jh7100_reset_status,
+static const struct reset_control_ops jh71x0_reset_ops = {
+	.assert		= jh71x0_reset_assert,
+	.deassert	= jh71x0_reset_deassert,
+	.reset		= jh71x0_reset_reset,
+	.status		= jh71x0_reset_status,
 };
 
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
 				   void __iomem *assert, void __iomem *status,
 				   const u64 *asserted, unsigned int nr_resets,
 				   struct module *owner)
 {
-	struct jh7100_reset *data;
+	struct jh71x0_reset *data;
 
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 
-	data->rcdev.ops = &jh7100_reset_ops;
+	data->rcdev.ops = &jh71x0_reset_ops;
 	data->rcdev.owner = owner;
 	data->rcdev.nr_resets = nr_resets;
 	data->rcdev.dev = dev;
@@ -129,4 +129,4 @@ int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_no
 
 	return devm_reset_controller_register(dev, &data->rcdev);
 }
-EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
+EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index 1fc5a648c8d8..ac9e80dd3f59 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -6,7 +6,7 @@
 #ifndef __RESET_STARFIVE_JH71X0_H
 #define __RESET_STARFIVE_JH71X0_H
 
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
 				   void __iomem *assert, void __iomem *status,
 				   const u64 *asserted, unsigned int nr_resets,
 				   struct module *owner);
-- 
2.38.1


WARNING: multiple messages have this Message-ID (diff)
From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Ben Dooks <ben.dooks@sifive.com>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Hal Feng <hal.feng@starfivetech.com>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
Date: Tue, 21 Feb 2023 10:46:33 +0800	[thread overview]
Message-ID: <20230221024645.127922-8-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20230221024645.127922-1-hal.feng@starfivetech.com>

From: Emil Renner Berthing <kernel@esmil.dk>

For the common code will be shared with the StarFive JH7110 SoC.

Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../reset/starfive/reset-starfive-jh7100.c    |  2 +-
 .../reset/starfive/reset-starfive-jh71x0.c    | 50 +++++++++----------
 .../reset/starfive/reset-starfive-jh71x0.h    |  2 +-
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 9d7cb4ed8869..5f06e5ae3346 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
-	return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
+	return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
 					      base + JH7100_RESET_ASSERT0,
 					      base + JH7100_RESET_STATUS0,
 					      jh7100_reset_asserted,
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
index 3577444a89c6..a689f4730ed7 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Reset driver for the StarFive JH7100 SoC
+ * Reset driver for the StarFive JH71X0 SoCs
  *
  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
  */
@@ -15,7 +15,7 @@
 
 #include "reset-starfive-jh71x0.h"
 
-struct jh7100_reset {
+struct jh71x0_reset {
 	struct reset_controller_dev rcdev;
 	/* protect registers against concurrent read-modify-write */
 	spinlock_t lock;
@@ -24,16 +24,16 @@ struct jh7100_reset {
 	const u64 *asserted;
 };
 
-static inline struct jh7100_reset *
-jh7100_reset_from(struct reset_controller_dev *rcdev)
+static inline struct jh71x0_reset *
+jh71x0_reset_from(struct reset_controller_dev *rcdev)
 {
-	return container_of(rcdev, struct jh7100_reset, rcdev);
+	return container_of(rcdev, struct jh71x0_reset, rcdev);
 }
 
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
 			       unsigned long id, bool assert)
 {
-	struct jh7100_reset *data = jh7100_reset_from(rcdev);
+	struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
 	unsigned long offset = BIT_ULL_WORD(id);
 	u64 mask = BIT_ULL_MASK(id);
 	void __iomem *reg_assert = data->assert + offset * sizeof(u64);
@@ -62,34 +62,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
 	return ret;
 }
 
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, true);
+	return jh71x0_reset_update(rcdev, id, true);
 }
 
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
 				 unsigned long id)
 {
-	return jh7100_reset_update(rcdev, id, false);
+	return jh71x0_reset_update(rcdev, id, false);
 }
 
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
 			      unsigned long id)
 {
 	int ret;
 
-	ret = jh7100_reset_assert(rcdev, id);
+	ret = jh71x0_reset_assert(rcdev, id);
 	if (ret)
 		return ret;
 
-	return jh7100_reset_deassert(rcdev, id);
+	return jh71x0_reset_deassert(rcdev, id);
 }
 
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
 			       unsigned long id)
 {
-	struct jh7100_reset *data = jh7100_reset_from(rcdev);
+	struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
 	unsigned long offset = BIT_ULL_WORD(id);
 	u64 mask = BIT_ULL_MASK(id);
 	void __iomem *reg_status = data->status + offset * sizeof(u64);
@@ -98,25 +98,25 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
 	return !((value ^ data->asserted[offset]) & mask);
 }
 
-static const struct reset_control_ops jh7100_reset_ops = {
-	.assert		= jh7100_reset_assert,
-	.deassert	= jh7100_reset_deassert,
-	.reset		= jh7100_reset_reset,
-	.status		= jh7100_reset_status,
+static const struct reset_control_ops jh71x0_reset_ops = {
+	.assert		= jh71x0_reset_assert,
+	.deassert	= jh71x0_reset_deassert,
+	.reset		= jh71x0_reset_reset,
+	.status		= jh71x0_reset_status,
 };
 
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
 				   void __iomem *assert, void __iomem *status,
 				   const u64 *asserted, unsigned int nr_resets,
 				   struct module *owner)
 {
-	struct jh7100_reset *data;
+	struct jh71x0_reset *data;
 
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 
-	data->rcdev.ops = &jh7100_reset_ops;
+	data->rcdev.ops = &jh71x0_reset_ops;
 	data->rcdev.owner = owner;
 	data->rcdev.nr_resets = nr_resets;
 	data->rcdev.dev = dev;
@@ -129,4 +129,4 @@ int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_no
 
 	return devm_reset_controller_register(dev, &data->rcdev);
 }
-EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
+EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index 1fc5a648c8d8..ac9e80dd3f59 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -6,7 +6,7 @@
 #ifndef __RESET_STARFIVE_JH71X0_H
 #define __RESET_STARFIVE_JH71X0_H
 
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
 				   void __iomem *assert, void __iomem *status,
 				   const u64 *asserted, unsigned int nr_resets,
 				   struct module *owner);
-- 
2.38.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-02-21  2:47 UTC|newest]

Thread overview: 143+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-21  2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-02-21  2:46 ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 17:10   ` Conor Dooley
2023-02-21 17:10     ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 17:13   ` Conor Dooley
2023-02-21 17:13     ` Conor Dooley
2023-02-21  2:46 ` Hal Feng [this message]
2023-02-21  2:46   ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21 17:17   ` Conor Dooley
2023-02-21 17:17     ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 17:23   ` Conor Dooley
2023-02-21 17:23     ` Conor Dooley
2023-02-23  3:40     ` Hal Feng
2023-02-23  3:40       ` Hal Feng
2023-02-22  9:13   ` Krzysztof Kozlowski
2023-02-22  9:13     ` Krzysztof Kozlowski
2023-02-22 10:40     ` Conor Dooley
2023-02-22 10:40       ` Conor Dooley
2023-02-23 10:22       ` Hal Feng
2023-02-23 10:22         ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 17:26   ` Conor Dooley
2023-02-21 17:26     ` Conor Dooley
2023-02-23  5:52     ` Hal Feng
2023-02-23  5:52       ` Hal Feng
2023-03-09 14:22   ` Geert Uytterhoeven
2023-03-09 14:22     ` Geert Uytterhoeven
2023-03-13  2:29     ` Hal Feng
2023-03-13  2:29       ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 15:12   ` Conor Dooley
2023-02-21 15:12     ` Conor Dooley
2023-02-23  6:17     ` Hal Feng
2023-02-23  6:17       ` Hal Feng
2023-02-26 16:07   ` Emil Renner Berthing
2023-02-26 16:07     ` Emil Renner Berthing
2023-02-28  2:30     ` Hal Feng
2023-02-28  2:30       ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-26 17:34   ` Emil Renner Berthing
2023-02-26 17:34     ` Emil Renner Berthing
2023-02-28  2:42     ` Hal Feng
2023-02-28  2:42       ` Hal Feng
2023-03-09  9:43       ` Hal Feng
2023-03-09  9:43         ` Hal Feng
2023-03-09 14:06         ` Emil Renner Berthing
2023-03-09 14:06           ` Emil Renner Berthing
2023-03-09 18:11           ` Conor Dooley
2023-03-09 18:11             ` Conor Dooley
2023-03-09 18:19             ` Emil Renner Berthing
2023-03-09 18:19               ` Emil Renner Berthing
2023-03-09 19:32               ` Palmer Dabbelt
2023-03-09 19:32                 ` Palmer Dabbelt
2023-02-21  2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 15:33   ` Emil Renner Berthing
2023-02-21 15:33     ` Emil Renner Berthing
2023-02-21 16:34     ` Conor Dooley
2023-02-21 16:34       ` Conor Dooley
2023-02-23  6:48       ` Hal Feng
2023-02-23  6:48         ` Hal Feng
2023-02-23  6:29     ` Hal Feng
2023-02-23  6:29       ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 11:38   ` Krzysztof Kozlowski
2023-02-21 11:38     ` Krzysztof Kozlowski
2023-02-21 15:10   ` Conor Dooley
2023-02-21 15:10     ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 17:03   ` Conor Dooley
2023-02-21 17:03     ` Conor Dooley
2023-02-23  7:16     ` Hal Feng
2023-02-23  7:16       ` Hal Feng
2023-02-27 18:10       ` Conor Dooley
2023-02-27 18:10         ` Conor Dooley
2023-02-21  2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21  2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-02-21  2:46   ` Hal Feng
2023-02-21 15:03   ` Emil Renner Berthing
2023-02-21 15:03     ` Emil Renner Berthing
2023-02-23  8:50     ` Hal Feng
2023-02-23  8:50       ` Hal Feng
2023-02-27 18:12       ` Conor Dooley
2023-02-27 18:12         ` Conor Dooley
2023-02-27 20:00         ` Conor Dooley
2023-02-27 20:00           ` Conor Dooley
2023-02-28  2:58           ` Hal Feng
2023-02-28  2:58             ` Hal Feng
2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv
2023-02-22 15:00   ` patchwork-bot+linux-riscv
2023-02-22 15:35   ` Conor Dooley
2023-03-03 19:08 ` Tommaso Merciai
2023-03-03 19:08   ` Tommaso Merciai
2023-03-06  3:29   ` Hal Feng
2023-03-06  3:29     ` Hal Feng
2023-03-06 10:22     ` Tommaso Merciai
2023-03-06 10:22       ` Tommaso Merciai
2023-03-07  8:36 ` Hal Feng
2023-03-07  8:36   ` Hal Feng
2023-03-07  8:51   ` Conor Dooley
2023-03-07  8:51     ` Conor Dooley
2023-03-07 10:08     ` Hal Feng
2023-03-07 10:08       ` Hal Feng
2023-03-08 12:28       ` Tommaso Merciai
2023-03-08 12:28         ` Tommaso Merciai
2023-03-08 13:36         ` Conor Dooley
2023-03-08 13:36           ` Conor Dooley
2023-03-09 16:49           ` Tommaso Merciai
2023-03-09 16:49             ` Tommaso Merciai
2023-03-09 17:52             ` Conor Dooley
2023-03-09 17:52               ` Conor Dooley
2023-03-09 18:58               ` Tommaso Merciai
2023-03-09 18:58                 ` Tommaso Merciai
2023-03-09 19:03                 ` Conor Dooley
2023-03-09 19:03                   ` Conor Dooley
2023-03-10  7:48                   ` Tommaso Merciai
2023-03-10  7:48                     ` Tommaso Merciai

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