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* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-17  6:23 Sahil Malhotra
  2021-11-17  6:23 ` [PATCH 2/2] configs: enabled DTB overlay feature for LS SoCs Sahil Malhotra
  2021-11-17  7:53 ` [PATCH 1/2] fsl-layerscape: add dtb overlay feature Michael Walle
  0 siblings, 2 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-17  6:23 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta
  Cc: Sahil Malhotra

From: Sahil Malhotra <sahil.malhotra@nxp.com>

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread
* RE:Re: [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2022-01-06  6:09 Sahil Malhotra (OSS)
  2022-01-06  7:40 ` Michael Walle
  0 siblings, 1 reply; 26+ messages in thread
From: Sahil Malhotra (OSS) @ 2022-01-06  6:09 UTC (permalink / raw)
  To: Michael Walle, Sahil Malhotra (OSS)
  Cc: ZHIZHIKIN Andrey, Clément Faure, Gaurav Jain, Pankaj Gupta,
	Priyanka Jain, u-boot, Varun Sethi, Ye Li

Hi Michael,

> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: Thursday, December 23, 2021 3:05 PM
> To: Sahil Malhotra (OSS) <sahil.malhotra@oss.nxp.com>
> Cc: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Clément Faure
> <clement.faure@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>; Pankaj Gupta
> <pankaj.gupta@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; u-
> boot@lists.denx.de; Varun Sethi <V.Sethi@nxp.com>; Ye Li <ye.li@nxp.com>
> Subject: Re: [EXT] Re: [PATCH 1/2] fsl-layerscape: add dtb overlay feature
> 
> Hi Sahil,
> 
> Am 2021-12-23 09:46, schrieb Sahil Malhotra (OSS):
> >> -----Original Message-----
> >> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Michael
> >> Walle
> >> Sent: Monday, December 20, 2021 6:23 PM
> >> To: Sahil Malhotra (OSS) <sahil.malhotra@oss.nxp.com>
> >> Cc: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Clément
> >> Faure <clement.faure@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>;
> >> Pankaj Gupta <pankaj.gupta@nxp.com>; Priyanka Jain
> >> <priyanka.jain@nxp.com>; u-boot@lists.denx.de; Varun Sethi
> >> <V.Sethi@nxp.com>; Ye Li <ye.li@nxp.com>
> >> Subject: [EXT] Re: [PATCH 1/2] fsl-layerscape: add dtb overlay
> >> feature
> >>
> >> Caution: EXT Email
> >>
> >> Hi Sahil,
> >>
> >> Am 2021-12-10 07:33, schrieb Sahil Malhotra (OSS):
> >> >> DT nodes can be statically disabled if we know that they are held
> >> >> by HAB and are not released to NS World.
> >> >>
> >> >> OP-TEE does set the status itself via dt_enable_secure_status(),
> >> >> which should present the properly configured FDT when U-Boot takes
> >> over.
> >> > Yes, OP-TEE set the status by dt_enable_secure_status() in DTB
> >> > overlay which gets merged with DTB provided for Linux bootup and
> >> > then Linux boots with merged DTB.
> >> > But u-boot uses the DTB embedded in its image. How can we modify
> >> > that DTB or merge DTB overlay passed by OP-TEE with uboot DTB ?
> >>
> >> But then u-boot has the "wrong" dtb. What is the reason, there is an
> >> overlay instead of a whole dtb? what if the overlay doesn't match the
> >> dtb?
> > "wrong" dtb means that uboot will not be aware of CAAM job ring which
> > is taken by OP-TEE and uboot on LS platforms currently use JR0, which
> > is not being used by any other entity in LS bootflow.
> 
> I don't know I follow. u-boot and linux should have the same device tree;
> regardless if that device is used or not. So applying the overlay just for linux isn't
> enough here.
Ok, I don't think that as of now, in all platforms uboot and linux have same devie
tree. 
But I will try to address your concern, but I don’t know how to apply overlay to
dtb which is embedded in u-boot binary, Can you please point me to one reference
which is doing this thing, I will take reference from there.

> > We don't use DTB in OP-TEE, but when we use CAAM in OP-TEE, OP-TEE
> > reserves One Job Ring for its use and that is communicated to Kernel
> > using DTB overlay.
> >
> >> what if the overlay doesn't match the dtb?
> > I didn't get this point, can you please elaborate a little.
> 
> You are merging a dtb fragment with an unknown dtb, right? Who says they
> match? you might have an old dtb where the supplied dtb fragment doesn't
> make any sense.
> 
> I might be missing something here. Eg. where is the linux dtb supposed to come
> from? This patchset is really missing an example and a description how things
> should work.
If supplied DTB does not match with DTB overlay fragment. then overlay will not get applied.
We don't have any control on where user picks the DTB, but we can only make sure DTB
overlay feature must work with DTBs which are upstreamed
If user makes its own customized DTB, we cannot make sure that things will work.

Regards,
Sahil Malhotra

^ permalink raw reply	[flat|nested] 26+ messages in thread
* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-16 10:16 Sahil Malhotra
  0 siblings, 0 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-16 10:16 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta
  Cc: Sahil Malhotra

From: Sahil Malhotra <sahil.malhotra@nxp.com>

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-16  8:34 Sahil Malhotra
  0 siblings, 0 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-16  8:34 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta
  Cc: Sahil Malhotra

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-16  8:30 Sahil Malhotra
  0 siblings, 0 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-16  8:30 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta
  Cc: Sahil Malhotra

From: Sahil Malhotra <sahil.malhotra@nxp.com>

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-16  6:49 Sahil Malhotra
  0 siblings, 0 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-16  6:49 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta
  Cc: Sahil Malhotra

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-16  6:46 Sahil Malhotra
  0 siblings, 0 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-16  6:46 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta
  Cc: Sahil Malhotra

From: Sahil Malhotra <sahil.malhotra@nxp.com>

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread
* [PATCH 1/2] fsl-layerscape: add dtb overlay feature
@ 2021-11-16  6:37 Sahil Malhotra
  0 siblings, 0 replies; 26+ messages in thread
From: Sahil Malhotra @ 2021-11-16  6:37 UTC (permalink / raw)
  To: u-boot, v.sethi, priyanka.jain, ye.li, clement.faure,
	gaurav.jain, pankaj.gupta, sahil.malhotra

From: Sahil Malhotra <sahil.malhotra@nxp.com>

This patch enables the DTB overlay feature for LS platforms.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c  | 39 +++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h  | 10 +++++
 arch/arm/cpu/armv8/fsl-layerscape/fdt.c       | 12 ++++++
 .../cpu/armv8/fsl-layerscape/lowlevel_init.S  | 25 ++++++++++++
 5 files changed, 87 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 598c36ee66..97f1f291dd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -7,6 +7,7 @@ obj-y += lowlevel.o
 obj-y += soc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_MP) += mp.o spintable.o
+obj-$(CONFIG_OF_LIBFDT_OVERLAY) += lowlevel_init.o dt_optee.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 endif
 obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
new file mode 100644
index 0000000000..2418ad09c7
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+#include <common.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/sizes.h>
+#include "dt_optee.h"
+
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd)
+{
+	int ret = 0;
+
+	/*
+	 * No BL32_BASE passed means no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[0]) {
+		debug("No BL32_BASE passed means no TEE running\n");
+		return ret;
+	}
+
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n", rom_pointer[2]);
+		ret = fdt_check_header((void *)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+			       fdt_totalsize((void *)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void *)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+			}
+		}
+	}
+	return ret;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
new file mode 100644
index 0000000000..d1ff25d531
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/dt_optee.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+#ifndef __DT_OPTEE_H__
+#define __DT_OPTEE_H__
+
+extern unsigned long rom_pointer[];
+int ft_add_optee_overlay(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index f1624ff30a..0824c62264 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -31,6 +31,7 @@
 #endif
 #include <asm/arch/speed.h>
 #include <fsl_qbman.h>
+#include "dt_optee.h"
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -698,3 +699,14 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	fdt_fixup_ecam(blob);
 #endif
 }
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	return ft_add_optee_overlay(blob, bd);
+#else
+	return 0;
+#endif
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
new file mode 100644
index 0000000000..1d6a2d85fa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel_init.S
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 32
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+	/* The firmware provided FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+
+	ldr	x1, =save_boot_params_ret
+	br	x1
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 26+ messages in thread

end of thread, other threads:[~2022-02-24 12:34 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-17  6:23 [PATCH 1/2] fsl-layerscape: add dtb overlay feature Sahil Malhotra
2021-11-17  6:23 ` [PATCH 2/2] configs: enabled DTB overlay feature for LS SoCs Sahil Malhotra
2021-11-17  7:53 ` [PATCH 1/2] fsl-layerscape: add dtb overlay feature Michael Walle
2021-11-17 18:11   ` Sahil Malhotra (OSS)
2021-11-17 18:20     ` Michael Walle
2021-11-29 11:55       ` Sahil Malhotra (OSS)
2021-11-29 17:47         ` Michael Walle
2021-12-08  6:12           ` Sahil Malhotra (OSS)
2021-12-08 10:13             ` ZHIZHIKIN Andrey
2021-12-10  6:33               ` Sahil Malhotra (OSS)
2021-12-17  6:19                 ` Sahil Malhotra (OSS)
2021-12-17  7:27                   ` Michael Walle
2021-12-20 12:52                 ` Michael Walle
2021-12-23  8:46                   ` [EXT] " Sahil Malhotra (OSS)
2021-12-23  9:34                     ` Michael Walle
2021-12-10  7:38           ` François Ozog
  -- strict thread matches above, loose matches on Subject: below --
2022-01-06  6:09 Sahil Malhotra (OSS)
2022-01-06  7:40 ` Michael Walle
2022-02-04 11:27   ` Sahil Malhotra (OSS)
2022-02-24 10:59     ` Sahil Malhotra (OSS)
2022-02-24 12:33       ` Michael Walle
2021-11-16 10:16 Sahil Malhotra
2021-11-16  8:34 Sahil Malhotra
2021-11-16  8:30 Sahil Malhotra
2021-11-16  6:49 Sahil Malhotra
2021-11-16  6:46 Sahil Malhotra
2021-11-16  6:37 Sahil Malhotra

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