From: Shannon Zhao <shannon.zhao@linaro.org> To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, marc.zyngier@arm.com, christoffer.dall@linaro.org, will.deacon@arm.com, wei@redhat.com, alex.bennee@linaro.org, peter.huangpeng@huawei.com, shannon.zhao@linaro.org Subject: [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Date: Thu, 24 Sep 2015 15:31:06 -0700 [thread overview] Message-ID: <1443133885-3366-2-git-send-email-shannon.zhao@linaro.org> (raw) In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> --- arch/arm64/include/asm/pmu.h | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/perf_event.c | 35 -------------------------------- 2 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h index b7710a5..b9f394a 100644 --- a/arch/arm64/include/asm/pmu.h +++ b/arch/arm64/include/asm/pmu.h @@ -19,6 +19,51 @@ #ifndef __ASM_PMU_H #define __ASM_PMU_H +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#define ARMV8_PMCR_N_MASK 0x1f +#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#define ARMV8_CNTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#define ARMV8_INTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ +#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#define ARMV8_EXCLUDE_EL1 (1 << 31) +#define ARMV8_EXCLUDE_EL0 (1 << 30) +#define ARMV8_INCLUDE_EL2 (1 << 27) + #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index f9a74d4..534e8ad 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -741,9 +741,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_COUNTER0 1 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#define ARMV8_MAX_COUNTERS 32 -#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -754,38 +751,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#define ARMV8_PMCR_N_MASK 0x1f -#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ -#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv3 - */ -#define ARMV8_EXCLUDE_EL1 (1 << 31) -#define ARMV8_EXCLUDE_EL0 (1 << 30) -#define ARMV8_INCLUDE_EL2 (1 << 27) - static inline u32 armv8pmu_pmcr_read(void) { u32 val; -- 2.1.4
WARNING: multiple messages have this Message-ID (diff)
From: shannon.zhao@linaro.org (Shannon Zhao) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Date: Thu, 24 Sep 2015 15:31:06 -0700 [thread overview] Message-ID: <1443133885-3366-2-git-send-email-shannon.zhao@linaro.org> (raw) In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> To use the ARMv8 PMU related register defines from the KVM code, we move the relevant definitions to asm/pmu.h header file. Signed-off-by: Anup Patel <anup.patel@linaro.org> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> --- arch/arm64/include/asm/pmu.h | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/perf_event.c | 35 -------------------------------- 2 files changed, 45 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h index b7710a5..b9f394a 100644 --- a/arch/arm64/include/asm/pmu.h +++ b/arch/arm64/include/asm/pmu.h @@ -19,6 +19,51 @@ #ifndef __ASM_PMU_H #define __ASM_PMU_H +#define ARMV8_MAX_COUNTERS 32 +#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) + +/* + * Per-CPU PMCR: config reg + */ +#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ +#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ +#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ +#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ +#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ +#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ +#define ARMV8_PMCR_N_MASK 0x1f +#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ + +/* + * PMCNTEN: counters enable reg + */ +#define ARMV8_CNTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMINTEN: counters interrupt enable reg + */ +#define ARMV8_INTEN_MASK 0xffffffff /* Mask for writable bits */ + +/* + * PMOVSR: counters overflow flag status reg + */ +#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ +#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK + +/* + * PMXEVTYPER: Event selection reg + */ +#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ +#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ + +/* + * Event filters for PMUv3 + */ +#define ARMV8_EXCLUDE_EL1 (1 << 31) +#define ARMV8_EXCLUDE_EL0 (1 << 30) +#define ARMV8_INCLUDE_EL2 (1 << 27) + #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index f9a74d4..534e8ad 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -741,9 +741,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_COUNTER0 1 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) -#define ARMV8_MAX_COUNTERS 32 -#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1) - /* * ARMv8 low level PMU access */ @@ -754,38 +751,6 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] #define ARMV8_IDX_TO_COUNTER(x) \ (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK) -/* - * Per-CPU PMCR: config reg - */ -#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */ -#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */ -#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */ -#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ -#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ -#define ARMV8_PMCR_N_MASK 0x1f -#define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ - -/* - * PMOVSR: counters overflow flag status reg - */ -#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */ -#define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv3 - */ -#define ARMV8_EXCLUDE_EL1 (1 << 31) -#define ARMV8_EXCLUDE_EL0 (1 << 30) -#define ARMV8_INCLUDE_EL2 (1 << 27) - static inline u32 armv8pmu_pmcr_read(void) { u32 val; -- 2.1.4
next prev parent reply other threads:[~2015-09-24 22:31 UTC|newest] Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-09-24 22:31 [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao [this message] 2015-09-24 22:31 ` [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-07 8:25 ` Marc Zyngier 2015-10-07 8:25 ` Marc Zyngier 2015-09-24 22:31 ` [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-16 5:35 ` Wei Huang 2015-10-16 5:35 ` Wei Huang 2015-10-21 6:27 ` Shannon Zhao 2015-10-21 6:27 ` Shannon Zhao 2015-10-21 6:27 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-16 6:08 ` Wei Huang 2015-10-16 6:08 ` Wei Huang 2015-10-21 6:32 ` Shannon Zhao 2015-10-21 6:32 ` Shannon Zhao 2015-10-21 6:32 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-16 15:06 ` Wei Huang 2015-10-16 15:06 ` Wei Huang 2015-10-21 6:48 ` Shannon Zhao 2015-10-21 6:48 ` Shannon Zhao 2015-10-21 6:48 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-16 15:25 ` Wei Huang 2015-10-16 15:25 ` Wei Huang 2015-10-21 7:02 ` Shannon Zhao 2015-10-21 7:02 ` Shannon Zhao 2015-10-21 7:02 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-07 8:17 ` Marc Zyngier 2015-10-07 8:17 ` Marc Zyngier 2015-09-24 22:31 ` [PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-16 15:28 ` Wei Huang 2015-10-16 15:28 ` Wei Huang 2015-09-24 22:31 ` [PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-09-24 22:31 ` [PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao 2015-09-24 22:31 ` Shannon Zhao 2015-10-16 4:55 ` [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Wei Huang 2015-10-16 4:55 ` Wei Huang 2015-10-16 17:01 ` Christopher Covington 2015-10-16 17:01 ` Christopher Covington 2015-10-21 7:26 ` Shannon Zhao 2015-10-21 7:26 ` Shannon Zhao 2015-10-21 7:26 ` Shannon Zhao 2015-10-26 11:33 ` Christoffer Dall 2015-10-26 11:33 ` Christoffer Dall 2015-10-27 1:15 ` Shannon Zhao 2015-10-27 1:15 ` Shannon Zhao
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