From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Wei Huang <wei@redhat.com>,
Shannon Zhao <shannon.zhao@linaro.org>,
<kvmarm@lists.cs.columbia.edu>
Cc: marc.zyngier@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
Date: Wed, 21 Oct 2015 14:27:11 +0800 [thread overview]
Message-ID: <5627303F.4030006@huawei.com> (raw)
In-Reply-To: <56208CB6.1050508@redhat.com>
On 2015/10/16 13:35, Wei Huang wrote:
>
> On 09/24/2015 05:31 PM, Shannon Zhao wrote:
>> > Add reset handler which gets host value of PMCR_EL0 and make writable
>> > bits architecturally UNKNOWN. Add a common access handler for PMU
>> > registers which emulates writing and reading register and add emulation
>> > for PMCR.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 81 +++++++++++++++++++++++++++++++++++++++++++++--
>> > 1 file changed, 79 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index b41607d..60c0842 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -33,6 +33,7 @@
>> > #include <asm/kvm_emulate.h>
>> > #include <asm/kvm_host.h>
>> > #include <asm/kvm_mmu.h>
>> > +#include <asm/pmu.h>
>> >
>> > #include <trace/events/kvm.h>
>> >
>> > @@ -446,6 +447,53 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>> > vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
>> > }
>> >
>> > +static void vcpu_sysreg_write(struct kvm_vcpu *vcpu,
>> > + const struct sys_reg_desc *r, u64 val)
>> > +{
>> > + if (!vcpu_mode_is_32bit(vcpu))
>> > + vcpu_sys_reg(vcpu, r->reg) = val;
>> > + else
>> > + vcpu_cp15(vcpu, r->reg) = lower_32_bits(val);
>> > +}
>> > +
>> > +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>> > +{
>> > + u64 pmcr, val;
>> > +
>> > + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
>> > + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN*/
>> > + val = (pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad);
> Two comments:
> (1) In Patch 1, ARMV8_PMCR_MASK is defined as 0x3f. According to ARMv8
> spec, PMCR_EL0.LC (bit 6) is also writable. Should ARMV8_PMCR_MASK be 0x7f?
According to the spec, it should be 0x7f.
> (2) According to spec the PMCR_EL0.E bit reset to 0, not UNKNOWN.
>
Yeah, will fix this.
Thanks,
--
Shannon
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Wei Huang <wei@redhat.com>,
Shannon Zhao <shannon.zhao@linaro.org>,
kvmarm@lists.cs.columbia.edu
Cc: marc.zyngier@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
Date: Wed, 21 Oct 2015 14:27:11 +0800 [thread overview]
Message-ID: <5627303F.4030006@huawei.com> (raw)
In-Reply-To: <56208CB6.1050508@redhat.com>
On 2015/10/16 13:35, Wei Huang wrote:
>
> On 09/24/2015 05:31 PM, Shannon Zhao wrote:
>> > Add reset handler which gets host value of PMCR_EL0 and make writable
>> > bits architecturally UNKNOWN. Add a common access handler for PMU
>> > registers which emulates writing and reading register and add emulation
>> > for PMCR.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 81 +++++++++++++++++++++++++++++++++++++++++++++--
>> > 1 file changed, 79 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index b41607d..60c0842 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -33,6 +33,7 @@
>> > #include <asm/kvm_emulate.h>
>> > #include <asm/kvm_host.h>
>> > #include <asm/kvm_mmu.h>
>> > +#include <asm/pmu.h>
>> >
>> > #include <trace/events/kvm.h>
>> >
>> > @@ -446,6 +447,53 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>> > vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
>> > }
>> >
>> > +static void vcpu_sysreg_write(struct kvm_vcpu *vcpu,
>> > + const struct sys_reg_desc *r, u64 val)
>> > +{
>> > + if (!vcpu_mode_is_32bit(vcpu))
>> > + vcpu_sys_reg(vcpu, r->reg) = val;
>> > + else
>> > + vcpu_cp15(vcpu, r->reg) = lower_32_bits(val);
>> > +}
>> > +
>> > +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>> > +{
>> > + u64 pmcr, val;
>> > +
>> > + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
>> > + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN*/
>> > + val = (pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad);
> Two comments:
> (1) In Patch 1, ARMV8_PMCR_MASK is defined as 0x3f. According to ARMv8
> spec, PMCR_EL0.LC (bit 6) is also writable. Should ARMV8_PMCR_MASK be 0x7f?
According to the spec, it should be 0x7f.
> (2) According to spec the PMCR_EL0.E bit reset to 0, not UNKNOWN.
>
Yeah, will fix this.
Thanks,
--
Shannon
WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
Date: Wed, 21 Oct 2015 14:27:11 +0800 [thread overview]
Message-ID: <5627303F.4030006@huawei.com> (raw)
In-Reply-To: <56208CB6.1050508@redhat.com>
On 2015/10/16 13:35, Wei Huang wrote:
>
> On 09/24/2015 05:31 PM, Shannon Zhao wrote:
>> > Add reset handler which gets host value of PMCR_EL0 and make writable
>> > bits architecturally UNKNOWN. Add a common access handler for PMU
>> > registers which emulates writing and reading register and add emulation
>> > for PMCR.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> > arch/arm64/kvm/sys_regs.c | 81 +++++++++++++++++++++++++++++++++++++++++++++--
>> > 1 file changed, 79 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index b41607d..60c0842 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -33,6 +33,7 @@
>> > #include <asm/kvm_emulate.h>
>> > #include <asm/kvm_host.h>
>> > #include <asm/kvm_mmu.h>
>> > +#include <asm/pmu.h>
>> >
>> > #include <trace/events/kvm.h>
>> >
>> > @@ -446,6 +447,53 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>> > vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
>> > }
>> >
>> > +static void vcpu_sysreg_write(struct kvm_vcpu *vcpu,
>> > + const struct sys_reg_desc *r, u64 val)
>> > +{
>> > + if (!vcpu_mode_is_32bit(vcpu))
>> > + vcpu_sys_reg(vcpu, r->reg) = val;
>> > + else
>> > + vcpu_cp15(vcpu, r->reg) = lower_32_bits(val);
>> > +}
>> > +
>> > +static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>> > +{
>> > + u64 pmcr, val;
>> > +
>> > + asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
>> > + /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN*/
>> > + val = (pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad);
> Two comments:
> (1) In Patch 1, ARMV8_PMCR_MASK is defined as 0x3f. According to ARMv8
> spec, PMCR_EL0.LC (bit 6) is also writable. Should ARMV8_PMCR_MASK be 0x7f?
According to the spec, it should be 0x7f.
> (2) According to spec the PMCR_EL0.E bit reset to 0, not UNKNOWN.
>
Yeah, will fix this.
Thanks,
--
Shannon
next prev parent reply other threads:[~2015-10-21 6:27 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-24 22:31 [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-07 8:25 ` Marc Zyngier
2015-10-07 8:25 ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 5:35 ` Wei Huang
2015-10-16 5:35 ` Wei Huang
2015-10-21 6:27 ` Shannon Zhao [this message]
2015-10-21 6:27 ` Shannon Zhao
2015-10-21 6:27 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 6:08 ` Wei Huang
2015-10-16 6:08 ` Wei Huang
2015-10-21 6:32 ` Shannon Zhao
2015-10-21 6:32 ` Shannon Zhao
2015-10-21 6:32 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:06 ` Wei Huang
2015-10-16 15:06 ` Wei Huang
2015-10-21 6:48 ` Shannon Zhao
2015-10-21 6:48 ` Shannon Zhao
2015-10-21 6:48 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:25 ` Wei Huang
2015-10-16 15:25 ` Wei Huang
2015-10-21 7:02 ` Shannon Zhao
2015-10-21 7:02 ` Shannon Zhao
2015-10-21 7:02 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-07 8:17 ` Marc Zyngier
2015-10-07 8:17 ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:28 ` Wei Huang
2015-10-16 15:28 ` Wei Huang
2015-09-24 22:31 ` [PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 4:55 ` [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Wei Huang
2015-10-16 4:55 ` Wei Huang
2015-10-16 17:01 ` Christopher Covington
2015-10-16 17:01 ` Christopher Covington
2015-10-21 7:26 ` Shannon Zhao
2015-10-21 7:26 ` Shannon Zhao
2015-10-21 7:26 ` Shannon Zhao
2015-10-26 11:33 ` Christoffer Dall
2015-10-26 11:33 ` Christoffer Dall
2015-10-27 1:15 ` Shannon Zhao
2015-10-27 1:15 ` Shannon Zhao
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