From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Wei Huang <wei@redhat.com>,
Shannon Zhao <shannon.zhao@linaro.org>,
<kvmarm@lists.cs.columbia.edu>
Cc: marc.zyngier@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
Date: Wed, 21 Oct 2015 14:32:42 +0800 [thread overview]
Message-ID: <5627318A.8090905@huawei.com> (raw)
In-Reply-To: <56209467.3010800@redhat.com>
On 2015/10/16 14:08, Wei Huang wrote:
>> +/**
>> > + * kvm_pmu_get_counter_value - get PMU counter value
>> > + * @vcpu: The vcpu pointer
>> > + * @select_idx: The counter index
>> > + */
>> > +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
>> > +{
>> > + u64 enabled, running;
>> > + struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> > + struct kvm_pmc *pmc = &pmu->pmc[select_idx];
>> > + u64 counter;
>> > +
>> > + if (!vcpu_mode_is_32bit(vcpu))
>> > + counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
> The select_idx is from PMSELR_EL0. According to PMUv3 spec, PMSELR_EL0
> is the register that "selects the current event counter PMEVCNTR<x> or
> the cycle counter, CCNT". The code here always reads the counter value
> from PMEVCNTR. It doesn't read the value from cycle counter when
> select_idx=0b11111. We might waste some perf counter resources here.
>
No, it does read the value from the cycle counter. When
select_idx=0b11111, PMEVCNTR0_EL0 + select_idx = PMCCNTR_EL0( See patch
03/20).
--
Shannon
WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Wei Huang <wei@redhat.com>,
Shannon Zhao <shannon.zhao@linaro.org>,
kvmarm@lists.cs.columbia.edu
Cc: marc.zyngier@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
Date: Wed, 21 Oct 2015 14:32:42 +0800 [thread overview]
Message-ID: <5627318A.8090905@huawei.com> (raw)
In-Reply-To: <56209467.3010800@redhat.com>
On 2015/10/16 14:08, Wei Huang wrote:
>> +/**
>> > + * kvm_pmu_get_counter_value - get PMU counter value
>> > + * @vcpu: The vcpu pointer
>> > + * @select_idx: The counter index
>> > + */
>> > +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
>> > +{
>> > + u64 enabled, running;
>> > + struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> > + struct kvm_pmc *pmc = &pmu->pmc[select_idx];
>> > + u64 counter;
>> > +
>> > + if (!vcpu_mode_is_32bit(vcpu))
>> > + counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
> The select_idx is from PMSELR_EL0. According to PMUv3 spec, PMSELR_EL0
> is the register that "selects the current event counter PMEVCNTR<x> or
> the cycle counter, CCNT". The code here always reads the counter value
> from PMEVCNTR. It doesn't read the value from cycle counter when
> select_idx=0b11111. We might waste some perf counter resources here.
>
No, it does read the value from the cycle counter. When
select_idx=0b11111, PMEVCNTR0_EL0 + select_idx = PMCCNTR_EL0( See patch
03/20).
--
Shannon
WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
Date: Wed, 21 Oct 2015 14:32:42 +0800 [thread overview]
Message-ID: <5627318A.8090905@huawei.com> (raw)
In-Reply-To: <56209467.3010800@redhat.com>
On 2015/10/16 14:08, Wei Huang wrote:
>> +/**
>> > + * kvm_pmu_get_counter_value - get PMU counter value
>> > + * @vcpu: The vcpu pointer
>> > + * @select_idx: The counter index
>> > + */
>> > +unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
>> > +{
>> > + u64 enabled, running;
>> > + struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> > + struct kvm_pmc *pmc = &pmu->pmc[select_idx];
>> > + u64 counter;
>> > +
>> > + if (!vcpu_mode_is_32bit(vcpu))
>> > + counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
> The select_idx is from PMSELR_EL0. According to PMUv3 spec, PMSELR_EL0
> is the register that "selects the current event counter PMEVCNTR<x> or
> the cycle counter, CCNT". The code here always reads the counter value
> from PMEVCNTR. It doesn't read the value from cycle counter when
> select_idx=0b11111. We might waste some perf counter resources here.
>
No, it does read the value from the cycle counter. When
select_idx=0b11111, PMEVCNTR0_EL0 + select_idx = PMCCNTR_EL0( See patch
03/20).
--
Shannon
next prev parent reply other threads:[~2015-10-21 6:32 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-24 22:31 [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-07 8:25 ` Marc Zyngier
2015-10-07 8:25 ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 5:35 ` Wei Huang
2015-10-16 5:35 ` Wei Huang
2015-10-21 6:27 ` Shannon Zhao
2015-10-21 6:27 ` Shannon Zhao
2015-10-21 6:27 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 6:08 ` Wei Huang
2015-10-16 6:08 ` Wei Huang
2015-10-21 6:32 ` Shannon Zhao [this message]
2015-10-21 6:32 ` Shannon Zhao
2015-10-21 6:32 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:06 ` Wei Huang
2015-10-16 15:06 ` Wei Huang
2015-10-21 6:48 ` Shannon Zhao
2015-10-21 6:48 ` Shannon Zhao
2015-10-21 6:48 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:25 ` Wei Huang
2015-10-16 15:25 ` Wei Huang
2015-10-21 7:02 ` Shannon Zhao
2015-10-21 7:02 ` Shannon Zhao
2015-10-21 7:02 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-07 8:17 ` Marc Zyngier
2015-10-07 8:17 ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:28 ` Wei Huang
2015-10-16 15:28 ` Wei Huang
2015-09-24 22:31 ` [PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 4:55 ` [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Wei Huang
2015-10-16 4:55 ` Wei Huang
2015-10-16 17:01 ` Christopher Covington
2015-10-16 17:01 ` Christopher Covington
2015-10-21 7:26 ` Shannon Zhao
2015-10-21 7:26 ` Shannon Zhao
2015-10-21 7:26 ` Shannon Zhao
2015-10-26 11:33 ` Christoffer Dall
2015-10-26 11:33 ` Christoffer Dall
2015-10-27 1:15 ` Shannon Zhao
2015-10-27 1:15 ` Shannon Zhao
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