From: Marc Zyngier <marc.zyngier@arm.com>
To: Shannon Zhao <shannon.zhao@linaro.org>, kvmarm@lists.cs.columbia.edu
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
christoffer.dall@linaro.org, will.deacon@arm.com, wei@redhat.com,
alex.bennee@linaro.org, peter.huangpeng@huawei.com
Subject: Re: [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers
Date: Wed, 07 Oct 2015 09:25:42 +0100 [thread overview]
Message-ID: <5614D706.9000106@arm.com> (raw)
In-Reply-To: <1443133885-3366-4-git-send-email-shannon.zhao@linaro.org>
On 24/09/15 23:31, Shannon Zhao wrote:
> We are about to trap and emulate acccesses to each PMU register
> individually. This adds the context offsets for the AArch64 PMU
> registers and their AArch32 counterparts.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> arch/arm64/include/asm/kvm_asm.h | 59 +++++++++++++++++++++++++++++++++++-----
> 1 file changed, 52 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
> index 67fa0de..0a4dfcc 100644
> --- a/arch/arm64/include/asm/kvm_asm.h
> +++ b/arch/arm64/include/asm/kvm_asm.h
> @@ -48,14 +48,36 @@
> #define MDSCR_EL1 22 /* Monitor Debug System Control Register */
> #define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */
>
> +/* Performance Monitors Registers */
> +#define PMCR_EL0 24 /* Control Register */
> +#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */
> +#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register */
> +#define PMSELR_EL0 27 /* Event Counter Selection Register */
> +#define PMCEID0_EL0 28 /* Common Event Identification Register 0 */
> +#define PMCEID1_EL0 29 /* Common Event Identification Register 1 */
> +#define PMEVCNTR0_EL0 30 /* Event Counter Register (0-30) */
> +#define PMEVCNTR30_EL0 60
> +#define PMCCNTR_EL0 61 /* Cycle Counter Register */
> +#define PMEVTYPER0_EL0 62 /* Event Type Register (0-30) */
> +#define PMEVTYPER30_EL0 92
> +#define PMCCFILTR_EL0 93 /* Cycle Count Filter Register */
> +#define PMXEVCNTR_EL0 94 /* Selected Event Count Register */
> +#define PMXEVTYPER_EL0 95 /* Selected Event Type Register */
> +#define PMCNTENSET_EL0 96 /* Count Enable Set Register */
> +#define PMCNTENCLR_EL0 97 /* Count Enable Clear Register */
> +#define PMINTENSET_EL1 98 /* Interrupt Enable Set Register */
> +#define PMINTENCLR_EL1 99 /* Interrupt Enable Clear Register */
> +#define PMUSERENR_EL0 100 /* User Enable Register */
> +#define PMSWINC_EL0 101 /* Software Increment Register */
> +
> /* 32bit specific registers. Keep them at the end of the range */
> -#define DACR32_EL2 24 /* Domain Access Control Register */
> -#define IFSR32_EL2 25 /* Instruction Fault Status Register */
> -#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
> -#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
> -#define TEECR32_EL1 28 /* ThumbEE Configuration Register */
> -#define TEEHBR32_EL1 29 /* ThumbEE Handler Base Register */
> -#define NR_SYS_REGS 30
> +#define DACR32_EL2 102 /* Domain Access Control Register */
> +#define IFSR32_EL2 103 /* Instruction Fault Status Register */
> +#define FPEXC32_EL2 104 /* Floating-Point Exception Control Register */
> +#define DBGVCR32_EL2 105 /* Debug Vector Catch Register */
> +#define TEECR32_EL1 106 /* ThumbEE Configuration Register */
> +#define TEEHBR32_EL1 107 /* ThumbEE Handler Base Register */
> +#define NR_SYS_REGS 108
This will need some rebasing - some of the registers have already
changed or disappeared. I really need to find a way to make this mess
more manageable...
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers
Date: Wed, 07 Oct 2015 09:25:42 +0100 [thread overview]
Message-ID: <5614D706.9000106@arm.com> (raw)
In-Reply-To: <1443133885-3366-4-git-send-email-shannon.zhao@linaro.org>
On 24/09/15 23:31, Shannon Zhao wrote:
> We are about to trap and emulate acccesses to each PMU register
> individually. This adds the context offsets for the AArch64 PMU
> registers and their AArch32 counterparts.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> arch/arm64/include/asm/kvm_asm.h | 59 +++++++++++++++++++++++++++++++++++-----
> 1 file changed, 52 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
> index 67fa0de..0a4dfcc 100644
> --- a/arch/arm64/include/asm/kvm_asm.h
> +++ b/arch/arm64/include/asm/kvm_asm.h
> @@ -48,14 +48,36 @@
> #define MDSCR_EL1 22 /* Monitor Debug System Control Register */
> #define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */
>
> +/* Performance Monitors Registers */
> +#define PMCR_EL0 24 /* Control Register */
> +#define PMOVSSET_EL0 25 /* Overflow Flag Status Set Register */
> +#define PMOVSCLR_EL0 26 /* Overflow Flag Status Clear Register */
> +#define PMSELR_EL0 27 /* Event Counter Selection Register */
> +#define PMCEID0_EL0 28 /* Common Event Identification Register 0 */
> +#define PMCEID1_EL0 29 /* Common Event Identification Register 1 */
> +#define PMEVCNTR0_EL0 30 /* Event Counter Register (0-30) */
> +#define PMEVCNTR30_EL0 60
> +#define PMCCNTR_EL0 61 /* Cycle Counter Register */
> +#define PMEVTYPER0_EL0 62 /* Event Type Register (0-30) */
> +#define PMEVTYPER30_EL0 92
> +#define PMCCFILTR_EL0 93 /* Cycle Count Filter Register */
> +#define PMXEVCNTR_EL0 94 /* Selected Event Count Register */
> +#define PMXEVTYPER_EL0 95 /* Selected Event Type Register */
> +#define PMCNTENSET_EL0 96 /* Count Enable Set Register */
> +#define PMCNTENCLR_EL0 97 /* Count Enable Clear Register */
> +#define PMINTENSET_EL1 98 /* Interrupt Enable Set Register */
> +#define PMINTENCLR_EL1 99 /* Interrupt Enable Clear Register */
> +#define PMUSERENR_EL0 100 /* User Enable Register */
> +#define PMSWINC_EL0 101 /* Software Increment Register */
> +
> /* 32bit specific registers. Keep them at the end of the range */
> -#define DACR32_EL2 24 /* Domain Access Control Register */
> -#define IFSR32_EL2 25 /* Instruction Fault Status Register */
> -#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
> -#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
> -#define TEECR32_EL1 28 /* ThumbEE Configuration Register */
> -#define TEEHBR32_EL1 29 /* ThumbEE Handler Base Register */
> -#define NR_SYS_REGS 30
> +#define DACR32_EL2 102 /* Domain Access Control Register */
> +#define IFSR32_EL2 103 /* Instruction Fault Status Register */
> +#define FPEXC32_EL2 104 /* Floating-Point Exception Control Register */
> +#define DBGVCR32_EL2 105 /* Debug Vector Catch Register */
> +#define TEECR32_EL1 106 /* ThumbEE Configuration Register */
> +#define TEEHBR32_EL1 107 /* ThumbEE Handler Base Register */
> +#define NR_SYS_REGS 108
This will need some rebasing - some of the registers have already
changed or disappeared. I really need to find a way to make this mess
more manageable...
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2015-10-07 8:25 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-24 22:31 [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-07 8:25 ` Marc Zyngier [this message]
2015-10-07 8:25 ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 5:35 ` Wei Huang
2015-10-16 5:35 ` Wei Huang
2015-10-21 6:27 ` Shannon Zhao
2015-10-21 6:27 ` Shannon Zhao
2015-10-21 6:27 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 6:08 ` Wei Huang
2015-10-16 6:08 ` Wei Huang
2015-10-21 6:32 ` Shannon Zhao
2015-10-21 6:32 ` Shannon Zhao
2015-10-21 6:32 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:06 ` Wei Huang
2015-10-16 15:06 ` Wei Huang
2015-10-21 6:48 ` Shannon Zhao
2015-10-21 6:48 ` Shannon Zhao
2015-10-21 6:48 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:25 ` Wei Huang
2015-10-16 15:25 ` Wei Huang
2015-10-21 7:02 ` Shannon Zhao
2015-10-21 7:02 ` Shannon Zhao
2015-10-21 7:02 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-07 8:17 ` Marc Zyngier
2015-10-07 8:17 ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 15:28 ` Wei Huang
2015-10-16 15:28 ` Wei Huang
2015-09-24 22:31 ` [PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-10-16 4:55 ` [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Wei Huang
2015-10-16 4:55 ` Wei Huang
2015-10-16 17:01 ` Christopher Covington
2015-10-16 17:01 ` Christopher Covington
2015-10-21 7:26 ` Shannon Zhao
2015-10-21 7:26 ` Shannon Zhao
2015-10-21 7:26 ` Shannon Zhao
2015-10-26 11:33 ` Christoffer Dall
2015-10-26 11:33 ` Christoffer Dall
2015-10-27 1:15 ` Shannon Zhao
2015-10-27 1:15 ` Shannon Zhao
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