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From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Christopher Covington <cov@codeaurora.org>,
	Wei Huang <wei@redhat.com>,
	Shannon Zhao <shannon.zhao@linaro.org>,
	<kvmarm@lists.cs.columbia.edu>
Cc: <marc.zyngier@arm.com>, <will.deacon@arm.com>,
	<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>
Subject: Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support
Date: Wed, 21 Oct 2015 15:26:46 +0800	[thread overview]
Message-ID: <56273E36.6000704@huawei.com> (raw)
In-Reply-To: <56212D5B.1050207@codeaurora.org>



On 2015/10/17 1:01, Christopher Covington wrote:
> On 10/16/2015 12:55 AM, Wei Huang wrote:
>> > 
>> > 
>> > On 09/24/2015 05:31 PM, Shannon Zhao wrote:
>>> >> This patchset adds guest PMU support for KVM on ARM64. It takes
>>> >> trap-and-emulate approach. When guest wants to monitor one event, it
>>> >> will be trapped by KVM and KVM will call perf_event API to create a perf
>>> >> event and call relevant perf_event APIs to get the count value of event.
>>> >>
>>> >> Use perf to test this patchset in guest. When using "perf list", it
>>> >> shows the list of the hardware events and hardware cache events perf
>>> >> supports. Then use "perf stat -e EVENT" to monitor some event. For
>>> >> example, use "perf stat -e cycles" to count cpu cycles and
>>> >> "perf stat -e cache-misses" to count cache misses.
>>> >>
>>> >> Below are the outputs of "perf stat -r 5 sleep 5" when running in host
>>> >> and guest.
>>> >>
>>> >> Host:
>>> >>  Performance counter stats for 'sleep 5' (5 runs):
>>> >>
>>> >>           0.551428      task-clock (msec)         #    0.000 CPUs utilized            ( +-  0.91% )
>>> >>                  1      context-switches          #    0.002 M/sec
>>> >>                  0      cpu-migrations            #    0.000 K/sec
>>> >>                 48      page-faults               #    0.088 M/sec                    ( +-  1.05% )
>>> >>            1150265      cycles                    #    2.086 GHz                      ( +-  0.92% )
>>> >>    <not supported>      stalled-cycles-frontend
>>> >>    <not supported>      stalled-cycles-backend
>>> >>             526398      instructions              #    0.46  insns per cycle          ( +-  0.89% )
>>> >>    <not supported>      branches
>>> >>               9485      branch-misses             #   17.201 M/sec                    ( +-  2.35% )
>>> >>
>>> >>        5.000831616 seconds time elapsed                                          ( +-  0.00% )
>>> >>
>>> >> Guest:
>>> >>  Performance counter stats for 'sleep 5' (5 runs):
>>> >>
>>> >>           0.730868      task-clock (msec)         #    0.000 CPUs utilized            ( +-  1.13% )
>>> >>                  1      context-switches          #    0.001 M/sec
>>> >>                  0      cpu-migrations            #    0.000 K/sec
>>> >>                 48      page-faults               #    0.065 M/sec                    ( +-  0.42% )
>>> >>            1642982      cycles                    #    2.248 GHz                      ( +-  1.04% )
>>> >>    <not supported>      stalled-cycles-frontend
>>> >>    <not supported>      stalled-cycles-backend
>>> >>             637964      instructions              #    0.39  insns per cycle          ( +-  0.65% )
>>> >>    <not supported>      branches
>>> >>              10377      branch-misses             #   14.198 M/sec                    ( +-  1.09% )
>>> >>
>>> >>        5.001289068 seconds time elapsed                                          ( +-  0.00% )
>>> >>
>> > 
>> > Thanks for V3. One suggestion is to run more perf stress tests, such as
>> > "perf test". So we know the corner cases are covered as much as possible.
> I'd also recommend Vince Weaver's perf_event_tests. It tests things like
> signal-on-counter-overflow that I've never seen anywhere else (other than some
> of my own code).
> 
> https://github.com/deater/perf_event_tests

Ok. Thanks for your suggestion.

-- 
Shannon


WARNING: multiple messages have this Message-ID (diff)
From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Christopher Covington <cov@codeaurora.org>,
	Wei Huang <wei@redhat.com>,
	Shannon Zhao <shannon.zhao@linaro.org>,
	kvmarm@lists.cs.columbia.edu
Cc: marc.zyngier@arm.com, will.deacon@arm.com,
	linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support
Date: Wed, 21 Oct 2015 15:26:46 +0800	[thread overview]
Message-ID: <56273E36.6000704@huawei.com> (raw)
In-Reply-To: <56212D5B.1050207@codeaurora.org>



On 2015/10/17 1:01, Christopher Covington wrote:
> On 10/16/2015 12:55 AM, Wei Huang wrote:
>> > 
>> > 
>> > On 09/24/2015 05:31 PM, Shannon Zhao wrote:
>>> >> This patchset adds guest PMU support for KVM on ARM64. It takes
>>> >> trap-and-emulate approach. When guest wants to monitor one event, it
>>> >> will be trapped by KVM and KVM will call perf_event API to create a perf
>>> >> event and call relevant perf_event APIs to get the count value of event.
>>> >>
>>> >> Use perf to test this patchset in guest. When using "perf list", it
>>> >> shows the list of the hardware events and hardware cache events perf
>>> >> supports. Then use "perf stat -e EVENT" to monitor some event. For
>>> >> example, use "perf stat -e cycles" to count cpu cycles and
>>> >> "perf stat -e cache-misses" to count cache misses.
>>> >>
>>> >> Below are the outputs of "perf stat -r 5 sleep 5" when running in host
>>> >> and guest.
>>> >>
>>> >> Host:
>>> >>  Performance counter stats for 'sleep 5' (5 runs):
>>> >>
>>> >>           0.551428      task-clock (msec)         #    0.000 CPUs utilized            ( +-  0.91% )
>>> >>                  1      context-switches          #    0.002 M/sec
>>> >>                  0      cpu-migrations            #    0.000 K/sec
>>> >>                 48      page-faults               #    0.088 M/sec                    ( +-  1.05% )
>>> >>            1150265      cycles                    #    2.086 GHz                      ( +-  0.92% )
>>> >>    <not supported>      stalled-cycles-frontend
>>> >>    <not supported>      stalled-cycles-backend
>>> >>             526398      instructions              #    0.46  insns per cycle          ( +-  0.89% )
>>> >>    <not supported>      branches
>>> >>               9485      branch-misses             #   17.201 M/sec                    ( +-  2.35% )
>>> >>
>>> >>        5.000831616 seconds time elapsed                                          ( +-  0.00% )
>>> >>
>>> >> Guest:
>>> >>  Performance counter stats for 'sleep 5' (5 runs):
>>> >>
>>> >>           0.730868      task-clock (msec)         #    0.000 CPUs utilized            ( +-  1.13% )
>>> >>                  1      context-switches          #    0.001 M/sec
>>> >>                  0      cpu-migrations            #    0.000 K/sec
>>> >>                 48      page-faults               #    0.065 M/sec                    ( +-  0.42% )
>>> >>            1642982      cycles                    #    2.248 GHz                      ( +-  1.04% )
>>> >>    <not supported>      stalled-cycles-frontend
>>> >>    <not supported>      stalled-cycles-backend
>>> >>             637964      instructions              #    0.39  insns per cycle          ( +-  0.65% )
>>> >>    <not supported>      branches
>>> >>              10377      branch-misses             #   14.198 M/sec                    ( +-  1.09% )
>>> >>
>>> >>        5.001289068 seconds time elapsed                                          ( +-  0.00% )
>>> >>
>> > 
>> > Thanks for V3. One suggestion is to run more perf stress tests, such as
>> > "perf test". So we know the corner cases are covered as much as possible.
> I'd also recommend Vince Weaver's perf_event_tests. It tests things like
> signal-on-counter-overflow that I've never seen anywhere else (other than some
> of my own code).
> 
> https://github.com/deater/perf_event_tests

Ok. Thanks for your suggestion.

-- 
Shannon


WARNING: multiple messages have this Message-ID (diff)
From: zhaoshenglong@huawei.com (Shannon Zhao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 00/20] KVM: ARM64: Add guest PMU support
Date: Wed, 21 Oct 2015 15:26:46 +0800	[thread overview]
Message-ID: <56273E36.6000704@huawei.com> (raw)
In-Reply-To: <56212D5B.1050207@codeaurora.org>



On 2015/10/17 1:01, Christopher Covington wrote:
> On 10/16/2015 12:55 AM, Wei Huang wrote:
>> > 
>> > 
>> > On 09/24/2015 05:31 PM, Shannon Zhao wrote:
>>> >> This patchset adds guest PMU support for KVM on ARM64. It takes
>>> >> trap-and-emulate approach. When guest wants to monitor one event, it
>>> >> will be trapped by KVM and KVM will call perf_event API to create a perf
>>> >> event and call relevant perf_event APIs to get the count value of event.
>>> >>
>>> >> Use perf to test this patchset in guest. When using "perf list", it
>>> >> shows the list of the hardware events and hardware cache events perf
>>> >> supports. Then use "perf stat -e EVENT" to monitor some event. For
>>> >> example, use "perf stat -e cycles" to count cpu cycles and
>>> >> "perf stat -e cache-misses" to count cache misses.
>>> >>
>>> >> Below are the outputs of "perf stat -r 5 sleep 5" when running in host
>>> >> and guest.
>>> >>
>>> >> Host:
>>> >>  Performance counter stats for 'sleep 5' (5 runs):
>>> >>
>>> >>           0.551428      task-clock (msec)         #    0.000 CPUs utilized            ( +-  0.91% )
>>> >>                  1      context-switches          #    0.002 M/sec
>>> >>                  0      cpu-migrations            #    0.000 K/sec
>>> >>                 48      page-faults               #    0.088 M/sec                    ( +-  1.05% )
>>> >>            1150265      cycles                    #    2.086 GHz                      ( +-  0.92% )
>>> >>    <not supported>      stalled-cycles-frontend
>>> >>    <not supported>      stalled-cycles-backend
>>> >>             526398      instructions              #    0.46  insns per cycle          ( +-  0.89% )
>>> >>    <not supported>      branches
>>> >>               9485      branch-misses             #   17.201 M/sec                    ( +-  2.35% )
>>> >>
>>> >>        5.000831616 seconds time elapsed                                          ( +-  0.00% )
>>> >>
>>> >> Guest:
>>> >>  Performance counter stats for 'sleep 5' (5 runs):
>>> >>
>>> >>           0.730868      task-clock (msec)         #    0.000 CPUs utilized            ( +-  1.13% )
>>> >>                  1      context-switches          #    0.001 M/sec
>>> >>                  0      cpu-migrations            #    0.000 K/sec
>>> >>                 48      page-faults               #    0.065 M/sec                    ( +-  0.42% )
>>> >>            1642982      cycles                    #    2.248 GHz                      ( +-  1.04% )
>>> >>    <not supported>      stalled-cycles-frontend
>>> >>    <not supported>      stalled-cycles-backend
>>> >>             637964      instructions              #    0.39  insns per cycle          ( +-  0.65% )
>>> >>    <not supported>      branches
>>> >>              10377      branch-misses             #   14.198 M/sec                    ( +-  1.09% )
>>> >>
>>> >>        5.001289068 seconds time elapsed                                          ( +-  0.00% )
>>> >>
>> > 
>> > Thanks for V3. One suggestion is to run more perf stress tests, such as
>> > "perf test". So we know the corner cases are covered as much as possible.
> I'd also recommend Vince Weaver's perf_event_tests. It tests things like
> signal-on-counter-overflow that I've never seen anywhere else (other than some
> of my own code).
> 
> https://github.com/deater/perf_event_tests

Ok. Thanks for your suggestion.

-- 
Shannon

  reply	other threads:[~2015-10-21  7:30 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-24 22:31 [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-09-24 22:31 ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-07  8:25   ` Marc Zyngier
2015-10-07  8:25     ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-16  5:35   ` Wei Huang
2015-10-16  5:35     ` Wei Huang
2015-10-21  6:27     ` Shannon Zhao
2015-10-21  6:27       ` Shannon Zhao
2015-10-21  6:27       ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-16  6:08   ` Wei Huang
2015-10-16  6:08     ` Wei Huang
2015-10-21  6:32     ` Shannon Zhao
2015-10-21  6:32       ` Shannon Zhao
2015-10-21  6:32       ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-16 15:06   ` Wei Huang
2015-10-16 15:06     ` Wei Huang
2015-10-21  6:48     ` Shannon Zhao
2015-10-21  6:48       ` Shannon Zhao
2015-10-21  6:48       ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-16 15:25   ` Wei Huang
2015-10-16 15:25     ` Wei Huang
2015-10-21  7:02     ` Shannon Zhao
2015-10-21  7:02       ` Shannon Zhao
2015-10-21  7:02       ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-07  8:17   ` Marc Zyngier
2015-10-07  8:17     ` Marc Zyngier
2015-09-24 22:31 ` [PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-16 15:28   ` Wei Huang
2015-10-16 15:28     ` Wei Huang
2015-09-24 22:31 ` [PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-09-24 22:31 ` [PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-09-24 22:31   ` Shannon Zhao
2015-10-16  4:55 ` [PATCH v3 00/20] KVM: ARM64: Add guest PMU support Wei Huang
2015-10-16  4:55   ` Wei Huang
2015-10-16 17:01   ` Christopher Covington
2015-10-16 17:01     ` Christopher Covington
2015-10-21  7:26     ` Shannon Zhao [this message]
2015-10-21  7:26       ` Shannon Zhao
2015-10-21  7:26       ` Shannon Zhao
2015-10-26 11:33 ` Christoffer Dall
2015-10-26 11:33   ` Christoffer Dall
2015-10-27  1:15   ` Shannon Zhao
2015-10-27  1:15     ` Shannon Zhao

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