From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
zhengxunli@mxic.com.tw
Subject: [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index
Date: Tue, 5 Jul 2022 17:11:34 +0800 [thread overview]
Message-ID: <1657012303-6464-2-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
The fspi dynamic lut use the last lut for all IPS operations, the
imx8ulp only supports 15 luts, so change the last lut index from
31 to 15.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index b2cd8e06f374..10e71e55d21a 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -65,9 +65,9 @@
/*
* The driver only uses one single LUT entry, that is updated on
* each call of exec_op(). Index 0 is preset at boot with a basic
- * read operation, so let's use the last entry (31).
+ * read operation, so let's use the last entry (15).
*/
-#define SEQID_LUT 31
+#define SEQID_LUT 15
/* Registers used by the driver */
#define FSPI_MCR0 0x00
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
zhengxunli@mxic.com.tw
Subject: [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index
Date: Tue, 5 Jul 2022 17:11:34 +0800 [thread overview]
Message-ID: <1657012303-6464-2-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
The fspi dynamic lut use the last lut for all IPS operations, the
imx8ulp only supports 15 luts, so change the last lut index from
31 to 15.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index b2cd8e06f374..10e71e55d21a 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -65,9 +65,9 @@
/*
* The driver only uses one single LUT entry, that is updated on
* each call of exec_op(). Index 0 is preset at boot with a basic
- * read operation, so let's use the last entry (31).
+ * read operation, so let's use the last entry (15).
*/
-#define SEQID_LUT 31
+#define SEQID_LUT 15
/* Registers used by the driver */
#define FSPI_MCR0 0x00
--
2.25.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
zhengxunli@mxic.com.tw
Subject: [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index
Date: Tue, 5 Jul 2022 17:11:34 +0800 [thread overview]
Message-ID: <1657012303-6464-2-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
The fspi dynamic lut use the last lut for all IPS operations, the
imx8ulp only supports 15 luts, so change the last lut index from
31 to 15.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index b2cd8e06f374..10e71e55d21a 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -65,9 +65,9 @@
/*
* The driver only uses one single LUT entry, that is updated on
* each call of exec_op(). Index 0 is preset at boot with a basic
- * read operation, so let's use the last entry (31).
+ * read operation, so let's use the last entry (15).
*/
-#define SEQID_LUT 31
+#define SEQID_LUT 15
/* Registers used by the driver */
#define FSPI_MCR0 0x00
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-07-05 9:26 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-05 9:11 [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen [this message]
2022-07-05 9:11 ` [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 03/11] spi: spi-nxp-fspi: add DTR mode support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 04/11] spi: spi-nxp-fspi: add function to select sample clock source for flash reading haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-06 21:02 ` Michael Walle
2022-07-06 21:02 ` Michael Walle
2022-07-06 21:02 ` Michael Walle
2022-07-05 9:11 ` [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 13:50 ` Michael Walle
2022-07-05 13:50 ` Michael Walle
2022-07-05 13:50 ` Michael Walle
2022-07-05 9:11 ` [PATCH 06/11] spi: spi-nxp-fspi: enable octal ddr for iMX8QM/QXP/DXL haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property nxp,fspi-dll-slvdly haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:48 ` Krzysztof Kozlowski
2022-07-05 9:48 ` Krzysztof Kozlowski
2022-07-05 9:48 ` Krzysztof Kozlowski
2022-07-05 10:28 ` Bough Chen
2022-07-05 10:28 ` Bough Chen
2022-07-05 10:28 ` Bough Chen
2022-07-05 10:36 ` Krzysztof Kozlowski
2022-07-05 10:36 ` Krzysztof Kozlowski
2022-07-05 10:36 ` Krzysztof Kozlowski
2022-07-05 13:19 ` Han Xu
2022-07-05 13:19 ` Han Xu
2022-07-05 13:19 ` Han Xu
2022-07-05 13:29 ` Krzysztof Kozlowski
2022-07-05 13:29 ` Krzysztof Kozlowski
2022-07-05 13:29 ` Krzysztof Kozlowski
2022-07-05 14:00 ` Han Xu
2022-07-05 14:00 ` Han Xu
2022-07-05 14:00 ` Han Xu
2022-07-05 14:03 ` Krzysztof Kozlowski
2022-07-05 14:03 ` Krzysztof Kozlowski
2022-07-05 14:03 ` Krzysztof Kozlowski
2022-07-05 14:31 ` Han Xu
2022-07-05 14:31 ` Han Xu
2022-07-05 14:31 ` Han Xu
2022-07-05 14:06 ` Michael Walle
2022-07-05 14:06 ` Michael Walle
2022-07-05 14:06 ` Michael Walle
2022-07-05 14:12 ` Krzysztof Kozlowski
2022-07-05 14:12 ` Krzysztof Kozlowski
2022-07-05 14:12 ` Krzysztof Kozlowski
2022-07-05 14:52 ` Han Xu
2022-07-05 14:52 ` Han Xu
2022-07-05 14:52 ` Han Xu
2022-07-05 14:58 ` Michael Walle
2022-07-05 14:58 ` Michael Walle
2022-07-05 14:58 ` Michael Walle
2022-07-05 15:07 ` Mark Brown
2022-07-05 15:07 ` Mark Brown
2022-07-05 15:07 ` Mark Brown
2022-07-05 15:38 ` Krzysztof Kozlowski
2022-07-05 15:38 ` Krzysztof Kozlowski
2022-07-05 15:38 ` Krzysztof Kozlowski
2022-07-05 15:50 ` Han Xu
2022-07-05 15:50 ` Han Xu
2022-07-05 15:50 ` Han Xu
2022-07-06 16:11 ` Rob Herring
2022-07-06 16:11 ` Rob Herring
2022-07-06 16:11 ` Rob Herring
2022-07-06 20:59 ` Michael Walle
2022-07-06 20:59 ` Michael Walle
2022-07-06 20:59 ` Michael Walle
2022-07-05 9:11 ` [PATCH 08/11] mtd: spi-nor: macronix: add support for Macronix octaflash haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-18 6:57 ` Michael Walle
2022-07-18 6:57 ` Michael Walle
2022-07-18 6:57 ` Michael Walle
2022-07-05 9:11 ` [PATCH 10/11] arm64: dts: imx8ulp: add flexspi support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 11/11] arm64: dts: imx8qm/imx8qxp: " haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 14:01 ` [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi Michael Walle
2022-07-05 14:01 ` Michael Walle
2022-07-05 14:01 ` Michael Walle
2022-07-05 23:06 ` Han Xu
2022-07-05 23:06 ` Han Xu
2022-07-05 23:06 ` Han Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1657012303-6464-2-git-send-email-haibo.chen@nxp.com \
--to=haibo.chen@nxp.com \
--cc=ashish.kumar@nxp.com \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=han.xu@nxp.com \
--cc=kernel@pengutronix.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=michael@walle.cc \
--cc=miquel.raynal@bootlin.com \
--cc=p.yadav@ti.com \
--cc=richard@nod.at \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
--cc=singh.kuldeep87k@gmail.com \
--cc=tudor.ambarus@microchip.com \
--cc=vigneshr@ti.com \
--cc=yogeshgaur.83@gmail.com \
--cc=zhengxunli@mxic.com.tw \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.