From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
zhengxunli@mxic.com.tw
Subject: [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support
Date: Tue, 5 Jul 2022 17:11:37 +0800 [thread overview]
Message-ID: <1657012303-6464-5-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
Not all platform currently supports octal DTR mode. lx2160a do not
implement DQS, this causes flash probe failure and therefore, provide
an option of quirk FSPI_QUIRK_DISABLE_DTR for platforms not support
DTR mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 34679dc0e1ad..61cf1b82c0d7 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -325,6 +325,9 @@
/* Access flash memory using IP bus only */
#define FSPI_QUIRK_USE_IP_ONLY BIT(0)
+/* Disable DTR */
+#define FSPI_QUIRK_DISABLE_DTR BIT(1)
+
struct nxp_fspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
@@ -337,7 +340,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
- .quirks = 0,
+ .quirks = FSPI_QUIRK_DISABLE_DTR,
.little_endian = true, /* little-endian */
};
@@ -1149,10 +1152,14 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
.get_name = nxp_fspi_get_name,
};
-static struct spi_controller_mem_caps nxp_fspi_mem_caps = {
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
.dtr = true,
};
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps_quirks = {
+ .dtr = false,
+};
+
static int nxp_fspi_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
@@ -1257,7 +1264,10 @@ static int nxp_fspi_probe(struct platform_device *pdev)
ctlr->bus_num = -1;
ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
ctlr->mem_ops = &nxp_fspi_mem_ops;
- ctlr->mem_caps = &nxp_fspi_mem_caps;
+ if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR)
+ ctlr->mem_caps = &nxp_fspi_mem_caps_quirks;
+ else
+ ctlr->mem_caps = &nxp_fspi_mem_caps;
nxp_fspi_default_setup(f);
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
zhengxunli@mxic.com.tw
Subject: [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support
Date: Tue, 5 Jul 2022 17:11:37 +0800 [thread overview]
Message-ID: <1657012303-6464-5-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
Not all platform currently supports octal DTR mode. lx2160a do not
implement DQS, this causes flash probe failure and therefore, provide
an option of quirk FSPI_QUIRK_DISABLE_DTR for platforms not support
DTR mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 34679dc0e1ad..61cf1b82c0d7 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -325,6 +325,9 @@
/* Access flash memory using IP bus only */
#define FSPI_QUIRK_USE_IP_ONLY BIT(0)
+/* Disable DTR */
+#define FSPI_QUIRK_DISABLE_DTR BIT(1)
+
struct nxp_fspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
@@ -337,7 +340,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
- .quirks = 0,
+ .quirks = FSPI_QUIRK_DISABLE_DTR,
.little_endian = true, /* little-endian */
};
@@ -1149,10 +1152,14 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
.get_name = nxp_fspi_get_name,
};
-static struct spi_controller_mem_caps nxp_fspi_mem_caps = {
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
.dtr = true,
};
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps_quirks = {
+ .dtr = false,
+};
+
static int nxp_fspi_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
@@ -1257,7 +1264,10 @@ static int nxp_fspi_probe(struct platform_device *pdev)
ctlr->bus_num = -1;
ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
ctlr->mem_ops = &nxp_fspi_mem_ops;
- ctlr->mem_caps = &nxp_fspi_mem_caps;
+ if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR)
+ ctlr->mem_caps = &nxp_fspi_mem_caps_quirks;
+ else
+ ctlr->mem_caps = &nxp_fspi_mem_caps;
nxp_fspi_default_setup(f);
--
2.25.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: haibo.chen@nxp.com
To: ashish.kumar@nxp.com, yogeshgaur.83@gmail.com,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, han.xu@nxp.com,
singh.kuldeep87k@gmail.com, tudor.ambarus@microchip.com,
p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
festevam@gmail.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org, haibo.chen@nxp.com,
zhengxunli@mxic.com.tw
Subject: [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support
Date: Tue, 5 Jul 2022 17:11:37 +0800 [thread overview]
Message-ID: <1657012303-6464-5-git-send-email-haibo.chen@nxp.com> (raw)
In-Reply-To: <1657012303-6464-1-git-send-email-haibo.chen@nxp.com>
From: Haibo Chen <haibo.chen@nxp.com>
Not all platform currently supports octal DTR mode. lx2160a do not
implement DQS, this causes flash probe failure and therefore, provide
an option of quirk FSPI_QUIRK_DISABLE_DTR for platforms not support
DTR mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 34679dc0e1ad..61cf1b82c0d7 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -325,6 +325,9 @@
/* Access flash memory using IP bus only */
#define FSPI_QUIRK_USE_IP_ONLY BIT(0)
+/* Disable DTR */
+#define FSPI_QUIRK_DISABLE_DTR BIT(1)
+
struct nxp_fspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
@@ -337,7 +340,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
.rxfifo = SZ_512, /* (64 * 64 bits) */
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
- .quirks = 0,
+ .quirks = FSPI_QUIRK_DISABLE_DTR,
.little_endian = true, /* little-endian */
};
@@ -1149,10 +1152,14 @@ static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
.get_name = nxp_fspi_get_name,
};
-static struct spi_controller_mem_caps nxp_fspi_mem_caps = {
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps = {
.dtr = true,
};
+static const struct spi_controller_mem_caps nxp_fspi_mem_caps_quirks = {
+ .dtr = false,
+};
+
static int nxp_fspi_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
@@ -1257,7 +1264,10 @@ static int nxp_fspi_probe(struct platform_device *pdev)
ctlr->bus_num = -1;
ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT;
ctlr->mem_ops = &nxp_fspi_mem_ops;
- ctlr->mem_caps = &nxp_fspi_mem_caps;
+ if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR)
+ ctlr->mem_caps = &nxp_fspi_mem_caps_quirks;
+ else
+ ctlr->mem_caps = &nxp_fspi_mem_caps;
nxp_fspi_default_setup(f);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-07-05 9:27 UTC|newest]
Thread overview: 99+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-05 9:11 [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 03/11] spi: spi-nxp-fspi: add DTR mode support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 04/11] spi: spi-nxp-fspi: add function to select sample clock source for flash reading haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-06 21:02 ` Michael Walle
2022-07-06 21:02 ` Michael Walle
2022-07-06 21:02 ` Michael Walle
2022-07-05 9:11 ` haibo.chen [this message]
2022-07-05 9:11 ` [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 13:50 ` Michael Walle
2022-07-05 13:50 ` Michael Walle
2022-07-05 13:50 ` Michael Walle
2022-07-05 9:11 ` [PATCH 06/11] spi: spi-nxp-fspi: enable octal ddr for iMX8QM/QXP/DXL haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property nxp,fspi-dll-slvdly haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:48 ` Krzysztof Kozlowski
2022-07-05 9:48 ` Krzysztof Kozlowski
2022-07-05 9:48 ` Krzysztof Kozlowski
2022-07-05 10:28 ` Bough Chen
2022-07-05 10:28 ` Bough Chen
2022-07-05 10:28 ` Bough Chen
2022-07-05 10:36 ` Krzysztof Kozlowski
2022-07-05 10:36 ` Krzysztof Kozlowski
2022-07-05 10:36 ` Krzysztof Kozlowski
2022-07-05 13:19 ` Han Xu
2022-07-05 13:19 ` Han Xu
2022-07-05 13:19 ` Han Xu
2022-07-05 13:29 ` Krzysztof Kozlowski
2022-07-05 13:29 ` Krzysztof Kozlowski
2022-07-05 13:29 ` Krzysztof Kozlowski
2022-07-05 14:00 ` Han Xu
2022-07-05 14:00 ` Han Xu
2022-07-05 14:00 ` Han Xu
2022-07-05 14:03 ` Krzysztof Kozlowski
2022-07-05 14:03 ` Krzysztof Kozlowski
2022-07-05 14:03 ` Krzysztof Kozlowski
2022-07-05 14:31 ` Han Xu
2022-07-05 14:31 ` Han Xu
2022-07-05 14:31 ` Han Xu
2022-07-05 14:06 ` Michael Walle
2022-07-05 14:06 ` Michael Walle
2022-07-05 14:06 ` Michael Walle
2022-07-05 14:12 ` Krzysztof Kozlowski
2022-07-05 14:12 ` Krzysztof Kozlowski
2022-07-05 14:12 ` Krzysztof Kozlowski
2022-07-05 14:52 ` Han Xu
2022-07-05 14:52 ` Han Xu
2022-07-05 14:52 ` Han Xu
2022-07-05 14:58 ` Michael Walle
2022-07-05 14:58 ` Michael Walle
2022-07-05 14:58 ` Michael Walle
2022-07-05 15:07 ` Mark Brown
2022-07-05 15:07 ` Mark Brown
2022-07-05 15:07 ` Mark Brown
2022-07-05 15:38 ` Krzysztof Kozlowski
2022-07-05 15:38 ` Krzysztof Kozlowski
2022-07-05 15:38 ` Krzysztof Kozlowski
2022-07-05 15:50 ` Han Xu
2022-07-05 15:50 ` Han Xu
2022-07-05 15:50 ` Han Xu
2022-07-06 16:11 ` Rob Herring
2022-07-06 16:11 ` Rob Herring
2022-07-06 16:11 ` Rob Herring
2022-07-06 20:59 ` Michael Walle
2022-07-06 20:59 ` Michael Walle
2022-07-06 20:59 ` Michael Walle
2022-07-05 9:11 ` [PATCH 08/11] mtd: spi-nor: macronix: add support for Macronix octaflash haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-18 6:57 ` Michael Walle
2022-07-18 6:57 ` Michael Walle
2022-07-18 6:57 ` Michael Walle
2022-07-05 9:11 ` [PATCH 10/11] arm64: dts: imx8ulp: add flexspi support haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` [PATCH 11/11] arm64: dts: imx8qm/imx8qxp: " haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 9:11 ` haibo.chen
2022-07-05 14:01 ` [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi Michael Walle
2022-07-05 14:01 ` Michael Walle
2022-07-05 14:01 ` Michael Walle
2022-07-05 23:06 ` Han Xu
2022-07-05 23:06 ` Han Xu
2022-07-05 23:06 ` Han Xu
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