From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>,
David Airlie <airlied@linux.ie>,
Thierry Reding <thierry.reding@gmail.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Chen-Yu Tsai <wens@csie.org>, Hans de Goede <hdegoede@redhat.com>,
Alexander Kaplan <alex@nextthing.co>,
Wynter Woods <wynter@nextthing.co>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Rob Clark <robdclark@gmail.com>, Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock
Date: Fri, 6 Nov 2015 16:11:09 -0800 [thread overview]
Message-ID: <20151107001109.GQ6114@lukather> (raw)
In-Reply-To: <20151030213734.GI19782@codeaurora.org>
[-- Attachment #1: Type: text/plain, Size: 1370 bytes --]
Hi,
On Fri, Oct 30, 2015 at 02:37:34PM -0700, Stephen Boyd wrote:
> On 10/30, Maxime Ripard wrote:
> > The TCON is a controller generating the timings to output videos signals,
> > acting like both a CRTC and an encoder.
> >
> > It has two channels depending on the output, each channel being driven by
> > its own clock (and own clock controller).
> >
> > Add a driver for the channel 1 clock.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Similar comments apply to patches 3 and 4. Was the same code
> copy/pasted two more times and then changed to have different
> values?
I don't really recall, but I probably used the same skeleton yeah.
> Looks like we should consolidate all that stuff into something more
> generic so that we don't have the same problems 3 times.
Does it?
They're both pretty different actually. One is a gate + mux + reset
(patch 3), the other one is actually a combination of two clocks, one
that is the parent of the other, the former being a gate + mux, the
latter a gate + div.
At least at the hardware level, they're very different, and adding
more code to deal with both case would complicate quite a lot the
probe code, for no real reasons.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
David Airlie <airlied-cv59FeDIM0c@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
Laurent Pinchart
<laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
Alexander Kaplan <alex-MflLfwwFzuz+yO7R74ARew@public.gmane.org>,
Wynter Woods <wynter-MflLfwwFzuz+yO7R74ARew@public.gmane.org>,
Boris Brezillon
<boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Thomas Petazzoni
<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Daniel Vetter <daniel-/w4YWyX8dFk@public.gmane.org>
Subject: Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock
Date: Fri, 6 Nov 2015 16:11:09 -0800 [thread overview]
Message-ID: <20151107001109.GQ6114@lukather> (raw)
In-Reply-To: <20151030213734.GI19782-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1360 bytes --]
Hi,
On Fri, Oct 30, 2015 at 02:37:34PM -0700, Stephen Boyd wrote:
> On 10/30, Maxime Ripard wrote:
> > The TCON is a controller generating the timings to output videos signals,
> > acting like both a CRTC and an encoder.
> >
> > It has two channels depending on the output, each channel being driven by
> > its own clock (and own clock controller).
> >
> > Add a driver for the channel 1 clock.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>
> Similar comments apply to patches 3 and 4. Was the same code
> copy/pasted two more times and then changed to have different
> values?
I don't really recall, but I probably used the same skeleton yeah.
> Looks like we should consolidate all that stuff into something more
> generic so that we don't have the same problems 3 times.
Does it?
They're both pretty different actually. One is a gate + mux + reset
(patch 3), the other one is actually a combination of two clocks, one
that is the parent of the other, the former being a gate + mux, the
latter a gate + div.
At least at the hardware level, they're very different, and adding
more code to deal with both case would complicate quite a lot the
probe code, for no real reasons.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock
Date: Fri, 6 Nov 2015 16:11:09 -0800 [thread overview]
Message-ID: <20151107001109.GQ6114@lukather> (raw)
In-Reply-To: <20151030213734.GI19782@codeaurora.org>
Hi,
On Fri, Oct 30, 2015 at 02:37:34PM -0700, Stephen Boyd wrote:
> On 10/30, Maxime Ripard wrote:
> > The TCON is a controller generating the timings to output videos signals,
> > acting like both a CRTC and an encoder.
> >
> > It has two channels depending on the output, each channel being driven by
> > its own clock (and own clock controller).
> >
> > Add a driver for the channel 1 clock.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Similar comments apply to patches 3 and 4. Was the same code
> copy/pasted two more times and then changed to have different
> values?
I don't really recall, but I probably used the same skeleton yeah.
> Looks like we should consolidate all that stuff into something more
> generic so that we don't have the same problems 3 times.
Does it?
They're both pretty different actually. One is a gate + mux + reset
(patch 3), the other one is actually a combination of two clocks, one
that is the parent of the other, the former being a gate + mux, the
latter a gate + div.
At least at the hardware level, they're very different, and adding
more code to deal with both case would complicate quite a lot the
probe code, for no real reasons.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-11-07 0:11 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-30 14:20 [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 21:29 ` Stephen Boyd
2015-10-30 21:29 ` Stephen Boyd
2015-11-06 23:39 ` Maxime Ripard
2015-11-06 23:39 ` Maxime Ripard
2015-11-06 23:39 ` Maxime Ripard
2015-11-12 20:31 ` Stephen Boyd
2015-11-12 20:31 ` Stephen Boyd
2015-11-19 15:42 ` Maxime Ripard
2015-11-19 15:42 ` Maxime Ripard
2015-11-19 15:42 ` Maxime Ripard
2015-10-31 10:28 ` Chen-Yu Tsai
2015-10-31 10:28 ` Chen-Yu Tsai
2015-10-31 10:28 ` Chen-Yu Tsai
2015-11-06 19:42 ` Maxime Ripard
2015-11-06 19:42 ` Maxime Ripard
2015-11-06 19:42 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 02/19] clk: sunxi: Add PLL3 clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 21:32 ` Stephen Boyd
2015-10-30 21:32 ` Stephen Boyd
2015-10-30 21:32 ` Stephen Boyd
2015-10-30 14:20 ` [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-31 10:19 ` Chen-Yu Tsai
2015-10-31 10:19 ` Chen-Yu Tsai
2015-11-06 22:11 ` Maxime Ripard
2015-11-06 22:11 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 21:37 ` Stephen Boyd
2015-10-30 21:37 ` Stephen Boyd
2015-11-07 0:11 ` Maxime Ripard [this message]
2015-11-07 0:11 ` Maxime Ripard
2015-11-07 0:11 ` Maxime Ripard
2015-10-31 9:53 ` Chen-Yu Tsai
2015-10-31 9:53 ` Chen-Yu Tsai
2015-10-31 9:53 ` Chen-Yu Tsai
2015-11-07 0:01 ` Maxime Ripard
2015-11-07 0:01 ` Maxime Ripard
2015-11-07 0:01 ` Maxime Ripard
2015-11-09 3:36 ` Chen-Yu Tsai
2015-11-09 3:36 ` Chen-Yu Tsai
2015-11-09 3:36 ` Chen-Yu Tsai
2015-11-19 15:35 ` Maxime Ripard
2015-11-19 15:35 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 05/19] clk: sunxi: add DRAM gates Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-11-09 4:18 ` Chen-Yu Tsai
2015-11-09 4:18 ` Chen-Yu Tsai
2015-11-09 4:18 ` Chen-Yu Tsai
2015-11-13 8:08 ` Chen-Yu Tsai
2015-11-13 8:08 ` Chen-Yu Tsai
2015-11-13 8:08 ` Chen-Yu Tsai
2015-11-19 15:43 ` Maxime Ripard
2015-11-19 15:43 ` Maxime Ripard
2015-11-19 15:43 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 16:01 ` Chen-Yu Tsai
2015-10-30 16:01 ` Chen-Yu Tsai
2015-10-30 16:01 ` Chen-Yu Tsai
2015-10-30 16:33 ` Hans de Goede
2015-10-30 16:33 ` Hans de Goede
2015-10-30 16:33 ` Hans de Goede
2015-10-30 14:20 ` [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 17:32 ` Thierry Reding
2015-10-30 17:32 ` Thierry Reding
2015-10-30 17:32 ` Thierry Reding
2015-11-07 0:44 ` Maxime Ripard
2015-11-07 0:44 ` Maxime Ripard
2015-11-07 0:44 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 08/19] drm: Add Allwinner A10 Display Engine support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:44 ` Daniel Vetter
2015-10-30 14:44 ` Daniel Vetter
2015-11-11 22:14 ` Maxime Ripard
2015-11-11 22:14 ` Maxime Ripard
2015-11-11 22:14 ` Maxime Ripard
2015-11-16 15:04 ` Daniel Vetter
2015-11-16 15:04 ` Daniel Vetter
2015-11-16 15:04 ` Daniel Vetter
2015-10-30 14:20 ` [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 16:40 ` Rob Herring
2015-10-30 16:40 ` Rob Herring
2015-10-30 16:40 ` Rob Herring
2015-10-30 17:37 ` Thierry Reding
2015-10-30 17:37 ` Thierry Reding
2015-10-30 17:37 ` Thierry Reding
2015-10-30 17:37 ` Thierry Reding
2015-11-01 14:28 ` Rob Herring
2015-11-01 14:28 ` Rob Herring
2015-11-01 14:28 ` Rob Herring
2015-11-01 14:28 ` Rob Herring
2015-11-06 22:32 ` Maxime Ripard
2015-11-06 22:32 ` Maxime Ripard
2015-11-06 22:32 ` Maxime Ripard
2015-11-06 22:32 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 10/19] drm: sun4i: Add RGB output Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-11-02 2:53 ` [linux-sunxi] " Jonathan Liu
2015-11-02 2:53 ` Jonathan Liu
2015-11-02 2:53 ` Jonathan Liu
2015-11-07 0:35 ` [linux-sunxi] " Maxime Ripard
2015-11-07 0:35 ` Maxime Ripard
2015-11-07 0:35 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 12/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 13/19] drm: sun4i: tv: Add NTSC " Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-11-09 4:24 ` Chen-Yu Tsai
2015-11-09 4:24 ` Chen-Yu Tsai
2015-11-09 4:24 ` Chen-Yu Tsai
2015-10-30 14:21 ` [PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 16/19] ARM: sun5i: dt: Add DRAM gates Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 18/19] ARM: sun5i: r8: Add AHB gates " Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 15:20 ` Chen-Yu Tsai
2015-10-30 15:20 ` Chen-Yu Tsai
2015-11-06 19:37 ` Maxime Ripard
2015-11-06 19:37 ` Maxime Ripard
2015-11-06 19:37 ` Maxime Ripard
2015-10-30 14:52 ` [PATCH 00/19] drm: Add Allwinner A10 display engine support Daniel Vetter
2015-10-30 14:52 ` Daniel Vetter
2015-10-30 14:52 ` Daniel Vetter
2015-11-12 5:12 ` Maxime Ripard
2015-11-12 5:12 ` Maxime Ripard
2015-11-12 5:12 ` Maxime Ripard
2015-10-30 15:02 ` Stefan Monnier
2015-11-09 3:43 ` Chen-Yu Tsai
2015-11-09 3:43 ` Chen-Yu Tsai
2015-11-09 3:43 ` Chen-Yu Tsai
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