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From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	David Airlie <airlied@linux.ie>,
	Thierry Reding <thierry.reding@gmail.com>,
	devicetree <devicetree@vger.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	linux-sunxi <linux-sunxi@googlegroups.com>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Chen-Yu Tsai <wens@csie.org>, Hans de Goede <hdegoede@redhat.com>,
	Alexander Kaplan <alex@nextthing.co>,
	Wynter Woods <wynter@nextthing.co>,
	Boris Brezillon <boris.brezillon@free-electrons.com>,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	Rob Clark <robdclark@gmail.com>, Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock
Date: Sat, 31 Oct 2015 18:19:59 +0800	[thread overview]
Message-ID: <CAGb2v66hjH_GpkXpHdpCM+mUv-CgvqxJNFzsoRJ5MWp04b+jew@mail.gmail.com> (raw)
In-Reply-To: <1446214865-3972-4-git-send-email-maxime.ripard@free-electrons.com>

Hi,

On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
>
> Add a driver for the channel 0 clock.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi/Makefile             |   1 +
>  drivers/clk/sunxi/clk-sun4i-tcon-ch0.c | 173 +++++++++++++++++++++++++++++++++
>  2 files changed, 174 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 40c32ffd912c..7821b2b63d58 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-y += clk-mod0.o
>  obj-y += clk-simple-gates.o
>  obj-y += clk-sun4i-display.o
>  obj-y += clk-sun4i-pll3.o
> +obj-y += clk-sun4i-tcon-ch0.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
> new file mode 100644
> index 000000000000..db10cfb94a1d
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
> @@ -0,0 +1,173 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN4I_A10_TCON_CH0_PARENTS     4
> +
> +#define SUN4I_A10_TCON_CH0_GATE_BIT    31
> +#define SUN4I_A10_TCON_CH0_RESET_SHIFT 29

This is sun5i specific.

A10s manual says bit 30 is the LCD reset, while bit 29 is the TV encoder reset.
A13/R8 don't mention TCON_CH0 clock. A10/A20 have no separate TV encoder reset.

Please rename the clock.

ChenYu

> +#define SUN4I_A10_TCON_CH0_MUX_MASK    3
> +#define SUN4I_A10_TCON_CH0_MUX_SHIFT   24
> +
> +struct reset_data {
> +       void __iomem                    *reg;
> +       spinlock_t                      *lock;
> +       struct reset_controller_dev     rcdev;
> +};
> +
> +static DEFINE_SPINLOCK(sun4i_a10_tcon_ch0_lock);
> +

WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock
Date: Sat, 31 Oct 2015 18:19:59 +0800	[thread overview]
Message-ID: <CAGb2v66hjH_GpkXpHdpCM+mUv-CgvqxJNFzsoRJ5MWp04b+jew@mail.gmail.com> (raw)
In-Reply-To: <1446214865-3972-4-git-send-email-maxime.ripard@free-electrons.com>

Hi,

On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
>
> Add a driver for the channel 0 clock.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi/Makefile             |   1 +
>  drivers/clk/sunxi/clk-sun4i-tcon-ch0.c | 173 +++++++++++++++++++++++++++++++++
>  2 files changed, 174 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 40c32ffd912c..7821b2b63d58 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -12,6 +12,7 @@ obj-y += clk-mod0.o
>  obj-y += clk-simple-gates.o
>  obj-y += clk-sun4i-display.o
>  obj-y += clk-sun4i-pll3.o
> +obj-y += clk-sun4i-tcon-ch0.o
>  obj-y += clk-sun8i-mbus.o
>  obj-y += clk-sun9i-core.o
>  obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
> new file mode 100644
> index 000000000000..db10cfb94a1d
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch0.c
> @@ -0,0 +1,173 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN4I_A10_TCON_CH0_PARENTS     4
> +
> +#define SUN4I_A10_TCON_CH0_GATE_BIT    31
> +#define SUN4I_A10_TCON_CH0_RESET_SHIFT 29

This is sun5i specific.

A10s manual says bit 30 is the LCD reset, while bit 29 is the TV encoder reset.
A13/R8 don't mention TCON_CH0 clock. A10/A20 have no separate TV encoder reset.

Please rename the clock.

ChenYu

> +#define SUN4I_A10_TCON_CH0_MUX_MASK    3
> +#define SUN4I_A10_TCON_CH0_MUX_SHIFT   24
> +
> +struct reset_data {
> +       void __iomem                    *reg;
> +       spinlock_t                      *lock;
> +       struct reset_controller_dev     rcdev;
> +};
> +
> +static DEFINE_SPINLOCK(sun4i_a10_tcon_ch0_lock);
> +

  reply	other threads:[~2015-10-31 10:20 UTC|newest]

Thread overview: 167+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-30 14:20 [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 21:29   ` Stephen Boyd
2015-10-30 21:29     ` Stephen Boyd
2015-11-06 23:39     ` Maxime Ripard
2015-11-06 23:39       ` Maxime Ripard
2015-11-06 23:39       ` Maxime Ripard
2015-11-12 20:31       ` Stephen Boyd
2015-11-12 20:31         ` Stephen Boyd
2015-11-19 15:42         ` Maxime Ripard
2015-11-19 15:42           ` Maxime Ripard
2015-11-19 15:42           ` Maxime Ripard
2015-10-31 10:28   ` Chen-Yu Tsai
2015-10-31 10:28     ` Chen-Yu Tsai
2015-10-31 10:28     ` Chen-Yu Tsai
2015-11-06 19:42     ` Maxime Ripard
2015-11-06 19:42       ` Maxime Ripard
2015-11-06 19:42       ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 02/19] clk: sunxi: Add PLL3 clock Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 21:32   ` Stephen Boyd
2015-10-30 21:32     ` Stephen Boyd
2015-10-30 21:32     ` Stephen Boyd
2015-10-30 14:20 ` [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-31 10:19   ` Chen-Yu Tsai [this message]
2015-10-31 10:19     ` Chen-Yu Tsai
2015-11-06 22:11     ` Maxime Ripard
2015-11-06 22:11       ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 21:37   ` Stephen Boyd
2015-10-30 21:37     ` Stephen Boyd
2015-11-07  0:11     ` Maxime Ripard
2015-11-07  0:11       ` Maxime Ripard
2015-11-07  0:11       ` Maxime Ripard
2015-10-31  9:53   ` Chen-Yu Tsai
2015-10-31  9:53     ` Chen-Yu Tsai
2015-10-31  9:53     ` Chen-Yu Tsai
2015-11-07  0:01     ` Maxime Ripard
2015-11-07  0:01       ` Maxime Ripard
2015-11-07  0:01       ` Maxime Ripard
2015-11-09  3:36       ` Chen-Yu Tsai
2015-11-09  3:36         ` Chen-Yu Tsai
2015-11-09  3:36         ` Chen-Yu Tsai
2015-11-19 15:35         ` Maxime Ripard
2015-11-19 15:35           ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 05/19] clk: sunxi: add DRAM gates Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-11-09  4:18   ` Chen-Yu Tsai
2015-11-09  4:18     ` Chen-Yu Tsai
2015-11-09  4:18     ` Chen-Yu Tsai
2015-11-13  8:08     ` Chen-Yu Tsai
2015-11-13  8:08       ` Chen-Yu Tsai
2015-11-13  8:08       ` Chen-Yu Tsai
2015-11-19 15:43       ` Maxime Ripard
2015-11-19 15:43         ` Maxime Ripard
2015-11-19 15:43         ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 16:01   ` Chen-Yu Tsai
2015-10-30 16:01     ` Chen-Yu Tsai
2015-10-30 16:01     ` Chen-Yu Tsai
2015-10-30 16:33     ` Hans de Goede
2015-10-30 16:33       ` Hans de Goede
2015-10-30 16:33       ` Hans de Goede
2015-10-30 14:20 ` [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 17:32   ` Thierry Reding
2015-10-30 17:32     ` Thierry Reding
2015-10-30 17:32     ` Thierry Reding
2015-11-07  0:44     ` Maxime Ripard
2015-11-07  0:44       ` Maxime Ripard
2015-11-07  0:44       ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 08/19] drm: Add Allwinner A10 Display Engine support Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:44   ` Daniel Vetter
2015-10-30 14:44     ` Daniel Vetter
2015-11-11 22:14     ` Maxime Ripard
2015-11-11 22:14       ` Maxime Ripard
2015-11-11 22:14       ` Maxime Ripard
2015-11-16 15:04       ` Daniel Vetter
2015-11-16 15:04         ` Daniel Vetter
2015-11-16 15:04         ` Daniel Vetter
2015-10-30 14:20 ` [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 16:40   ` Rob Herring
2015-10-30 16:40     ` Rob Herring
2015-10-30 16:40     ` Rob Herring
2015-10-30 17:37     ` Thierry Reding
2015-10-30 17:37       ` Thierry Reding
2015-10-30 17:37       ` Thierry Reding
2015-10-30 17:37       ` Thierry Reding
2015-11-01 14:28       ` Rob Herring
2015-11-01 14:28         ` Rob Herring
2015-11-01 14:28         ` Rob Herring
2015-11-01 14:28         ` Rob Herring
2015-11-06 22:32     ` Maxime Ripard
2015-11-06 22:32       ` Maxime Ripard
2015-11-06 22:32       ` Maxime Ripard
2015-11-06 22:32       ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 10/19] drm: sun4i: Add RGB output Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-11-02  2:53   ` [linux-sunxi] " Jonathan Liu
2015-11-02  2:53     ` Jonathan Liu
2015-11-02  2:53     ` Jonathan Liu
2015-11-07  0:35     ` [linux-sunxi] " Maxime Ripard
2015-11-07  0:35       ` Maxime Ripard
2015-11-07  0:35       ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 12/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 13/19] drm: sun4i: tv: Add NTSC " Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:20   ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-11-09  4:24   ` Chen-Yu Tsai
2015-11-09  4:24     ` Chen-Yu Tsai
2015-11-09  4:24     ` Chen-Yu Tsai
2015-10-30 14:21 ` [PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 16/19] ARM: sun5i: dt: Add DRAM gates Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 18/19] ARM: sun5i: r8: Add AHB gates " Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 14:21   ` Maxime Ripard
2015-10-30 15:20   ` Chen-Yu Tsai
2015-10-30 15:20     ` Chen-Yu Tsai
2015-11-06 19:37     ` Maxime Ripard
2015-11-06 19:37       ` Maxime Ripard
2015-11-06 19:37       ` Maxime Ripard
2015-10-30 14:52 ` [PATCH 00/19] drm: Add Allwinner A10 display engine support Daniel Vetter
2015-10-30 14:52   ` Daniel Vetter
2015-10-30 14:52   ` Daniel Vetter
2015-11-12  5:12   ` Maxime Ripard
2015-11-12  5:12     ` Maxime Ripard
2015-11-12  5:12     ` Maxime Ripard
2015-10-30 15:02 ` Stefan Monnier
2015-11-09  3:43 ` Chen-Yu Tsai
2015-11-09  3:43   ` Chen-Yu Tsai
2015-11-09  3:43   ` Chen-Yu Tsai

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