From: Chen-Yu Tsai <wens@csie.org>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>,
Mike Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
David Airlie <airlied@linux.ie>,
Thierry Reding <thierry.reding@gmail.com>,
devicetree <devicetree@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
linux-sunxi <linux-sunxi@googlegroups.com>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Hans de Goede <hdegoede@redhat.com>,
Alexander Kaplan <alex@nextthing.co>,
Wynter Woods <wynter@nextthing.co>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Rob Clark <robdclark@gmail.com>, Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock
Date: Mon, 9 Nov 2015 11:36:15 +0800 [thread overview]
Message-ID: <CAGb2v65MUrBKA=pAC95evdiSBMaewRcnLUhBcqCbx_Pc6Jutnw@mail.gmail.com> (raw)
In-Reply-To: <20151107000139.GP6114@lukather>
On Sat, Nov 7, 2015 at 8:01 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sat, Oct 31, 2015 at 05:53:26PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > The TCON is a controller generating the timings to output videos signals,
>> > acting like both a CRTC and an encoder.
>> >
>> > It has two channels depending on the output, each channel being driven by
>> > its own clock (and own clock controller).
>> >
>> > Add a driver for the channel 1 clock.
>> >
>> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> > ---
>> > drivers/clk/sunxi/Makefile | 1 +
>> > drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | 167 +++++++++++++++++++++++++++++++++
>> > 2 files changed, 168 insertions(+)
>> > create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
>>
>> According to the documents I have, this variant of the TCON clock
>> is specific to sun5i. On sun4i/sun7i, TCON CH1 clock has the same
>> layout as TCON CH0 and the other display clocks.
>
> At least for the A20, it's not true.
>
> Make sure you do not confuse LCD1 CH0 (p79, which is a channel 0
> clock), with LCD0 CH1 (p81, which is a channel 1 clock).
Right. The names are great for confusing the reader. :(
>> > + sclk1_parents[0] = sclk2_name;
>> > + sclk1_parents[1] = sclk2d2_name;
>>
>> Is there any need to expose these 2 clocks via DT using of_clk_add_provider?
>
> No, as far as I'm aware, there's no user external to this clock
> driver.
>
>> Note that these complex clock trees within a clock node breaks the
>> assigned-clock-parents mechanism, as you can no longer specify the output
>> clock's direct parents.
>
> There's no point of changing the parent either. Hardware blocks are
> always connected to the leaf clock (sclk1). We could also model it as
> an extra 1-bit divider, which would simplify a bit the logic though.
Probably not. You still have a gate to handle. It's just moving the
divider from 1 clock to the other. I think the current approach of
modeling it like the hardware is better.
About reparenting, what I meant was if sclk2 is not exposed through
of_clk_add_provider, then we can't do assigned-clocks stuff on it,
like setting a default parent or making each channel use a different
source pll.
What I'm saying is if it is not expected to work with another core
binding, we should probably note it somewhere.
Regards
ChenYu
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
To: Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Mike Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
David Airlie <airlied-cv59FeDIM0c@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
devicetree <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
linux-arm-kernel
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
linux-kernel
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
linux-clk <linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
dri-devel
<dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
linux-sunxi <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>,
Laurent Pinchart
<laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>,
Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
Alexander Kaplan <alex-MflLfwwFzuz+yO7R74ARew@public.gmane.org>,
Wynter Woods <wynter-MflLfwwFzuz+yO7R74ARew@public.gmane.org>,
Boris Brezillon
<boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Thomas Petazzoni
<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Rob Clark <robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Daniel Vetter <daniel-/w4YWyX8dFk@public.gmane.org>
Subject: Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock
Date: Mon, 9 Nov 2015 11:36:15 +0800 [thread overview]
Message-ID: <CAGb2v65MUrBKA=pAC95evdiSBMaewRcnLUhBcqCbx_Pc6Jutnw@mail.gmail.com> (raw)
In-Reply-To: <20151107000139.GP6114@lukather>
On Sat, Nov 7, 2015 at 8:01 AM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Sat, Oct 31, 2015 at 05:53:26PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
>> <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>> > The TCON is a controller generating the timings to output videos signals,
>> > acting like both a CRTC and an encoder.
>> >
>> > It has two channels depending on the output, each channel being driven by
>> > its own clock (and own clock controller).
>> >
>> > Add a driver for the channel 1 clock.
>> >
>> > Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> > ---
>> > drivers/clk/sunxi/Makefile | 1 +
>> > drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | 167 +++++++++++++++++++++++++++++++++
>> > 2 files changed, 168 insertions(+)
>> > create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
>>
>> According to the documents I have, this variant of the TCON clock
>> is specific to sun5i. On sun4i/sun7i, TCON CH1 clock has the same
>> layout as TCON CH0 and the other display clocks.
>
> At least for the A20, it's not true.
>
> Make sure you do not confuse LCD1 CH0 (p79, which is a channel 0
> clock), with LCD0 CH1 (p81, which is a channel 1 clock).
Right. The names are great for confusing the reader. :(
>> > + sclk1_parents[0] = sclk2_name;
>> > + sclk1_parents[1] = sclk2d2_name;
>>
>> Is there any need to expose these 2 clocks via DT using of_clk_add_provider?
>
> No, as far as I'm aware, there's no user external to this clock
> driver.
>
>> Note that these complex clock trees within a clock node breaks the
>> assigned-clock-parents mechanism, as you can no longer specify the output
>> clock's direct parents.
>
> There's no point of changing the parent either. Hardware blocks are
> always connected to the leaf clock (sclk1). We could also model it as
> an extra 1-bit divider, which would simplify a bit the logic though.
Probably not. You still have a gate to handle. It's just moving the
divider from 1 clock to the other. I think the current approach of
modeling it like the hardware is better.
About reparenting, what I meant was if sclk2 is not exposed through
of_clk_add_provider, then we can't do assigned-clocks stuff on it,
like setting a default parent or making each channel use a different
source pll.
What I'm saying is if it is not expected to work with another core
binding, we should probably note it somewhere.
Regards
ChenYu
WARNING: multiple messages have this Message-ID (diff)
From: wens@csie.org (Chen-Yu Tsai)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock
Date: Mon, 9 Nov 2015 11:36:15 +0800 [thread overview]
Message-ID: <CAGb2v65MUrBKA=pAC95evdiSBMaewRcnLUhBcqCbx_Pc6Jutnw@mail.gmail.com> (raw)
In-Reply-To: <20151107000139.GP6114@lukather>
On Sat, Nov 7, 2015 at 8:01 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sat, Oct 31, 2015 at 05:53:26PM +0800, Chen-Yu Tsai wrote:
>> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > The TCON is a controller generating the timings to output videos signals,
>> > acting like both a CRTC and an encoder.
>> >
>> > It has two channels depending on the output, each channel being driven by
>> > its own clock (and own clock controller).
>> >
>> > Add a driver for the channel 1 clock.
>> >
>> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> > ---
>> > drivers/clk/sunxi/Makefile | 1 +
>> > drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | 167 +++++++++++++++++++++++++++++++++
>> > 2 files changed, 168 insertions(+)
>> > create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
>>
>> According to the documents I have, this variant of the TCON clock
>> is specific to sun5i. On sun4i/sun7i, TCON CH1 clock has the same
>> layout as TCON CH0 and the other display clocks.
>
> At least for the A20, it's not true.
>
> Make sure you do not confuse LCD1 CH0 (p79, which is a channel 0
> clock), with LCD0 CH1 (p81, which is a channel 1 clock).
Right. The names are great for confusing the reader. :(
>> > + sclk1_parents[0] = sclk2_name;
>> > + sclk1_parents[1] = sclk2d2_name;
>>
>> Is there any need to expose these 2 clocks via DT using of_clk_add_provider?
>
> No, as far as I'm aware, there's no user external to this clock
> driver.
>
>> Note that these complex clock trees within a clock node breaks the
>> assigned-clock-parents mechanism, as you can no longer specify the output
>> clock's direct parents.
>
> There's no point of changing the parent either. Hardware blocks are
> always connected to the leaf clock (sclk1). We could also model it as
> an extra 1-bit divider, which would simplify a bit the logic though.
Probably not. You still have a gate to handle. It's just moving the
divider from 1 clock to the other. I think the current approach of
modeling it like the hardware is better.
About reparenting, what I meant was if sclk2 is not exposed through
of_clk_add_provider, then we can't do assigned-clocks stuff on it,
like setting a default parent or making each channel use a different
source pll.
What I'm saying is if it is not expected to work with another core
binding, we should probably note it somewhere.
Regards
ChenYu
next prev parent reply other threads:[~2015-11-09 3:36 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-30 14:20 [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 21:29 ` Stephen Boyd
2015-10-30 21:29 ` Stephen Boyd
2015-11-06 23:39 ` Maxime Ripard
2015-11-06 23:39 ` Maxime Ripard
2015-11-06 23:39 ` Maxime Ripard
2015-11-12 20:31 ` Stephen Boyd
2015-11-12 20:31 ` Stephen Boyd
2015-11-19 15:42 ` Maxime Ripard
2015-11-19 15:42 ` Maxime Ripard
2015-11-19 15:42 ` Maxime Ripard
2015-10-31 10:28 ` Chen-Yu Tsai
2015-10-31 10:28 ` Chen-Yu Tsai
2015-10-31 10:28 ` Chen-Yu Tsai
2015-11-06 19:42 ` Maxime Ripard
2015-11-06 19:42 ` Maxime Ripard
2015-11-06 19:42 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 02/19] clk: sunxi: Add PLL3 clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 21:32 ` Stephen Boyd
2015-10-30 21:32 ` Stephen Boyd
2015-10-30 21:32 ` Stephen Boyd
2015-10-30 14:20 ` [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-31 10:19 ` Chen-Yu Tsai
2015-10-31 10:19 ` Chen-Yu Tsai
2015-11-06 22:11 ` Maxime Ripard
2015-11-06 22:11 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 21:37 ` Stephen Boyd
2015-10-30 21:37 ` Stephen Boyd
2015-11-07 0:11 ` Maxime Ripard
2015-11-07 0:11 ` Maxime Ripard
2015-11-07 0:11 ` Maxime Ripard
2015-10-31 9:53 ` Chen-Yu Tsai
2015-10-31 9:53 ` Chen-Yu Tsai
2015-10-31 9:53 ` Chen-Yu Tsai
2015-11-07 0:01 ` Maxime Ripard
2015-11-07 0:01 ` Maxime Ripard
2015-11-07 0:01 ` Maxime Ripard
2015-11-09 3:36 ` Chen-Yu Tsai [this message]
2015-11-09 3:36 ` Chen-Yu Tsai
2015-11-09 3:36 ` Chen-Yu Tsai
2015-11-19 15:35 ` Maxime Ripard
2015-11-19 15:35 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 05/19] clk: sunxi: add DRAM gates Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-11-09 4:18 ` Chen-Yu Tsai
2015-11-09 4:18 ` Chen-Yu Tsai
2015-11-09 4:18 ` Chen-Yu Tsai
2015-11-13 8:08 ` Chen-Yu Tsai
2015-11-13 8:08 ` Chen-Yu Tsai
2015-11-13 8:08 ` Chen-Yu Tsai
2015-11-19 15:43 ` Maxime Ripard
2015-11-19 15:43 ` Maxime Ripard
2015-11-19 15:43 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 16:01 ` Chen-Yu Tsai
2015-10-30 16:01 ` Chen-Yu Tsai
2015-10-30 16:01 ` Chen-Yu Tsai
2015-10-30 16:33 ` Hans de Goede
2015-10-30 16:33 ` Hans de Goede
2015-10-30 16:33 ` Hans de Goede
2015-10-30 14:20 ` [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 17:32 ` Thierry Reding
2015-10-30 17:32 ` Thierry Reding
2015-10-30 17:32 ` Thierry Reding
2015-11-07 0:44 ` Maxime Ripard
2015-11-07 0:44 ` Maxime Ripard
2015-11-07 0:44 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 08/19] drm: Add Allwinner A10 Display Engine support Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:44 ` Daniel Vetter
2015-10-30 14:44 ` Daniel Vetter
2015-11-11 22:14 ` Maxime Ripard
2015-11-11 22:14 ` Maxime Ripard
2015-11-11 22:14 ` Maxime Ripard
2015-11-16 15:04 ` Daniel Vetter
2015-11-16 15:04 ` Daniel Vetter
2015-11-16 15:04 ` Daniel Vetter
2015-10-30 14:20 ` [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 16:40 ` Rob Herring
2015-10-30 16:40 ` Rob Herring
2015-10-30 16:40 ` Rob Herring
2015-10-30 17:37 ` Thierry Reding
2015-10-30 17:37 ` Thierry Reding
2015-10-30 17:37 ` Thierry Reding
2015-10-30 17:37 ` Thierry Reding
2015-11-01 14:28 ` Rob Herring
2015-11-01 14:28 ` Rob Herring
2015-11-01 14:28 ` Rob Herring
2015-11-01 14:28 ` Rob Herring
2015-11-06 22:32 ` Maxime Ripard
2015-11-06 22:32 ` Maxime Ripard
2015-11-06 22:32 ` Maxime Ripard
2015-11-06 22:32 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 10/19] drm: sun4i: Add RGB output Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-11-02 2:53 ` [linux-sunxi] " Jonathan Liu
2015-11-02 2:53 ` Jonathan Liu
2015-11-02 2:53 ` Jonathan Liu
2015-11-07 0:35 ` [linux-sunxi] " Maxime Ripard
2015-11-07 0:35 ` Maxime Ripard
2015-11-07 0:35 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 12/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` [PATCH 13/19] drm: sun4i: tv: Add NTSC " Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:20 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-11-09 4:24 ` Chen-Yu Tsai
2015-11-09 4:24 ` Chen-Yu Tsai
2015-11-09 4:24 ` Chen-Yu Tsai
2015-10-30 14:21 ` [PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 16/19] ARM: sun5i: dt: Add DRAM gates Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 18/19] ARM: sun5i: r8: Add AHB gates " Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 14:21 ` Maxime Ripard
2015-10-30 15:20 ` Chen-Yu Tsai
2015-10-30 15:20 ` Chen-Yu Tsai
2015-11-06 19:37 ` Maxime Ripard
2015-11-06 19:37 ` Maxime Ripard
2015-11-06 19:37 ` Maxime Ripard
2015-10-30 14:52 ` [PATCH 00/19] drm: Add Allwinner A10 display engine support Daniel Vetter
2015-10-30 14:52 ` Daniel Vetter
2015-10-30 14:52 ` Daniel Vetter
2015-11-12 5:12 ` Maxime Ripard
2015-11-12 5:12 ` Maxime Ripard
2015-11-12 5:12 ` Maxime Ripard
2015-10-30 15:02 ` Stefan Monnier
2015-11-09 3:43 ` Chen-Yu Tsai
2015-11-09 3:43 ` Chen-Yu Tsai
2015-11-09 3:43 ` Chen-Yu Tsai
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