From: Maxime Ripard <maxime.ripard@free-electrons.com> To: Chen-Yu Tsai <wens@csie.org> Cc: Mike Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, David Airlie <airlied@linux.ie>, Thierry Reding <thierry.reding@gmail.com>, devicetree <devicetree@vger.kernel.org>, linux-arm-kernel <linux-arm-kernel@lists.infradead.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, dri-devel <dri-devel@lists.freedesktop.org>, linux-sunxi <linux-sunxi@googlegroups.com>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Hans de Goede <hdegoede@redhat.com>, Alexander Kaplan <alex@nextthing.co>, Wynter Woods <wynter@nextthing.co>, Boris Brezillon <boris.brezillon@free-electrons.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Rob Clark <robdclark@gmail.com>, Daniel Vetter <daniel@ffwll.ch> Subject: Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Date: Thu, 19 Nov 2015 16:35:16 +0100 [thread overview] Message-ID: <20151119153516.GP32142@lukather> (raw) In-Reply-To: <CAGb2v65MUrBKA=pAC95evdiSBMaewRcnLUhBcqCbx_Pc6Jutnw@mail.gmail.com> [-- Attachment #1: Type: text/plain, Size: 1809 bytes --] On Mon, Nov 09, 2015 at 11:36:15AM +0800, Chen-Yu Tsai wrote: > >> > + sclk1_parents[0] = sclk2_name; > >> > + sclk1_parents[1] = sclk2d2_name; > >> > >> Is there any need to expose these 2 clocks via DT using of_clk_add_provider? > > > > No, as far as I'm aware, there's no user external to this clock > > driver. > > > >> Note that these complex clock trees within a clock node breaks the > >> assigned-clock-parents mechanism, as you can no longer specify the output > >> clock's direct parents. > > > > There's no point of changing the parent either. Hardware blocks are > > always connected to the leaf clock (sclk1). We could also model it as > > an extra 1-bit divider, which would simplify a bit the logic though. > > Probably not. You still have a gate to handle. It's just moving the > divider from 1 clock to the other. I think the current approach of > modeling it like the hardware is better. Not really if you model it using sclk2 being a mux + gate, and sclk1 being a divider + gate. It works great using the composite clocks. > About reparenting, what I meant was if sclk2 is not exposed through > of_clk_add_provider, then we can't do assigned-clocks stuff on it, > like setting a default parent or making each channel use a different > source pll. And we don't really want to. Using the divider allow us to simply set the rate of sclk1, and the mux / divider will do the rest. Since only sclk1 is exposed to the rest of the system, we do not really care about the rate of sclk2 anyway. > What I'm saying is if it is not expected to work with another core > binding, we should probably note it somewhere. Indeed. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [-- Attachment #2: Digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --]
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From: maxime.ripard@free-electrons.com (Maxime Ripard) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Date: Thu, 19 Nov 2015 16:35:16 +0100 [thread overview] Message-ID: <20151119153516.GP32142@lukather> (raw) In-Reply-To: <CAGb2v65MUrBKA=pAC95evdiSBMaewRcnLUhBcqCbx_Pc6Jutnw@mail.gmail.com> On Mon, Nov 09, 2015 at 11:36:15AM +0800, Chen-Yu Tsai wrote: > >> > + sclk1_parents[0] = sclk2_name; > >> > + sclk1_parents[1] = sclk2d2_name; > >> > >> Is there any need to expose these 2 clocks via DT using of_clk_add_provider? > > > > No, as far as I'm aware, there's no user external to this clock > > driver. > > > >> Note that these complex clock trees within a clock node breaks the > >> assigned-clock-parents mechanism, as you can no longer specify the output > >> clock's direct parents. > > > > There's no point of changing the parent either. Hardware blocks are > > always connected to the leaf clock (sclk1). We could also model it as > > an extra 1-bit divider, which would simplify a bit the logic though. > > Probably not. You still have a gate to handle. It's just moving the > divider from 1 clock to the other. I think the current approach of > modeling it like the hardware is better. Not really if you model it using sclk2 being a mux + gate, and sclk1 being a divider + gate. It works great using the composite clocks. > About reparenting, what I meant was if sclk2 is not exposed through > of_clk_add_provider, then we can't do assigned-clocks stuff on it, > like setting a default parent or making each channel use a different > source pll. And we don't really want to. Using the divider allow us to simply set the rate of sclk1, and the mux / divider will do the rest. Since only sclk1 is exposed to the rest of the system, we do not really care about the rate of sclk2 anyway. > What I'm saying is if it is not expected to work with another core > binding, we should probably note it somewhere. Indeed. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151119/a439163e/attachment.sig>
next prev parent reply other threads:[~2015-11-19 15:35 UTC|newest] Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-10-30 14:20 [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 21:29 ` Stephen Boyd 2015-10-30 21:29 ` Stephen Boyd 2015-11-06 23:39 ` Maxime Ripard 2015-11-06 23:39 ` Maxime Ripard 2015-11-06 23:39 ` Maxime Ripard 2015-11-12 20:31 ` Stephen Boyd 2015-11-12 20:31 ` Stephen Boyd 2015-11-19 15:42 ` Maxime Ripard 2015-11-19 15:42 ` Maxime Ripard 2015-11-19 15:42 ` Maxime Ripard 2015-10-31 10:28 ` Chen-Yu Tsai 2015-10-31 10:28 ` Chen-Yu Tsai 2015-10-31 10:28 ` Chen-Yu Tsai 2015-11-06 19:42 ` Maxime Ripard 2015-11-06 19:42 ` Maxime Ripard 2015-11-06 19:42 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 02/19] clk: sunxi: Add PLL3 clock Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 21:32 ` Stephen Boyd 2015-10-30 21:32 ` Stephen Boyd 2015-10-30 21:32 ` Stephen Boyd 2015-10-30 14:20 ` [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-31 10:19 ` Chen-Yu Tsai 2015-10-31 10:19 ` Chen-Yu Tsai 2015-11-06 22:11 ` Maxime Ripard 2015-11-06 22:11 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 21:37 ` Stephen Boyd 2015-10-30 21:37 ` Stephen Boyd 2015-11-07 0:11 ` Maxime Ripard 2015-11-07 0:11 ` Maxime Ripard 2015-11-07 0:11 ` Maxime Ripard 2015-10-31 9:53 ` Chen-Yu Tsai 2015-10-31 9:53 ` Chen-Yu Tsai 2015-10-31 9:53 ` Chen-Yu Tsai 2015-11-07 0:01 ` Maxime Ripard 2015-11-07 0:01 ` Maxime Ripard 2015-11-07 0:01 ` Maxime Ripard 2015-11-09 3:36 ` Chen-Yu Tsai 2015-11-09 3:36 ` Chen-Yu Tsai 2015-11-09 3:36 ` Chen-Yu Tsai 2015-11-19 15:35 ` Maxime Ripard [this message] 2015-11-19 15:35 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 05/19] clk: sunxi: add DRAM gates Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-11-09 4:18 ` Chen-Yu Tsai 2015-11-09 4:18 ` Chen-Yu Tsai 2015-11-09 4:18 ` Chen-Yu Tsai 2015-11-13 8:08 ` Chen-Yu Tsai 2015-11-13 8:08 ` Chen-Yu Tsai 2015-11-13 8:08 ` Chen-Yu Tsai 2015-11-19 15:43 ` Maxime Ripard 2015-11-19 15:43 ` Maxime Ripard 2015-11-19 15:43 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 16:01 ` Chen-Yu Tsai 2015-10-30 16:01 ` Chen-Yu Tsai 2015-10-30 16:01 ` Chen-Yu Tsai 2015-10-30 16:33 ` Hans de Goede 2015-10-30 16:33 ` Hans de Goede 2015-10-30 16:33 ` Hans de Goede 2015-10-30 14:20 ` [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 17:32 ` Thierry Reding 2015-10-30 17:32 ` Thierry Reding 2015-10-30 17:32 ` Thierry Reding 2015-11-07 0:44 ` Maxime Ripard 2015-11-07 0:44 ` Maxime Ripard 2015-11-07 0:44 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 08/19] drm: Add Allwinner A10 Display Engine support Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:44 ` Daniel Vetter 2015-10-30 14:44 ` Daniel Vetter 2015-11-11 22:14 ` Maxime Ripard 2015-11-11 22:14 ` Maxime Ripard 2015-11-11 22:14 ` Maxime Ripard 2015-11-16 15:04 ` Daniel Vetter 2015-11-16 15:04 ` Daniel Vetter 2015-11-16 15:04 ` Daniel Vetter 2015-10-30 14:20 ` [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 16:40 ` Rob Herring 2015-10-30 16:40 ` Rob Herring 2015-10-30 16:40 ` Rob Herring 2015-10-30 17:37 ` Thierry Reding 2015-10-30 17:37 ` Thierry Reding 2015-10-30 17:37 ` Thierry Reding 2015-10-30 17:37 ` Thierry Reding 2015-11-01 14:28 ` Rob Herring 2015-11-01 14:28 ` Rob Herring 2015-11-01 14:28 ` Rob Herring 2015-11-01 14:28 ` Rob Herring 2015-11-06 22:32 ` Maxime Ripard 2015-11-06 22:32 ` Maxime Ripard 2015-11-06 22:32 ` Maxime Ripard 2015-11-06 22:32 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 10/19] drm: sun4i: Add RGB output Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-11-02 2:53 ` [linux-sunxi] " Jonathan Liu 2015-11-02 2:53 ` Jonathan Liu 2015-11-02 2:53 ` Jonathan Liu 2015-11-07 0:35 ` [linux-sunxi] " Maxime Ripard 2015-11-07 0:35 ` Maxime Ripard 2015-11-07 0:35 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 12/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` [PATCH 13/19] drm: sun4i: tv: Add NTSC " Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:20 ` Maxime Ripard 2015-10-30 14:21 ` [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-11-09 4:24 ` Chen-Yu Tsai 2015-11-09 4:24 ` Chen-Yu Tsai 2015-11-09 4:24 ` Chen-Yu Tsai 2015-10-30 14:21 ` [PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` [PATCH 16/19] ARM: sun5i: dt: Add DRAM gates Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` [PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` [PATCH 18/19] ARM: sun5i: r8: Add AHB gates " Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 14:21 ` Maxime Ripard 2015-10-30 15:20 ` Chen-Yu Tsai 2015-10-30 15:20 ` Chen-Yu Tsai 2015-11-06 19:37 ` Maxime Ripard 2015-11-06 19:37 ` Maxime Ripard 2015-11-06 19:37 ` Maxime Ripard 2015-10-30 14:52 ` [PATCH 00/19] drm: Add Allwinner A10 display engine support Daniel Vetter 2015-10-30 14:52 ` Daniel Vetter 2015-10-30 14:52 ` Daniel Vetter 2015-11-12 5:12 ` Maxime Ripard 2015-11-12 5:12 ` Maxime Ripard 2015-11-12 5:12 ` Maxime Ripard 2015-10-30 15:02 ` Stefan Monnier 2015-11-09 3:43 ` Chen-Yu Tsai 2015-11-09 3:43 ` Chen-Yu Tsai 2015-11-09 3:43 ` Chen-Yu Tsai
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