From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Conor.Dooley@microchip.com Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, LKML <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Date: Mon, 15 Aug 2022 20:44:53 +0100 [thread overview] Message-ID: <CA+V-a8s=RoZmMvDqnBpYZTR2uotv6srumeoRn2=828zhAbOQZA@mail.gmail.com> (raw) In-Reply-To: <ca555430-055c-debb-fdb4-fa7f78129780@microchip.com> Hi Conor, Thank you for the review. On Mon, Aug 15, 2022 at 7:52 PM <Conor.Dooley@microchip.com> wrote: > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default > > upstream kernel to boot on RZ/Five SMARC EVK board. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > * New patch > > --- > > arch/riscv/configs/defconfig | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > > index aed332a9d4ea..de0ccf816c08 100644 > > --- a/arch/riscv/configs/defconfig > > +++ b/arch/riscv/configs/defconfig > > @@ -26,6 +26,7 @@ CONFIG_EXPERT=y > > # CONFIG_SYSFS_SYSCALL is not set > > CONFIG_PROFILING=y > > CONFIG_SOC_MICROCHIP_POLARFIRE=y > > +CONFIG_SOC_RENESAS_RZFIVE=y > > CONFIG_SOC_SIFIVE=y > > CONFIG_SOC_STARFIVE=y > > CONFIG_SOC_VIRT=y > > @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y > > CONFIG_SERIAL_8250=y > > CONFIG_SERIAL_8250_CONSOLE=y > > CONFIG_SERIAL_OF_PLATFORM=y > > +CONFIG_SERIAL_SH_SCI=y > > What's this? The patch text makes this look like an accidental > inclusion, but I figure it is required for boot? This enables the serial driver used by the RZ/Five SoC. SInce the intention was to have a bootable board with default defconfig. I'll update the commit message. Cheers, Prabhakar > Thanks, > Conor. > > > CONFIG_VIRTIO_CONSOLE=y > > CONFIG_HW_RANDOM=y > > CONFIG_HW_RANDOM_VIRTIO=y > > -- > > 2.25.1 > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Conor.Dooley@microchip.com Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, LKML <linux-kernel@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Date: Mon, 15 Aug 2022 20:44:53 +0100 [thread overview] Message-ID: <CA+V-a8s=RoZmMvDqnBpYZTR2uotv6srumeoRn2=828zhAbOQZA@mail.gmail.com> (raw) In-Reply-To: <ca555430-055c-debb-fdb4-fa7f78129780@microchip.com> Hi Conor, Thank you for the review. On Mon, Aug 15, 2022 at 7:52 PM <Conor.Dooley@microchip.com> wrote: > > On 15/08/2022 16:14, Lad Prabhakar wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default > > upstream kernel to boot on RZ/Five SMARC EVK board. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > * New patch > > --- > > arch/riscv/configs/defconfig | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > > index aed332a9d4ea..de0ccf816c08 100644 > > --- a/arch/riscv/configs/defconfig > > +++ b/arch/riscv/configs/defconfig > > @@ -26,6 +26,7 @@ CONFIG_EXPERT=y > > # CONFIG_SYSFS_SYSCALL is not set > > CONFIG_PROFILING=y > > CONFIG_SOC_MICROCHIP_POLARFIRE=y > > +CONFIG_SOC_RENESAS_RZFIVE=y > > CONFIG_SOC_SIFIVE=y > > CONFIG_SOC_STARFIVE=y > > CONFIG_SOC_VIRT=y > > @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y > > CONFIG_SERIAL_8250=y > > CONFIG_SERIAL_8250_CONSOLE=y > > CONFIG_SERIAL_OF_PLATFORM=y > > +CONFIG_SERIAL_SH_SCI=y > > What's this? The patch text makes this look like an accidental > inclusion, but I figure it is required for boot? This enables the serial driver used by the RZ/Five SoC. SInce the intention was to have a bootable board with default defconfig. I'll update the commit message. Cheers, Prabhakar > Thanks, > Conor. > > > CONFIG_VIRTIO_CONSOLE=y > > CONFIG_HW_RANDOM=y > > CONFIG_HW_RANDOM_VIRTIO=y > > -- > > 2.25.1 > > >
next prev parent reply other threads:[~2022-08-15 19:46 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:11 ` Conor.Dooley 2022-08-15 19:11 ` Conor.Dooley 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:42 ` Conor.Dooley 2022-08-15 19:42 ` Conor.Dooley 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:53 ` Conor.Dooley 2022-08-18 18:53 ` Conor.Dooley 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:59 ` Conor.Dooley 2022-08-19 7:59 ` Conor.Dooley 2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 18:40 ` Conor.Dooley 2022-08-19 18:40 ` Conor.Dooley 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 19:44 ` Lad, Prabhakar [this message] 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:49 ` Conor.Dooley 2022-08-15 19:49 ` Conor.Dooley 2022-08-19 8:46 ` Geert Uytterhoeven 2022-08-19 8:46 ` Geert Uytterhoeven
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