Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC

From: <Conor.Dooley@microchip.com>
To: <prabhakar.csengg@gmail.com>, <Conor.Dooley@microchip.com>
Cc: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<geert+renesas@glider.be>, <anup@brainfault.org>,
	<linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC
Date: Mon, 15 Aug 2022 19:49:06 +0000	[thread overview]
Message-ID: <c7889bcb-c765-a30c-6d93-c6c1ac0152e3@microchip.com> (raw)
In-Reply-To: <CA+V-a8s=RoZmMvDqnBpYZTR2uotv6srumeoRn2=828zhAbOQZA@mail.gmail.com>

On 15/08/2022 20:44, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Thank you for the review.
> 
> On Mon, Aug 15, 2022 at 7:52 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Enable Renesas RZ/Five SoC config in defconfig. It allows the default
>>> upstream kernel to boot on RZ/Five SMARC EVK board.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> ---
>>> v1->v2
>>> * New patch
>>> ---
>>>  arch/riscv/configs/defconfig | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
>>> index aed332a9d4ea..de0ccf816c08 100644
>>> --- a/arch/riscv/configs/defconfig
>>> +++ b/arch/riscv/configs/defconfig
>>> @@ -26,6 +26,7 @@ CONFIG_EXPERT=y
>>>  # CONFIG_SYSFS_SYSCALL is not set
>>>  CONFIG_PROFILING=y
>>>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>>> +CONFIG_SOC_RENESAS_RZFIVE=y
>>>  CONFIG_SOC_SIFIVE=y
>>>  CONFIG_SOC_STARFIVE=y
>>>  CONFIG_SOC_VIRT=y
>>> @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y
>>>  CONFIG_SERIAL_8250=y
>>>  CONFIG_SERIAL_8250_CONSOLE=y
>>>  CONFIG_SERIAL_OF_PLATFORM=y
>>> +CONFIG_SERIAL_SH_SCI=y
>>
>> What's this? The patch text makes this look like an accidental
>> inclusion, but I figure it is required for boot?
> This enables the serial driver used by the RZ/Five SoC. SInce the
> intention was to have a bootable board with default defconfig. I'll
> update the commit message.

SGTM, feel free to add
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
when you send your next version if you like.

Conor.
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