From: Geert Uytterhoeven <geert@linux-m68k.org> To: Conor Dooley <Conor.Dooley@microchip.com> Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Prabhakar Lad <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Sat, 20 Aug 2022 14:07:28 +0200 [thread overview] Message-ID: <CAMuHMdUSud4-0ercQe3cyg1RXqg4DKTfgvPh5wc8ibca6dyDKQ@mail.gmail.com> (raw) In-Reply-To: <47cec683-dc17-7aa2-3511-b0244020d571@microchip.com> Hi Conor, On Sat, Aug 20, 2022 at 10:49 AM <Conor.Dooley@microchip.com> wrote: > On 20/08/2022 09:45, Geert Uytterhoeven wrote: > > On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote: > >> On 15/08/2022 16:14, Lad Prabhakar wrote: > >>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > >>> Single). > >>> > >>> Below is the list of IP blocks added in the initial SoC DTSI which can be > >>> used to boot via initramfs on RZ/Five SMARC EVK: > >>> - AX45MP CPU > >>> - CPG > >>> - PINCTRL > >>> - PLIC > >>> - SCIF0 > >>> - SYSC > >>> > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >> That aside, by convention so far we have put things like extals or > >> reference clocks below the /cpus node. Could you do the same here too > >> please? > > > > Really? We've been putting them at the root node for a long time, > > since the separate "clocks" grouping subnode was deprecated. > > The extal-clk is not even part of the SoC, so it should definitely > > not be under the /cpus node. > > Under may have been a confusing choice of words, I meant "physically" > under it in the file. Maybe after would have been a better choice of > words? I wasn't suggesting you put it inside the CPUs node. > Does that make more sense? Oh right, you mean the order of the nodes. Yes, "extal-clk" should be after "cpus", following alphabetical sort order, as the nodes have no unit addresses. Sorry for missing that in my review. I also misread "below" (in Dutch there is only a single word for "below" and "under" ;-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
WARNING: multiple messages have this Message-ID (diff)
From: Geert Uytterhoeven <geert@linux-m68k.org> To: Conor Dooley <Conor.Dooley@microchip.com> Cc: "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Anup Patel <anup@brainfault.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Prabhakar Lad <prabhakar.csengg@gmail.com>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Sat, 20 Aug 2022 14:07:28 +0200 [thread overview] Message-ID: <CAMuHMdUSud4-0ercQe3cyg1RXqg4DKTfgvPh5wc8ibca6dyDKQ@mail.gmail.com> (raw) In-Reply-To: <47cec683-dc17-7aa2-3511-b0244020d571@microchip.com> Hi Conor, On Sat, Aug 20, 2022 at 10:49 AM <Conor.Dooley@microchip.com> wrote: > On 20/08/2022 09:45, Geert Uytterhoeven wrote: > > On Fri, Aug 19, 2022 at 8:40 PM <Conor.Dooley@microchip.com> wrote: > >> On 15/08/2022 16:14, Lad Prabhakar wrote: > >>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > >>> Single). > >>> > >>> Below is the list of IP blocks added in the initial SoC DTSI which can be > >>> used to boot via initramfs on RZ/Five SMARC EVK: > >>> - AX45MP CPU > >>> - CPG > >>> - PINCTRL > >>> - PLIC > >>> - SCIF0 > >>> - SYSC > >>> > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >> That aside, by convention so far we have put things like extals or > >> reference clocks below the /cpus node. Could you do the same here too > >> please? > > > > Really? We've been putting them at the root node for a long time, > > since the separate "clocks" grouping subnode was deprecated. > > The extal-clk is not even part of the SoC, so it should definitely > > not be under the /cpus node. > > Under may have been a confusing choice of words, I meant "physically" > under it in the file. Maybe after would have been a better choice of > words? I wasn't suggesting you put it inside the CPUs node. > Does that make more sense? Oh right, you mean the order of the nodes. Yes, "extal-clk" should be after "cpus", following alphabetical sort order, as the nodes have no unit addresses. Sorry for missing that in my review. I also misread "below" (in Dutch there is only a single word for "below" and "under" ;-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-20 12:07 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-15 15:14 [PATCH v2 0/8] Add support for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 15:14 ` [PATCH v2 1/8] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:11 ` Conor.Dooley 2022-08-15 19:11 ` Conor.Dooley 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-18 13:00 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 2/8] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-18 14:55 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 3/8] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:14 ` Conor.Dooley 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:40 ` Lad, Prabhakar 2022-08-15 19:42 ` Conor.Dooley 2022-08-15 19:42 ` Conor.Dooley 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-16 7:52 ` Krzysztof Kozlowski 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 15:00 ` Geert Uytterhoeven 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-18 18:14 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 4/8] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:10 ` Conor.Dooley 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 19:57 ` Lad, Prabhakar 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 20:05 ` Conor.Dooley 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-15 21:44 ` Lad, Prabhakar 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 15:16 ` Geert Uytterhoeven 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:19 ` Lad, Prabhakar 2022-08-18 18:53 ` Conor.Dooley 2022-08-18 18:53 ` Conor.Dooley 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:35 ` Geert Uytterhoeven 2022-08-19 7:59 ` Conor.Dooley 2022-08-19 7:59 ` Conor.Dooley 2022-08-15 15:14 ` [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 8:04 ` Geert Uytterhoeven 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 11:42 ` Lad, Prabhakar 2022-08-19 18:40 ` Conor.Dooley 2022-08-19 18:40 ` Conor.Dooley 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:45 ` Geert Uytterhoeven 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 8:49 ` Conor.Dooley 2022-08-20 12:07 ` Geert Uytterhoeven [this message] 2022-08-20 12:07 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 19:00 ` Conor.Dooley 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-15 20:16 ` Lad, Prabhakar 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 8:25 ` Geert Uytterhoeven 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 11:39 ` Lad, Prabhakar 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 18:15 ` Conor.Dooley 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-19 8:11 ` Geert Uytterhoeven 2022-08-15 15:14 ` [PATCH v2 7/8] MAINTAINERS: Add entry for Renesas RISC-V architecture Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 8:42 ` Geert Uytterhoeven 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-19 9:08 ` Lad, Prabhakar 2022-08-15 15:14 ` [PATCH v2 8/8] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Lad Prabhakar 2022-08-15 15:14 ` Lad Prabhakar 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 18:52 ` Conor.Dooley 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:44 ` Lad, Prabhakar 2022-08-15 19:49 ` Conor.Dooley 2022-08-15 19:49 ` Conor.Dooley 2022-08-19 8:46 ` Geert Uytterhoeven 2022-08-19 8:46 ` Geert Uytterhoeven
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