Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK

From: <Conor.Dooley@microchip.com>
To: <prabhakar.csengg@gmail.com>, <geert@linux-m68k.org>
Cc: <prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<geert+renesas@glider.be>, <anup@brainfault.org>,
	<linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 6/8] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
Date: Fri, 19 Aug 2022 18:15:59 +0000	[thread overview]
Message-ID: <c8f2b4ae-9921-157d-bb43-8fd8154255e0@microchip.com> (raw)
In-Reply-To: <CA+V-a8t-O8ro8U3n46sjMS=HBJC-09V2hrdNXUCyhEZDrsiTfg@mail.gmail.com>

On 19/08/2022 12:39, Lad, Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Geert,
> 
> 
> On Fri, Aug 19, 2022 at 9:25 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>
>> Hi Prabhakar,
>>
>> On Mon, Aug 15, 2022 at 10:16 PM Lad, Prabhakar
>> <prabhakar.csengg@gmail.com> wrote:
>>> On Mon, Aug 15, 2022 at 8:00 PM <Conor.Dooley@microchip.com> wrote:
>>>> On 15/08/2022 16:14, Lad Prabhakar wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> Enable the minimal blocks required for booting the Renesas RZ/Five
>>>>> SMARC EVK with initramfs.
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> ---
>>>>> v1->v2
>>>>> * New patch
>>>>> ---
>>>>>  arch/riscv/boot/dts/Makefile                  |  1 +
>>>>>  arch/riscv/boot/dts/renesas/Makefile          |  2 ++
>>>>>  .../boot/dts/renesas/r9a07g043f01-smarc.dts   | 16 ++++++++++
>>>>>  .../boot/dts/renesas/rzfive-smarc-som.dtsi    | 22 +++++++++++++
>>>>>  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 32 +++++++++++++++++++
>>>>>  5 files changed, 73 insertions(+)
>>>>>  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
>>>>>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
>>>>>  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
>>>>
>>>> Just to sort out some of my own confusion here - is the smarc EVK
>>>> shared between your arm boards and the riscv ones? Or just the
>>>> peripherals etc on the soc?
>>>>
>>> RZ/Five SoC is pin compatible with RZ/G2UL Type 1 SoC (ARM64). RZ/G2UL
>>> SMARC EVK carrier board can be swapped with RZ/Five or RZ/G2UL SMARC
>>> SoM and still be used.
>>>
>>>> If it is the forver, does the approach suggested here for the
>>>> allwinner stuff make sense to also use for risc-v stuff with
>>>> shared parts of devicetrees?
>>>> https://lore.kernel.org/linux-riscv/3cd9ed5b-8348-38ac-feb1-9a7da858cebc@microchip.com/
>>>>
>>> it does make sense. But I wonder where we would place the common
>>> shared dtsi that can be used by two arch's.
>>
>> You can keep it under arch/arm/boot/dts/renesas/, and refer to
>> it from riscv as <arm64/renesas/...>.
>> Cfr. the symlinks under scripts/dtc/include-prefixes/arm64/ and
>> e.g. cros-ec-keyboard.dtsi.
>>

Is this something that you intend doing or is that future work?
I had a quick, and I mean quick, look through the arm smarc dtsi
and none of them appeared to be a 1:1 match with what I see here.

I assume that's got something to do with the "minimal" in the
patch's subject line, and some re-org of the arm files would be
required? In any case, you've not introduced any more dtbs_check
detectable issues so you're good in my book whichever way you do
it.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>