From: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com> To: Matt Roper <matthew.d.roper@intel.com>, <intel-gfx@lists.freedesktop.org> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v2 08/13] drm/i915/xehp/guc: enable compute engine inside GuC Date: Tue, 1 Mar 2022 10:55:39 -0800 [thread overview] Message-ID: <055877c8-b99b-e8c0-d56b-c02ffd9d15c5@intel.com> (raw) In-Reply-To: <20220228174245.1569581-9-matthew.d.roper@intel.com> On 2/28/2022 9:42 AM, Matt Roper wrote: > From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Tell GuC that CCS is enabled by setting a bit in its ADS. > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Original-author: Michel Thierry > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 +++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 84f189738a68..e629443e07ae 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1327,6 +1327,9 @@ > #define ECOBITS_PPGTT_CACHE64B (3 << 8) > #define ECOBITS_PPGTT_CACHE4B (0 << 8) > > +#define GEN12_RCU_MODE _MMIO(0x14800) > +#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) Having the definition of this register in this patch is a bit weird, because we're save/restoring a register we're not programming. Maybe flip the order of this patch and the next one and move the register definition to that? Daniele > + > #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) > #define CHV_FGT_DISABLE_SS0 (1 << 10) > #define CHV_FGT_DISABLE_SS1 (1 << 11) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 847e00390b00..9bb551b83e7a 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -335,6 +335,10 @@ static int guc_mmio_regset_init(struct temp_regset *regset, > ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); > ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); > > + if (engine->class == RENDER_CLASS && > + CCS_MASK(engine->gt)) > + ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true); > + > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) > ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); > > @@ -430,6 +434,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt, > struct iosys_map *info_map) > { > info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); > + info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt)); > info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); > info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); > info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
WARNING: multiple messages have this Message-ID (diff)
From: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com> To: Matt Roper <matthew.d.roper@intel.com>, <intel-gfx@lists.freedesktop.org> Cc: dri-devel@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2 08/13] drm/i915/xehp/guc: enable compute engine inside GuC Date: Tue, 1 Mar 2022 10:55:39 -0800 [thread overview] Message-ID: <055877c8-b99b-e8c0-d56b-c02ffd9d15c5@intel.com> (raw) In-Reply-To: <20220228174245.1569581-9-matthew.d.roper@intel.com> On 2/28/2022 9:42 AM, Matt Roper wrote: > From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > Tell GuC that CCS is enabled by setting a bit in its ADS. > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Original-author: Michel Thierry > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 +++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 84f189738a68..e629443e07ae 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1327,6 +1327,9 @@ > #define ECOBITS_PPGTT_CACHE64B (3 << 8) > #define ECOBITS_PPGTT_CACHE4B (0 << 8) > > +#define GEN12_RCU_MODE _MMIO(0x14800) > +#define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) Having the definition of this register in this patch is a bit weird, because we're save/restoring a register we're not programming. Maybe flip the order of this patch and the next one and move the register definition to that? Daniele > + > #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) > #define CHV_FGT_DISABLE_SS0 (1 << 10) > #define CHV_FGT_DISABLE_SS1 (1 << 11) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 847e00390b00..9bb551b83e7a 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -335,6 +335,10 @@ static int guc_mmio_regset_init(struct temp_regset *regset, > ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); > ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); > > + if (engine->class == RENDER_CLASS && > + CCS_MASK(engine->gt)) > + ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true); > + > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) > ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); > > @@ -430,6 +434,7 @@ static void fill_engine_enable_masks(struct intel_gt *gt, > struct iosys_map *info_map) > { > info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); > + info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt)); > info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); > info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); > info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt));
next prev parent reply other threads:[~2022-03-01 18:55 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-28 17:42 [PATCH v2 00/13] i915: Prepare for Xe_HP compute engines Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 01/13] drm/i915/xehp: Define compute class and engine Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 02/13] drm/i915/xehp: CCS shares the render reset domain Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 03/13] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 04/13] drm/i915/xehp: compute engine pipe_control Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 6:54 ` Lucas De Marchi 2022-03-01 6:54 ` [Intel-gfx] " Lucas De Marchi 2022-02-28 17:42 ` [PATCH v2 05/13] drm/i915/xehp: CCS should use RCS setup functions Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 06/13] drm/i915: Move context descriptor fields to intel_lrc.h Matt Roper 2022-02-28 17:42 ` Matt Roper 2022-03-01 6:57 ` [Intel-gfx] " Lucas De Marchi 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 07/13] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper 2022-02-28 17:42 ` Matt Roper 2022-02-28 17:42 ` [PATCH v2 08/13] drm/i915/xehp/guc: enable compute engine inside GuC Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 18:55 ` Ceraolo Spurio, Daniele [this message] 2022-03-01 18:55 ` Ceraolo Spurio, Daniele 2022-02-28 17:42 ` [PATCH v2 09/13] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 10/13] drm/i915/xehp: Don't support parallel submission on compute / render Matt Roper 2022-02-28 17:42 ` Matt Roper 2022-03-01 19:04 ` Ceraolo Spurio, Daniele 2022-03-01 19:04 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-02-28 17:42 ` [PATCH v2 11/13] drm/i915/xehp: handle fused off CCS engines Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 22:54 ` Matt Roper 2022-03-01 22:54 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 12/13] drm/i915/xehp: Add compute workarounds Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 19:31 ` Ceraolo Spurio, Daniele 2022-02-28 17:42 ` [PATCH v2 13/13] drm/i915/xehpsdv: Move render/compute engine reset domains related workarounds Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Prepare for Xe_HP compute engines Patchwork 2022-02-28 22:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-02-28 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-01 9:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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