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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 06/13] drm/i915: Move context descriptor fields to intel_lrc.h
Date: Mon, 28 Feb 2022 09:42:38 -0800	[thread overview]
Message-ID: <20220228174245.1569581-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220228174245.1569581-1-matthew.d.roper@intel.com>

This is a more appropriate header for these definitions.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 34 -----------------------
 drivers/gpu/drm/i915/gt/intel_lrc.h       | 34 +++++++++++++++++++++++
 3 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index edba18c942cf..b0982a9e4476 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -21,6 +21,7 @@
 #include "intel_gt.h"
 #include "intel_gt_requests.h"
 #include "intel_gt_pm.h"
+#include "intel_lrc.h"
 #include "intel_lrc_reg.h"
 #include "intel_reset.h"
 #include "intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 69b826a3c381..84f189738a68 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1499,38 +1499,4 @@
 
 #define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)
 
-enum {
-	INTEL_ADVANCED_CONTEXT = 0,
-	INTEL_LEGACY_32B_CONTEXT,
-	INTEL_ADVANCED_AD_CONTEXT,
-	INTEL_LEGACY_64B_CONTEXT
-};
-
-enum {
-	FAULT_AND_HANG = 0,
-	FAULT_AND_HALT, /* Debug only */
-	FAULT_AND_STREAM,
-	FAULT_AND_CONTINUE /* Unsupported */
-};
-
-#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
-#define   GEN8_CTX_VALID			(1 << 0)
-#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
-#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
-#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
-#define   GEN8_CTX_PRIVILEGE			(1 << 8)
-#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
-#define   GEN8_CTX_ID_SHIFT			32
-#define   GEN8_CTX_ID_WIDTH			21
-#define   GEN11_SW_CTX_ID_SHIFT			37
-#define   GEN11_SW_CTX_ID_WIDTH			11
-#define   GEN11_ENGINE_CLASS_SHIFT		61
-#define   GEN11_ENGINE_CLASS_WIDTH		3
-#define   GEN11_ENGINE_INSTANCE_SHIFT		48
-#define   GEN11_ENGINE_INSTANCE_WIDTH		6
-#define   XEHP_SW_CTX_ID_SHIFT			39
-#define   XEHP_SW_CTX_ID_WIDTH			16
-#define   XEHP_SW_COUNTER_SHIFT			58
-#define   XEHP_SW_COUNTER_WIDTH			6
-
 #endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 0b76f096b559..820f8f41fc1f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -69,4 +69,38 @@ void lrc_check_regs(const struct intel_context *ce,
 
 void lrc_update_runtime(struct intel_context *ce);
 
+enum {
+	INTEL_ADVANCED_CONTEXT = 0,
+	INTEL_LEGACY_32B_CONTEXT,
+	INTEL_ADVANCED_AD_CONTEXT,
+	INTEL_LEGACY_64B_CONTEXT
+};
+
+enum {
+	FAULT_AND_HANG = 0,
+	FAULT_AND_HALT, /* Debug only */
+	FAULT_AND_STREAM,
+	FAULT_AND_CONTINUE /* Unsupported */
+};
+
+#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
+#define   GEN8_CTX_VALID			(1 << 0)
+#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
+#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
+#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
+#define   GEN8_CTX_PRIVILEGE			(1 << 8)
+#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
+#define   GEN8_CTX_ID_SHIFT			32
+#define   GEN8_CTX_ID_WIDTH			21
+#define   GEN11_SW_CTX_ID_SHIFT			37
+#define   GEN11_SW_CTX_ID_WIDTH			11
+#define   GEN11_ENGINE_CLASS_SHIFT		61
+#define   GEN11_ENGINE_CLASS_WIDTH		3
+#define   GEN11_ENGINE_INSTANCE_SHIFT		48
+#define   GEN11_ENGINE_INSTANCE_WIDTH		6
+#define   XEHP_SW_CTX_ID_SHIFT			39
+#define   XEHP_SW_CTX_ID_WIDTH			16
+#define   XEHP_SW_COUNTER_SHIFT			58
+#define   XEHP_SW_COUNTER_WIDTH			6
+
 #endif /* __INTEL_LRC_H__ */
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH v2 06/13] drm/i915: Move context descriptor fields to intel_lrc.h
Date: Mon, 28 Feb 2022 09:42:38 -0800	[thread overview]
Message-ID: <20220228174245.1569581-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220228174245.1569581-1-matthew.d.roper@intel.com>

This is a more appropriate header for these definitions.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |  1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h   | 34 -----------------------
 drivers/gpu/drm/i915/gt/intel_lrc.h       | 34 +++++++++++++++++++++++
 3 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index edba18c942cf..b0982a9e4476 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -21,6 +21,7 @@
 #include "intel_gt.h"
 #include "intel_gt_requests.h"
 #include "intel_gt_pm.h"
+#include "intel_lrc.h"
 #include "intel_lrc_reg.h"
 #include "intel_reset.h"
 #include "intel_ring.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 69b826a3c381..84f189738a68 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1499,38 +1499,4 @@
 
 #define GEN12_SFC_DONE(n)			_MMIO(0x1cc000 + (n) * 0x1000)
 
-enum {
-	INTEL_ADVANCED_CONTEXT = 0,
-	INTEL_LEGACY_32B_CONTEXT,
-	INTEL_ADVANCED_AD_CONTEXT,
-	INTEL_LEGACY_64B_CONTEXT
-};
-
-enum {
-	FAULT_AND_HANG = 0,
-	FAULT_AND_HALT, /* Debug only */
-	FAULT_AND_STREAM,
-	FAULT_AND_CONTINUE /* Unsupported */
-};
-
-#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
-#define   GEN8_CTX_VALID			(1 << 0)
-#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
-#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
-#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
-#define   GEN8_CTX_PRIVILEGE			(1 << 8)
-#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
-#define   GEN8_CTX_ID_SHIFT			32
-#define   GEN8_CTX_ID_WIDTH			21
-#define   GEN11_SW_CTX_ID_SHIFT			37
-#define   GEN11_SW_CTX_ID_WIDTH			11
-#define   GEN11_ENGINE_CLASS_SHIFT		61
-#define   GEN11_ENGINE_CLASS_WIDTH		3
-#define   GEN11_ENGINE_INSTANCE_SHIFT		48
-#define   GEN11_ENGINE_INSTANCE_WIDTH		6
-#define   XEHP_SW_CTX_ID_SHIFT			39
-#define   XEHP_SW_CTX_ID_WIDTH			16
-#define   XEHP_SW_COUNTER_SHIFT			58
-#define   XEHP_SW_COUNTER_WIDTH			6
-
 #endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index 0b76f096b559..820f8f41fc1f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -69,4 +69,38 @@ void lrc_check_regs(const struct intel_context *ce,
 
 void lrc_update_runtime(struct intel_context *ce);
 
+enum {
+	INTEL_ADVANCED_CONTEXT = 0,
+	INTEL_LEGACY_32B_CONTEXT,
+	INTEL_ADVANCED_AD_CONTEXT,
+	INTEL_LEGACY_64B_CONTEXT
+};
+
+enum {
+	FAULT_AND_HANG = 0,
+	FAULT_AND_HALT, /* Debug only */
+	FAULT_AND_STREAM,
+	FAULT_AND_CONTINUE /* Unsupported */
+};
+
+#define   CTX_GTT_ADDRESS_MASK			GENMASK(31, 12)
+#define   GEN8_CTX_VALID			(1 << 0)
+#define   GEN8_CTX_FORCE_PD_RESTORE		(1 << 1)
+#define   GEN8_CTX_FORCE_RESTORE		(1 << 2)
+#define   GEN8_CTX_L3LLC_COHERENT		(1 << 5)
+#define   GEN8_CTX_PRIVILEGE			(1 << 8)
+#define   GEN8_CTX_ADDRESSING_MODE_SHIFT	3
+#define   GEN8_CTX_ID_SHIFT			32
+#define   GEN8_CTX_ID_WIDTH			21
+#define   GEN11_SW_CTX_ID_SHIFT			37
+#define   GEN11_SW_CTX_ID_WIDTH			11
+#define   GEN11_ENGINE_CLASS_SHIFT		61
+#define   GEN11_ENGINE_CLASS_WIDTH		3
+#define   GEN11_ENGINE_INSTANCE_SHIFT		48
+#define   GEN11_ENGINE_INSTANCE_WIDTH		6
+#define   XEHP_SW_CTX_ID_SHIFT			39
+#define   XEHP_SW_CTX_ID_WIDTH			16
+#define   XEHP_SW_COUNTER_SHIFT			58
+#define   XEHP_SW_COUNTER_WIDTH			6
+
 #endif /* __INTEL_LRC_H__ */
-- 
2.34.1


  parent reply	other threads:[~2022-02-28 17:43 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-28 17:42 [PATCH v2 00/13] i915: Prepare for Xe_HP compute engines Matt Roper
2022-02-28 17:42 ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` [PATCH v2 01/13] drm/i915/xehp: Define compute class and engine Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` [PATCH v2 02/13] drm/i915/xehp: CCS shares the render reset domain Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` [PATCH v2 03/13] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` [PATCH v2 04/13] drm/i915/xehp: compute engine pipe_control Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-03-01  6:54   ` Lucas De Marchi
2022-03-01  6:54     ` [Intel-gfx] " Lucas De Marchi
2022-02-28 17:42 ` [PATCH v2 05/13] drm/i915/xehp: CCS should use RCS setup functions Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` Matt Roper [this message]
2022-02-28 17:42   ` [PATCH v2 06/13] drm/i915: Move context descriptor fields to intel_lrc.h Matt Roper
2022-03-01  6:57   ` [Intel-gfx] " Lucas De Marchi
2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 07/13] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper
2022-02-28 17:42   ` Matt Roper
2022-02-28 17:42 ` [PATCH v2 08/13] drm/i915/xehp/guc: enable compute engine inside GuC Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-03-01 18:55   ` Ceraolo Spurio, Daniele
2022-03-01 18:55     ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-02-28 17:42 ` [PATCH v2 09/13] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 10/13] drm/i915/xehp: Don't support parallel submission on compute / render Matt Roper
2022-02-28 17:42   ` Matt Roper
2022-03-01 19:04   ` Ceraolo Spurio, Daniele
2022-03-01 19:04     ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-02-28 17:42 ` [PATCH v2 11/13] drm/i915/xehp: handle fused off CCS engines Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-03-01 22:54   ` Matt Roper
2022-03-01 22:54     ` [Intel-gfx] " Matt Roper
2022-02-28 17:42 ` [PATCH v2 12/13] drm/i915/xehp: Add compute workarounds Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-03-01 19:31   ` Ceraolo Spurio, Daniele
2022-02-28 17:42 ` [PATCH v2 13/13] drm/i915/xehpsdv: Move render/compute engine reset domains related workarounds Matt Roper
2022-02-28 17:42   ` [Intel-gfx] " Matt Roper
2022-02-28 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Prepare for Xe_HP compute engines Patchwork
2022-02-28 22:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-28 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-01  9:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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