From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>, dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Aravind Iddamsetty <aravind.iddamsetty@intel.com>, Vinay Belgaumkar <vinay.belgaumkar@intel.com> Subject: [PATCH v2 09/13] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Date: Mon, 28 Feb 2022 09:42:41 -0800 [thread overview] Message-ID: <20220228174245.1569581-10-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220228174245.1569581-1-matthew.d.roper@intel.com> We have to specify in the Render Control Unit Mode register when CCS is enabled. v2: - Move RCU_MODE programming to a helper function. (Tvrtko) - Clean up and clarify comments. (Tvrtko) - Add RCU_MODE to the GuC save/restore list. (Daniele) Bspec: 46034 Original-author: Michel Thierry Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 +++++++++++++++++ .../drm/i915/gt/intel_execlists_submission.c | 16 ++++++++++++++++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++++++++++ 4 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index be4b1e65442f..1c0ab05c3c40 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -265,6 +265,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine, void intel_engine_destroy_pinned_context(struct intel_context *ce); +void xehp_enable_ccs_engines(struct intel_engine_cs *engine); + #define ENGINE_PHYSICAL 0 #define ENGINE_MOCK 1 #define ENGINE_VIRTUAL 2 diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 2136c56d3abc..92f4cf9833ee 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -2070,6 +2070,23 @@ intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) return active; } +void xehp_enable_ccs_engines(struct intel_engine_cs *engine) +{ + /* + * If there are any non-fused-off CCS engines, we need to enable CCS + * support in the RCU_MODE register. This only needs to be done once, + * so for simplicity we'll take care of this in the RCS engine's + * resume handler; since the RCS and all CCS engines belong to the + * same reset domain and are reset together, this will also take care + * of re-applying the setting after i915-triggered resets. + */ + if (!CCS_MASK(engine->gt)) + return; + + intel_uncore_write(engine->uncore, GEN12_RCU_MODE, + _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "mock_engine.c" #include "selftest_engine.c" diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index c8407cc96c42..574c0542c92f 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2914,6 +2914,19 @@ static int execlists_resume(struct intel_engine_cs *engine) return 0; } +static int gen12_rcs_resume(struct intel_engine_cs *engine) +{ + int ret; + + ret = execlists_resume(engine); + if (ret) + return ret; + + xehp_enable_ccs_engines(engine); + + return 0; +} + static void execlists_reset_prepare(struct intel_engine_cs *engine) { ENGINE_TRACE(engine, "depth<-%d\n", @@ -3468,6 +3481,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine) engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; break; } + + if (engine->class == RENDER_CLASS) + engine->resume = gen12_rcs_resume; } int intel_execlists_submission_setup(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 6db8bb1982ca..7e42fecd6093 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3619,6 +3619,19 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine) return !sched_engine->tasklet.callback; } +static int gen12_rcs_resume(struct intel_engine_cs *engine) +{ + int ret; + + ret = guc_resume(engine); + if (ret) + return ret; + + xehp_enable_ccs_engines(engine); + + return 0; +} + static void guc_set_default_submission(struct intel_engine_cs *engine) { engine->submit_request = guc_submit_request; @@ -3739,6 +3752,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine) engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; break; } + + if (engine->class == RENDER_CLASS) + engine->resume = gen12_rcs_resume; } static inline void guc_default_irqs(struct intel_engine_cs *engine) -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com> To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2 09/13] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Date: Mon, 28 Feb 2022 09:42:41 -0800 [thread overview] Message-ID: <20220228174245.1569581-10-matthew.d.roper@intel.com> (raw) In-Reply-To: <20220228174245.1569581-1-matthew.d.roper@intel.com> We have to specify in the Render Control Unit Mode register when CCS is enabled. v2: - Move RCU_MODE programming to a helper function. (Tvrtko) - Clean up and clarify comments. (Tvrtko) - Add RCU_MODE to the GuC save/restore list. (Daniele) Bspec: 46034 Original-author: Michel Thierry Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 2 ++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 +++++++++++++++++ .../drm/i915/gt/intel_execlists_submission.c | 16 ++++++++++++++++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++++++++++ 4 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index be4b1e65442f..1c0ab05c3c40 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -265,6 +265,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine, void intel_engine_destroy_pinned_context(struct intel_context *ce); +void xehp_enable_ccs_engines(struct intel_engine_cs *engine); + #define ENGINE_PHYSICAL 0 #define ENGINE_MOCK 1 #define ENGINE_VIRTUAL 2 diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 2136c56d3abc..92f4cf9833ee 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -2070,6 +2070,23 @@ intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) return active; } +void xehp_enable_ccs_engines(struct intel_engine_cs *engine) +{ + /* + * If there are any non-fused-off CCS engines, we need to enable CCS + * support in the RCU_MODE register. This only needs to be done once, + * so for simplicity we'll take care of this in the RCS engine's + * resume handler; since the RCS and all CCS engines belong to the + * same reset domain and are reset together, this will also take care + * of re-applying the setting after i915-triggered resets. + */ + if (!CCS_MASK(engine->gt)) + return; + + intel_uncore_write(engine->uncore, GEN12_RCU_MODE, + _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE)); +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "mock_engine.c" #include "selftest_engine.c" diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index c8407cc96c42..574c0542c92f 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2914,6 +2914,19 @@ static int execlists_resume(struct intel_engine_cs *engine) return 0; } +static int gen12_rcs_resume(struct intel_engine_cs *engine) +{ + int ret; + + ret = execlists_resume(engine); + if (ret) + return ret; + + xehp_enable_ccs_engines(engine); + + return 0; +} + static void execlists_reset_prepare(struct intel_engine_cs *engine) { ENGINE_TRACE(engine, "depth<-%d\n", @@ -3468,6 +3481,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine) engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; break; } + + if (engine->class == RENDER_CLASS) + engine->resume = gen12_rcs_resume; } int intel_execlists_submission_setup(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 6db8bb1982ca..7e42fecd6093 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3619,6 +3619,19 @@ static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine) return !sched_engine->tasklet.callback; } +static int gen12_rcs_resume(struct intel_engine_cs *engine) +{ + int ret; + + ret = guc_resume(engine); + if (ret) + return ret; + + xehp_enable_ccs_engines(engine); + + return 0; +} + static void guc_set_default_submission(struct intel_engine_cs *engine) { engine->submit_request = guc_submit_request; @@ -3739,6 +3752,9 @@ static void rcs_submission_override(struct intel_engine_cs *engine) engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; break; } + + if (engine->class == RENDER_CLASS) + engine->resume = gen12_rcs_resume; } static inline void guc_default_irqs(struct intel_engine_cs *engine) -- 2.34.1
next prev parent reply other threads:[~2022-02-28 17:43 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-28 17:42 [PATCH v2 00/13] i915: Prepare for Xe_HP compute engines Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 01/13] drm/i915/xehp: Define compute class and engine Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 02/13] drm/i915/xehp: CCS shares the render reset domain Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 03/13] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 04/13] drm/i915/xehp: compute engine pipe_control Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 6:54 ` Lucas De Marchi 2022-03-01 6:54 ` [Intel-gfx] " Lucas De Marchi 2022-02-28 17:42 ` [PATCH v2 05/13] drm/i915/xehp: CCS should use RCS setup functions Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 06/13] drm/i915: Move context descriptor fields to intel_lrc.h Matt Roper 2022-02-28 17:42 ` Matt Roper 2022-03-01 6:57 ` [Intel-gfx] " Lucas De Marchi 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 07/13] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper 2022-02-28 17:42 ` Matt Roper 2022-02-28 17:42 ` [PATCH v2 08/13] drm/i915/xehp/guc: enable compute engine inside GuC Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 18:55 ` Ceraolo Spurio, Daniele 2022-03-01 18:55 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-02-28 17:42 ` Matt Roper [this message] 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 09/13] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper 2022-02-28 17:42 ` [Intel-gfx] [PATCH v2 10/13] drm/i915/xehp: Don't support parallel submission on compute / render Matt Roper 2022-02-28 17:42 ` Matt Roper 2022-03-01 19:04 ` Ceraolo Spurio, Daniele 2022-03-01 19:04 ` [Intel-gfx] " Ceraolo Spurio, Daniele 2022-02-28 17:42 ` [PATCH v2 11/13] drm/i915/xehp: handle fused off CCS engines Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 22:54 ` Matt Roper 2022-03-01 22:54 ` [Intel-gfx] " Matt Roper 2022-02-28 17:42 ` [PATCH v2 12/13] drm/i915/xehp: Add compute workarounds Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-03-01 19:31 ` Ceraolo Spurio, Daniele 2022-02-28 17:42 ` [PATCH v2 13/13] drm/i915/xehpsdv: Move render/compute engine reset domains related workarounds Matt Roper 2022-02-28 17:42 ` [Intel-gfx] " Matt Roper 2022-02-28 22:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Prepare for Xe_HP compute engines Patchwork 2022-02-28 22:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-02-28 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-01 9:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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