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From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
Subject: Re: [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC
Date: Wed, 21 Jul 2021 17:56:16 -0700	[thread overview]
Message-ID: <132fceb9-4078-1823-451c-f18a2ceeb751@intel.com> (raw)
In-Reply-To: <039a95d3-c44c-bab7-0f53-75098a55acc6@intel.com>



On 7/21/2021 10:24 AM, Michal Wajdeczko wrote:
> 
> 
> On 21.07.2021 18:11, Vinay Belgaumkar wrote:
>> Add macros to check for SLPC support. This feature is currently supported
>> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>>
>> Include templates for SLPC init/fini and enable.
>>
>> v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
>> template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal W)
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>
>> drm/i915/guc/slpc: Lay out slpc init/enable/fini
>>
>> Declare init/fini and enable function templates.
>>
>> v2: Rebase
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/Makefile                 |  1 +
>>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  2 +
>>   drivers/gpu/drm/i915/gt/uc/intel_guc.h        |  4 ++
>>   drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 63 +++++++++++++++++++
>>   drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   | 33 ++++++++++
>>   .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 15 +++++
>>   drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  6 +-
>>   drivers/gpu/drm/i915/gt/uc/intel_uc.h         |  2 +
>>   8 files changed, 124 insertions(+), 2 deletions(-)
>>   create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>   create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
>>   create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index ab7679957623..d8eac4468df9 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
>>   	  gt/uc/intel_guc_fw.o \
>>   	  gt/uc/intel_guc_log.o \
>>   	  gt/uc/intel_guc_log_debugfs.o \
>> +	  gt/uc/intel_guc_slpc.o \
>>   	  gt/uc/intel_guc_submission.o \
>>   	  gt/uc/intel_huc.o \
>>   	  gt/uc/intel_huc_debugfs.o \
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 979128e28372..39bc3c16057b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -7,6 +7,7 @@
>>   #include "gt/intel_gt_irq.h"
>>   #include "gt/intel_gt_pm_irq.h"
>>   #include "intel_guc.h"
>> +#include "intel_guc_slpc.h"
>>   #include "intel_guc_ads.h"
>>   #include "intel_guc_submission.h"
>>   #include "i915_drv.h"
>> @@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>>   	intel_guc_ct_init_early(&guc->ct);
>>   	intel_guc_log_init_early(&guc->log);
>>   	intel_guc_submission_init_early(guc);
>> +	intel_guc_slpc_init_early(&guc->slpc);
>>   
>>   	mutex_init(&guc->send_mutex);
>>   	spin_lock_init(&guc->irq_lock);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> index 9c62c68fb132..8cecfad9d7b1 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> @@ -15,6 +15,7 @@
>>   #include "intel_guc_ct.h"
>>   #include "intel_guc_log.h"
>>   #include "intel_guc_reg.h"
>> +#include "intel_guc_slpc_types.h"
>>   #include "intel_uc_fw.h"
>>   #include "i915_utils.h"
>>   #include "i915_vma.h"
>> @@ -30,6 +31,7 @@ struct intel_guc {
>>   	struct intel_uc_fw fw;
>>   	struct intel_guc_log log;
>>   	struct intel_guc_ct ct;
>> +	struct intel_guc_slpc slpc;
>>   
>>   	/* Global engine used to submit requests to GuC */
>>   	struct i915_sched_engine *sched_engine;
>> @@ -57,6 +59,8 @@ struct intel_guc {
>>   
>>   	bool submission_supported;
>>   	bool submission_selected;
>> +	bool slpc_supported;
>> +	bool slpc_selected;
>>   
>>   	struct i915_vma *ads_vma;
>>   	struct __guc_ads_blob *ads_blob;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> new file mode 100644
>> index 000000000000..d9feb430ce35
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -0,0 +1,63 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +#include "i915_drv.h"
>> +#include "intel_guc_slpc.h"
>> +#include "gt/intel_gt.h"
>> +
>> +static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
>> +{
>> +	return container_of(slpc, struct intel_guc, slpc);
>> +}
>> +
>> +static bool __detect_slpc_supported(struct intel_guc *guc)
>> +{
>> +	/* GuC SLPC is unavailable for pre-Gen12 */
>> +	return guc->submission_supported &&
>> +		GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
>> +}
>> +
>> +static bool __guc_slpc_selected(struct intel_guc *guc)
>> +{
>> +	if (!intel_guc_slpc_is_supported(guc))
>> +		return false;
>> +
>> +	return guc->submission_selected;
>> +}
>> +
>> +void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
>> +{
>> +	struct intel_guc *guc = slpc_to_guc(slpc);
>> +
>> +	guc->slpc_supported = __detect_slpc_supported(guc);
>> +	guc->slpc_selected = __guc_slpc_selected(guc);
>> +}
>> +
>> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> +{
>> +	return 0;
>> +}
>> +
>> +/*
>> + * intel_guc_slpc_enable() - Start SLPC
>> + * @slpc: pointer to intel_guc_slpc.
>> + *
>> + * SLPC is enabled by setting up the shared data structure and
>> + * sending reset event to GuC SLPC. Initial data is setup in
>> + * intel_guc_slpc_init. Here we send the reset event. We do
>> + * not currently need a slpc_disable since this is taken care
> 
> s/slpc/SLPC

ok.

> 
>> + * of automatically when a reset/suspend occurs and the GuC
>> + * CTB is destroyed.
> 
> quite large description of the empty function ;)
> better to add it together with actual body

Sure, will move to next patch that defines it fully.

> 
>> + *
>> + * Return: 0 on success, non-zero error code on failure.
>> + */
>> +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>> +{
>> +	return 0;
>> +}
>> +
>> +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
>> +{
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
>> new file mode 100644
>> index 000000000000..c3b0ad7f0f93
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
>> @@ -0,0 +1,33 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +#ifndef _INTEL_GUC_SLPC_H_
>> +#define _INTEL_GUC_SLPC_H_
>> +
>> +#include "intel_guc_submission.h"
>> +#include "intel_guc_slpc_types.h"
>> +
>> +static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
>> +{
>> +	return guc->slpc_supported;
>> +}
>> +
>> +static inline bool intel_guc_slpc_is_wanted(struct intel_guc *guc)
>> +{
>> +	return guc->slpc_selected;
>> +}
>> +
>> +static inline bool intel_guc_slpc_is_used(struct intel_guc *guc)
>> +{
>> +	return intel_guc_submission_is_used(guc) && intel_guc_slpc_is_wanted(guc);
>> +}
>> +
>> +void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
>> +
>> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
>> +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
>> +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> new file mode 100644
>> index 000000000000..b85148265b1f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +#ifndef _INTEL_GUC_SLPC_TYPES_H_
>> +#define _INTEL_GUC_SLPC_TYPES_H_
>> +
>> +#include <linux/types.h>
> 
> likely not needed at this point, add when needed
ok.
> 
>> +
>> +struct intel_guc_slpc {
>> +
> 
> no need to have this empty line
> 
Done.
Thanks,
Vinay.

> Thanks,
> Michal
> 
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index da57d18d9f6b..e6bd9406c7b2 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -75,16 +75,18 @@ static void __confirm_options(struct intel_uc *uc)
>>   	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
>>   
>>   	drm_dbg(&i915->drm,
>> -		"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
>> +		"enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
>>   		i915->params.enable_guc,
>>   		yesno(intel_uc_wants_guc(uc)),
>>   		yesno(intel_uc_wants_guc_submission(uc)),
>> -		yesno(intel_uc_wants_huc(uc)));
>> +		yesno(intel_uc_wants_huc(uc)),
>> +		yesno(intel_uc_wants_guc_slpc(uc)));
>>   
>>   	if (i915->params.enable_guc == 0) {
>>   		GEM_BUG_ON(intel_uc_wants_guc(uc));
>>   		GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
>>   		GEM_BUG_ON(intel_uc_wants_huc(uc));
>> +		GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
>>   		return;
>>   	}
>>   
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>> index e2da2b6e76e1..925a58ca6b94 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>> @@ -8,6 +8,7 @@
>>   
>>   #include "intel_guc.h"
>>   #include "intel_guc_submission.h"
>> +#include "intel_guc_slpc.h"
>>   #include "intel_huc.h"
>>   #include "i915_params.h"
>>   
>> @@ -83,6 +84,7 @@ __uc_state_checker(x, func, uses, used)
>>   uc_state_checkers(guc, guc);
>>   uc_state_checkers(huc, huc);
>>   uc_state_checkers(guc, guc_submission);
>> +uc_state_checkers(guc, guc_slpc);
>>   
>>   #undef uc_state_checkers
>>   #undef __uc_state_checker
>>
> 

WARNING: multiple messages have this Message-ID (diff)
From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
To: Michal Wajdeczko <michal.wajdeczko@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC
Date: Wed, 21 Jul 2021 17:56:16 -0700	[thread overview]
Message-ID: <132fceb9-4078-1823-451c-f18a2ceeb751@intel.com> (raw)
In-Reply-To: <039a95d3-c44c-bab7-0f53-75098a55acc6@intel.com>



On 7/21/2021 10:24 AM, Michal Wajdeczko wrote:
> 
> 
> On 21.07.2021 18:11, Vinay Belgaumkar wrote:
>> Add macros to check for SLPC support. This feature is currently supported
>> for Gen12+ and enabled whenever GuC submission is enabled/selected.
>>
>> Include templates for SLPC init/fini and enable.
>>
>> v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
>> template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal W)
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>
>> drm/i915/guc/slpc: Lay out slpc init/enable/fini
>>
>> Declare init/fini and enable function templates.
>>
>> v2: Rebase
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com>
>> ---
>>   drivers/gpu/drm/i915/Makefile                 |  1 +
>>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  2 +
>>   drivers/gpu/drm/i915/gt/uc/intel_guc.h        |  4 ++
>>   drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 63 +++++++++++++++++++
>>   drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   | 33 ++++++++++
>>   .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 15 +++++
>>   drivers/gpu/drm/i915/gt/uc/intel_uc.c         |  6 +-
>>   drivers/gpu/drm/i915/gt/uc/intel_uc.h         |  2 +
>>   8 files changed, 124 insertions(+), 2 deletions(-)
>>   create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>   create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
>>   create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index ab7679957623..d8eac4468df9 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
>>   	  gt/uc/intel_guc_fw.o \
>>   	  gt/uc/intel_guc_log.o \
>>   	  gt/uc/intel_guc_log_debugfs.o \
>> +	  gt/uc/intel_guc_slpc.o \
>>   	  gt/uc/intel_guc_submission.o \
>>   	  gt/uc/intel_huc.o \
>>   	  gt/uc/intel_huc_debugfs.o \
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index 979128e28372..39bc3c16057b 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -7,6 +7,7 @@
>>   #include "gt/intel_gt_irq.h"
>>   #include "gt/intel_gt_pm_irq.h"
>>   #include "intel_guc.h"
>> +#include "intel_guc_slpc.h"
>>   #include "intel_guc_ads.h"
>>   #include "intel_guc_submission.h"
>>   #include "i915_drv.h"
>> @@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>>   	intel_guc_ct_init_early(&guc->ct);
>>   	intel_guc_log_init_early(&guc->log);
>>   	intel_guc_submission_init_early(guc);
>> +	intel_guc_slpc_init_early(&guc->slpc);
>>   
>>   	mutex_init(&guc->send_mutex);
>>   	spin_lock_init(&guc->irq_lock);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> index 9c62c68fb132..8cecfad9d7b1 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>> @@ -15,6 +15,7 @@
>>   #include "intel_guc_ct.h"
>>   #include "intel_guc_log.h"
>>   #include "intel_guc_reg.h"
>> +#include "intel_guc_slpc_types.h"
>>   #include "intel_uc_fw.h"
>>   #include "i915_utils.h"
>>   #include "i915_vma.h"
>> @@ -30,6 +31,7 @@ struct intel_guc {
>>   	struct intel_uc_fw fw;
>>   	struct intel_guc_log log;
>>   	struct intel_guc_ct ct;
>> +	struct intel_guc_slpc slpc;
>>   
>>   	/* Global engine used to submit requests to GuC */
>>   	struct i915_sched_engine *sched_engine;
>> @@ -57,6 +59,8 @@ struct intel_guc {
>>   
>>   	bool submission_supported;
>>   	bool submission_selected;
>> +	bool slpc_supported;
>> +	bool slpc_selected;
>>   
>>   	struct i915_vma *ads_vma;
>>   	struct __guc_ads_blob *ads_blob;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> new file mode 100644
>> index 000000000000..d9feb430ce35
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -0,0 +1,63 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +#include "i915_drv.h"
>> +#include "intel_guc_slpc.h"
>> +#include "gt/intel_gt.h"
>> +
>> +static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
>> +{
>> +	return container_of(slpc, struct intel_guc, slpc);
>> +}
>> +
>> +static bool __detect_slpc_supported(struct intel_guc *guc)
>> +{
>> +	/* GuC SLPC is unavailable for pre-Gen12 */
>> +	return guc->submission_supported &&
>> +		GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
>> +}
>> +
>> +static bool __guc_slpc_selected(struct intel_guc *guc)
>> +{
>> +	if (!intel_guc_slpc_is_supported(guc))
>> +		return false;
>> +
>> +	return guc->submission_selected;
>> +}
>> +
>> +void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
>> +{
>> +	struct intel_guc *guc = slpc_to_guc(slpc);
>> +
>> +	guc->slpc_supported = __detect_slpc_supported(guc);
>> +	guc->slpc_selected = __guc_slpc_selected(guc);
>> +}
>> +
>> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> +{
>> +	return 0;
>> +}
>> +
>> +/*
>> + * intel_guc_slpc_enable() - Start SLPC
>> + * @slpc: pointer to intel_guc_slpc.
>> + *
>> + * SLPC is enabled by setting up the shared data structure and
>> + * sending reset event to GuC SLPC. Initial data is setup in
>> + * intel_guc_slpc_init. Here we send the reset event. We do
>> + * not currently need a slpc_disable since this is taken care
> 
> s/slpc/SLPC

ok.

> 
>> + * of automatically when a reset/suspend occurs and the GuC
>> + * CTB is destroyed.
> 
> quite large description of the empty function ;)
> better to add it together with actual body

Sure, will move to next patch that defines it fully.

> 
>> + *
>> + * Return: 0 on success, non-zero error code on failure.
>> + */
>> +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>> +{
>> +	return 0;
>> +}
>> +
>> +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
>> +{
>> +}
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
>> new file mode 100644
>> index 000000000000..c3b0ad7f0f93
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
>> @@ -0,0 +1,33 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +#ifndef _INTEL_GUC_SLPC_H_
>> +#define _INTEL_GUC_SLPC_H_
>> +
>> +#include "intel_guc_submission.h"
>> +#include "intel_guc_slpc_types.h"
>> +
>> +static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
>> +{
>> +	return guc->slpc_supported;
>> +}
>> +
>> +static inline bool intel_guc_slpc_is_wanted(struct intel_guc *guc)
>> +{
>> +	return guc->slpc_selected;
>> +}
>> +
>> +static inline bool intel_guc_slpc_is_used(struct intel_guc *guc)
>> +{
>> +	return intel_guc_submission_is_used(guc) && intel_guc_slpc_is_wanted(guc);
>> +}
>> +
>> +void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
>> +
>> +int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
>> +int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
>> +void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> new file mode 100644
>> index 000000000000..b85148265b1f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -0,0 +1,15 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2021 Intel Corporation
>> + */
>> +
>> +#ifndef _INTEL_GUC_SLPC_TYPES_H_
>> +#define _INTEL_GUC_SLPC_TYPES_H_
>> +
>> +#include <linux/types.h>
> 
> likely not needed at this point, add when needed
ok.
> 
>> +
>> +struct intel_guc_slpc {
>> +
> 
> no need to have this empty line
> 
Done.
Thanks,
Vinay.

> Thanks,
> Michal
> 
>> +};
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index da57d18d9f6b..e6bd9406c7b2 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -75,16 +75,18 @@ static void __confirm_options(struct intel_uc *uc)
>>   	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
>>   
>>   	drm_dbg(&i915->drm,
>> -		"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
>> +		"enable_guc=%d (guc:%s submission:%s huc:%s slpc:%s)\n",
>>   		i915->params.enable_guc,
>>   		yesno(intel_uc_wants_guc(uc)),
>>   		yesno(intel_uc_wants_guc_submission(uc)),
>> -		yesno(intel_uc_wants_huc(uc)));
>> +		yesno(intel_uc_wants_huc(uc)),
>> +		yesno(intel_uc_wants_guc_slpc(uc)));
>>   
>>   	if (i915->params.enable_guc == 0) {
>>   		GEM_BUG_ON(intel_uc_wants_guc(uc));
>>   		GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
>>   		GEM_BUG_ON(intel_uc_wants_huc(uc));
>> +		GEM_BUG_ON(intel_uc_wants_guc_slpc(uc));
>>   		return;
>>   	}
>>   
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>> index e2da2b6e76e1..925a58ca6b94 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>> @@ -8,6 +8,7 @@
>>   
>>   #include "intel_guc.h"
>>   #include "intel_guc_submission.h"
>> +#include "intel_guc_slpc.h"
>>   #include "intel_huc.h"
>>   #include "i915_params.h"
>>   
>> @@ -83,6 +84,7 @@ __uc_state_checker(x, func, uses, used)
>>   uc_state_checkers(guc, guc);
>>   uc_state_checkers(huc, huc);
>>   uc_state_checkers(guc, guc_submission);
>> +uc_state_checkers(guc, guc_slpc);
>>   
>>   #undef uc_state_checkers
>>   #undef __uc_state_checker
>>
> 
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  reply	other threads:[~2021-07-22  0:56 UTC|newest]

Thread overview: 104+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 16:11 [PATCH v2 00/14] drm/i915/guc: Enable GuC based power management features Vinay Belgaumkar
2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 16:11 ` [PATCH 01/14] drm/i915/guc: SQUASHED PATCH - DO NOT REVIEW Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 16:11 ` [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 17:24   ` Michal Wajdeczko
2021-07-21 17:24     ` [Intel-gfx] " Michal Wajdeczko
2021-07-22  0:56     ` Belgaumkar, Vinay [this message]
2021-07-22  0:56       ` Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 03/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 16:11 ` [PATCH 04/14] drm/i915/guc/slpc: Adding SLPC communication interfaces Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 17:25   ` Michal Wajdeczko
2021-07-21 17:25     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 19:26     ` Belgaumkar, Vinay
2021-07-23 19:26       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 05/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 17:26   ` Michal Wajdeczko
2021-07-21 17:26     ` Michal Wajdeczko
2021-07-23 19:30     ` Belgaumkar, Vinay
2021-07-23 19:30       ` Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 17:38   ` Michal Wajdeczko
2021-07-21 17:38     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 19:28     ` Belgaumkar, Vinay
2021-07-23 19:28       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 23:44   ` kernel test robot
2021-07-21 23:44     ` kernel test robot
2021-07-21 23:44     ` [Intel-gfx] " kernel test robot
2021-07-22  2:36   ` kernel test robot
2021-07-22  2:36     ` kernel test robot
2021-07-22  2:36     ` [Intel-gfx] " kernel test robot
2021-07-22 18:07   ` kernel test robot
2021-07-22 18:07     ` kernel test robot
2021-07-22 18:07     ` [Intel-gfx] " kernel test robot
2021-07-22 18:07   ` [RFC PATCH] drm/i915/guc/slpc: slpc_decode_min_freq() can be static kernel test robot
2021-07-22 18:07     ` kernel test robot
2021-07-22 18:07     ` [Intel-gfx] " kernel test robot
2021-07-23 13:04   ` [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events kernel test robot
2021-07-23 13:04     ` kernel test robot
2021-07-23 13:04     ` [Intel-gfx] " kernel test robot
2021-07-24 16:30   ` kernel test robot
2021-07-24 16:30     ` kernel test robot
2021-07-24 16:30     ` [Intel-gfx] " kernel test robot
2021-07-21 16:11 ` [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 17:42   ` Michal Wajdeczko
2021-07-21 17:42     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 19:35     ` Belgaumkar, Vinay
2021-07-23 19:35       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 18:00   ` Michal Wajdeczko
2021-07-21 18:00     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 19:43     ` Belgaumkar, Vinay
2021-07-23 19:43       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 18:05   ` Michal Wajdeczko
2021-07-21 18:05     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 19:49     ` Belgaumkar, Vinay
2021-07-23 19:49       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-22  1:29   ` kernel test robot
2021-07-22  1:29     ` kernel test robot
2021-07-22  1:29     ` [Intel-gfx] " kernel test robot
2021-07-24  0:31   ` kernel test robot
2021-07-24  0:31     ` kernel test robot
2021-07-24  0:31     ` [Intel-gfx] " kernel test robot
2021-07-24  0:31   ` [RFC PATCH] drm/i915/guc/slpc: intel_eval_slpc_support() can be static kernel test robot
2021-07-24  0:31     ` kernel test robot
2021-07-24  0:31     ` [Intel-gfx] " kernel test robot
2021-07-25  2:57   ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info kernel test robot
2021-07-25  2:57     ` kernel test robot
2021-07-25  2:57     ` [Intel-gfx] " kernel test robot
2021-07-21 16:11 ` [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 16:11 ` [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 18:09   ` Michal Wajdeczko
2021-07-21 18:09     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 22:25     ` Belgaumkar, Vinay
2021-07-23 22:25       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 18:13   ` Michal Wajdeczko
2021-07-21 18:13     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 22:28     ` Belgaumkar, Vinay
2021-07-23 22:28       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 16:11 ` [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 16:11 ` [PATCH 14/14] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar
2021-07-21 16:11   ` [Intel-gfx] " Vinay Belgaumkar
2021-07-21 18:21   ` Michal Wajdeczko
2021-07-21 18:21     ` [Intel-gfx] " Michal Wajdeczko
2021-07-23 22:29     ` Belgaumkar, Vinay
2021-07-23 22:29       ` [Intel-gfx] " Belgaumkar, Vinay
2021-07-21 20:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Enable GuC based power management features Patchwork
2021-07-21 20:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-21 20:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-22  1:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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