From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com> To: Michal Wajdeczko <michal.wajdeczko@intel.com>, <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>, Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Subject: Re: [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Date: Fri, 23 Jul 2021 15:28:30 -0700 [thread overview] Message-ID: <3af453f6-c549-7101-05fd-6adca8b2e045@intel.com> (raw) In-Reply-To: <c8b72a61-61a2-a32e-1842-6d296154733d@intel.com> On 7/21/2021 11:13 AM, Michal Wajdeczko wrote: > > > On 21.07.2021 18:11, Vinay Belgaumkar wrote: >> Update the get/set min/max freq hooks to work for >> SLPC case as well. Consolidate helpers for requested/min/max >> frequency get/set to intel_rps where the proper action can >> be taken depending on whether slpc is enabled. > > s/slpc/SLPC ok. > >> >> v2: Add wrappers for getting rp0/1/n frequencies, update >> softlimits in set min/max slpc functions. Also check for >> boundary conditions before setting them. >> >> v3: Address review comments (Michal W) >> >> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_rps.c | 165 ++++++++++++++++++++ >> drivers/gpu/drm/i915/gt/intel_rps.h | 11 ++ >> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 14 ++ >> drivers/gpu/drm/i915/i915_pmu.c | 2 +- >> drivers/gpu/drm/i915/i915_reg.h | 2 + >> drivers/gpu/drm/i915/i915_sysfs.c | 77 ++------- >> 6 files changed, 207 insertions(+), 64 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c >> index e858eeb2c59d..48d4147165a9 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c >> @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) >> return rps_to_gt(rps)->uncore; >> } >> >> +static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps) >> +{ >> + struct intel_gt *gt = rps_to_gt(rps); >> + >> + return >->uc.guc.slpc; >> +} >> + >> static bool rps_uses_slpc(struct intel_rps *rps) >> { >> struct intel_gt *gt = rps_to_gt(rps); >> @@ -1960,6 +1967,164 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps) >> return freq; >> } >> >> +u32 intel_rps_read_punit_req(struct intel_rps *rps) >> +{ >> + struct intel_uncore *uncore = rps_to_uncore(rps); >> + >> + return intel_uncore_read(uncore, GEN6_RPNSWREQ); >> +} >> + >> +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq) >> +{ >> + u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT; >> + >> + return req; >> +} >> + >> +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps) >> +{ >> + u32 freq = intel_rps_get_req(rps, intel_rps_read_punit_req(rps)); >> + >> + return intel_gpu_freq(rps, freq); >> +} >> + >> +u32 intel_rps_get_requested_frequency(struct intel_rps *rps) >> +{ >> + if (rps_uses_slpc(rps)) >> + return intel_rps_read_punit_req_frequency(rps); >> + else >> + return intel_gpu_freq(rps, rps->cur_freq); >> +} >> + >> +u32 intel_rps_get_max_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->max_freq_softlimit; >> + else >> + return intel_gpu_freq(rps, rps->max_freq_softlimit); >> +} >> + >> +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->rp0_freq; >> + else >> + return intel_gpu_freq(rps, rps->rp0_freq); >> +} >> + >> +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->rp1_freq; >> + else >> + return intel_gpu_freq(rps, rps->rp1_freq); >> +} >> + >> +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->min_freq; >> + else >> + return intel_gpu_freq(rps, rps->min_freq); >> +} >> + >> +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val) >> +{ >> + struct drm_i915_private *i915 = rps_to_i915(rps); >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + int ret = 0; >> + >> + if (rps_uses_slpc(rps)) >> + return intel_guc_slpc_set_max_freq(slpc, val); >> + >> + mutex_lock(&rps->lock); >> + >> + val = intel_freq_opcode(rps, val); >> + if (val < rps->min_freq || >> + val > rps->max_freq || >> + val < rps->min_freq_softlimit) { >> + ret = -EINVAL; >> + goto unlock; >> + } >> + >> + if (val > rps->rp0_freq) >> + drm_dbg(&i915->drm, "User requested overclocking to %d\n", >> + intel_gpu_freq(rps, val)); >> + >> + rps->max_freq_softlimit = val; >> + >> + val = clamp_t(int, rps->cur_freq, >> + rps->min_freq_softlimit, >> + rps->max_freq_softlimit); >> + >> + /* >> + * We still need *_set_rps to process the new max_delay and >> + * update the interrupt limits and PMINTRMSK even though >> + * frequency request may be unchanged. >> + */ >> + intel_rps_set(rps, val); >> + >> +unlock: >> + mutex_unlock(&rps->lock); >> + >> + return ret; >> +} >> + >> +u32 intel_rps_get_min_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->min_freq_softlimit; >> + else >> + return intel_gpu_freq(rps, rps->min_freq_softlimit); >> +} >> + >> +int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + int ret = 0; >> + >> + if (rps_uses_slpc(rps)) >> + return intel_guc_slpc_set_min_freq(slpc, val); >> + >> + mutex_lock(&rps->lock); >> + >> + val = intel_freq_opcode(rps, val); >> + if (val < rps->min_freq || >> + val > rps->max_freq || >> + val > rps->max_freq_softlimit) { >> + ret = -EINVAL; >> + goto unlock; >> + } >> + >> + rps->min_freq_softlimit = val; >> + >> + val = clamp_t(int, rps->cur_freq, >> + rps->min_freq_softlimit, >> + rps->max_freq_softlimit); >> + >> + /* >> + * We still need *_set_rps to process the new min_delay and >> + * update the interrupt limits and PMINTRMSK even though >> + * frequency request may be unchanged. >> + */ >> + intel_rps_set(rps, val); >> + >> +unlock: >> + mutex_unlock(&rps->lock); >> + >> + return ret; >> +} >> + >> /* External interface for intel_ips.ko */ >> >> static struct drm_i915_private __rcu *ips_mchdev; >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h >> index 1d2cfc98b510..6a66690dfb0f 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.h >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h >> @@ -31,6 +31,17 @@ int intel_gpu_freq(struct intel_rps *rps, int val); >> int intel_freq_opcode(struct intel_rps *rps, int val); >> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1); >> u32 intel_rps_read_actual_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_requested_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_min_frequency(struct intel_rps *rps); >> +int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val); >> +u32 intel_rps_get_max_frequency(struct intel_rps *rps); >> +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val); >> +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); >> +u32 intel_rps_read_punit_req(struct intel_rps *rps); >> +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq); >> +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); >> >> void gen5_rps_irq_handler(struct intel_rps *rps); >> void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir); >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> index 134c57ca10b7..05d8870ec6da 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> @@ -301,6 +301,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val) >> struct drm_i915_private *i915 = slpc_to_i915(slpc); >> intel_wakeref_t wakeref; >> >> + if ((val < slpc->min_freq) || >> + (val > slpc->rp0_freq) || >> + (val < slpc->min_freq_softlimit)) >> + return -EINVAL; >> + >> with_intel_runtime_pm(&i915->runtime_pm, wakeref) { >> ret = slpc_set_param(slpc, >> SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, >> @@ -313,6 +318,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val) >> } >> } >> >> + slpc->max_freq_softlimit = val; >> + >> return ret; >> } >> >> @@ -359,6 +366,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) >> struct drm_i915_private *i915 = guc_to_gt(guc)->i915; >> intel_wakeref_t wakeref; >> >> + if ((val < slpc->min_freq) || >> + (val > slpc->rp0_freq) || >> + (val > slpc->max_freq_softlimit)) >> + return -EINVAL; >> + >> with_intel_runtime_pm(&i915->runtime_pm, wakeref) { >> ret = slpc_set_param(slpc, >> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, >> @@ -371,6 +383,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) >> } >> } >> >> + slpc->min_freq_softlimit = val; >> + >> return ret; >> } >> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c >> index 34d37d46a126..a896bec18255 100644 >> --- a/drivers/gpu/drm/i915/i915_pmu.c >> +++ b/drivers/gpu/drm/i915/i915_pmu.c >> @@ -407,7 +407,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) >> >> if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) { >> add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ], >> - intel_gpu_freq(rps, rps->cur_freq), >> + intel_rps_get_requested_frequency(rps), >> period_ns / 1000); >> } >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 92392c1da0e6..a5d893625736 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -9198,6 +9198,8 @@ enum { >> #define GEN9_FREQUENCY(x) ((x) << 23) >> #define GEN6_OFFSET(x) ((x) << 19) >> #define GEN6_AGGRESSIVE_TURBO (0 << 15) >> +#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23 >> + >> #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) >> #define GEN6_RC_CONTROL _MMIO(0xA090) >> #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) >> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c >> index 873bf996ceb5..346646a0b43b 100644 >> --- a/drivers/gpu/drm/i915/i915_sysfs.c >> +++ b/drivers/gpu/drm/i915/i915_sysfs.c >> @@ -272,7 +272,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, >> struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); >> struct intel_rps *rps = &i915->gt.rps; >> >> - return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->cur_freq)); >> + return sysfs_emit(buf, "%d\n", intel_rps_get_requested_frequency(rps)); >> } >> >> static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) >> @@ -326,9 +326,10 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, >> static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) >> { >> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); >> - struct intel_rps *rps = &dev_priv->gt.rps; >> + struct intel_gt *gt = &dev_priv->gt; >> + struct intel_rps *rps = >->rps; >> >> - return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->max_freq_softlimit)); >> + return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps)); >> } >> >> static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> @@ -336,7 +337,8 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> const char *buf, size_t count) >> { >> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); >> - struct intel_rps *rps = &dev_priv->gt.rps; >> + struct intel_gt *gt = &dev_priv->gt; >> + struct intel_rps *rps = >->rps; >> ssize_t ret; >> u32 val; >> >> @@ -344,35 +346,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> if (ret) >> return ret; >> >> - mutex_lock(&rps->lock); >> - >> - val = intel_freq_opcode(rps, val); >> - if (val < rps->min_freq || >> - val > rps->max_freq || >> - val < rps->min_freq_softlimit) { >> - ret = -EINVAL; >> - goto unlock; >> - } >> - >> - if (val > rps->rp0_freq) >> - DRM_DEBUG("User requested overclocking to %d\n", >> - intel_gpu_freq(rps, val)); >> - >> - rps->max_freq_softlimit = val; >> - >> - val = clamp_t(int, rps->cur_freq, >> - rps->min_freq_softlimit, >> - rps->max_freq_softlimit); >> - >> - /* >> - * We still need *_set_rps to process the new max_delay and >> - * update the interrupt limits and PMINTRMSK even though >> - * frequency request may be unchanged. >> - */ >> - intel_rps_set(rps, val); >> - >> -unlock: >> - mutex_unlock(&rps->lock); >> + ret = intel_rps_set_max_frequency(rps, val); >> >> return ret ?: count; >> } >> @@ -380,9 +354,10 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) >> { >> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); >> - struct intel_rps *rps = &dev_priv->gt.rps; >> + struct intel_gt *gt = &dev_priv->gt; >> + struct intel_rps *rps = >->rps; >> >> - return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->min_freq_softlimit)); >> + return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps)); >> } >> >> static ssize_t gt_min_freq_mhz_store(struct device *kdev, >> @@ -398,31 +373,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, >> if (ret) >> return ret; >> >> - mutex_lock(&rps->lock); >> - >> - val = intel_freq_opcode(rps, val); >> - if (val < rps->min_freq || >> - val > rps->max_freq || >> - val > rps->max_freq_softlimit) { >> - ret = -EINVAL; >> - goto unlock; >> - } >> - >> - rps->min_freq_softlimit = val; >> - >> - val = clamp_t(int, rps->cur_freq, >> - rps->min_freq_softlimit, >> - rps->max_freq_softlimit); >> - >> - /* >> - * We still need *_set_rps to process the new min_delay and >> - * update the interrupt limits and PMINTRMSK even though >> - * frequency request may be unchanged. >> - */ >> - intel_rps_set(rps, val); >> - >> -unlock: >> - mutex_unlock(&rps->lock); >> + ret = intel_rps_set_min_frequency(rps, val); >> >> return ret ?: count; >> } >> @@ -448,11 +399,11 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr >> u32 val; >> >> if (attr == &dev_attr_gt_RP0_freq_mhz) >> - val = intel_gpu_freq(rps, rps->rp0_freq); >> + val = intel_rps_get_rp0_frequency(rps); >> else if (attr == &dev_attr_gt_RP1_freq_mhz) >> - val = intel_gpu_freq(rps, rps->rp1_freq); >> + val = intel_rps_get_rp1_frequency(rps); >> else if (attr == &dev_attr_gt_RPn_freq_mhz) >> - val = intel_gpu_freq(rps, rps->min_freq); >> + val = intel_rps_get_rpn_frequency(rps); >> else >> BUG(); >> >> > > LGTM, but likely you will want someone who is more familiar with RPS to > give r-b, from my side, with typo fixed, this is: Thanks, Vinay. > > Acked-by: Michal Wajdeczko <michal.wajdeczko@intel.com> >
WARNING: multiple messages have this Message-ID (diff)
From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com> To: Michal Wajdeczko <michal.wajdeczko@intel.com>, <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Date: Fri, 23 Jul 2021 15:28:30 -0700 [thread overview] Message-ID: <3af453f6-c549-7101-05fd-6adca8b2e045@intel.com> (raw) In-Reply-To: <c8b72a61-61a2-a32e-1842-6d296154733d@intel.com> On 7/21/2021 11:13 AM, Michal Wajdeczko wrote: > > > On 21.07.2021 18:11, Vinay Belgaumkar wrote: >> Update the get/set min/max freq hooks to work for >> SLPC case as well. Consolidate helpers for requested/min/max >> frequency get/set to intel_rps where the proper action can >> be taken depending on whether slpc is enabled. > > s/slpc/SLPC ok. > >> >> v2: Add wrappers for getting rp0/1/n frequencies, update >> softlimits in set min/max slpc functions. Also check for >> boundary conditions before setting them. >> >> v3: Address review comments (Michal W) >> >> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_rps.c | 165 ++++++++++++++++++++ >> drivers/gpu/drm/i915/gt/intel_rps.h | 11 ++ >> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 14 ++ >> drivers/gpu/drm/i915/i915_pmu.c | 2 +- >> drivers/gpu/drm/i915/i915_reg.h | 2 + >> drivers/gpu/drm/i915/i915_sysfs.c | 77 ++------- >> 6 files changed, 207 insertions(+), 64 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c >> index e858eeb2c59d..48d4147165a9 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c >> @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) >> return rps_to_gt(rps)->uncore; >> } >> >> +static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps) >> +{ >> + struct intel_gt *gt = rps_to_gt(rps); >> + >> + return >->uc.guc.slpc; >> +} >> + >> static bool rps_uses_slpc(struct intel_rps *rps) >> { >> struct intel_gt *gt = rps_to_gt(rps); >> @@ -1960,6 +1967,164 @@ u32 intel_rps_read_actual_frequency(struct intel_rps *rps) >> return freq; >> } >> >> +u32 intel_rps_read_punit_req(struct intel_rps *rps) >> +{ >> + struct intel_uncore *uncore = rps_to_uncore(rps); >> + >> + return intel_uncore_read(uncore, GEN6_RPNSWREQ); >> +} >> + >> +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq) >> +{ >> + u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT; >> + >> + return req; >> +} >> + >> +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps) >> +{ >> + u32 freq = intel_rps_get_req(rps, intel_rps_read_punit_req(rps)); >> + >> + return intel_gpu_freq(rps, freq); >> +} >> + >> +u32 intel_rps_get_requested_frequency(struct intel_rps *rps) >> +{ >> + if (rps_uses_slpc(rps)) >> + return intel_rps_read_punit_req_frequency(rps); >> + else >> + return intel_gpu_freq(rps, rps->cur_freq); >> +} >> + >> +u32 intel_rps_get_max_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->max_freq_softlimit; >> + else >> + return intel_gpu_freq(rps, rps->max_freq_softlimit); >> +} >> + >> +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->rp0_freq; >> + else >> + return intel_gpu_freq(rps, rps->rp0_freq); >> +} >> + >> +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->rp1_freq; >> + else >> + return intel_gpu_freq(rps, rps->rp1_freq); >> +} >> + >> +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->min_freq; >> + else >> + return intel_gpu_freq(rps, rps->min_freq); >> +} >> + >> +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val) >> +{ >> + struct drm_i915_private *i915 = rps_to_i915(rps); >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + int ret = 0; >> + >> + if (rps_uses_slpc(rps)) >> + return intel_guc_slpc_set_max_freq(slpc, val); >> + >> + mutex_lock(&rps->lock); >> + >> + val = intel_freq_opcode(rps, val); >> + if (val < rps->min_freq || >> + val > rps->max_freq || >> + val < rps->min_freq_softlimit) { >> + ret = -EINVAL; >> + goto unlock; >> + } >> + >> + if (val > rps->rp0_freq) >> + drm_dbg(&i915->drm, "User requested overclocking to %d\n", >> + intel_gpu_freq(rps, val)); >> + >> + rps->max_freq_softlimit = val; >> + >> + val = clamp_t(int, rps->cur_freq, >> + rps->min_freq_softlimit, >> + rps->max_freq_softlimit); >> + >> + /* >> + * We still need *_set_rps to process the new max_delay and >> + * update the interrupt limits and PMINTRMSK even though >> + * frequency request may be unchanged. >> + */ >> + intel_rps_set(rps, val); >> + >> +unlock: >> + mutex_unlock(&rps->lock); >> + >> + return ret; >> +} >> + >> +u32 intel_rps_get_min_frequency(struct intel_rps *rps) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + >> + if (rps_uses_slpc(rps)) >> + return slpc->min_freq_softlimit; >> + else >> + return intel_gpu_freq(rps, rps->min_freq_softlimit); >> +} >> + >> +int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val) >> +{ >> + struct intel_guc_slpc *slpc = rps_to_slpc(rps); >> + int ret = 0; >> + >> + if (rps_uses_slpc(rps)) >> + return intel_guc_slpc_set_min_freq(slpc, val); >> + >> + mutex_lock(&rps->lock); >> + >> + val = intel_freq_opcode(rps, val); >> + if (val < rps->min_freq || >> + val > rps->max_freq || >> + val > rps->max_freq_softlimit) { >> + ret = -EINVAL; >> + goto unlock; >> + } >> + >> + rps->min_freq_softlimit = val; >> + >> + val = clamp_t(int, rps->cur_freq, >> + rps->min_freq_softlimit, >> + rps->max_freq_softlimit); >> + >> + /* >> + * We still need *_set_rps to process the new min_delay and >> + * update the interrupt limits and PMINTRMSK even though >> + * frequency request may be unchanged. >> + */ >> + intel_rps_set(rps, val); >> + >> +unlock: >> + mutex_unlock(&rps->lock); >> + >> + return ret; >> +} >> + >> /* External interface for intel_ips.ko */ >> >> static struct drm_i915_private __rcu *ips_mchdev; >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h >> index 1d2cfc98b510..6a66690dfb0f 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.h >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h >> @@ -31,6 +31,17 @@ int intel_gpu_freq(struct intel_rps *rps, int val); >> int intel_freq_opcode(struct intel_rps *rps, int val); >> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1); >> u32 intel_rps_read_actual_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_requested_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_min_frequency(struct intel_rps *rps); >> +int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val); >> +u32 intel_rps_get_max_frequency(struct intel_rps *rps); >> +int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val); >> +u32 intel_rps_get_rp0_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); >> +u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); >> +u32 intel_rps_read_punit_req(struct intel_rps *rps); >> +u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq); >> +u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); >> >> void gen5_rps_irq_handler(struct intel_rps *rps); >> void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir); >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> index 134c57ca10b7..05d8870ec6da 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c >> @@ -301,6 +301,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val) >> struct drm_i915_private *i915 = slpc_to_i915(slpc); >> intel_wakeref_t wakeref; >> >> + if ((val < slpc->min_freq) || >> + (val > slpc->rp0_freq) || >> + (val < slpc->min_freq_softlimit)) >> + return -EINVAL; >> + >> with_intel_runtime_pm(&i915->runtime_pm, wakeref) { >> ret = slpc_set_param(slpc, >> SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, >> @@ -313,6 +318,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val) >> } >> } >> >> + slpc->max_freq_softlimit = val; >> + >> return ret; >> } >> >> @@ -359,6 +366,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) >> struct drm_i915_private *i915 = guc_to_gt(guc)->i915; >> intel_wakeref_t wakeref; >> >> + if ((val < slpc->min_freq) || >> + (val > slpc->rp0_freq) || >> + (val > slpc->max_freq_softlimit)) >> + return -EINVAL; >> + >> with_intel_runtime_pm(&i915->runtime_pm, wakeref) { >> ret = slpc_set_param(slpc, >> SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, >> @@ -371,6 +383,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val) >> } >> } >> >> + slpc->min_freq_softlimit = val; >> + >> return ret; >> } >> >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c >> index 34d37d46a126..a896bec18255 100644 >> --- a/drivers/gpu/drm/i915/i915_pmu.c >> +++ b/drivers/gpu/drm/i915/i915_pmu.c >> @@ -407,7 +407,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) >> >> if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) { >> add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ], >> - intel_gpu_freq(rps, rps->cur_freq), >> + intel_rps_get_requested_frequency(rps), >> period_ns / 1000); >> } >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 92392c1da0e6..a5d893625736 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -9198,6 +9198,8 @@ enum { >> #define GEN9_FREQUENCY(x) ((x) << 23) >> #define GEN6_OFFSET(x) ((x) << 19) >> #define GEN6_AGGRESSIVE_TURBO (0 << 15) >> +#define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23 >> + >> #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) >> #define GEN6_RC_CONTROL _MMIO(0xA090) >> #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) >> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c >> index 873bf996ceb5..346646a0b43b 100644 >> --- a/drivers/gpu/drm/i915/i915_sysfs.c >> +++ b/drivers/gpu/drm/i915/i915_sysfs.c >> @@ -272,7 +272,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, >> struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); >> struct intel_rps *rps = &i915->gt.rps; >> >> - return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->cur_freq)); >> + return sysfs_emit(buf, "%d\n", intel_rps_get_requested_frequency(rps)); >> } >> >> static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) >> @@ -326,9 +326,10 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, >> static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) >> { >> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); >> - struct intel_rps *rps = &dev_priv->gt.rps; >> + struct intel_gt *gt = &dev_priv->gt; >> + struct intel_rps *rps = >->rps; >> >> - return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->max_freq_softlimit)); >> + return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps)); >> } >> >> static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> @@ -336,7 +337,8 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> const char *buf, size_t count) >> { >> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); >> - struct intel_rps *rps = &dev_priv->gt.rps; >> + struct intel_gt *gt = &dev_priv->gt; >> + struct intel_rps *rps = >->rps; >> ssize_t ret; >> u32 val; >> >> @@ -344,35 +346,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> if (ret) >> return ret; >> >> - mutex_lock(&rps->lock); >> - >> - val = intel_freq_opcode(rps, val); >> - if (val < rps->min_freq || >> - val > rps->max_freq || >> - val < rps->min_freq_softlimit) { >> - ret = -EINVAL; >> - goto unlock; >> - } >> - >> - if (val > rps->rp0_freq) >> - DRM_DEBUG("User requested overclocking to %d\n", >> - intel_gpu_freq(rps, val)); >> - >> - rps->max_freq_softlimit = val; >> - >> - val = clamp_t(int, rps->cur_freq, >> - rps->min_freq_softlimit, >> - rps->max_freq_softlimit); >> - >> - /* >> - * We still need *_set_rps to process the new max_delay and >> - * update the interrupt limits and PMINTRMSK even though >> - * frequency request may be unchanged. >> - */ >> - intel_rps_set(rps, val); >> - >> -unlock: >> - mutex_unlock(&rps->lock); >> + ret = intel_rps_set_max_frequency(rps, val); >> >> return ret ?: count; >> } >> @@ -380,9 +354,10 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev, >> static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) >> { >> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); >> - struct intel_rps *rps = &dev_priv->gt.rps; >> + struct intel_gt *gt = &dev_priv->gt; >> + struct intel_rps *rps = >->rps; >> >> - return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->min_freq_softlimit)); >> + return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps)); >> } >> >> static ssize_t gt_min_freq_mhz_store(struct device *kdev, >> @@ -398,31 +373,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, >> if (ret) >> return ret; >> >> - mutex_lock(&rps->lock); >> - >> - val = intel_freq_opcode(rps, val); >> - if (val < rps->min_freq || >> - val > rps->max_freq || >> - val > rps->max_freq_softlimit) { >> - ret = -EINVAL; >> - goto unlock; >> - } >> - >> - rps->min_freq_softlimit = val; >> - >> - val = clamp_t(int, rps->cur_freq, >> - rps->min_freq_softlimit, >> - rps->max_freq_softlimit); >> - >> - /* >> - * We still need *_set_rps to process the new min_delay and >> - * update the interrupt limits and PMINTRMSK even though >> - * frequency request may be unchanged. >> - */ >> - intel_rps_set(rps, val); >> - >> -unlock: >> - mutex_unlock(&rps->lock); >> + ret = intel_rps_set_min_frequency(rps, val); >> >> return ret ?: count; >> } >> @@ -448,11 +399,11 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr >> u32 val; >> >> if (attr == &dev_attr_gt_RP0_freq_mhz) >> - val = intel_gpu_freq(rps, rps->rp0_freq); >> + val = intel_rps_get_rp0_frequency(rps); >> else if (attr == &dev_attr_gt_RP1_freq_mhz) >> - val = intel_gpu_freq(rps, rps->rp1_freq); >> + val = intel_rps_get_rp1_frequency(rps); >> else if (attr == &dev_attr_gt_RPn_freq_mhz) >> - val = intel_gpu_freq(rps, rps->min_freq); >> + val = intel_rps_get_rpn_frequency(rps); >> else >> BUG(); >> >> > > LGTM, but likely you will want someone who is more familiar with RPS to > give r-b, from my side, with typo fixed, this is: Thanks, Vinay. > > Acked-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-23 22:28 UTC|newest] Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-21 16:11 [PATCH v2 00/14] drm/i915/guc: Enable GuC based power management features Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 01/14] drm/i915/guc: SQUASHED PATCH - DO NOT REVIEW Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:24 ` Michal Wajdeczko 2021-07-21 17:24 ` [Intel-gfx] " Michal Wajdeczko 2021-07-22 0:56 ` Belgaumkar, Vinay 2021-07-22 0:56 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 03/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 04/14] drm/i915/guc/slpc: Adding SLPC communication interfaces Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:25 ` Michal Wajdeczko 2021-07-21 17:25 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:26 ` Belgaumkar, Vinay 2021-07-23 19:26 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 05/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:26 ` Michal Wajdeczko 2021-07-21 17:26 ` Michal Wajdeczko 2021-07-23 19:30 ` Belgaumkar, Vinay 2021-07-23 19:30 ` Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:38 ` Michal Wajdeczko 2021-07-21 17:38 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:28 ` Belgaumkar, Vinay 2021-07-23 19:28 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 23:44 ` kernel test robot 2021-07-21 23:44 ` kernel test robot 2021-07-21 23:44 ` [Intel-gfx] " kernel test robot 2021-07-22 2:36 ` kernel test robot 2021-07-22 2:36 ` kernel test robot 2021-07-22 2:36 ` [Intel-gfx] " kernel test robot 2021-07-22 18:07 ` kernel test robot 2021-07-22 18:07 ` kernel test robot 2021-07-22 18:07 ` [Intel-gfx] " kernel test robot 2021-07-22 18:07 ` [RFC PATCH] drm/i915/guc/slpc: slpc_decode_min_freq() can be static kernel test robot 2021-07-22 18:07 ` kernel test robot 2021-07-22 18:07 ` [Intel-gfx] " kernel test robot 2021-07-23 13:04 ` [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events kernel test robot 2021-07-23 13:04 ` kernel test robot 2021-07-23 13:04 ` [Intel-gfx] " kernel test robot 2021-07-24 16:30 ` kernel test robot 2021-07-24 16:30 ` kernel test robot 2021-07-24 16:30 ` [Intel-gfx] " kernel test robot 2021-07-21 16:11 ` [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:42 ` Michal Wajdeczko 2021-07-21 17:42 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:35 ` Belgaumkar, Vinay 2021-07-23 19:35 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:00 ` Michal Wajdeczko 2021-07-21 18:00 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:43 ` Belgaumkar, Vinay 2021-07-23 19:43 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:05 ` Michal Wajdeczko 2021-07-21 18:05 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:49 ` Belgaumkar, Vinay 2021-07-23 19:49 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-22 1:29 ` kernel test robot 2021-07-22 1:29 ` kernel test robot 2021-07-22 1:29 ` [Intel-gfx] " kernel test robot 2021-07-24 0:31 ` kernel test robot 2021-07-24 0:31 ` kernel test robot 2021-07-24 0:31 ` [Intel-gfx] " kernel test robot 2021-07-24 0:31 ` [RFC PATCH] drm/i915/guc/slpc: intel_eval_slpc_support() can be static kernel test robot 2021-07-24 0:31 ` kernel test robot 2021-07-24 0:31 ` [Intel-gfx] " kernel test robot 2021-07-25 2:57 ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info kernel test robot 2021-07-25 2:57 ` kernel test robot 2021-07-25 2:57 ` [Intel-gfx] " kernel test robot 2021-07-21 16:11 ` [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:09 ` Michal Wajdeczko 2021-07-21 18:09 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 22:25 ` Belgaumkar, Vinay 2021-07-23 22:25 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:13 ` Michal Wajdeczko 2021-07-21 18:13 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 22:28 ` Belgaumkar, Vinay [this message] 2021-07-23 22:28 ` Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 14/14] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:21 ` Michal Wajdeczko 2021-07-21 18:21 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 22:29 ` Belgaumkar, Vinay 2021-07-23 22:29 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 20:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Enable GuC based power management features Patchwork 2021-07-21 20:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-21 20:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-22 1:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-28 21:11 [PATCH v4 00/14] drm/i915/guc/slpc: " Vinay Belgaumkar 2021-07-28 21:11 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar 2021-07-29 20:28 ` Michal Wajdeczko 2021-07-30 2:00 [PATCH v5 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar 2021-07-30 2:01 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar 2021-07-30 20:21 [PATCH v6 00/14] drm/i915/guc/slpc: Enable GuC based power management features Vinay Belgaumkar 2021-07-30 20:21 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=3af453f6-c549-7101-05fd-6adca8b2e045@intel.com \ --to=vinay.belgaumkar@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=michal.wajdeczko@intel.com \ --cc=sujaritha.sundaresan@intel.com \ --cc=tvrtko.ursulin@linux.intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.