From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>, Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> Subject: [PATCH 03/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Date: Wed, 21 Jul 2021 09:11:09 -0700 [thread overview] Message-ID: <20210721161120.24610-4-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210721161120.24610-1-vinay.belgaumkar@intel.com> Also ensure uc_init is called before we initialize RPS so that we can check for SLPC support. We do not need to enable up/down interrupts when SLPC is enabled. However, we still need the ARAT interrupt, which will be enabled separately later. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ceeb517ba259..f94d2e1ec3fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) intel_gt_init_timelines(gt); intel_gt_pm_init_early(gt); - intel_rps_init_early(>->rps); intel_uc_init_early(>->uc); + intel_rps_init_early(>->rps); } int intel_gt_probe_lmem(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 0c8e7f2b06f0..e858eeb2c59d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) return rps_to_gt(rps)->uncore; } +static bool rps_uses_slpc(struct intel_rps *rps) +{ + struct intel_gt *gt = rps_to_gt(rps); + + return intel_uc_uses_guc_slpc(>->uc); +} + static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) { return mask & ~rps->pm_intrmsk_mbz; @@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps) { struct intel_gt *gt = rps_to_gt(rps); + GEM_BUG_ON(rps_uses_slpc(rps)); + GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", rps->pm_events, rps_pm_mask(rps, rps->last_freq)); @@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val) struct drm_i915_private *i915 = rps_to_i915(rps); u32 swreq; + GEM_BUG_ON(rps_uses_slpc(rps)); + if (GRAPHICS_VER(i915) >= 9) swreq = GEN9_FREQUENCY(val); else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) @@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps) { int adj; + if (!intel_rps_is_enabled(rps)) + return; + GEM_BUG_ON(atomic_read(&rps->num_waiters)); if (!intel_rps_clear_active(rps)) @@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps) { struct drm_i915_private *i915 = rps_to_i915(rps); + if (rps_uses_slpc(rps)) + return; + if (IS_CHERRYVIEW(i915)) chv_rps_init(rps); else if (IS_VALLEYVIEW(i915)) @@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps) void intel_rps_sanitize(struct intel_rps *rps) { + if (rps_uses_slpc(rps)) + return; + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) rps_disable_interrupts(rps); } -- 2.25.0
WARNING: multiple messages have this Message-ID (diff)
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 03/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Date: Wed, 21 Jul 2021 09:11:09 -0700 [thread overview] Message-ID: <20210721161120.24610-4-vinay.belgaumkar@intel.com> (raw) In-Reply-To: <20210721161120.24610-1-vinay.belgaumkar@intel.com> Also ensure uc_init is called before we initialize RPS so that we can check for SLPC support. We do not need to enable up/down interrupts when SLPC is enabled. However, we still need the ARAT interrupt, which will be enabled separately later. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Sundaresan Sujaritha <sujaritha.sundaresan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ceeb517ba259..f94d2e1ec3fe 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) intel_gt_init_timelines(gt); intel_gt_pm_init_early(gt); - intel_rps_init_early(>->rps); intel_uc_init_early(>->uc); + intel_rps_init_early(>->rps); } int intel_gt_probe_lmem(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 0c8e7f2b06f0..e858eeb2c59d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps *rps) return rps_to_gt(rps)->uncore; } +static bool rps_uses_slpc(struct intel_rps *rps) +{ + struct intel_gt *gt = rps_to_gt(rps); + + return intel_uc_uses_guc_slpc(>->uc); +} + static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask) { return mask & ~rps->pm_intrmsk_mbz; @@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps) { struct intel_gt *gt = rps_to_gt(rps); + GEM_BUG_ON(rps_uses_slpc(rps)); + GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n", rps->pm_events, rps_pm_mask(rps, rps->last_freq)); @@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val) struct drm_i915_private *i915 = rps_to_i915(rps); u32 swreq; + GEM_BUG_ON(rps_uses_slpc(rps)); + if (GRAPHICS_VER(i915) >= 9) swreq = GEN9_FREQUENCY(val); else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) @@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps) { int adj; + if (!intel_rps_is_enabled(rps)) + return; + GEM_BUG_ON(atomic_read(&rps->num_waiters)); if (!intel_rps_clear_active(rps)) @@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps) { struct drm_i915_private *i915 = rps_to_i915(rps); + if (rps_uses_slpc(rps)) + return; + if (IS_CHERRYVIEW(i915)) chv_rps_init(rps); else if (IS_VALLEYVIEW(i915)) @@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps) void intel_rps_sanitize(struct intel_rps *rps) { + if (rps_uses_slpc(rps)) + return; + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6) rps_disable_interrupts(rps); } -- 2.25.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-07-21 16:12 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-21 16:11 [PATCH v2 00/14] drm/i915/guc: Enable GuC based power management features Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 01/14] drm/i915/guc: SQUASHED PATCH - DO NOT REVIEW Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 02/14] drm/i915/guc/slpc: Initial definitions for SLPC Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:24 ` Michal Wajdeczko 2021-07-21 17:24 ` [Intel-gfx] " Michal Wajdeczko 2021-07-22 0:56 ` Belgaumkar, Vinay 2021-07-22 0:56 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` Vinay Belgaumkar [this message] 2021-07-21 16:11 ` [Intel-gfx] [PATCH 03/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 04/14] drm/i915/guc/slpc: Adding SLPC communication interfaces Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:25 ` Michal Wajdeczko 2021-07-21 17:25 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:26 ` Belgaumkar, Vinay 2021-07-23 19:26 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 05/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:26 ` Michal Wajdeczko 2021-07-21 17:26 ` Michal Wajdeczko 2021-07-23 19:30 ` Belgaumkar, Vinay 2021-07-23 19:30 ` Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:38 ` Michal Wajdeczko 2021-07-21 17:38 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:28 ` Belgaumkar, Vinay 2021-07-23 19:28 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 23:44 ` kernel test robot 2021-07-21 23:44 ` kernel test robot 2021-07-21 23:44 ` [Intel-gfx] " kernel test robot 2021-07-22 2:36 ` kernel test robot 2021-07-22 2:36 ` kernel test robot 2021-07-22 2:36 ` [Intel-gfx] " kernel test robot 2021-07-22 18:07 ` kernel test robot 2021-07-22 18:07 ` kernel test robot 2021-07-22 18:07 ` [Intel-gfx] " kernel test robot 2021-07-22 18:07 ` [RFC PATCH] drm/i915/guc/slpc: slpc_decode_min_freq() can be static kernel test robot 2021-07-22 18:07 ` kernel test robot 2021-07-22 18:07 ` [Intel-gfx] " kernel test robot 2021-07-23 13:04 ` [PATCH 06/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events kernel test robot 2021-07-23 13:04 ` kernel test robot 2021-07-23 13:04 ` [Intel-gfx] " kernel test robot 2021-07-24 16:30 ` kernel test robot 2021-07-24 16:30 ` kernel test robot 2021-07-24 16:30 ` [Intel-gfx] " kernel test robot 2021-07-21 16:11 ` [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 17:42 ` Michal Wajdeczko 2021-07-21 17:42 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:35 ` Belgaumkar, Vinay 2021-07-23 19:35 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:00 ` Michal Wajdeczko 2021-07-21 18:00 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:43 ` Belgaumkar, Vinay 2021-07-23 19:43 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:05 ` Michal Wajdeczko 2021-07-21 18:05 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 19:49 ` Belgaumkar, Vinay 2021-07-23 19:49 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-22 1:29 ` kernel test robot 2021-07-22 1:29 ` kernel test robot 2021-07-22 1:29 ` [Intel-gfx] " kernel test robot 2021-07-24 0:31 ` kernel test robot 2021-07-24 0:31 ` kernel test robot 2021-07-24 0:31 ` [Intel-gfx] " kernel test robot 2021-07-24 0:31 ` [RFC PATCH] drm/i915/guc/slpc: intel_eval_slpc_support() can be static kernel test robot 2021-07-24 0:31 ` kernel test robot 2021-07-24 0:31 ` [Intel-gfx] " kernel test robot 2021-07-25 2:57 ` [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info kernel test robot 2021-07-25 2:57 ` kernel test robot 2021-07-25 2:57 ` [Intel-gfx] " kernel test robot 2021-07-21 16:11 ` [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:09 ` Michal Wajdeczko 2021-07-21 18:09 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 22:25 ` Belgaumkar, Vinay 2021-07-23 22:25 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:13 ` Michal Wajdeczko 2021-07-21 18:13 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 22:28 ` Belgaumkar, Vinay 2021-07-23 22:28 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 16:11 ` [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 16:11 ` [PATCH 14/14] drm/i915/guc/rc: Setup and enable GUCRC feature Vinay Belgaumkar 2021-07-21 16:11 ` [Intel-gfx] " Vinay Belgaumkar 2021-07-21 18:21 ` Michal Wajdeczko 2021-07-21 18:21 ` [Intel-gfx] " Michal Wajdeczko 2021-07-23 22:29 ` Belgaumkar, Vinay 2021-07-23 22:29 ` [Intel-gfx] " Belgaumkar, Vinay 2021-07-21 20:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Enable GuC based power management features Patchwork 2021-07-21 20:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-07-21 20:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-22 1:37 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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