[RFC] ValleyView support

[RFC] ValleyView support

[Jesse Barnes]

In this set, you can see why I was asking about register offsets and
splitting the display code.  Included are a few cleanups to help me keep
my sanity, but as I mentioned in my other mail I think we should go
further.

Many of these are ok to apply as-is, so let me know what order you'd
like them in and I can re-post and work on the remainder.

Thanks,
Jesse

[PATCH 01/25] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

[Jesse Barnes]

It's only used by the main read/write functions, so we can keep it with
them.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    6 ++++++
 drivers/gpu/drm/i915/i915_drv.h |    6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0694e17..06533cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -979,6 +979,12 @@ MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL and additional rights");
 
+/* We give fast paths for the really cool registers */
+#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+       (((dev_priv)->info->gen >= 6) && \
+        ((reg) < 0x40000) &&            \
+        ((reg) != FORCEWAKE))
+
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 	u##x val = 0; \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0f19f5..83ace70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1429,12 +1429,6 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
 
-/* We give fast paths for the really cool registers */
-#define NEEDS_FORCE_WAKE(dev_priv, reg) \
-	(((dev_priv)->info->gen >= 6) && \
-	 ((reg) < 0x40000) &&		 \
-	 ((reg) != FORCEWAKE))
-
 #define __i915_read(x, y) \
 	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
 
-- 
1.7.5.4

[PATCH 02/25] drm/i915: add debug message when EDID fetch fails

[Jesse Barnes]

It's pretty obvious but nice to see in the logs anyway.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_modes.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index 2978a3f..c3b1af8 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -78,6 +78,8 @@ int intel_ddc_get_modes(struct drm_connector *connector,
 		drm_edid_to_eld(connector, edid);
 		connector->display_info.raw_edid = NULL;
 		kfree(edid);
+	} else {
+		DRM_DEBUG_KMS("failed to fetch edid\n");
 	}
 
 	return ret;
-- 
1.7.5.4

[PATCH 03/25] drm/i915: re-order GT IIR bit definitions

[Jesse Barnes]

They were all over the place, order them by position and add a few.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..af5cd25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3063,18 +3063,26 @@
 #define DE_PIPEB_VBLANK_IVB		(1<<5)
 #define DE_PIPEA_VBLANK_IVB		(1<<0)
 
+#define MASTER_IER_VLV			0x4400c /* Gunit master IER */
+#define   MASTER_INTERRUPT_ENABLE	(1<<31)
+
 #define DEISR   0x44000
 #define DEIMR   0x44004
 #define DEIIR   0x44008
 #define DEIER   0x4400c
 
 /* GT interrupt */
-#define GT_PIPE_NOTIFY		(1 << 4)
-#define GT_SYNC_STATUS          (1 << 2)
-#define GT_USER_INTERRUPT       (1 << 0)
-#define GT_BSD_USER_INTERRUPT   (1 << 5)
-#define GT_GEN6_BSD_USER_INTERRUPT	(1 << 12)
-#define GT_BLT_USER_INTERRUPT	(1 << 22)
+#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
+#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
+#define GT_BLT_USER_INTERRUPT			(1 << 22)
+#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
+#define GT_GEN6_BSD_USER_INTERRUPT		(1 << 12)
+#define GT_BSD_USER_INTERRUPT			(1 << 5)
+#define GT_L3_PARITY_ERROR_INTERRUPT		(1 << 5) /* IVB+ */
+#define GT_PIPE_NOTIFY				(1 << 4)
+#define GT_RENDER_CS_ERROR_INTERRUPT		(1 << 3)
+#define GT_SYNC_STATUS				(1 << 2)
+#define GT_USER_INTERRUPT			(1 << 0)
 
 #define GTISR   0x44010
 #define GTIMR   0x44014
-- 
1.7.5.4

[PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

[Jesse Barnes]

From: Rohit Jain <rohit.jain@intel.com>

Added support for parsing the OEM Customizable Modes Block (#20)
in the VBIOS table.

Signed-off-by: Rohit Jain <rohit.jain@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay A. Purushothaman <vijay.a.purushothaman@intel.com>
Acked-by: Jesse Barnes <jesse.barnes@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_bios.c |   15 +++++++++++++++
 drivers/gpu/drm/i915/intel_bios.h |   36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 8168d8f..6c170ca 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -450,6 +450,20 @@ parse_driver_features(struct drm_i915_private *dev_priv,
 }
 
 static void
+parse_oem_custom_data(struct drm_i915_private *dev_priv,
+		       struct bdb_header *bdb)
+{
+	struct bdb_oem_custom *oem_data;
+
+	oem_data = find_section(bdb, BDB_OEM_CUSTOM);
+	if (!oem_data)
+		return;
+
+	/* TBD: Read relevant info into dev_priv */
+	return;
+}
+
+static void
 parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
 {
 	struct bdb_edp *edp;
@@ -685,6 +699,7 @@ intel_parse_bios(struct drm_device *dev)
 	parse_sdvo_device_mapping(dev_priv, bdb);
 	parse_device_mapping(dev_priv, bdb);
 	parse_driver_features(dev_priv, bdb);
+	parse_oem_custom_data(dev_priv, bdb);
 	parse_edp(dev_priv, bdb);
 
 	if (bios)
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index dbda6e3..11ff802 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -432,6 +432,42 @@ struct bdb_driver_features {
 	u8 custom_vbt_version;
 } __attribute__((packed));
 
+struct oem_mode_info {
+	/* Mode Flags */
+	u8 mode_flag_video_bios:1;
+	u8 mode_flag_driver:1;
+	u8 mode_flag_reserved:6;
+
+	/* Display Flags */
+	u8 crt:1;
+	u8 tv:1;
+	u8 efp:1;
+	u8 lfp:1;
+	u8 crt2:1;
+	u8 tv2:1;
+	u8 efp2:1;
+	u8 lfp2:1;
+
+	u16 x_res;
+	u16 y_res;
+
+	/* Colour Depth */
+	u8 color_depth_8bpp:1;
+	u8 color_depth_16bpp:1;
+	u8 color_depth_32bpp:1;
+	u8 color_depth_reserved:5;
+
+	u8 refresh_rate;
+
+	/* TBD: OEM DTD Value (18 bytes) */
+} __attribute__((packed));
+
+struct bdb_oem_custom {
+	u8 num_rows;
+	u8 row_size;
+	struct oem_mode_info mode_info[6]; /* mode_info[]? */
+} __attribute__((packed));
+
 #define EDP_18BPP	0
 #define EDP_24BPP	1
 #define EDP_30BPP	2
-- 
1.7.5.4

[PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView

[Jesse Barnes]

ValleyView and similar hardware (like CedarView) put some display
related registers like the PLL controls and dividers on a DPIO bus.  Add
simple indirect register access routines to get to those registers.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h      |    4 ++
 drivers/gpu/drm/i915/i915_reg.h      |   55 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   76 ++++++++++++++++++++++++++++++++++
 3 files changed, 135 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 83ace70..0294330 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -354,6 +354,10 @@ typedef struct drm_i915_private {
 
 	/* protects the irq masks */
 	spinlock_t irq_lock;
+
+	/* DPIO indirect register protection */
+	spinlock_t dpio_lock;
+
 	/** Cached value of IMR to avoid reads in updating the bitfield */
 	u32 pipestat[2];
 	u32 irq_mask;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index af5cd25..ad6b5e0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -301,6 +301,61 @@
 #define  DEBUG_RESET_RENDER		(1<<8)
 #define  DEBUG_RESET_DISPLAY		(1<<9)
 
+/*
+ * DPIO - a special bus for various display related registers to hide behind:
+ *  0x800c: m1, m2, n, p1, p2, k dividers
+ *  0x8014: REF and SFR select
+ *  0x8014: N divider, VCO select
+ *  0x801c/3c: core clock bits
+ *  0x8048/68: low pass filter coefficients
+ *  0x8100: fast clock controls
+ */
+#define DPIO_PKT			0x2100
+#define  DPIO_RID			(0<<24)
+#define  DPIO_OP_WRITE			(1<<16)
+#define  DPIO_OP_READ			(0<<16)
+#define  DPIO_PORTID			(0x12<<8)
+#define  DPIO_BYTE			(0xf<<4)
+#define  DPIO_BUSY			(1<<0) /* status only */
+#define DPIO_DATA			0x2104
+#define DPIO_REG			0x2108
+#define DPIO_CTL			0x2110
+#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
+#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
+#define  DPIO_SFR_BYPASS		(1<<1)
+#define  DPIO_RESET			(1<<0)
+
+#define _DPIO_DIV_A			0x800c
+#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
+#define   DPIO_K_SHIFT			(24) /* 4 bits */
+#define   DPIO_P1_SHIFT			(21) /* 3 bits */
+#define   DPIO_P2_SHIFT			(16) /* 5 bits */
+#define   DPIO_N_SHIFT			(12) /* 4 bits */
+#define   DPIO_ENABLE_CALIBRATION	(1<<11)
+#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
+#define   DPIO_M2DIV_MASK		0xff
+#define _DPIO_DIV_B			0x802c
+#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
+
+#define _DPIO_REFSFR_A			0x8014
+#define   DPIO_REFSEL_OVERRIDE		27
+#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
+#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
+#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
+#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
+#define _DPIO_REFSFR_B			0x8034
+#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
+
+#define _DPIO_CORE_CLK_A		0x801c
+#define _DPIO_CORE_CLK_B		0x803c
+#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
+
+#define _DPIO_LFP_COEFF_A		0x8048
+#define _DPIO_LFP_COEFF_B		0x8068
+#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
+
+#define DPIO_FASTCLK_DISABLE		0x8100
 
 /*
  * Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de1ba19..b8daeef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -360,6 +360,79 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
 	.find_pll = intel_find_pll_ironlake_dp,
 };
 
+#define wait_for_atomic_us(COND, US) ({ \
+	int i, ret__ = -ETIMEDOUT;	\
+	for (i = 0; i < (US); i++) {	\
+		if ((COND)) {		\
+			ret__ = 0;	\
+			break;		\
+		}			\
+		udelay(1);		\
+	}				\
+	ret__;				\
+})
+
+#if 0
+static u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
+{
+	unsigned long flags;
+	u32 val = 0;
+
+	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+		DRM_ERROR("DPIO idle wait timed out\n");
+		goto out_unlock;
+	}
+
+	I915_WRITE(DPIO_REG, reg);
+	I915_WRITE(DPIO_PKT, reg);
+	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
+		   DPIO_BYTE);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+		DRM_ERROR("DPIO read wait timed out\n");
+		goto out_unlock;
+	}
+	val = I915_READ(DPIO_DATA);
+
+out_unlock:
+	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+	return val;
+}
+#endif
+
+static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
+			     u32 val)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+		DRM_ERROR("DPIO idle wait timed out\n");
+		goto out_unlock;
+	}
+
+	I915_WRITE(DPIO_DATA, val);
+	I915_WRITE(DPIO_REG, reg);
+	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
+		   DPIO_BYTE);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
+		DRM_ERROR("DPIO write wait timed out\n");
+
+out_unlock:
+	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+}
+
+static void vlv_init_dpio(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Reset the DPIO config */
+	I915_WRITE(DPIO_CTL, 0);
+	POSTING_READ(DPIO_CTL);
+	I915_WRITE(DPIO_CTL, 1);
+	POSTING_READ(DPIO_CTL);
+}
+
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 						int refclk)
 {
@@ -9187,6 +9260,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_rc6(dev);
 
+	if (IS_VALLEYVIEW(dev))
+		vlv_init_dpio(dev);
+
 	mutex_unlock(&dev->struct_mutex);
 
 	/* Disable the irq before mode object teardown, for the irq might
-- 
1.7.5.4

[PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support

[Jesse Barnes]

ValleyView is a CedarView-like chip but with an Ivybridge graphics core.
This patch adds initial framework for supporting this chip.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c      |   21 +++++++++
 drivers/gpu/drm/i915/i915_drv.h      |    2 +
 drivers/gpu/drm/i915/i915_reg.h      |   59 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   82 +++++++++++++++++++++++++++++++++-
 4 files changed, 163 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 06533cb..b83a0dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -248,6 +248,24 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.has_llc = 1,
 };
 
+static const struct intel_device_info intel_valleyview_m_info = {
+	.gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_fbc = 0,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.is_valleyview = 1,
+};
+
+static const struct intel_device_info intel_valleyview_d_info = {
+	.gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_fbc = 0,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.is_valleyview = 1,
+};
+
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
@@ -292,6 +310,9 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 	{0, 0, 0}
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0294330..2b8b32d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -255,6 +255,7 @@ struct intel_device_info {
 	u8 is_broadwater:1;
 	u8 is_crestline:1;
 	u8 is_ivybridge:1;
+	u8 is_valleyview:1;
 	u8 has_fbc:1;
 	u8 has_pipe_cxsr:1;
 	u8 has_hotplug:1;
@@ -1005,6 +1006,7 @@ struct drm_i915_file_private {
 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
 #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
+#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 
 /*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad6b5e0..7d33c49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -851,8 +851,11 @@
 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
 #define   DPLL_VCO_ENABLE		(1 << 31)
 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
+#define   DPLL_EXT_BUFFER_ENABLE	(1 << 30) /* VLV */
 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
+#define   DPLL_REFA_CLK_ENABLE		(1 << 29) /* VLV */
 #define   DPLL_VGA_MODE_DIS		(1 << 28)
+#define   DPLL_DUAL_PIPE		(1 << 26) /* VLV */
 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
 #define   DPLL_MODE_MASK		(3 << 26)
@@ -863,6 +866,9 @@
 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
+#define   DPLL_VOLTAGE_LDO		(1<<14)
+#define   DPLL_INTEGRATED_CLOCK		(1<<13)
+#define   DPLL_RATE_SWITCH		(1<<8)
 
 #define SRX_INDEX		0x3c4
 #define SRX_DATA		0x3c5
@@ -958,6 +964,9 @@
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
 #define _DPLL_B_MD 0x06020 /* 965+ only */
 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
+
+#define RAWCLK_FREQ			0x6024 /* VLV */
+
 #define _FPA0	0x06040
 #define _FPA1	0x06044
 #define _FPB0	0x06048
@@ -1098,6 +1107,12 @@
 #define RAMCLK_GATE_D		0x6210		/* CRL only */
 #define DEUC			0x6214          /* CRL only */
 
+#define FW_BLC_SELF_VLV		0x6500
+#define  FW_CSPWRDWNEN		(1<<15)
+#define MI_ARB_VLV		0x6504
+#define  DISP_TRICKLE_FEED_DIS	(1<<2)
+#define CZCLK_CDCLK_FREQ_RATIO	0x6508
+
 /*
  * Palette regs
  */
@@ -2475,23 +2490,30 @@
 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
 #define _PIPEASTAT		0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
+#define   SPRITE1_FLIPDONE_INT_EN		(1UL<<30) /* VLV only; typo, should be status? */
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
+#define   PLANE_FLIP_DONE_INT_EN		(1UL<<26) /* VLV only, ?? */
 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
+#define   SPRITE0_FLIP_DONE_INT_EN		(1UL<<26) /* VLV only, ?? */
 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
+#define   PIPEA_HBLANK_INT_EN			(1UL<<16) /* VLV only, ?? */
 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
+#define   SPRITE1_FLIPDONE_INT_STATUS		(1UL<<15) /* VLV only */
+#define   SPRITE0_FLIPDONE_INT_STATUS		(1UL<<15) /* VLV only */
 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
+#define   PLANE_FLIPDONE_INT_STATUS		(1UL<<10) /* VLV only */
 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
@@ -2516,6 +2538,40 @@
 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
+#define DPFLIPSTAT				0x70028 /* VLV only */
+#define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
+#define   PIPEB_HLINE_INT_EN			(1<<28)
+#define   PIPEB_VBLANK_INT_EN			(1<<27)
+#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
+#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
+#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
+#define   PIPEA_LINE_COMPARE_STATUS		(1<<21)
+#define   PIPEA_HLINE_INT_EN			(1<<20)
+#define   PIPEA_VBLANK_INT_EN			(1<<19)
+#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
+#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
+#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
+
+#define DPINVGTT				0x7002c /* VLV only */
+#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
+#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
+#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
+#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
+#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
+#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
+#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
+#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
+#define   DPINVGTT_EN_MASK			0xff0000
+#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
+#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
+#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
+#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
+#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
+#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
+#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
+#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
+#define   DPINVGTT_STATUS_MASK			0xff
+
 #define DSPARB			0x70030
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
@@ -2550,6 +2606,7 @@
 #define I915_FIFO_LINE_SIZE	64
 #define I830_FIFO_LINE_SIZE	32
 
+#define VALLEYVIEW_FIFO_SIZE	255
 #define G4X_FIFO_SIZE		127
 #define I965_FIFO_SIZE		512
 #define I945_FIFO_SIZE		127
@@ -2557,6 +2614,7 @@
 #define I855GM_FIFO_SIZE	127 /* In cachelines */
 #define I830_FIFO_SIZE		95
 
+#define VALLEYVIEW_MAX_WM	0xff
 #define G4X_MAX_WM		0x3f
 #define I915_MAX_WM		0x3f
 
@@ -2571,6 +2629,7 @@
 #define PINEVIEW_CURSOR_DFT_WM	0
 #define PINEVIEW_CURSOR_GUARD_WM	5
 
+#define VALLEYVIEW_CURSOR_MAX_WM 64
 #define I965_CURSOR_FIFO	64
 #define I965_CURSOR_MAX_WM	32
 #define I965_CURSOR_DFT_WM	8
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b8daeef..084e154 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3530,6 +3530,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 	return true;
 }
 
+static int valleyview_get_display_clock_speed(struct drm_device *dev)
+{
+	return 400000; /* FIXME */
+}
+
 static int i945_get_display_clock_speed(struct drm_device *dev)
 {
 	return 400000;
@@ -3679,6 +3684,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
 	2,
 	G4X_FIFO_LINE_SIZE,
 };
+static const struct intel_watermark_params valleyview_wm_info = {
+	VALLEYVIEW_FIFO_SIZE,
+	VALLEYVIEW_MAX_WM,
+	VALLEYVIEW_MAX_WM,
+	2,
+	G4X_FIFO_LINE_SIZE,
+};
+static const struct intel_watermark_params valleyview_cursor_wm_info = {
+	I965_CURSOR_FIFO,
+	VALLEYVIEW_CURSOR_MAX_WM,
+	I965_CURSOR_DFT_WM,
+	2,
+	G4X_FIFO_LINE_SIZE,
+};
 static const struct intel_watermark_params i965_cursor_wm_info = {
 	I965_CURSOR_FIFO,
 	I965_CURSOR_MAX_WM,
@@ -4203,6 +4222,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
 
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
+static void valleyview_update_wm(struct drm_device *dev)
+{
+	static const int sr_latency_ns = 12000;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
+	int plane_sr, cursor_sr;
+	unsigned int enabled = 0;
+
+	if (g4x_compute_wm0(dev, 0,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planea_wm, &cursora_wm))
+		enabled |= 1;
+
+	if (g4x_compute_wm0(dev, 1,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planeb_wm, &cursorb_wm))
+		enabled |= 2;
+
+	plane_sr = cursor_sr = 0;
+	if (single_plane_enabled(enabled) &&
+	    g4x_compute_srwm(dev, ffs(enabled) - 1,
+			     sr_latency_ns,
+			     &valleyview_wm_info,
+			     &valleyview_cursor_wm_info,
+			     &plane_sr, &cursor_sr))
+		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+	else
+		I915_WRITE(FW_BLC_SELF,
+			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
+
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
+		      planea_wm, cursora_wm,
+		      planeb_wm, cursorb_wm,
+		      plane_sr, cursor_sr);
+
+	I915_WRITE(DSPFW1,
+		   (plane_sr << DSPFW_SR_SHIFT) |
+		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
+		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
+		   planea_wm);
+	I915_WRITE(DSPFW2,
+		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
+		   (cursora_wm << DSPFW_CURSORA_SHIFT));
+	I915_WRITE(DSPFW3,
+		   (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
+}
+
 static void g4x_update_wm(struct drm_device *dev)
 {
 	static const int sr_latency_ns = 12000;
@@ -8488,6 +8556,11 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 
+static void valleyview_init_clock_gating(struct drm_device *dev)
+{
+	return;
+}
+
 static void ironlake_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8895,7 +8968,10 @@ static void intel_init_display(struct drm_device *dev)
 	}
 
 	/* Returns the core display clock speed */
-	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
+	if (IS_VALLEYVIEW(dev))
+		dev_priv->display.get_display_clock_speed =
+			valleyview_get_display_clock_speed;
+	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_I915G(dev))
@@ -8990,6 +9066,10 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else
 			dev_priv->display.update_wm = NULL;
+	} else if (IS_VALLEYVIEW(dev)) {
+		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.init_clock_gating =
+			valleyview_init_clock_gating;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
-- 
1.7.5.4

[PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set

[Jesse Barnes]

ValleyView needs something different here, and it cleans up the function
quite a bit.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |  408 +++++++++++++++++++--------------
 1 files changed, 235 insertions(+), 173 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 084e154..f9ac7b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5245,6 +5245,233 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	}
 }
 
+static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
+			      struct drm_display_mode *adjusted_mode)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 temp, lvds_sync = 0;
+
+	temp = I915_READ(LVDS);
+	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
+	if (pipe == 1) {
+		temp |= LVDS_PIPEB_SELECT;
+	} else {
+		temp &= ~LVDS_PIPEB_SELECT;
+	}
+	/* set the corresponsding LVDS_BORDER bit */
+	temp |= dev_priv->lvds_border_bits;
+	/* Set the B0-B3 data pairs corresponding to whether we're going to
+	 * set the DPLLs for dual-channel mode or not.
+	 */
+	if (clock->p2 == 7)
+		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
+	else
+		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
+
+	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
+	 * appropriately here, but we need to look more thoroughly into how
+	 * panels behave in the two modes.
+	 */
+	/* set the dithering flag on LVDS as needed */
+	if (INTEL_INFO(dev)->gen >= 4) {
+		if (dev_priv->lvds_dither)
+			temp |= LVDS_ENABLE_DITHER;
+		else
+			temp &= ~LVDS_ENABLE_DITHER;
+	}
+	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+		lvds_sync |= LVDS_HSYNC_POLARITY;
+	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+		lvds_sync |= LVDS_VSYNC_POLARITY;
+	if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
+	    != lvds_sync) {
+		char flags[2] = "-+";
+		DRM_INFO("Changing LVDS panel from "
+			 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
+			 flags[!(temp & LVDS_HSYNC_POLARITY)],
+			 flags[!(temp & LVDS_VSYNC_POLARITY)],
+			 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
+			 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
+		temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+		temp |= lvds_sync;
+	}
+	I915_WRITE(LVDS, temp);
+}
+
+static void i9xx_update_pll(struct drm_crtc *crtc,
+			    struct drm_display_mode *mode,
+			    struct drm_display_mode *adjusted_mode,
+			    intel_clock_t *clock, intel_clock_t *reduced_clock,
+			    int num_connectors)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 dpll;
+	bool is_sdvo;
+
+	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+	dpll = DPLL_VGA_MODE_DIS;
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+		dpll |= DPLLB_MODE_LVDS;
+	else
+		dpll |= DPLLB_MODE_DAC_SERIAL;
+	if (is_sdvo) {
+		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+		if (pixel_multiplier > 1) {
+			if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+				dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+		}
+		dpll |= DPLL_DVO_HIGH_SPEED;
+	}
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		dpll |= DPLL_DVO_HIGH_SPEED;
+
+	/* compute bitmask from p1 value */
+	if (IS_PINEVIEW(dev))
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
+	else {
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+		if (IS_G4X(dev) && reduced_clock)
+			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	}
+	switch (clock->p2) {
+	case 5:
+		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
+		break;
+	case 7:
+		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
+		break;
+	case 10:
+		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
+		break;
+	case 14:
+		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
+		break;
+	}
+	if (INTEL_INFO(dev)->gen >= 4)
+		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
+
+	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
+		dpll |= PLL_REF_INPUT_TVCLKINBC;
+	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
+		/* XXX: just matching BIOS for now */
+		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
+		dpll |= 3;
+	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+	else
+		dpll |= PLL_REF_INPUT_DREFCLK;
+
+	dpll |= DPLL_VCO_ENABLE;
+	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
+	 * This is an exception to the general rule that mode_set doesn't turn
+	 * things on.
+	 */
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+		intel_update_lvds(crtc, clock, adjusted_mode);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	if (INTEL_INFO(dev)->gen >= 4) {
+		u32 temp = 0;
+		if (is_sdvo) {
+			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+			if (temp > 1)
+				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+			else
+				temp = 0;
+		}
+		I915_WRITE(DPLL_MD(pipe), temp);
+	} else {
+		/* The pixel multiplier can only be updated once the
+		 * DPLL is enabled and the clocks are stable.
+		 *
+		 * So write it again.
+		 */
+		I915_WRITE(DPLL(pipe), dpll);
+	}
+}
+
+static void i8xx_update_pll(struct drm_crtc *crtc,
+			    struct drm_display_mode *adjusted_mode,
+			    intel_clock_t *clock,
+			    int num_connectors)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 dpll;
+
+	dpll = DPLL_VGA_MODE_DIS;
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+	} else {
+		if (clock->p1 == 2)
+			dpll |= PLL_P1_DIVIDE_BY_TWO;
+		else
+			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+		if (clock->p2 == 4)
+			dpll |= PLL_P2_DIVIDE_BY_4;
+	}
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
+		/* XXX: just matching BIOS for now */
+		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
+		dpll |= 3;
+	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+	else
+		dpll |= PLL_REF_INPUT_DREFCLK;
+
+	dpll |= DPLL_VCO_ENABLE;
+	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
+	 * This is an exception to the general rule that mode_set doesn't turn
+	 * things on.
+	 */
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+		intel_update_lvds(crtc, clock, adjusted_mode);
+
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	/* The pixel multiplier can only be updated once the
+	 * DPLL is enabled and the clocks are stable.
+	 *
+	 * So write it again.
+	 */
+	I915_WRITE(DPLL(pipe), dpll);
+}
+
 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 			      struct drm_display_mode *mode,
 			      struct drm_display_mode *adjusted_mode,
@@ -5258,15 +5485,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
-	u32 dpll, dspcntr, pipeconf, vsyncshift;
-	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
-	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
+	u32 dspcntr, pipeconf, vsyncshift;
+	bool ok, has_reduced_clock = false, is_sdvo = false;
+	bool is_lvds = false, is_tv = false;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
 	int ret;
-	u32 temp;
-	u32 lvds_sync = 0;
 
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
@@ -5282,18 +5507,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 			if (encoder->needs_tv_clock)
 				is_tv = true;
 			break;
-		case INTEL_OUTPUT_DVO:
-			is_dvo = true;
-			break;
 		case INTEL_OUTPUT_TVOUT:
 			is_tv = true;
 			break;
-		case INTEL_OUTPUT_ANALOG:
-			is_crt = true;
-			break;
-		case INTEL_OUTPUT_DISPLAYPORT:
-			is_dp = true;
-			break;
 		}
 
 		num_connectors++;
@@ -5337,71 +5553,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
 				 &reduced_clock : NULL);
 
-	dpll = DPLL_VGA_MODE_DIS;
-
-	if (!IS_GEN2(dev)) {
-		if (is_lvds)
-			dpll |= DPLLB_MODE_LVDS;
-		else
-			dpll |= DPLLB_MODE_DAC_SERIAL;
-		if (is_sdvo) {
-			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
-			if (pixel_multiplier > 1) {
-				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
-			}
-			dpll |= DPLL_DVO_HIGH_SPEED;
-		}
-		if (is_dp)
-			dpll |= DPLL_DVO_HIGH_SPEED;
-
-		/* compute bitmask from p1 value */
-		if (IS_PINEVIEW(dev))
-			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
-		else {
-			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-			if (IS_G4X(dev) && has_reduced_clock)
-				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
-		}
-		switch (clock.p2) {
-		case 5:
-			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
-			break;
-		case 7:
-			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
-			break;
-		case 10:
-			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
-			break;
-		case 14:
-			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
-			break;
-		}
-		if (INTEL_INFO(dev)->gen >= 4)
-			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
-	} else {
-		if (is_lvds) {
-			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-		} else {
-			if (clock.p1 == 2)
-				dpll |= PLL_P1_DIVIDE_BY_TWO;
-			else
-				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-			if (clock.p2 == 4)
-				dpll |= PLL_P2_DIVIDE_BY_4;
-		}
-	}
-
-	if (is_sdvo && is_tv)
-		dpll |= PLL_REF_INPUT_TVCLKINBC;
-	else if (is_tv)
-		/* XXX: just matching BIOS for now */
-		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
-		dpll |= 3;
-	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
-		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+	if (IS_GEN2(dev))
+		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
 	else
-		dpll |= PLL_REF_INPUT_DREFCLK;
+		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
+				has_reduced_clock ? &reduced_clock : NULL,
+				num_connectors);
 
 	/* setup pipeconf */
 	pipeconf = I915_READ(PIPECONF(pipe));
@@ -5430,105 +5587,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* default to 8bpc */
 	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
-	if (is_dp) {
-		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
-			pipeconf |= PIPECONF_BPP_6 |
-				    PIPECONF_DITHER_EN |
-				    PIPECONF_DITHER_TYPE_SP;
-		}
-	}
-
-	dpll |= DPLL_VCO_ENABLE;
 
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
-	 * This is an exception to the general rule that mode_set doesn't turn
-	 * things on.
-	 */
-	if (is_lvds) {
-		temp = I915_READ(LVDS);
-		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
-		if (pipe == 1) {
-			temp |= LVDS_PIPEB_SELECT;
-		} else {
-			temp &= ~LVDS_PIPEB_SELECT;
-		}
-		/* set the corresponsding LVDS_BORDER bit */
-		temp |= dev_priv->lvds_border_bits;
-		/* Set the B0-B3 data pairs corresponding to whether we're going to
-		 * set the DPLLs for dual-channel mode or not.
-		 */
-		if (clock.p2 == 7)
-			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
-		else
-			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
-
-		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
-		 * appropriately here, but we need to look more thoroughly into how
-		 * panels behave in the two modes.
-		 */
-		/* set the dithering flag on LVDS as needed */
-		if (INTEL_INFO(dev)->gen >= 4) {
-			if (dev_priv->lvds_dither)
-				temp |= LVDS_ENABLE_DITHER;
-			else
-				temp &= ~LVDS_ENABLE_DITHER;
-		}
-		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-			lvds_sync |= LVDS_HSYNC_POLARITY;
-		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-			lvds_sync |= LVDS_VSYNC_POLARITY;
-		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
-		    != lvds_sync) {
-			char flags[2] = "-+";
-			DRM_INFO("Changing LVDS panel from "
-				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
-				 flags[!(temp & LVDS_HSYNC_POLARITY)],
-				 flags[!(temp & LVDS_VSYNC_POLARITY)],
-				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
-				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
-			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
-			temp |= lvds_sync;
-		}
-		I915_WRITE(LVDS, temp);
-	}
-
-	if (is_dp) {
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
-	}
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	if (INTEL_INFO(dev)->gen >= 4) {
-		temp = 0;
-		if (is_sdvo) {
-			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
-			if (temp > 1)
-				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-			else
-				temp = 0;
-		}
-		I915_WRITE(DPLL_MD(pipe), temp);
-	} else {
-		/* The pixel multiplier can only be updated once the
-		 * DPLL is enabled and the clocks are stable.
-		 *
-		 * So write it again.
-		 */
-		I915_WRITE(DPLL(pipe), dpll);
-	}
-
 	if (HAS_PIPE_CXSR(dev)) {
 		if (intel_crtc->lowfreq_avail) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
-- 
1.7.5.4

[PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions

[Jesse Barnes]

From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>

Add some VLV limit structures and update the PLL code.

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |  231 +++++++++++++++++++++++++++++++++-
 2 files changed, 229 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d33c49..bb6b49f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -866,6 +866,7 @@
 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
+#define   DPLL_LOCK			(1<<15) /* VLV */
 #define   DPLL_VOLTAGE_LDO		(1<<14)
 #define   DPLL_INTEGRATED_CLOCK		(1<<13)
 #define   DPLL_RATE_SWITCH		(1<<8)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f9ac7b7..ea64dc8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -98,6 +98,10 @@ static bool
 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *match_clock,
 			   intel_clock_t *best_clock);
+static bool
+intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+			int target, int refclk, intel_clock_t *match_clock,
+			intel_clock_t *best_clock);
 
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
@@ -360,6 +364,48 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
 	.find_pll = intel_find_pll_ironlake_dp,
 };
 
+static const intel_limit_t intel_limits_vlv_dac = {
+	.dot = { .min = 25000, .max = 270000 },
+	.vco = { .min = 4000000, .max = 6000000 },
+	.n = { .min = 1, .max = 7 },
+	.m = { .min = 22, .max = 450 }, /* guess */
+	.m1 = { .min = 2, .max = 3 },
+	.m2 = { .min = 11, .max = 156 },
+	.p = { .min = 10, .max = 30 },
+	.p1 = { .min = 2, .max = 3 },
+	.p2 = { .dot_limit = 270000,
+		.p2_slow = 10, .p2_fast = 5 },
+	.find_pll = intel_vlv_find_best_pll,
+};
+
+static const intel_limit_t intel_limits_vlv_hdmi = {
+	.dot = { .min = 20000, .max = 165000 },
+	.vco = { .min = 5994000, .max = 4000000 },
+	.n = { .min = 1, .max = 7 },
+	.m = { .min = 60, .max = 300 }, /* guess */
+	.m1 = { .min = 2, .max = 3 },
+	.m2 = { .min = 11, .max = 156 },
+	.p = { .min = 10, .max = 30 },
+	.p1 = { .min = 2, .max = 3 },
+	.p2 = { .dot_limit = 270000,
+		.p2_slow = 10, .p2_fast = 5 },
+	.find_pll = intel_vlv_find_best_pll,
+};
+
+static const intel_limit_t intel_limits_vlv_dp = {
+	.dot = { .min = 162000, .max = 270000 },
+	.vco = { .min = 5994000, .max = 4000000 },
+	.n = { .min = 1, .max = 7 },
+	.m = { .min = 60, .max = 300 }, /* guess */
+	.m1 = { .min = 2, .max = 3 },
+	.m2 = { .min = 11, .max = 156 },
+	.p = { .min = 10, .max = 30 },
+	.p1 = { .min = 2, .max = 3 },
+	.p2 = { .dot_limit = 270000,
+		.p2_slow = 10, .p2_fast = 5 },
+	.find_pll = intel_vlv_find_best_pll,
+};
+
 #define wait_for_atomic_us(COND, US) ({ \
 	int i, ret__ = -ETIMEDOUT;	\
 	for (i = 0; i < (US); i++) {	\
@@ -504,6 +550,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 			limit = &intel_limits_pineview_lvds;
 		else
 			limit = &intel_limits_pineview_sdvo;
+	} else if (IS_VALLEYVIEW(dev)) {
+		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
+			limit = &intel_limits_vlv_dac;
+		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+			limit = &intel_limits_vlv_hdmi;
+		else
+			limit = &intel_limits_vlv_dp;
 	} else if (!IS_GEN2(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i9xx_lvds;
@@ -779,6 +832,84 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return true;
 }
 
+static bool
+intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+			int target, int refclk, intel_clock_t *match_clock,
+			intel_clock_t *best_clock)
+{
+	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
+	u32 m, n, fastclk, minvco, maxvco;
+	u32 updrate, minupdate, fracbits, p;
+	unsigned long bestppm, ppm, absppm;
+	int dotclk;
+
+	dotclk = target * 1000;
+
+	bestppm = 1000000;
+	ppm = 0;
+	absppm = 0;
+
+	fastclk = dotclk / (2*100);
+	minvco = limit->vco.min;
+	maxvco = limit->vco.max;
+	updrate = 0;
+	minupdate = 19200;
+	fracbits = 1;
+
+	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
+	bestm1 = bestm2 = bestp1 = bestp2 = 0;
+
+	for(n = 1; n <= ((refclk) / minupdate); n++) {
+		updrate = refclk / n;
+		for (p1 = 3; p1 > 1; p1--) {
+			for (p2 = 21; p2 > 0; p2--) {
+				if (p2 > 10)
+					p2 = p2 - 1;
+				p = p1 * p2;
+
+				for( m1=2; m1 <= 3; m1++) {
+					m2 = (((2*(fastclk * p * n / m1 )) +
+					       refclk) / (2*refclk));
+					m = m1 * m2;
+					vco = updrate * m;
+					if(vco >= minvco && vco < maxvco) {
+						ppm = 1000000 *((vco / p) -
+								fastclk) /
+							fastclk;
+						absppm = (ppm > 0)? ppm: (-ppm);
+						if (absppm < 100 &&
+						    ((p1 * p2) >
+						     (bestp1 * bestp2))) {
+							bestppm = 0;
+							bestn = n;
+							bestm1 = m1;
+							bestm2 = m2;
+							bestp1 = p1;
+							bestp2 = p2;
+						}
+						if (absppm < bestppm - 10) {
+							bestppm = absppm;
+							bestn = n;
+							bestm1 = m1;
+							bestm2 = m2;
+							bestp1 = p1;
+							bestp2 = p2;
+						}
+					}
+				}
+			} /* Next p2 */
+		} /* Next p1 */
+	}/* Next n */
+
+	best_clock->n = bestn;
+	best_clock->m1 = bestm1;
+	best_clock->m2 = bestm2;
+	best_clock->p1 = bestp1;
+	best_clock->p2 = bestp2;
+
+	return true;
+}
+
 /**
  * intel_wait_for_vblank - wait for vblank on a given pipe
  * @dev: drm device
@@ -1221,7 +1352,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	u32 val;
 
 	/* No really, not for ILK+ */
-	BUG_ON(dev_priv->info->gen >= 5);
+	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
@@ -2966,6 +3097,7 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
 		return;
 
 	ring = LP_RING(dev_priv);
+
 	tmp = I915_READ_CTL(ring);
 	if (tmp & RING_WAIT)
 		I915_WRITE_CTL(ring, tmp);
@@ -5169,14 +5301,38 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
 	return display_bpc != bpc;
 }
 
+static int vlv_get_refclk(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int refclk = 27000; /* for DP & HDMI */
+
+	return 100000; /* only one validated so far */
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
+		refclk = 96000;
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+		if (intel_panel_use_ssc(dev_priv))
+			refclk = 100000;
+		else
+			refclk = 96000;
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		refclk = 100000;
+	}
+
+	return refclk;
+}
+
 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int refclk;
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
-	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
+	if (IS_VALLEYVIEW(dev)) {
+		refclk = vlv_get_refclk(crtc);
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+		   intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
 		refclk = dev_priv->lvds_ssc_freq * 1000;
 		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
 			      refclk / 1000);
@@ -5301,6 +5457,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
 	I915_WRITE(LVDS, temp);
 }
 
+static void vlv_update_pll(struct drm_crtc *crtc,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode,
+			   intel_clock_t *clock, intel_clock_t *reduced_clock,
+			   int refclk, int num_connectors)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 dpll, mdiv, pdiv;
+	u32 bestn, bestm1, bestm2, bestp1, bestp2;
+	bool is_hdmi;
+
+	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+	bestn = clock->n;
+	bestm1 = clock->m1;
+	bestm2 = clock->m2;
+	bestp1 = clock->p1;
+	bestp2 = clock->p2;
+
+	/* Enable DPIO clock input */
+	dpll = DPLL_EXT_BUFFER_ENABLE | DPLL_REFA_CLK_ENABLE |
+		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK;
+	I915_WRITE(DPLL(pipe), dpll);
+	POSTING_READ(DPLL(pipe));
+
+	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
+	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
+	mdiv |= ((bestn << DPIO_N_SHIFT));
+	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
+	mdiv |= (1 << DPIO_K_SHIFT);
+	mdiv |= DPIO_ENABLE_CALIBRATION;
+	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+
+	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
+
+	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
+		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
+
+	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+
+	dpll |= DPLL_VCO_ENABLE;
+	I915_WRITE(DPLL(pipe), dpll);
+	POSTING_READ(DPLL(pipe));
+	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK) == DPLL_LOCK), 1))
+		DRM_ERROR("DPLL %d failed to lock\n", pipe);
+
+	if (is_hdmi) {
+		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+
+		if (temp > 1)
+			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+		else
+			temp = 0;
+
+		I915_WRITE(DPLL_MD(pipe), temp);
+		POSTING_READ(DPLL_MD(pipe));
+	}
+
+	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
+}
+
 static void i9xx_update_pll(struct drm_crtc *crtc,
 			    struct drm_display_mode *mode,
 			    struct drm_display_mode *adjusted_mode,
@@ -5555,6 +5777,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	if (IS_GEN2(dev))
 		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
+	else if (IS_VALLEYVIEW(dev))
+		vlv_update_pll(crtc, mode, adjusted_mode, &clock, NULL,
+			       refclk, num_connectors);
 	else
 		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
-- 
1.7.5.4

[PATCH 09/25] drm/915: program driain latency regs on ValleyView

[Jesse Barnes]

From: Gajanan Bhat <gajanan.bhat@intel.com>

This patch adds support for programming drain latency registers of Pondicherry
memory arbiter of Valleyview.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |   16 +++++++
 drivers/gpu/drm/i915/intel_display.c |   76 ++++++++++++++++++++++++++++++++++
 2 files changed, 92 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb6b49f..2ff9822 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2602,6 +2602,22 @@
 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
 
+/* drain latency register values*/
+#define DRAIN_LATENCY_PRECISION_32	32
+#define DRAIN_LATENCY_PRECISION_16	16
+#define VLV_DDL1			0x70050
+#define DDL_CURSORA_PRECISION_32	(1<<31)
+#define DDL_CURSORA_PRECISION_16	(0<<31)
+#define DDL_CURSORA_SHIFT		24
+#define DDL_PLANEA_PRECISION_32		(1<<7)
+#define DDL_PLANEA_PRECISION_16		(0<<7)
+#define VLV_DDL2			0x70054
+#define DDL_CURSORB_PRECISION_32	(1<<31)
+#define DDL_CURSORB_PRECISION_16	(0<<31)
+#define DDL_CURSORB_SHIFT		24
+#define DDL_PLANEB_PRECISION_32		(1<<7)
+#define DDL_PLANEB_PRECISION_16		(0<<7)
+
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE	64
 #define I915_FIFO_LINE_SIZE	64
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ea64dc8..efb6465 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4352,6 +4352,80 @@ static bool g4x_compute_srwm(struct drm_device *dev,
 			      display, cursor);
 }
 
+static int valleyview_compute_dl(struct drm_device *dev,
+					int plane,
+					int *plane_prec_mult,
+					int *plane_dl,
+					int *cursor_prec_mult,
+					int *cursor_dl)
+{
+	struct drm_crtc *crtc;
+	int clock, pixel_size;
+	int entries;
+
+	crtc = intel_get_crtc_for_plane(dev, plane);
+	if (crtc->fb == NULL || !crtc->enabled)
+		return false;
+
+	clock = crtc->mode.clock;	/* VESA DOT Clock */
+	pixel_size = crtc->fb->bits_per_pixel / 8;	/* BPP */
+
+	entries = (clock / 1000) * pixel_size;
+	*plane_prec_mult = (entries > 256) ?
+		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+	*plane_dl = (64 * *plane_prec_mult * 4) / ((clock / 1000) * pixel_size);
+
+	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
+	*cursor_prec_mult = (entries > 256) ?
+		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+	*cursor_dl = (64 * *cursor_prec_mult * 4) / ((clock / 1000) * 4);
+
+	return true;
+}
+
+/*
+ * Update drain latency registers of memory arbiter
+ *
+ * Valleyview SoC has a new memory arbiter and needs drain latency registers
+ * to be programmed. Each plane has a drain latency multiplier and a drain
+ * latency value.
+ */
+
+static void valleyview_update_dl(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int planea_prec, planea_dl, planeb_prec, planeb_dl;
+	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
+	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
+							either 16 or 32 */
+
+	/* For plane A, Cursor A */
+	if (valleyview_compute_dl(dev, 0, &plane_prec_mult, &planea_dl,
+					&cursor_prec_mult, &cursora_dl)) {
+		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
+		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
+
+		I915_WRITE(VLV_DDL1, cursora_prec |
+				(cursora_dl << DDL_CURSORA_SHIFT) |
+				planea_prec | planea_dl);
+	}
+
+	/* For plane B, Cursor B */
+	if (valleyview_compute_dl(dev, 1, &plane_prec_mult, &planeb_dl,
+					&cursor_prec_mult, &cursorb_dl)) {
+		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
+		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
+
+		I915_WRITE(VLV_DDL2, cursorb_prec |
+				(cursorb_dl << DDL_CURSORB_SHIFT) |
+				planeb_prec | planeb_dl);
+	}
+}
+
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
 static void valleyview_update_wm(struct drm_device *dev)
@@ -4362,6 +4436,8 @@ static void valleyview_update_wm(struct drm_device *dev)
 	int plane_sr, cursor_sr;
 	unsigned int enabled = 0;
 
+	valleyview_update_dl(dev);
+
 	if (g4x_compute_wm0(dev, 0,
 			    &valleyview_wm_info, latency_ns,
 			    &valleyview_cursor_wm_info, latency_ns,
-- 
1.7.5.4

[PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView

[Jesse Barnes]

From: Shobhit Kumar <shobhit.kumar@intel.com>

VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same

Signed-off-by: Beeresh G <beeresh.g@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |   12 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
 2 files changed, 19 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ff9822..c187398 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3717,6 +3717,18 @@
 
 #define BLC_PWM_PCH_CTL2	0xc8254
 
+#define PIPEA_PP_STATUS         0x61200
+#define PIPEA_PP_CONTROL        0x61204
+#define PIPEA_PP_ON_DELAYS      0x61208
+#define PIPEA_PP_OFF_DELAYS     0x6120c
+#define PIPEA_PP_DIVISOR        0x61210
+
+#define PIPEB_PP_STATUS         0x61300
+#define PIPEB_PP_CONTROL        0x61304
+#define PIPEB_PP_ON_DELAYS      0x61308
+#define PIPEB_PP_OFF_DELAYS     0x6130c
+#define PIPEB_PP_DIVISOR        0x61310
+
 #define PCH_PP_STATUS		0xc7200
 #define PCH_PP_CONTROL		0xc7204
 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 110552f..a831bb5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -311,7 +311,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+	if (IS_VALLEYVIEW(dev)) {
+		if (I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT)
+			return (I915_READ(PIPEB_PP_STATUS) & PP_ON) != 0;
+		else
+			return (I915_READ(PIPEA_PP_STATUS) & PP_ON) != 0;
+	} else
+		return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
-- 
1.7.5.4

[PATCH 11/25] drm/i915: Enable HDMI on ValleyView

[Jesse Barnes]

From: Shobhit Kumar <shobhit.kumar@intel.com>

HDMI register offsets are different in Valleyview. Add support for the
same.

Signed-off-by: Beeresh G <beeresh.g@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h   |   16 +++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |   39 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 54 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c187398..f04bfbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3452,6 +3452,21 @@
 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
+#define VLV_VIDEO_DIP_CTL_A		0x60220
+#define VLV_VIDEO_DIP_DATA_A		0x60208
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
+
+#define VLV_VIDEO_DIP_CTL_B		0x61170
+#define VLV_VIDEO_DIP_DATA_B		0x61174
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
+
+#define VLV_TVIDEO_DIP_CTL(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
+#define VLV_TVIDEO_DIP_DATA(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
+#define VLV_TVIDEO_DIP_GCP(pipe) \
+	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
 #define _TRANS_HSYNC_B           0xe1008
@@ -3672,6 +3687,7 @@
 #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
 
 /* or SDVOB */
+#define VLV_HDMIB 0x61140
 #define HDMIB   0xe1140
 #define  PORT_ENABLE    (1 << 31)
 #define  TRANSCODER(pipe)       ((pipe) << 30)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..3f4a2d2 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -177,6 +177,37 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
 
 	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
 }
+
+static void vlv_write_infoframe(struct drm_encoder *encoder,
+				     struct dip_infoframe *frame)
+{
+	uint32_t *data = (uint32_t *)frame;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = encoder->crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	unsigned i, len = DIP_HEADER_SIZE + frame->len;
+	u32 flags, val = I915_READ(reg);
+
+	intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+	flags = intel_infoframe_index(frame);
+
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+
+	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+		data++;
+	}
+
+	flags |= intel_infoframe_flags(frame);
+
+	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+}
+
 static void intel_set_infoframe(struct drm_encoder *encoder,
 				struct dip_infoframe *frame)
 {
@@ -522,10 +553,12 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
 	/* Set up the DDC bus. */
+	/* For VLV SDVOB == HDMIB */
 	if (sdvox_reg == SDVOB) {
 		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
 		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
+	/* For VLV SDVOC == HDMIC */
 	} else if (sdvox_reg == SDVOC) {
 		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
 		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
@@ -549,7 +582,11 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 	if (!HAS_PCH_SPLIT(dev)) {
 		intel_hdmi->write_infoframe = i9xx_write_infoframe;
 		I915_WRITE(VIDEO_DIP_CTL, 0);
-	} else {
+	} else if (IS_VALLEYVIEW(dev)) {
+		intel_hdmi->write_infoframe = vlv_write_infoframe;
+		for_each_pipe(i)
+			I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
+	}  else {
 		intel_hdmi->write_infoframe = ironlake_write_infoframe;
 		for_each_pipe(i)
 			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
-- 
1.7.5.4

[PATCH 12/25] agp/intel: map more registers for use by the GTT code

[Jesse Barnes]

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
register for doing so is above the range we normally map.  Map the whole
register space to make sure we can get it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-gtt.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac..19b6486 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1211,7 +1211,7 @@ static int i9xx_setup(void)
 
 	reg_addr &= 0xfff80000;
 
-	intel_private.registers = ioremap(reg_addr, 128 * 4096);
+	intel_private.registers = ioremap(reg_addr, MB(2));
 	if (!intel_private.registers)
 		return -ENOMEM;
 
-- 
1.7.5.4

[PATCH 13/25] agp/intel: add Valleyview specific PTE entry function

[Jesse Barnes]

On VLV we need to flush the TLBs of the Gunit when updating PTEs.  We
could put this off until we've written a whole block of entries, but we
don't currently have a nice place to put that.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-agp.h |    1 +
 drivers/char/agp/intel-gtt.c |   19 ++++++++++++++++++-
 2 files changed, 19 insertions(+), 1 deletions(-)

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5da67f1..4c0854d 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -96,6 +96,7 @@
 #define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
 
 #define GFX_FLSH_CNTL		0x2170 /* 915+ */
+#define GFX_FLSH_CNTL_VLV	0x0x101008
 
 #define I810_DRAM_CTL		0x3000
 #define I810_DRAM_ROW_0		0x00000001
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 19b6486..8d5bef3 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1179,6 +1179,23 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 	writel(addr | pte_flags, intel_private.gtt + entry);
 }
 
+static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
+				   unsigned int flags)
+{
+	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
+	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
+	u32 pte_flags;
+
+	if (type_mask == AGP_USER_MEMORY)
+		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+
+	/* gen6 has bit11-4 for physical addr bit39-32 */
+	addr |= (addr >> 28) & 0xff0;
+	writel(addr | pte_flags, intel_private.gtt + entry);
+
+	writel(1, intel_private.registers + GFX_FLUSH_CNTL_VLV);
+}
+
 static void gen6_cleanup(void)
 {
 }
@@ -1350,7 +1367,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
 	.gen = 6,
 	.setup = i9xx_setup,
 	.cleanup = gen6_cleanup,
-	.write_entry = gen6_write_entry,
+	.write_entry = valleyview_write_entry,
 	.dma_mask_size = 40,
 	.check_flags = gen6_check_flags,
 	.chipset_flush = i9xx_chipset_flush,
-- 
1.7.5.4

[PATCH 14/25] agp/intel: always use uncached mappings on VLV

[Jesse Barnes]

Until the snoopable ones are debugged.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-gtt.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 8d5bef3..25911a1 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1186,8 +1186,7 @@ static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
 	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
 	u32 pte_flags;
 
-	if (type_mask == AGP_USER_MEMORY)
-		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
 
 	/* gen6 has bit11-4 for physical addr bit39-32 */
 	addr |= (addr >> 28) & 0xff0;
-- 
1.7.5.4

[PATCH 15/25] drm/i915: add ValleyView specific CRT detect function

[Jesse Barnes]

Might be able to merge this back in at some point, but we're seeing bugs
with ADPA based detection, so keep it separate for now with explicit
hotplug trigger usage.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_crt.c |   40 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4d3d736..4d33398 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -212,6 +212,41 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 	return ret;
 }
 
+static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 adpa;
+	bool ret;
+	u32 save_adpa;
+
+	save_adpa = adpa = I915_READ(ADPA);
+	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
+
+	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
+
+	I915_WRITE(ADPA, adpa);
+
+	if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
+		     1000)) {
+		DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
+		I915_WRITE(ADPA, save_adpa);
+	}
+
+	/* Check the status to see if both blue and green are on now */
+	adpa = I915_READ(ADPA);
+	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
+		ret = true;
+	else
+		ret = false;
+
+	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
+
+	ret = true;
+
+	return ret;
+}
+
 /**
  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  *
@@ -231,6 +266,9 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 	if (HAS_PCH_SPLIT(dev))
 		return intel_ironlake_crt_detect_hotplug(connector);
 
+	if (IS_VALLEYVIEW(dev))
+		return valleyview_crt_detect_hotplug(connector);
+
 	/*
 	 * On 4 series desktop, CRT detect sequence need to be done twice
 	 * to get a reliable result.
@@ -300,6 +338,8 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
 		} else {
 			DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 		}
+	} else {
+		DRM_DEBUG_KMS("ddc probe failed\n");
 	}
 
 	return false;
-- 
1.7.5.4

[PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

[Jesse Barnes]

ValleyView handles force wake differently than previous chipsets, so add
a couple of new functions for it.

But it's also untested, so no need to call these untested functions yet.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c      |   28 +++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h      |    3 +++
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 4 files changed, 34 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b83a0dc..e4fa294 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -462,6 +462,31 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+void vlv_force_wake_get(struct drm_i915_private *dev_priv)
+{
+	int count;
+
+	count = 0;
+
+	/* Already awake? */
+	if ((I915_READ(0x130094) & 0xa1) == 0xa1)
+		return;
+
+	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
+	POSTING_READ(FORCEWAKE_VLV);
+
+	count = 0;
+	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
+		udelay(10);
+}
+
+void vlv_force_wake_put(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
+	/* FIXME: confirm VLV behavior with Punit folks */
+	POSTING_READ(FORCEWAKE_VLV);
+}
+
 static int i915_drm_freeze(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1004,7 +1029,8 @@ MODULE_LICENSE("GPL and additional rights");
 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
        (((dev_priv)->info->gen >= 6) && \
         ((reg) < 0x40000) &&            \
-        ((reg) != FORCEWAKE))
+        ((reg) != FORCEWAKE)) && \
+       (!IS_VALLEYVIEW((dev_priv)->dev))
 
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b8b32d..178a955 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1394,6 +1394,9 @@ extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
 
+extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
+extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
+
 /* overlay */
 #ifdef CONFIG_DEBUG_FS
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f04bfbf..e9be070 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3865,6 +3865,8 @@
 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
 
 #define  FORCEWAKE				0xA18C
+#define  FORCEWAKE_VLV				0x1300b0
+#define  FORCEWAKE_ACK_VLV			0x1300b4
 #define  FORCEWAKE_ACK				0x130090
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define  FORCEWAKE_MT_ACK			0x130040
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efb6465..6e6f8b0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9433,6 +9433,8 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.update_wm = valleyview_update_wm;
 		dev_priv->display.init_clock_gating =
 			valleyview_init_clock_gating;
+		dev_priv->display.force_wake_get = vlv_force_wake_get;
+		dev_priv->display.force_wake_put = vlv_force_wake_put;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
-- 
1.7.5.4

[PATCH 17/25] drm/i915: ValleyView cacheability is different

[Jesse Barnes]

The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
it does writes, so we can't use the cache bits the same way.

So map the status and pipe control pages as uncached on ValleyView, and
only set the pages to cached if we're on a supported platform.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c         |    2 +
 drivers/gpu/drm/i915/intel_ringbuffer.c |   35 ++++++++++++++++++++++++------
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e4fa294..a636703 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -255,6 +255,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.is_valleyview = 1,
+	.has_llc = 0,
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
@@ -264,6 +265,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.is_valleyview = 1,
+	.has_llc = 0,
 };
 
 static const struct pci_device_id pciidlist[] = {		/* aka */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ca3972f..f52abc4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
 {
 	struct pipe_control *pc;
 	struct drm_i915_gem_object *obj;
+	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
+	struct drm_device *dev;
 	int ret;
 
 	if (ring->private)
@@ -335,14 +337,19 @@ init_pipe_control(struct intel_ring_buffer *ring)
 		goto err;
 	}
 
-	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+	i915_gem_object_set_cache_level(obj, cache_level);
 
 	ret = i915_gem_object_pin(obj, 4096, true);
 	if (ret)
 		goto err_unref;
-
+	dev = obj->base.dev;
 	pc->gtt_offset = obj->gtt_offset;
-	pc->cpu_page =  kmap(obj->pages[0]);
+	if (!HAS_LLC(ring->dev))
+		pc->cpu_page = ioremap(dev->agp->base +
+				       obj->gtt_offset,
+				       PAGE_SIZE);
+	else
+		pc->cpu_page =  kmap(obj->pages[0]);
 	if (pc->cpu_page == NULL)
 		goto err_unpin;
 
@@ -364,12 +371,17 @@ cleanup_pipe_control(struct intel_ring_buffer *ring)
 {
 	struct pipe_control *pc = ring->private;
 	struct drm_i915_gem_object *obj;
+	struct drm_device *dev;
 
 	if (!ring->private)
 		return;
 
 	obj = pc->obj;
-	kunmap(obj->pages[0]);
+	dev = obj->base.dev;
+	if (IS_VALLEYVIEW(dev))
+		iounmap(pc->cpu_page);
+	else
+		kunmap(obj->pages[0]);
 	i915_gem_object_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
 
@@ -929,7 +941,10 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
 	if (obj == NULL)
 		return;
 
-	kunmap(obj->pages[0]);
+	if (IS_VALLEYVIEW(dev_priv->dev))
+		iounmap(ring->status_page.page_addr);
+	else
+		kunmap(obj->pages[0]);
 	i915_gem_object_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
 	ring->status_page.obj = NULL;
@@ -942,6 +957,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
+	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
 	int ret;
 
 	obj = i915_gem_alloc_object(dev, 4096);
@@ -951,7 +967,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
 		goto err;
 	}
 
-	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+	i915_gem_object_set_cache_level(obj, cache_level);
 
 	ret = i915_gem_object_pin(obj, 4096, true);
 	if (ret != 0) {
@@ -959,7 +975,12 @@ static int init_status_page(struct intel_ring_buffer *ring)
 	}
 
 	ring->status_page.gfx_addr = obj->gtt_offset;
-	ring->status_page.page_addr = kmap(obj->pages[0]);
+	if (!HAS_LLC(ring->dev))
+		ring->status_page.page_addr = ioremap(dev->agp->base +
+						      obj->gtt_offset,
+						      PAGE_SIZE);
+	else
+		ring->status_page.page_addr = kmap(obj->pages[0]);
 	if (ring->status_page.page_addr == NULL) {
 		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 		goto err_unpin;
-- 
1.7.5.4

[PATCH 18/25] drm/i915: ValleyView IRQ support

[Jesse Barnes]

ValleyView has a new interrupt architecture; best to put it in a new set
of functions.  Also make sure the ring mask functions handle ValleyView.

FIXME: fix flipping; need to enable interrupts and call prepare/finish

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |   40 ++++-
 drivers/gpu/drm/i915/i915_irq.c         |  338 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h         |    5 +
 drivers/gpu/drm/i915/intel_ringbuffer.c |    4 +-
 4 files changed, 382 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdb7cce..6d47f51 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -468,7 +468,45 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 	if (ret)
 		return ret;
 
-	if (!HAS_PCH_SPLIT(dev)) {
+	if (IS_VALLEYVIEW(dev)) {
+		seq_printf(m, "Display IER:\t%08x\n",
+			   I915_READ(IER_VLV));
+		seq_printf(m, "Display IIR:\t%08x\n",
+			   I915_READ(IIR_VLV));
+		seq_printf(m, "Display IIR_RW:\t%08x\n",
+			   I915_READ(IIR_VLV_RW));
+		seq_printf(m, "Display IMR:\t%08x\n",
+			   I915_READ(IMR_VLV));
+		for_each_pipe(pipe)
+			seq_printf(m, "Pipe %c stat:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(PIPESTAT(pipe)));
+
+		seq_printf(m, "Master IER:\t%08x\n",
+			   I915_READ(MASTER_IER_VLV));
+
+		seq_printf(m, "Render IER:\t%08x\n",
+			   I915_READ(GTIER));
+		seq_printf(m, "Render IIR:\t%08x\n",
+			   I915_READ(GTIIR));
+		seq_printf(m, "Render IMR:\t%08x\n",
+			   I915_READ(GTIMR));
+
+		seq_printf(m, "PM IER:\t\t%08x\n",
+			   I915_READ(GEN6_PMIER));
+		seq_printf(m, "PM IIR:\t\t%08x\n",
+			   I915_READ(GEN6_PMIIR));
+		seq_printf(m, "PM IMR:\t\t%08x\n",
+			   I915_READ(GEN6_PMIMR));
+
+		seq_printf(m, "Port hotplug:\t%08x\n",
+			   I915_READ(PORT_HOTPLUG_EN));
+		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
+			   I915_READ(DPFLIPSTAT));
+		seq_printf(m, "DPINVGTT:\t%08x\n",
+			   I915_READ(DPINVGTT));
+
+	} else if (!HAS_PCH_SPLIT(dev)) {
 		seq_printf(m, "Interrupt enable:    %08x\n",
 			   I915_READ(IER));
 		seq_printf(m, "Interrupt identity:  %08x\n",
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index afd4e03..11422ef 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -118,6 +118,10 @@ void intel_enable_asle(struct drm_device *dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long irqflags;
 
+	/* FIXME: opregion/asle for VLV */
+	if (IS_VALLEYVIEW(dev))
+		return;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 
 	if (HAS_PCH_SPLIT(dev))
@@ -424,6 +428,119 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 
+static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
+{
+	struct drm_device *dev = (struct drm_device *) arg;
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	u32 iir, gt_iir, pm_iir;
+	irqreturn_t ret = IRQ_NONE;
+	unsigned long irqflags;
+	int pipe;
+	u32 pipe_stats[I915_MAX_PIPES];
+	u32 vblank_status;
+	int vblank = 0;
+	bool blc_event;
+
+	atomic_inc(&dev_priv->irq_received);
+
+	vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
+		PIPE_VBLANK_INTERRUPT_STATUS;
+
+	while (true) {
+		iir = I915_READ(IIR_VLV);
+		gt_iir = I915_READ(GTIIR);
+		pm_iir = I915_READ(GEN6_PMIIR);
+
+		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
+			goto out;
+
+		ret = IRQ_HANDLED;
+
+		if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+			notify_ring(dev, &dev_priv->ring[RCS]);
+		if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
+			notify_ring(dev, &dev_priv->ring[VCS]);
+		if (gt_iir & GT_BLT_USER_INTERRUPT)
+			notify_ring(dev, &dev_priv->ring[BCS]);
+
+		if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
+			      GT_BSD_CS_ERROR_INTERRUPT |
+			      GT_RENDER_CS_ERROR_INTERRUPT)) {
+			DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
+			i915_handle_error(dev, false);
+		}
+
+		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+		for_each_pipe(pipe) {
+			int reg = PIPESTAT(pipe);
+			pipe_stats[pipe] = I915_READ(reg);
+
+			/*
+			 * Clear the PIPE*STAT regs before the IIR
+			 */
+			if (pipe_stats[pipe] & 0x8000ffff) {
+				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+					DRM_DEBUG_DRIVER("pipe %c underrun\n",
+							 pipe_name(pipe));
+				I915_WRITE(reg, pipe_stats[pipe]);
+			}
+		}
+		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+		/* Consume port.  Then clear IIR or we'll miss events */
+		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
+			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
+
+			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
+					 hotplug_status);
+			if (hotplug_status & dev_priv->hotplug_supported_mask)
+				queue_work(dev_priv->wq,
+					   &dev_priv->hotplug_work);
+
+			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
+			I915_READ(PORT_HOTPLUG_STAT);
+		}
+
+
+		if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
+			drm_handle_vblank(dev, 0);
+			vblank++;
+			if (!dev_priv->flip_pending_is_done) {
+				intel_finish_page_flip(dev, 0);
+			}
+		}
+
+		if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
+			drm_handle_vblank(dev, 1);
+			vblank++;
+			if (!dev_priv->flip_pending_is_done) {
+				intel_finish_page_flip(dev, 0);
+			}
+		}
+
+		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+			blc_event = true;
+
+		if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
+			unsigned long flags;
+			spin_lock_irqsave(&dev_priv->rps_lock, flags);
+			WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
+			dev_priv->pm_iir |= pm_iir;
+			I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
+			POSTING_READ(GEN6_PMIMR);
+			spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
+			queue_work(dev_priv->wq, &dev_priv->rps_work);
+		}
+
+		I915_WRITE(GTIIR, gt_iir);
+		I915_WRITE(GEN6_PMIIR, pm_iir);
+		I915_WRITE(IIR_VLV, iir);
+	}
+
+out:
+	return ret;
+}
+
 static void pch_irq_handler(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1582,6 +1699,32 @@ static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
 	return 0;
 }
 
+static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+	u32 dpfl, imr;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return -EINVAL;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	dpfl = I915_READ(DPFLIPSTAT);
+	imr = I915_READ(IMR_VLV);
+	if (pipe == 0) {
+		dpfl |= PIPEA_VBLANK_INT_EN;
+		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
+	} else {
+		dpfl |= PIPEA_VBLANK_INT_EN;
+		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
+	}
+	I915_WRITE(DPFLIPSTAT, dpfl);
+	I915_WRITE(IMR_VLV, imr);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+	return 0;
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -1623,6 +1766,28 @@ static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+	u32 dpfl, imr;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	dpfl = I915_READ(DPFLIPSTAT);
+	imr = I915_READ(IMR_VLV);
+	if (pipe == 0) {
+		dpfl &= ~PIPEA_VBLANK_INT_EN;
+		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
+	} else {
+		dpfl &= ~PIPEB_VBLANK_INT_EN;
+		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
+	}
+	I915_WRITE(IMR_VLV, imr);
+	I915_WRITE(DPFLIPSTAT, dpfl);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
+
 /* Set the vblank monitor pipe
  */
 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
@@ -1832,6 +1997,53 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 	POSTING_READ(SDEIER);
 }
 
+static void valleyview_irq_preinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int pipe;
+
+	atomic_set(&dev_priv->irq_received, 0);
+
+	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+
+	/* VLV magic */
+	I915_WRITE(IMR_VLV, 0);
+	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
+	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
+	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
+
+	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+		/* Workaround stalls observed on Sandy Bridge GPUs by
+		 * making the blitter command streamer generate a
+		 * write to the Hardware Status Page for
+		 * MI_USER_INTERRUPT.  This appears to serialize the
+		 * previous seqno write out before the interrupt
+		 * happens.
+		 */
+		I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
+		I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
+	}
+
+	/* and GT */
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIMR, 0xffffffff);
+	I915_WRITE(GTIER, 0x0);
+	POSTING_READ(GTIER);
+
+	I915_WRITE(DPINVGTT, 0xff);
+
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+	I915_WRITE(IIR_VLV, 0xffffffff);
+	I915_WRITE(IMR_VLV, 0xffffffff);
+	I915_WRITE(IER_VLV, 0x0);
+	POSTING_READ(IER_VLV);
+}
+
 /*
  * Enable digital hotplug on the PCH, and configure the DP short pulse
  * duration to 2ms (which is the minimum in the Display Port spec)
@@ -1978,6 +2190,96 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static int valleyview_irq_postinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	u32 render_irqs;
+	u32 enable_mask;
+	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
+	u16 msid;
+
+	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
+	enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
+
+	dev_priv->irq_mask = ~enable_mask;
+
+
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+	dev_priv->pipestat[0] = 0;
+	dev_priv->pipestat[1] = 0;
+
+	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+
+	/* Hack for broken MSIs on VLV */
+	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
+	pci_read_config_word(dev->pdev, 0x98, &msid);
+	msid &= 0xff; /* mask out delivery bits */
+	msid |= (1<<14);
+	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
+
+	I915_WRITE(IMR_VLV, dev_priv->irq_mask);
+	I915_WRITE(IER_VLV, enable_mask);
+	I915_WRITE(IIR_VLV, 0xffffffff);
+	I915_WRITE(PIPESTAT(0), 0xffff);
+	I915_WRITE(PIPESTAT(1), 0xffff);
+	POSTING_READ(IER_VLV);
+
+	I915_WRITE(IIR_VLV, 0xffffffff);
+	I915_WRITE(IIR_VLV, 0xffffffff);
+
+	render_irqs = GT_BLT_FLUSHDW_NOTIFY_INTERRUPT |
+		GT_BLT_CS_ERROR_INTERRUPT |
+		GT_BLT_USER_INTERRUPT |
+		GT_GEN6_BSD_USER_INTERRUPT |
+		GT_BSD_CS_ERROR_INTERRUPT |
+		GT_L3_PARITY_ERROR_INTERRUPT |
+		GT_PIPE_NOTIFY |
+		GT_RENDER_CS_ERROR_INTERRUPT |
+		GT_SYNC_STATUS |
+		GT_USER_INTERRUPT;
+
+	dev_priv->gt_irq_mask = ~render_irqs;
+
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIMR, 0);
+	I915_WRITE(GTIER, render_irqs);
+	POSTING_READ(GTIER);
+
+	/* ack & enable invalid PTE error interrupts */
+#if 0 /* FIXME: add support to irq handler for checking these bits */
+	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
+	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
+#endif
+
+	I915_WRITE(MASTER_IER_VLV, MASTER_INTERRUPT_ENABLE);
+#if 0 /* FIXME: check register definitions; some have moved */
+	/* Note HDMI and DP share bits */
+	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+		hotplug_en |= HDMID_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
+		hotplug_en |= CRT_HOTPLUG_INT_EN;
+		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+	}
+#endif
+
+	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
+
+	return 0;
+}
+
 static void i915_driver_irq_preinstall(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2081,6 +2383,30 @@ static int i915_driver_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void valleyview_irq_uninstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int pipe;
+
+	if (!dev_priv)
+		return;
+
+	dev_priv->vblank_pipe = 0;
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	I915_WRITE(HWSTAM, 0xffffffff);
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+	I915_WRITE(IIR_VLV, 0xffffffff);
+	I915_WRITE(IMR_VLV, 0xffffffff);
+	I915_WRITE(IER_VLV, 0x0);
+	POSTING_READ(IER_VLV);
+}
+
 static void ironlake_irq_uninstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2136,7 +2462,8 @@ void intel_irq_init(struct drm_device *dev)
 {
 	dev->driver->get_vblank_counter = i915_get_vblank_counter;
 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
+	    IS_VALLEYVIEW(dev)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
 	}
@@ -2147,7 +2474,14 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->get_vblank_timestamp = NULL;
 	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_VALLEYVIEW(dev)) {
+		dev->driver->irq_handler = valleyview_irq_handler;
+		dev->driver->irq_preinstall = valleyview_irq_preinstall;
+		dev->driver->irq_postinstall = valleyview_irq_postinstall;
+		dev->driver->irq_uninstall = valleyview_irq_uninstall;
+		dev->driver->enable_vblank = valleyview_enable_vblank;
+		dev->driver->disable_vblank = valleyview_disable_vblank;
+	} else if (IS_IVYBRIDGE(dev)) {
 		/* Share pre & uninstall handlers with ILK/SNB */
 		dev->driver->irq_handler = ivybridge_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9be070..df258ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -510,6 +510,11 @@
 #define IIR		0x020a4
 #define IMR		0x020a8
 #define ISR		0x020ac
+#define IIR_VLV_RW	0x182084
+#define IER_VLV		0x1820a0
+#define IIR_VLV		0x1820a4
+#define IMR_VLV		0x1820a8
+#define ISR_VLV		0x1820ac
 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f52abc4..72cff2a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -699,7 +699,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
 
 	spin_lock(&ring->irq_lock);
 	if (ring->irq_refcount++ == 0) {
-		if (HAS_PCH_SPLIT(dev))
+		if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
 			ironlake_enable_irq(dev_priv,
 					    GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 		else
@@ -718,7 +718,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
 
 	spin_lock(&ring->irq_lock);
 	if (--ring->irq_refcount == 0) {
-		if (HAS_PCH_SPLIT(dev))
+		if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
 			ironlake_disable_irq(dev_priv,
 					     GT_USER_INTERRUPT |
 					     GT_PIPE_NOTIFY);
-- 
1.7.5.4

[PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

[Jesse Barnes]

Although internally the MMIO offsets for display regs haven't changed,
their visibility through the PCI BAR has been affected by the addition
of the Gunit, which occupies the low part of the address space.

Display regs on VLV are offset into the BAR by 0x180000, so we need to
add that for any display register offset.

This patch is a hack to do just that, but ultimately we need to split
our display and render code more cleanly and add accessor functions for
them.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |   83 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a636703..48fc5ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1034,6 +1034,80 @@ MODULE_LICENSE("GPL and additional rights");
         ((reg) != FORCEWAKE)) && \
        (!IS_VALLEYVIEW((dev_priv)->dev))
 
+static bool IS_DISPLAYREG(u32 reg)
+{
+	if (reg >= RENDER_RING_BASE &&
+	    reg < RENDER_RING_BASE + 0xff)
+		return false;
+	if (reg >= GEN6_BSD_RING_BASE &&
+	    reg < GEN6_BSD_RING_BASE + 0xff)
+		return false;
+	if (reg >= BLT_RING_BASE &&
+	    reg < BLT_RING_BASE + 0xff)
+		return false;
+
+	if (reg == PGTBL_ER)
+		return false;
+
+	if (reg >= IPEIR_I965 &&
+	    reg < HWSTAM)
+		return false;
+
+	if (reg == MI_MODE)
+		return false;
+
+	if (reg == GFX_MODE_GEN7)
+		return false;
+
+	if (reg == RENDER_HWS_PGA_GEN7 ||
+	    reg == BSD_HWS_PGA_GEN7 ||
+	    reg == BLT_HWS_PGA_GEN7)
+		return false;
+
+	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
+	    reg == GEN6_BSD_RNCID)
+		return false;
+
+	if (reg == GEN6_BLITTER_ECOSKPD)
+		return false;
+
+	if (reg >= 0x4000c &&
+	    reg <= 0x4002c)
+		return false;
+
+	if (reg >= 0x4f000 &&
+	    reg <= 0x4f08f)
+		return false;
+
+	if (reg >= 0x4f100 &&
+	    reg <= 0x4f11f)
+		return false;
+
+	if (reg >= MASTER_IER_VLV &&
+	    reg <= GEN6_PMIER)
+		return false;
+
+	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
+	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
+		return false;
+
+	if (reg >= IIR_VLV_RW &&
+	    reg <= ISR_VLV)
+		return false;
+
+	if (reg == MASTER_IER_VLV)
+		return false;
+
+	if (reg == FORCEWAKE_VLV ||
+	    reg == FORCEWAKE_ACK_VLV)
+		return false;
+
+	if (reg == GEN6_GDRST)
+		return false;
+
+	return true;
+}
+
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 	u##x val = 0; \
@@ -1046,6 +1120,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 		if (dev_priv->forcewake_count == 0) \
 			dev_priv->display.force_wake_put(dev_priv); \
 		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
+	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
+		val = read##y(dev_priv->regs + reg + 0x180000);		\
 	} else { \
 		val = read##y(dev_priv->regs + reg); \
 	} \
@@ -1065,8 +1141,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-	} \
-	write##y(val, dev_priv->regs + reg); \
+	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
+		write##y(val, dev_priv->regs + reg + 0x180000);		\
+	} else {							\
+		write##y(val, dev_priv->regs + reg);			\
+	}								\
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
-- 
1.7.5.4

[PATCH 20/25] drm/i915: check for disabled interrupts on ValleyView

[Jesse Barnes]

Haven't seen this yet, but it doesn't hurt.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1f441f5..f47a28b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1951,6 +1951,8 @@ i915_wait_request(struct intel_ring_buffer *ring,
 	if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 		if (HAS_PCH_SPLIT(ring->dev))
 			ier = I915_READ(DEIER) | I915_READ(GTIER);
+		else if (IS_VALLEYVIEW(ring->dev))
+			ier = I915_READ(GTIER) | I915_READ(IER_VLV);
 		else
 			ier = I915_READ(IER);
 		if (!ier) {
-- 
1.7.5.4

[PATCH 21/25] drm/i915: add HDMI and DP port enumeration on ValleyView

[Jesse Barnes]

ValleyView is similar to IbexPeak here, but with different register
offsets.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e6f8b0..58accf5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8303,6 +8303,24 @@ static void intel_setup_outputs(struct drm_device *dev)
 		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
 			intel_dp_init(dev, PCH_DP_D);
 
+	} else if (IS_VALLEYVIEW(dev)) {
+		int found;
+
+		if (I915_READ(VLV_HDMIB) & PORT_DETECTED) {
+			/* SDVOB multiplex with HDMIB */
+			found = intel_sdvo_init(dev, VLV_HDMIB);
+			if (!found)
+				intel_hdmi_init(dev, VLV_HDMIB);
+			if (!found && (I915_READ(DP_B) & DP_DETECTED))
+				intel_dp_init(dev, DP_B);
+		}
+
+		if (I915_READ(SDVOC) & PORT_DETECTED)
+			intel_hdmi_init(dev, SDVOC);
+
+		/* Shares lanes with HDMI on SDVOC */
+		if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED))
+			intel_dp_init(dev, DP_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
-- 
1.7.5.4

[PATCH 22/25] drm/i915: remove some unneeded debug messages

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 58accf5..541c0a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2075,14 +2075,14 @@ static void intel_update_fbc(struct drm_device *dev)
 	struct drm_i915_gem_object *obj;
 	int enable_fbc;
 
-	DRM_DEBUG_KMS("\n");
-
 	if (!i915_powersave)
 		return;
 
 	if (!I915_HAS_FBC(dev))
 		return;
 
+	DRM_DEBUG_KMS("\n");
+
 	/*
 	 * If FBC is already on, we just have to verify that we can
 	 * keep it that way...
-- 
1.7.5.4

[PATCH 23/25] drm/i915: add ValleyView clock gating init

[Jesse Barnes]

Set the same bits as IVB plus a few others.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |   18 +++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   41 ++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df258ab..4aa6d1d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -638,6 +638,9 @@
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
+#define CACHE_MODE_1		0x7004 /* IVB+ */
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
+
 /* GEN6 interrupt control */
 #define GEN6_RENDER_HWSTAM	0x2098
 #define GEN6_RENDER_IMR		0x20a8
@@ -3255,6 +3258,20 @@
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
 
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
+# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
+
+#define GEN7_L3CNTLREG1				0xB01C
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+
+/* WaCatErrorRejectionIssue */
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
+#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
+
 /* PCH */
 
 /* south display engine interrupt */
@@ -3888,6 +3905,7 @@
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
 
 #define GEN6_UCGCTL2				0x9404
+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 541c0a6..8668d38 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8939,6 +8939,47 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+	I915_WRITE(WM3_LP_ILK, 0);
+	I915_WRITE(WM2_LP_ILK, 0);
+	I915_WRITE(WM1_LP_ILK, 0);
+
+	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
+	 * This implements the WaDisableRCZUnitClockGating workaround.
+	 */
+	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+
+	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
+
+	I915_WRITE(IVB_CHICKEN3,
+		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
+		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
+
+	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
+	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+
+	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
+	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
+
+	/* This is required by WaCatErrorRejectionIssue */
+	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+
+	for_each_pipe(pipe) {
+		I915_WRITE(DSPCNTR(pipe),
+			   I915_READ(DSPCNTR(pipe)) |
+			   DISPPLANE_TRICKLE_FEED_DISABLE);
+		intel_flush_display_plane(dev_priv, pipe);
+	}
+
 	return;
 }
 
-- 
1.7.5.4

[PATCH 24/25] drm/i915: add has_turbo bit to driver info struct

[Jesse Barnes]

Since ValleyView is a gen7 chip but doesn't have the same turbo interface.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c      |    4 ++++
 drivers/gpu/drm/i915/i915_drv.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 3 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 48fc5ab..6c92ded 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -220,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_turbo = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
@@ -229,6 +230,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_turbo = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_d_info = {
@@ -237,6 +239,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_turbo = 1,
 };
 
 static const struct intel_device_info intel_ivybridge_m_info = {
@@ -246,6 +249,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.has_llc = 1,
+	.has_turbo = 1,
 };
 
 static const struct intel_device_info intel_valleyview_m_info = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 178a955..024f574 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -266,6 +266,7 @@ struct intel_device_info {
 	u8 has_bsd_ring:1;
 	u8 has_blt_ring:1;
 	u8 has_llc:1;
+	u8 has_turbo:1;
 };
 
 #define I915_PPGTT_PD_ENTRIES 512
@@ -1025,6 +1026,7 @@ struct drm_i915_file_private {
 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
+#define HAS_TURBO(dev)		(INTEL_INFO(dev)->has_turbo)
 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >=6)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8668d38..dc0ef17 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9715,7 +9715,7 @@ void intel_modeset_init(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	if (HAS_TURBO(dev)) {
 		gen6_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
 	}
-- 
1.7.5.4

[PATCH 25/25] drm/i915: don't write ring regs until they're set up

[Jesse Barnes]

intel_clear_scanline_wait tries to clear ring wait conditions when we
turn off pipes, to prevent hanging WAIT_EVENT and similar commands.  But
we call it early before rings have been setup during initialization and
shouldn't touch the ring regs yet.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dc0ef17..1a8cb30 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3098,6 +3098,10 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
 
 	ring = LP_RING(dev_priv);
 
+	/* This may be called before rings are initialized */
+	if (!ring->mmio_base)
+		return;
+
 	tmp = I915_READ_CTL(ring);
 	if (tmp & RING_WAIT)
 		I915_WRITE_CTL(ring, tmp);
-- 
1.7.5.4

Re: [PATCH 01/25] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 372 bytes --]

On Wed, Mar 21, 2012 at 16:48, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> It's only used by the main read/write functions, so we can keep it with
> them.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

(One patch less from my own series to send).

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

[-- Attachment #1.2: Type: text/html, Size: 830 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02/25] drm/i915: add debug message when EDID fetch fails

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 394 bytes --]

On Wed, Mar 21, 2012 at 16:48, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> +       } else {

+               DRM_DEBUG_KMS("failed to fetch edid\n");
>        }
>


Wouldn't it be prettier if we also add some:
   ...
   err = -ENXIO;

or similar error in that block, to let the caller know that we failed as
well?


>        return ret;
>

-- 
Eugeni Dodonov
 <http://eugeni.dodonov.net/>

[-- Attachment #1.2: Type: text/html, Size: 1052 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:27PM -0700, Jesse Barnes wrote:
> ValleyView is a CedarView-like chip but with an Ivybridge graphics core.
> This patch adds initial framework for supporting this chip.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c      |   21 +++++++++
>  drivers/gpu/drm/i915/i915_drv.h      |    2 +
>  drivers/gpu/drm/i915/i915_reg.h      |   59 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   82 +++++++++++++++++++++++++++++++++-
>  4 files changed, 163 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 06533cb..b83a0dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -248,6 +248,24 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.has_llc = 1,
>  };
>  
> +static const struct intel_device_info intel_valleyview_m_info = {
> +	.gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_fbc = 0,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.is_valleyview = 1,
> +};
> +
> +static const struct intel_device_info intel_valleyview_d_info = {
> +	.gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_fbc = 0,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.is_valleyview = 1,
> +};
> +
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
>  	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
> @@ -292,6 +310,9 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
>  	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
>  	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
> +	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
> +	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
> +	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),

This should be in the last patch.

>  	{0, 0, 0}
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0294330..2b8b32d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -255,6 +255,7 @@ struct intel_device_info {
>  	u8 is_broadwater:1;
>  	u8 is_crestline:1;
>  	u8 is_ivybridge:1;
> +	u8 is_valleyview:1;
>  	u8 has_fbc:1;
>  	u8 has_pipe_cxsr:1;
>  	u8 has_hotplug:1;
> @@ -1005,6 +1006,7 @@ struct drm_i915_file_private {
>  #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
>  #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
>  #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
> +#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ad6b5e0..7d33c49 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -851,8 +851,11 @@
>  #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
>  #define   DPLL_VCO_ENABLE		(1 << 31)
>  #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
> +#define   DPLL_EXT_BUFFER_ENABLE	(1 << 30) /* VLV */
>  #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
> +#define   DPLL_REFA_CLK_ENABLE		(1 << 29) /* VLV */
>  #define   DPLL_VGA_MODE_DIS		(1 << 28)
> +#define   DPLL_DUAL_PIPE		(1 << 26) /* VLV */

Please postfix VLV bits with _VLV. Afaics new bits in an existing reg are
postfixed with the marketing name/gen/codename of the chip that introduced
them. New regs that fit into existing register blocks are also postfixed.
Completely new regs are usually prefixed.

More of these below.

>  #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
>  #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
>  #define   DPLL_MODE_MASK		(3 << 26)
> @@ -863,6 +866,9 @@
>  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
> +#define   DPLL_VOLTAGE_LDO		(1<<14)
> +#define   DPLL_INTEGRATED_CLOCK		(1<<13)
> +#define   DPLL_RATE_SWITCH		(1<<8)
>  
>  #define SRX_INDEX		0x3c4
>  #define SRX_DATA		0x3c5
> @@ -958,6 +964,9 @@
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
>  #define _DPLL_B_MD 0x06020 /* 965+ only */
>  #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
> +
> +#define RAWCLK_FREQ			0x6024 /* VLV */
> +
>  #define _FPA0	0x06040
>  #define _FPA1	0x06044
>  #define _FPB0	0x06048
> @@ -1098,6 +1107,12 @@
>  #define RAMCLK_GATE_D		0x6210		/* CRL only */
>  #define DEUC			0x6214          /* CRL only */
>  
> +#define FW_BLC_SELF_VLV		0x6500
> +#define  FW_CSPWRDWNEN		(1<<15)
> +#define MI_ARB_VLV		0x6504
> +#define  DISP_TRICKLE_FEED_DIS	(1<<2)
> +#define CZCLK_CDCLK_FREQ_RATIO	0x6508
> +
>  /*
>   * Palette regs
>   */
> @@ -2475,23 +2490,30 @@
>  #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
>  #define _PIPEASTAT		0x70024
>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
> +#define   SPRITE1_FLIPDONE_INT_EN		(1UL<<30) /* VLV only; typo, should be status? */
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
>  #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
>  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
> +#define   PLANE_FLIP_DONE_INT_EN		(1UL<<26) /* VLV only, ?? */
>  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
>  #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
>  #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
>  #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
> +#define   SPRITE0_FLIP_DONE_INT_EN		(1UL<<26) /* VLV only, ?? */
>  #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
>  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
>  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
>  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
> +#define   PIPEA_HBLANK_INT_EN			(1UL<<16) /* VLV only, ?? */
>  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
> +#define   SPRITE1_FLIPDONE_INT_STATUS		(1UL<<15) /* VLV only */
> +#define   SPRITE0_FLIPDONE_INT_STATUS		(1UL<<15) /* VLV only */
>  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
>  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
>  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
> +#define   PLANE_FLIPDONE_INT_STATUS		(1UL<<10) /* VLV only */
>  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
>  #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
>  #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
> @@ -2516,6 +2538,40 @@
>  #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
>  #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
>  
> +#define DPFLIPSTAT				0x70028 /* VLV only */
> +#define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
> +#define   PIPEB_HLINE_INT_EN			(1<<28)
> +#define   PIPEB_VBLANK_INT_EN			(1<<27)
> +#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
> +#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
> +#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
> +#define   PIPEA_LINE_COMPARE_STATUS		(1<<21)
> +#define   PIPEA_HLINE_INT_EN			(1<<20)
> +#define   PIPEA_VBLANK_INT_EN			(1<<19)
> +#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
> +#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
> +#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
> +
> +#define DPINVGTT				0x7002c /* VLV only */
> +#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
> +#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
> +#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
> +#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
> +#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
> +#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
> +#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
> +#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
> +#define   DPINVGTT_EN_MASK			0xff0000
> +#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
> +#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
> +#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
> +#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
> +#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
> +#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
> +#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
> +#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
> +#define   DPINVGTT_STATUS_MASK			0xff
> +
>  #define DSPARB			0x70030
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
> @@ -2550,6 +2606,7 @@
>  #define I915_FIFO_LINE_SIZE	64
>  #define I830_FIFO_LINE_SIZE	32
>  
> +#define VALLEYVIEW_FIFO_SIZE	255
>  #define G4X_FIFO_SIZE		127
>  #define I965_FIFO_SIZE		512
>  #define I945_FIFO_SIZE		127
> @@ -2557,6 +2614,7 @@
>  #define I855GM_FIFO_SIZE	127 /* In cachelines */
>  #define I830_FIFO_SIZE		95
>  
> +#define VALLEYVIEW_MAX_WM	0xff
>  #define G4X_MAX_WM		0x3f
>  #define I915_MAX_WM		0x3f
>  
> @@ -2571,6 +2629,7 @@
>  #define PINEVIEW_CURSOR_DFT_WM	0
>  #define PINEVIEW_CURSOR_GUARD_WM	5
>  
> +#define VALLEYVIEW_CURSOR_MAX_WM 64
>  #define I965_CURSOR_FIFO	64
>  #define I965_CURSOR_MAX_WM	32
>  #define I965_CURSOR_DFT_WM	8

Imo the watermark, clock speed and clock gating code below would look good
in a separate patch ;-) You're already overflowing the subject of this one
here.

> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8daeef..084e154 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3530,6 +3530,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
>  	return true;
>  }
>  
> +static int valleyview_get_display_clock_speed(struct drm_device *dev)
> +{
> +	return 400000; /* FIXME */
> +}
> +
>  static int i945_get_display_clock_speed(struct drm_device *dev)
>  {
>  	return 400000;
> @@ -3679,6 +3684,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
>  	2,
>  	G4X_FIFO_LINE_SIZE,
>  };
> +static const struct intel_watermark_params valleyview_wm_info = {
> +	VALLEYVIEW_FIFO_SIZE,
> +	VALLEYVIEW_MAX_WM,
> +	VALLEYVIEW_MAX_WM,
> +	2,
> +	G4X_FIFO_LINE_SIZE,
> +};
> +static const struct intel_watermark_params valleyview_cursor_wm_info = {
> +	I965_CURSOR_FIFO,
> +	VALLEYVIEW_CURSOR_MAX_WM,
> +	I965_CURSOR_DFT_WM,
> +	2,
> +	G4X_FIFO_LINE_SIZE,
> +};
>  static const struct intel_watermark_params i965_cursor_wm_info = {
>  	I965_CURSOR_FIFO,
>  	I965_CURSOR_MAX_WM,
> @@ -4203,6 +4222,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
>  
>  #define single_plane_enabled(mask) is_power_of_2(mask)
>  
> +static void valleyview_update_wm(struct drm_device *dev)
> +{
> +	static const int sr_latency_ns = 12000;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
> +	int plane_sr, cursor_sr;
> +	unsigned int enabled = 0;
> +
> +	if (g4x_compute_wm0(dev, 0,
> +			    &valleyview_wm_info, latency_ns,
> +			    &valleyview_cursor_wm_info, latency_ns,
> +			    &planea_wm, &cursora_wm))
> +		enabled |= 1;
> +
> +	if (g4x_compute_wm0(dev, 1,
> +			    &valleyview_wm_info, latency_ns,
> +			    &valleyview_cursor_wm_info, latency_ns,
> +			    &planeb_wm, &cursorb_wm))
> +		enabled |= 2;
> +
> +	plane_sr = cursor_sr = 0;
> +	if (single_plane_enabled(enabled) &&
> +	    g4x_compute_srwm(dev, ffs(enabled) - 1,
> +			     sr_latency_ns,
> +			     &valleyview_wm_info,
> +			     &valleyview_cursor_wm_info,
> +			     &plane_sr, &cursor_sr))
> +		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
> +	else
> +		I915_WRITE(FW_BLC_SELF,
> +			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
> +
> +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> +		      planea_wm, cursora_wm,
> +		      planeb_wm, cursorb_wm,
> +		      plane_sr, cursor_sr);
> +
> +	I915_WRITE(DSPFW1,
> +		   (plane_sr << DSPFW_SR_SHIFT) |
> +		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> +		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
> +		   planea_wm);
> +	I915_WRITE(DSPFW2,
> +		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
> +		   (cursora_wm << DSPFW_CURSORA_SHIFT));
> +	I915_WRITE(DSPFW3,
> +		   (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
> +}
> +
>  static void g4x_update_wm(struct drm_device *dev)
>  {
>  	static const int sr_latency_ns = 12000;
> @@ -8488,6 +8556,11 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&dev_priv->dev->struct_mutex);
>  }
>  
> +static void valleyview_init_clock_gating(struct drm_device *dev)
> +{
> +	return;
> +}
> +
>  static void ironlake_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -8895,7 +8968,10 @@ static void intel_init_display(struct drm_device *dev)
>  	}
>  
>  	/* Returns the core display clock speed */
> -	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
> +	if (IS_VALLEYVIEW(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			valleyview_get_display_clock_speed;
> +	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
>  		dev_priv->display.get_display_clock_speed =
>  			i945_get_display_clock_speed;
>  	else if (IS_I915G(dev))
> @@ -8990,6 +9066,10 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.write_eld = ironlake_write_eld;
>  		} else
>  			dev_priv->display.update_wm = NULL;
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		dev_priv->display.update_wm = valleyview_update_wm;
> +		dev_priv->display.init_clock_gating =
> +			valleyview_init_clock_gating;
>  	} else if (IS_PINEVIEW(dev)) {
>  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
>  					    dev_priv->is_ddr3,
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 02/25] drm/i915: add debug message when EDID fetch fails

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 756 bytes --]

On Wed, 21 Mar 2012 17:44:12 -0300
Eugeni Dodonov <eugeni@dodonov.net> wrote:

> On Wed, Mar 21, 2012 at 16:48, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:
> 
> > +       } else {
> 
> +               DRM_DEBUG_KMS("failed to fetch edid\n");
> >        }
> >
> 
> 
> Wouldn't it be prettier if we also add some:
>    ...
>    err = -ENXIO;
> 
> or similar error in that block, to let the caller know that we failed as
> well?
> 
> 
> >        return ret;
> >
> 

Maybe but I think most callers just check for the EDID later anyway.

Really this patch can be dropped, but I was wondering exactly where the
GPIO side of things was failing and added some debug output...

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:28PM -0700, Jesse Barnes wrote:
> ValleyView needs something different here, and it cleans up the function
> quite a bit.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Simply resending the patch doesn't make it better ;-)

http://lists.freedesktop.org/archives/intel-gfx/2012-January/014408.html

... and can the first Jesse tell the second Jesse to drop his sob line?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |  408 +++++++++++++++++++--------------
>  1 files changed, 235 insertions(+), 173 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 084e154..f9ac7b7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5245,6 +5245,233 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>  	}
>  }
>  
> +static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
> +			      struct drm_display_mode *adjusted_mode)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 temp, lvds_sync = 0;
> +
> +	temp = I915_READ(LVDS);
> +	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> +	if (pipe == 1) {
> +		temp |= LVDS_PIPEB_SELECT;
> +	} else {
> +		temp &= ~LVDS_PIPEB_SELECT;
> +	}
> +	/* set the corresponsding LVDS_BORDER bit */
> +	temp |= dev_priv->lvds_border_bits;
> +	/* Set the B0-B3 data pairs corresponding to whether we're going to
> +	 * set the DPLLs for dual-channel mode or not.
> +	 */
> +	if (clock->p2 == 7)
> +		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> +	else
> +		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> +
> +	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> +	 * appropriately here, but we need to look more thoroughly into how
> +	 * panels behave in the two modes.
> +	 */
> +	/* set the dithering flag on LVDS as needed */
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		if (dev_priv->lvds_dither)
> +			temp |= LVDS_ENABLE_DITHER;
> +		else
> +			temp &= ~LVDS_ENABLE_DITHER;
> +	}
> +	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> +		lvds_sync |= LVDS_HSYNC_POLARITY;
> +	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> +		lvds_sync |= LVDS_VSYNC_POLARITY;
> +	if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
> +	    != lvds_sync) {
> +		char flags[2] = "-+";
> +		DRM_INFO("Changing LVDS panel from "
> +			 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
> +			 flags[!(temp & LVDS_HSYNC_POLARITY)],
> +			 flags[!(temp & LVDS_VSYNC_POLARITY)],
> +			 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
> +			 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
> +		temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> +		temp |= lvds_sync;
> +	}
> +	I915_WRITE(LVDS, temp);
> +}
> +
> +static void i9xx_update_pll(struct drm_crtc *crtc,
> +			    struct drm_display_mode *mode,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
> +			    int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll;
> +	bool is_sdvo;
> +
> +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		dpll |= DPLLB_MODE_LVDS;
> +	else
> +		dpll |= DPLLB_MODE_DAC_SERIAL;
> +	if (is_sdvo) {
> +		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
> +		if (pixel_multiplier > 1) {
> +			if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> +				dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
> +		}
> +		dpll |= DPLL_DVO_HIGH_SPEED;
> +	}
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		dpll |= DPLL_DVO_HIGH_SPEED;
> +
> +	/* compute bitmask from p1 value */
> +	if (IS_PINEVIEW(dev))
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> +	else {
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +		if (IS_G4X(dev) && reduced_clock)
> +			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> +	}
> +	switch (clock->p2) {
> +	case 5:
> +		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
> +		break;
> +	case 7:
> +		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
> +		break;
> +	case 10:
> +		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
> +		break;
> +	case 14:
> +		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
> +		break;
> +	}
> +	if (INTEL_INFO(dev)->gen >= 4)
> +		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
> +
> +	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		dpll |= PLL_REF_INPUT_TVCLKINBC;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		/* XXX: just matching BIOS for now */
> +		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> +		dpll |= 3;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> +		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	else
> +		dpll |= PLL_REF_INPUT_DREFCLK;
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> +	 * This is an exception to the general rule that mode_set doesn't turn
> +	 * things on.
> +	 */
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		intel_update_lvds(crtc, clock, adjusted_mode);
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		u32 temp = 0;
> +		if (is_sdvo) {
> +			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> +			if (temp > 1)
> +				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +			else
> +				temp = 0;
> +		}
> +		I915_WRITE(DPLL_MD(pipe), temp);
> +	} else {
> +		/* The pixel multiplier can only be updated once the
> +		 * DPLL is enabled and the clocks are stable.
> +		 *
> +		 * So write it again.
> +		 */
> +		I915_WRITE(DPLL(pipe), dpll);
> +	}
> +}
> +
> +static void i8xx_update_pll(struct drm_crtc *crtc,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock,
> +			    int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll;
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +	} else {
> +		if (clock->p1 == 2)
> +			dpll |= PLL_P1_DIVIDE_BY_TWO;
> +		else
> +			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +		if (clock->p2 == 4)
> +			dpll |= PLL_P2_DIVIDE_BY_4;
> +	}
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		/* XXX: just matching BIOS for now */
> +		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> +		dpll |= 3;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> +		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	else
> +		dpll |= PLL_REF_INPUT_DREFCLK;
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> +	 * This is an exception to the general rule that mode_set doesn't turn
> +	 * things on.
> +	 */
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		intel_update_lvds(crtc, clock, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The pixel multiplier can only be updated once the
> +	 * DPLL is enabled and the clocks are stable.
> +	 *
> +	 * So write it again.
> +	 */
> +	I915_WRITE(DPLL(pipe), dpll);
> +}
> +
>  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  			      struct drm_display_mode *mode,
>  			      struct drm_display_mode *adjusted_mode,
> @@ -5258,15 +5485,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	int refclk, num_connectors = 0;
>  	intel_clock_t clock, reduced_clock;
> -	u32 dpll, dspcntr, pipeconf, vsyncshift;
> -	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
> -	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
> +	u32 dspcntr, pipeconf, vsyncshift;
> +	bool ok, has_reduced_clock = false, is_sdvo = false;
> +	bool is_lvds = false, is_tv = false;
>  	struct drm_mode_config *mode_config = &dev->mode_config;
>  	struct intel_encoder *encoder;
>  	const intel_limit_t *limit;
>  	int ret;
> -	u32 temp;
> -	u32 lvds_sync = 0;
>  
>  	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
>  		if (encoder->base.crtc != crtc)
> @@ -5282,18 +5507,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  			if (encoder->needs_tv_clock)
>  				is_tv = true;
>  			break;
> -		case INTEL_OUTPUT_DVO:
> -			is_dvo = true;
> -			break;
>  		case INTEL_OUTPUT_TVOUT:
>  			is_tv = true;
>  			break;
> -		case INTEL_OUTPUT_ANALOG:
> -			is_crt = true;
> -			break;
> -		case INTEL_OUTPUT_DISPLAYPORT:
> -			is_dp = true;
> -			break;
>  		}
>  
>  		num_connectors++;
> @@ -5337,71 +5553,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
>  				 &reduced_clock : NULL);
>  
> -	dpll = DPLL_VGA_MODE_DIS;
> -
> -	if (!IS_GEN2(dev)) {
> -		if (is_lvds)
> -			dpll |= DPLLB_MODE_LVDS;
> -		else
> -			dpll |= DPLLB_MODE_DAC_SERIAL;
> -		if (is_sdvo) {
> -			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
> -			if (pixel_multiplier > 1) {
> -				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
> -			}
> -			dpll |= DPLL_DVO_HIGH_SPEED;
> -		}
> -		if (is_dp)
> -			dpll |= DPLL_DVO_HIGH_SPEED;
> -
> -		/* compute bitmask from p1 value */
> -		if (IS_PINEVIEW(dev))
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> -		else {
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -			if (IS_G4X(dev) && has_reduced_clock)
> -				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> -		}
> -		switch (clock.p2) {
> -		case 5:
> -			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
> -			break;
> -		case 7:
> -			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
> -			break;
> -		case 10:
> -			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
> -			break;
> -		case 14:
> -			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
> -			break;
> -		}
> -		if (INTEL_INFO(dev)->gen >= 4)
> -			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
> -	} else {
> -		if (is_lvds) {
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -		} else {
> -			if (clock.p1 == 2)
> -				dpll |= PLL_P1_DIVIDE_BY_TWO;
> -			else
> -				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -			if (clock.p2 == 4)
> -				dpll |= PLL_P2_DIVIDE_BY_4;
> -		}
> -	}
> -
> -	if (is_sdvo && is_tv)
> -		dpll |= PLL_REF_INPUT_TVCLKINBC;
> -	else if (is_tv)
> -		/* XXX: just matching BIOS for now */
> -		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> -		dpll |= 3;
> -	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> -		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	if (IS_GEN2(dev))
> +		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
>  	else
> -		dpll |= PLL_REF_INPUT_DREFCLK;
> +		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> +				has_reduced_clock ? &reduced_clock : NULL,
> +				num_connectors);
>  
>  	/* setup pipeconf */
>  	pipeconf = I915_READ(PIPECONF(pipe));
> @@ -5430,105 +5587,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	/* default to 8bpc */
>  	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
> -	if (is_dp) {
> -		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> -			pipeconf |= PIPECONF_BPP_6 |
> -				    PIPECONF_DITHER_EN |
> -				    PIPECONF_DITHER_TYPE_SP;
> -		}
> -	}
> -
> -	dpll |= DPLL_VCO_ENABLE;
>  
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> -	 * This is an exception to the general rule that mode_set doesn't turn
> -	 * things on.
> -	 */
> -	if (is_lvds) {
> -		temp = I915_READ(LVDS);
> -		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> -		if (pipe == 1) {
> -			temp |= LVDS_PIPEB_SELECT;
> -		} else {
> -			temp &= ~LVDS_PIPEB_SELECT;
> -		}
> -		/* set the corresponsding LVDS_BORDER bit */
> -		temp |= dev_priv->lvds_border_bits;
> -		/* Set the B0-B3 data pairs corresponding to whether we're going to
> -		 * set the DPLLs for dual-channel mode or not.
> -		 */
> -		if (clock.p2 == 7)
> -			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> -		else
> -			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> -
> -		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> -		 * appropriately here, but we need to look more thoroughly into how
> -		 * panels behave in the two modes.
> -		 */
> -		/* set the dithering flag on LVDS as needed */
> -		if (INTEL_INFO(dev)->gen >= 4) {
> -			if (dev_priv->lvds_dither)
> -				temp |= LVDS_ENABLE_DITHER;
> -			else
> -				temp &= ~LVDS_ENABLE_DITHER;
> -		}
> -		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> -			lvds_sync |= LVDS_HSYNC_POLARITY;
> -		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> -			lvds_sync |= LVDS_VSYNC_POLARITY;
> -		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
> -		    != lvds_sync) {
> -			char flags[2] = "-+";
> -			DRM_INFO("Changing LVDS panel from "
> -				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
> -				 flags[!(temp & LVDS_HSYNC_POLARITY)],
> -				 flags[!(temp & LVDS_VSYNC_POLARITY)],
> -				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
> -				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
> -			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> -			temp |= lvds_sync;
> -		}
> -		I915_WRITE(LVDS, temp);
> -	}
> -
> -	if (is_dp) {
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> -	}
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	if (INTEL_INFO(dev)->gen >= 4) {
> -		temp = 0;
> -		if (is_sdvo) {
> -			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> -			if (temp > 1)
> -				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> -			else
> -				temp = 0;
> -		}
> -		I915_WRITE(DPLL_MD(pipe), temp);
> -	} else {
> -		/* The pixel multiplier can only be updated once the
> -		 * DPLL is enabled and the clocks are stable.
> -		 *
> -		 * So write it again.
> -		 */
> -		I915_WRITE(DPLL(pipe), dpll);
> -	}
> -
>  	if (HAS_PIPE_CXSR(dev)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 09/25] drm/915: program driain latency regs on ValleyView

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:30PM -0700, Jesse Barnes wrote:
> From: Gajanan Bhat <gajanan.bhat@intel.com>
> 
> This patch adds support for programming drain latency registers of Pondicherry
> memory arbiter of Valleyview.

s/driain/drain in the subject. I've read drisomething and got momentarily
confused.

> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   16 +++++++
>  drivers/gpu/drm/i915/intel_display.c |   76 ++++++++++++++++++++++++++++++++++
>  2 files changed, 92 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bb6b49f..2ff9822 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2602,6 +2602,22 @@
>  #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
>  #define   DSPFW_HPLL_SR_MASK		(0x1ff)
>  
> +/* drain latency register values*/
> +#define DRAIN_LATENCY_PRECISION_32	32
> +#define DRAIN_LATENCY_PRECISION_16	16
> +#define VLV_DDL1			0x70050
> +#define DDL_CURSORA_PRECISION_32	(1<<31)
> +#define DDL_CURSORA_PRECISION_16	(0<<31)
> +#define DDL_CURSORA_SHIFT		24
> +#define DDL_PLANEA_PRECISION_32		(1<<7)
> +#define DDL_PLANEA_PRECISION_16		(0<<7)
> +#define VLV_DDL2			0x70054
> +#define DDL_CURSORB_PRECISION_32	(1<<31)
> +#define DDL_CURSORB_PRECISION_16	(0<<31)
> +#define DDL_CURSORB_SHIFT		24
> +#define DDL_PLANEB_PRECISION_32		(1<<7)
> +#define DDL_PLANEB_PRECISION_16		(0<<7)
> +
>  /* FIFO watermark sizes etc */
>  #define G4X_FIFO_LINE_SIZE	64
>  #define I915_FIFO_LINE_SIZE	64
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ea64dc8..efb6465 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4352,6 +4352,80 @@ static bool g4x_compute_srwm(struct drm_device *dev,
>  			      display, cursor);
>  }
>  
> +static int valleyview_compute_dl(struct drm_device *dev,
> +					int plane,
> +					int *plane_prec_mult,
> +					int *plane_dl,
> +					int *cursor_prec_mult,
> +					int *cursor_dl)
> +{

Bikeshed, but imo important: Can we make the unimportant part in these
function names less noise and instead make the interesting part readable?
I.e. s/valleyview/vlv/ and s/dl/drain_latency or drain_lat

> +	struct drm_crtc *crtc;
> +	int clock, pixel_size;
> +	int entries;
> +
> +	crtc = intel_get_crtc_for_plane(dev, plane);
> +	if (crtc->fb == NULL || !crtc->enabled)
> +		return false;
> +
> +	clock = crtc->mode.clock;	/* VESA DOT Clock */
> +	pixel_size = crtc->fb->bits_per_pixel / 8;	/* BPP */
> +
> +	entries = (clock / 1000) * pixel_size;
> +	*plane_prec_mult = (entries > 256) ?
> +		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +	*plane_dl = (64 * *plane_prec_mult * 4) / ((clock / 1000) * pixel_size);
> +
> +	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
> +	*cursor_prec_mult = (entries > 256) ?
> +		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +	*cursor_dl = (64 * *cursor_prec_mult * 4) / ((clock / 1000) * 4);
> +
> +	return true;
> +}
> +
> +/*
> + * Update drain latency registers of memory arbiter
> + *
> + * Valleyview SoC has a new memory arbiter and needs drain latency registers
> + * to be programmed. Each plane has a drain latency multiplier and a drain
> + * latency value.
> + */
> +
> +static void valleyview_update_dl(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int planea_prec, planea_dl, planeb_prec, planeb_dl;
> +	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
> +	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
> +							either 16 or 32 */
> +
> +	/* For plane A, Cursor A */
> +	if (valleyview_compute_dl(dev, 0, &plane_prec_mult, &planea_dl,
> +					&cursor_prec_mult, &cursora_dl)) {
> +		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> +		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> +
> +		I915_WRITE(VLV_DDL1, cursora_prec |
> +				(cursora_dl << DDL_CURSORA_SHIFT) |
> +				planea_prec | planea_dl);
> +	}
> +
> +	/* For plane B, Cursor B */
> +	if (valleyview_compute_dl(dev, 1, &plane_prec_mult, &planeb_dl,
> +					&cursor_prec_mult, &cursorb_dl)) {
> +		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> +		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> +
> +		I915_WRITE(VLV_DDL2, cursorb_prec |
> +				(cursorb_dl << DDL_CURSORB_SHIFT) |
> +				planeb_prec | planeb_dl);
> +	}
> +}
> +
>  #define single_plane_enabled(mask) is_power_of_2(mask)
>  
>  static void valleyview_update_wm(struct drm_device *dev)
> @@ -4362,6 +4436,8 @@ static void valleyview_update_wm(struct drm_device *dev)
>  	int plane_sr, cursor_sr;
>  	unsigned int enabled = 0;
>  
> +	valleyview_update_dl(dev);
> +
>  	if (g4x_compute_wm0(dev, 0,
>  			    &valleyview_wm_info, latency_ns,
>  			    &valleyview_cursor_wm_info, latency_ns,
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 11/25] drm/i915: Enable HDMI on ValleyView

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:32PM -0700, Jesse Barnes wrote:
> From: Shobhit Kumar <shobhit.kumar@intel.com>
> 
> HDMI register offsets are different in Valleyview. Add support for the
> same.
> 
> Signed-off-by: Beeresh G <beeresh.g@intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |   16 +++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c |   39 ++++++++++++++++++++++++++++++++++++-
>  2 files changed, 54 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c187398..f04bfbf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3452,6 +3452,21 @@
>  #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>  #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>  
> +#define VLV_VIDEO_DIP_CTL_A		0x60220
> +#define VLV_VIDEO_DIP_DATA_A		0x60208
> +#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
> +
> +#define VLV_VIDEO_DIP_CTL_B		0x61170
> +#define VLV_VIDEO_DIP_DATA_B		0x61174
> +#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
> +
> +#define VLV_TVIDEO_DIP_CTL(pipe) \
> +	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
> +#define VLV_TVIDEO_DIP_DATA(pipe) \
> +	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
> +#define VLV_TVIDEO_DIP_GCP(pipe) \
> +	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
> +
>  #define _TRANS_HTOTAL_B          0xe1000
>  #define _TRANS_HBLANK_B          0xe1004
>  #define _TRANS_HSYNC_B           0xe1008
> @@ -3672,6 +3687,7 @@
>  #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
>  
>  /* or SDVOB */
> +#define VLV_HDMIB 0x61140
>  #define HDMIB   0xe1140
>  #define  PORT_ENABLE    (1 << 31)
>  #define  TRANSCODER(pipe)       ((pipe) << 30)
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index cae3e5f..3f4a2d2 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -177,6 +177,37 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
>  
>  	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>  }
> +
> +static void vlv_write_infoframe(struct drm_encoder *encoder,
> +				     struct dip_infoframe *frame)
> +{
> +	uint32_t *data = (uint32_t *)frame;
> +	struct drm_device *dev = encoder->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_crtc *crtc = encoder->crtc;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
> +	unsigned i, len = DIP_HEADER_SIZE + frame->len;
> +	u32 flags, val = I915_READ(reg);
> +
> +	intel_wait_for_vblank(dev, intel_crtc->pipe);
> +
> +	flags = intel_infoframe_index(frame);
> +
> +	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
> +
> +	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
> +
> +	for (i = 0; i < len; i += 4) {
> +		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
> +		data++;
> +	}
> +
> +	flags |= intel_infoframe_flags(frame);
> +
> +	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
> +}
> +
>  static void intel_set_infoframe(struct drm_encoder *encoder,
>  				struct dip_infoframe *frame)
>  {
> @@ -522,10 +553,12 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
>  	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>  
>  	/* Set up the DDC bus. */
> +	/* For VLV SDVOB == HDMIB */
>  	if (sdvox_reg == SDVOB) {
>  		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
>  		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
>  		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
> +	/* For VLV SDVOC == HDMIC */

I'm a bit confused about these two comments here. Afaict the code already
works that way, not just on vlv. Can we just drop this hunk?

>  	} else if (sdvox_reg == SDVOC) {
>  		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
>  		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
> @@ -549,7 +582,11 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
>  	if (!HAS_PCH_SPLIT(dev)) {
>  		intel_hdmi->write_infoframe = i9xx_write_infoframe;
>  		I915_WRITE(VIDEO_DIP_CTL, 0);
> -	} else {
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		intel_hdmi->write_infoframe = vlv_write_infoframe;
> +		for_each_pipe(i)
> +			I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
> +	}  else {
>  		intel_hdmi->write_infoframe = ironlake_write_infoframe;
>  		for_each_pipe(i)
>  			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 12/25] agp/intel: map more registers for use by the GTT code

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:33PM -0700, Jesse Barnes wrote:
> We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
> register for doing so is above the range we normally map.  Map the whole
> register space to make sure we can get it.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/char/agp/intel-gtt.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 5cf47ac..19b6486 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1211,7 +1211,7 @@ static int i9xx_setup(void)
>  
>  	reg_addr &= 0xfff80000;
>  
> -	intel_private.registers = ioremap(reg_addr, 128 * 4096);
> +	intel_private.registers = ioremap(reg_addr, MB(2));

If I'm reading my lspci output correctly, my i915g only has 1mb, not to.
-Daniel

>  	if (!intel_private.registers)
>  		return -ENOMEM;
>  
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 13/25] agp/intel: add Valleyview specific PTE entry function

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:34PM -0700, Jesse Barnes wrote:
> On VLV we need to flush the TLBs of the Gunit when updating PTEs.  We
> could put this off until we've written a whole block of entries, but we
> don't currently have a nice place to put that.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/char/agp/intel-agp.h |    1 +
>  drivers/char/agp/intel-gtt.c |   19 ++++++++++++++++++-
>  2 files changed, 19 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
> index 5da67f1..4c0854d 100644
> --- a/drivers/char/agp/intel-agp.h
> +++ b/drivers/char/agp/intel-agp.h
> @@ -96,6 +96,7 @@
>  #define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
>  
>  #define GFX_FLSH_CNTL		0x2170 /* 915+ */
> +#define GFX_FLSH_CNTL_VLV	0x0x101008
>  
>  #define I810_DRAM_CTL		0x3000
>  #define I810_DRAM_ROW_0		0x00000001
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 19b6486..8d5bef3 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1179,6 +1179,23 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
>  	writel(addr | pte_flags, intel_private.gtt + entry);
>  }
>  
> +static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
> +				   unsigned int flags)
> +{
> +	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
> +	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
> +	u32 pte_flags;
> +
> +	if (type_mask == AGP_USER_MEMORY)
> +		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
> +
> +	/* gen6 has bit11-4 for physical addr bit39-32 */
> +	addr |= (addr >> 28) & 0xff0;
> +	writel(addr | pte_flags, intel_private.gtt + entry);
> +
> +	writel(1, intel_private.registers + GFX_FLUSH_CNTL_VLV);
> +}
> +
>  static void gen6_cleanup(void)
>  {
>  }
> @@ -1350,7 +1367,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
>  	.gen = 6,
>  	.setup = i9xx_setup,
>  	.cleanup = gen6_cleanup,
> -	.write_entry = gen6_write_entry,
> +	.write_entry = valleyview_write_entry,
>  	.dma_mask_size = 40,
>  	.check_flags = gen6_check_flags,
>  	.chipset_flush = i9xx_chipset_flush,

By now I'm pretty sure you want to add a new vlv gtt driver - this won't
work so well on snb. One thing on my todo that's been on it for way too
long is to move all the gtt crap to drm/i915/i915_gem_gtt.c for gen6+
(where we never supported ums). This could make the vlv code in here a bit
.impler, but I'm ok with adding more cruft in intel-gtt.c, too.

-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 14/25] agp/intel: always use uncached mappings on VLV

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:35PM -0700, Jesse Barnes wrote:
> Until the snoopable ones are debugged.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/char/agp/intel-gtt.c |    3 +--
>  1 files changed, 1 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 8d5bef3..25911a1 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1186,8 +1186,7 @@ static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
>  	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
>  	u32 pte_flags;
>  
> -	if (type_mask == AGP_USER_MEMORY)
> -		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
> +	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;

Squash this with the previous one. Even for the snb we'll never see
AGP_USER_MEMORY because only the ums driver ever used this. Before gem.
And I think even then you need to dig out pretty old userspace to actually
see it.
-Daniel
>  
>  	/* gen6 has bit11-4 for physical addr bit39-32 */
>  	addr |= (addr >> 28) & 0xff0;
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:37PM -0700, Jesse Barnes wrote:
> ValleyView handles force wake differently than previous chipsets, so add
> a couple of new functions for it.
> 
> But it's also untested, so no need to call these untested functions yet.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

So we have forcewake but we don't need forcewak?! Can you explain how this
works for dense me a bit?
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c      |   28 +++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_drv.h      |    3 +++
>  drivers/gpu/drm/i915/i915_reg.h      |    2 ++
>  drivers/gpu/drm/i915/intel_display.c |    2 ++
>  4 files changed, 34 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b83a0dc..e4fa294 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -462,6 +462,31 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
>  	return ret;
>  }
>  
> +void vlv_force_wake_get(struct drm_i915_private *dev_priv)
> +{
> +	int count;
> +
> +	count = 0;
> +
> +	/* Already awake? */
> +	if ((I915_READ(0x130094) & 0xa1) == 0xa1)
> +		return;
> +
> +	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
> +	POSTING_READ(FORCEWAKE_VLV);
> +
> +	count = 0;
> +	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
> +		udelay(10);
> +}
> +
> +void vlv_force_wake_put(struct drm_i915_private *dev_priv)
> +{
> +	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
> +	/* FIXME: confirm VLV behavior with Punit folks */
> +	POSTING_READ(FORCEWAKE_VLV);
> +}
> +
>  static int i915_drm_freeze(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1004,7 +1029,8 @@ MODULE_LICENSE("GPL and additional rights");
>  #define NEEDS_FORCE_WAKE(dev_priv, reg) \
>         (((dev_priv)->info->gen >= 6) && \
>          ((reg) < 0x40000) &&            \
> -        ((reg) != FORCEWAKE))
> +        ((reg) != FORCEWAKE)) && \
> +       (!IS_VALLEYVIEW((dev_priv)->dev))
>  
>  #define __i915_read(x, y) \
>  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2b8b32d..178a955 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1394,6 +1394,9 @@ extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
>  extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
>  extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
>  
> +extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
> +extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
> +
>  /* overlay */
>  #ifdef CONFIG_DEBUG_FS
>  extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f04bfbf..e9be070 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3865,6 +3865,8 @@
>  #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
>  
>  #define  FORCEWAKE				0xA18C
> +#define  FORCEWAKE_VLV				0x1300b0
> +#define  FORCEWAKE_ACK_VLV			0x1300b4
>  #define  FORCEWAKE_ACK				0x130090
>  #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
>  #define  FORCEWAKE_MT_ACK			0x130040
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index efb6465..6e6f8b0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9433,6 +9433,8 @@ static void intel_init_display(struct drm_device *dev)
>  		dev_priv->display.update_wm = valleyview_update_wm;
>  		dev_priv->display.init_clock_gating =
>  			valleyview_init_clock_gating;
> +		dev_priv->display.force_wake_get = vlv_force_wake_get;
> +		dev_priv->display.force_wake_put = vlv_force_wake_put;
>  	} else if (IS_PINEVIEW(dev)) {
>  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
>  					    dev_priv->is_ddr3,
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 17/25] drm/i915: ValleyView cacheability is different

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:38PM -0700, Jesse Barnes wrote:
> The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> it does writes, so we can't use the cache bits the same way.
> 
> So map the status and pipe control pages as uncached on ValleyView, and
> only set the pages to cached if we're on a supported platform.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c         |    2 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   35 ++++++++++++++++++++++++------
>  2 files changed, 30 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e4fa294..a636703 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -255,6 +255,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
> +	.has_llc = 0,
>  };
>  
>  static const struct intel_device_info intel_valleyview_d_info = {
> @@ -264,6 +265,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
> +	.has_llc = 0,

Usually we don't set feature bits to 0, please drop these 2 hunks.

>  };
>  
>  static const struct pci_device_id pciidlist[] = {		/* aka */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ca3972f..f52abc4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
>  {
>  	struct pipe_control *pc;
>  	struct drm_i915_gem_object *obj;
> +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> +	struct drm_device *dev;

Nope, that's not gonna work. Afaik we have 3 kinds of snoopable bus access
from the gpu:
- llc, i.e. snoopable access for all render operations, support if
  intel_info->has_llc == 1
- snoopable access to untiled mem with the blitter, supported on all
  generations (down to mighty old i81x)
- snoopable access to the hw status page

Please clear up the confusion here. Below you also use the IS_VLV macro,
that seems more appropriate. Also I'm wondering whether this is supposed
to be fixed in future silicon revisions, if so please mark this as a w/a
that can be reaped as soon as we don't use this early silicon for testing
any more.
-Daniel


>  	int ret;
>  
>  	if (ring->private)
> @@ -335,14 +337,19 @@ init_pipe_control(struct intel_ring_buffer *ring)
>  		goto err;
>  	}
>  
> -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> +	i915_gem_object_set_cache_level(obj, cache_level);
>  
>  	ret = i915_gem_object_pin(obj, 4096, true);
>  	if (ret)
>  		goto err_unref;
> -
> +	dev = obj->base.dev;
>  	pc->gtt_offset = obj->gtt_offset;
> -	pc->cpu_page =  kmap(obj->pages[0]);
> +	if (!HAS_LLC(ring->dev))
> +		pc->cpu_page = ioremap(dev->agp->base +
> +				       obj->gtt_offset,
> +				       PAGE_SIZE);
> +	else
> +		pc->cpu_page =  kmap(obj->pages[0]);
>  	if (pc->cpu_page == NULL)
>  		goto err_unpin;
>  
> @@ -364,12 +371,17 @@ cleanup_pipe_control(struct intel_ring_buffer *ring)
>  {
>  	struct pipe_control *pc = ring->private;
>  	struct drm_i915_gem_object *obj;
> +	struct drm_device *dev;
>  
>  	if (!ring->private)
>  		return;
>  
>  	obj = pc->obj;
> -	kunmap(obj->pages[0]);
> +	dev = obj->base.dev;
> +	if (IS_VALLEYVIEW(dev))
> +		iounmap(pc->cpu_page);
> +	else
> +		kunmap(obj->pages[0]);
>  	i915_gem_object_unpin(obj);
>  	drm_gem_object_unreference(&obj->base);
>  
> @@ -929,7 +941,10 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
>  	if (obj == NULL)
>  		return;
>  
> -	kunmap(obj->pages[0]);
> +	if (IS_VALLEYVIEW(dev_priv->dev))
> +		iounmap(ring->status_page.page_addr);
> +	else
> +		kunmap(obj->pages[0]);
>  	i915_gem_object_unpin(obj);
>  	drm_gem_object_unreference(&obj->base);
>  	ring->status_page.obj = NULL;
> @@ -942,6 +957,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  	struct drm_device *dev = ring->dev;
>  	drm_i915_private_t *dev_priv = dev->dev_private;
>  	struct drm_i915_gem_object *obj;
> +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
>  	int ret;
>  
>  	obj = i915_gem_alloc_object(dev, 4096);
> @@ -951,7 +967,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  		goto err;
>  	}
>  
> -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> +	i915_gem_object_set_cache_level(obj, cache_level);
>  
>  	ret = i915_gem_object_pin(obj, 4096, true);
>  	if (ret != 0) {
> @@ -959,7 +975,12 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  	}
>  
>  	ring->status_page.gfx_addr = obj->gtt_offset;
> -	ring->status_page.page_addr = kmap(obj->pages[0]);
> +	if (!HAS_LLC(ring->dev))
> +		ring->status_page.page_addr = ioremap(dev->agp->base +
> +						      obj->gtt_offset,
> +						      PAGE_SIZE);
> +	else
> +		ring->status_page.page_addr = kmap(obj->pages[0]);
>  	if (ring->status_page.page_addr == NULL) {
>  		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
>  		goto err_unpin;
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 14/25] agp/intel: always use uncached mappings on VLV

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:18PM +0100, Daniel Vetter wrote:
> On Wed, Mar 21, 2012 at 12:48:35PM -0700, Jesse Barnes wrote:
> > Until the snoopable ones are debugged.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/char/agp/intel-gtt.c |    3 +--
> >  1 files changed, 1 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> > index 8d5bef3..25911a1 100644
> > --- a/drivers/char/agp/intel-gtt.c
> > +++ b/drivers/char/agp/intel-gtt.c
> > @@ -1186,8 +1186,7 @@ static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
> >  	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
> >  	u32 pte_flags;
> >  
> > -	if (type_mask == AGP_USER_MEMORY)
> > -		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
> > +	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
> 
> Squash this with the previous one. Even for the snb we'll never see
> AGP_USER_MEMORY because only the ums driver ever used this. Before gem.
> And I think even then you need to dig out pretty old userspace to actually
> see it.

Scrap the AGP_USER_MEMORY comment, Chris corrected me on irc that I'm
talking nonsense. I've confused this with the old code from i81x, too many
nightmares from reading that stuff ;-) 'The squash with previous' still
holds.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 07/25] drm/i915: split out DPLL update code from i9xx_crtc_mode_set

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 891 bytes --]

On Wed, 21 Mar 2012 21:55:55 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:28PM -0700, Jesse Barnes wrote:
> > ValleyView needs something different here, and it cleans up the function
> > quite a bit.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Simply resending the patch doesn't make it better ;-)
> 
> http://lists.freedesktop.org/archives/intel-gfx/2012-January/014408.html

Yes but reposting *and* fixing up all the conflicts is surely worth
something.

> ... and can the first Jesse tell the second Jesse to drop his sob line?

Sure, I'll let him know.  I'll ask him to re-post the patch too; I'm
too lazy to split it.

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 827 bytes --]

On Wed, 21 Mar 2012 22:11:25 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:37PM -0700, Jesse Barnes wrote:
> > ValleyView handles force wake differently than previous chipsets, so add
> > a couple of new functions for it.
> > 
> > But it's also untested, so no need to call these untested functions yet.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> So we have forcewake but we don't need forcewak?! Can you explain how this
> works for dense me a bit?

We need force wake, just not for any parts I've tested yet (the early
ones had the Punit disabled).

This code adheres to the spec, but I'll need a part with the Punit
enabled in order to test & verify.  Until then we can leave it disabled.

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote:
> Although internally the MMIO offsets for display regs haven't changed,
> their visibility through the PCI BAR has been affected by the addition
> of the Gunit, which occupies the low part of the address space.
> 
> Display regs on VLV are offset into the BAR by 0x180000, so we need to
> add that for any display register offset.
> 
> This patch is a hack to do just that, but ultimately we need to split
> our display and render code more cleanly and add accessor functions for
> them.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like
you've proposed + I915_DISPLAY_READ/WRITE like we already have for the
ring stuff is much better ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c |   83 ++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 81 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a636703..48fc5ab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1034,6 +1034,80 @@ MODULE_LICENSE("GPL and additional rights");
>          ((reg) != FORCEWAKE)) && \
>         (!IS_VALLEYVIEW((dev_priv)->dev))
>  
> +static bool IS_DISPLAYREG(u32 reg)
> +{
> +	if (reg >= RENDER_RING_BASE &&
> +	    reg < RENDER_RING_BASE + 0xff)
> +		return false;
> +	if (reg >= GEN6_BSD_RING_BASE &&
> +	    reg < GEN6_BSD_RING_BASE + 0xff)
> +		return false;
> +	if (reg >= BLT_RING_BASE &&
> +	    reg < BLT_RING_BASE + 0xff)
> +		return false;
> +
> +	if (reg == PGTBL_ER)
> +		return false;
> +
> +	if (reg >= IPEIR_I965 &&
> +	    reg < HWSTAM)
> +		return false;
> +
> +	if (reg == MI_MODE)
> +		return false;
> +
> +	if (reg == GFX_MODE_GEN7)
> +		return false;
> +
> +	if (reg == RENDER_HWS_PGA_GEN7 ||
> +	    reg == BSD_HWS_PGA_GEN7 ||
> +	    reg == BLT_HWS_PGA_GEN7)
> +		return false;
> +
> +	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
> +	    reg == GEN6_BSD_RNCID)
> +		return false;
> +
> +	if (reg == GEN6_BLITTER_ECOSKPD)
> +		return false;
> +
> +	if (reg >= 0x4000c &&
> +	    reg <= 0x4002c)
> +		return false;
> +
> +	if (reg >= 0x4f000 &&
> +	    reg <= 0x4f08f)
> +		return false;
> +
> +	if (reg >= 0x4f100 &&
> +	    reg <= 0x4f11f)
> +		return false;
> +
> +	if (reg >= MASTER_IER_VLV &&
> +	    reg <= GEN6_PMIER)
> +		return false;
> +
> +	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
> +	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
> +		return false;
> +
> +	if (reg >= IIR_VLV_RW &&
> +	    reg <= ISR_VLV)
> +		return false;
> +
> +	if (reg == MASTER_IER_VLV)
> +		return false;
> +
> +	if (reg == FORCEWAKE_VLV ||
> +	    reg == FORCEWAKE_ACK_VLV)
> +		return false;
> +
> +	if (reg == GEN6_GDRST)
> +		return false;
> +
> +	return true;
> +}
> +
>  #define __i915_read(x, y) \
>  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  	u##x val = 0; \
> @@ -1046,6 +1120,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  		if (dev_priv->forcewake_count == 0) \
>  			dev_priv->display.force_wake_put(dev_priv); \
>  		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
> +	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
> +		val = read##y(dev_priv->regs + reg + 0x180000);		\
>  	} else { \
>  		val = read##y(dev_priv->regs + reg); \
>  	} \
> @@ -1065,8 +1141,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
>  	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
>  	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
>  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
> -	} \
> -	write##y(val, dev_priv->regs + reg); \
> +	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
> +		write##y(val, dev_priv->regs + reg + 0x180000);		\
> +	} else {							\
> +		write##y(val, dev_priv->regs + reg);			\
> +	}								\
>  	if (unlikely(__fifo_ret)) { \
>  		gen6_gt_check_fifodbg(dev_priv); \
>  	} \
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 17/25] drm/i915: ValleyView cacheability is different

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 3263 bytes --]

On Wed, 21 Mar 2012 22:19:36 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:38PM -0700, Jesse Barnes wrote:
> > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> > it does writes, so we can't use the cache bits the same way.
> > 
> > So map the status and pipe control pages as uncached on ValleyView, and
> > only set the pages to cached if we're on a supported platform.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c         |    2 +
> >  drivers/gpu/drm/i915/intel_ringbuffer.c |   35 ++++++++++++++++++++++++------
> >  2 files changed, 30 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index e4fa294..a636703 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -255,6 +255,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
> >  	.has_bsd_ring = 1,
> >  	.has_blt_ring = 1,
> >  	.is_valleyview = 1,
> > +	.has_llc = 0,
> >  };
> >  
> >  static const struct intel_device_info intel_valleyview_d_info = {
> > @@ -264,6 +265,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
> >  	.has_bsd_ring = 1,
> >  	.has_blt_ring = 1,
> >  	.is_valleyview = 1,
> > +	.has_llc = 0,
> 
> Usually we don't set feature bits to 0, please drop these 2 hunks.
> 
> >  };
> >  
> >  static const struct pci_device_id pciidlist[] = {		/* aka */
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index ca3972f..f52abc4 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
> >  {
> >  	struct pipe_control *pc;
> >  	struct drm_i915_gem_object *obj;
> > +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> > +	struct drm_device *dev;
> 
> Nope, that's not gonna work. Afaik we have 3 kinds of snoopable bus access
> from the gpu:
> - llc, i.e. snoopable access for all render operations, support if
>   intel_info->has_llc == 1
> - snoopable access to untiled mem with the blitter, supported on all
>   generations (down to mighty old i81x)
> - snoopable access to the hw status page
> 
> Please clear up the confusion here. Below you also use the IS_VLV macro,
> that seems more appropriate. Also I'm wondering whether this is supposed
> to be fixed in future silicon revisions, if so please mark this as a w/a
> that can be reaped as soon as we don't use this early silicon for testing
> any more.

Yeah I don't like this either.  I have a meeting with the hw guys on
Friday and will try to clear this up.

It may be best to just check for IS_VALLEYVIEW here instead (this is
what I had before, then I decided to get clever so I could squash in
the HAS_LLC change in i915_gem.c).  You're right there are multiple
types of cacheability we need to accommodate.

So maybe HAS_LLC for i915_gem.c and HWS_CACHEABLE or something to
easily identify the retro chips...

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 22/25] drm/i915: remove some unneeded debug messages

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:43PM -0700, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

So you've achieved the contentless-error-msg nirvana? Luckily for you one
of these is quality work from China ;-) Patch applied to next, thanks.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 58accf5..541c0a6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2075,14 +2075,14 @@ static void intel_update_fbc(struct drm_device *dev)
>  	struct drm_i915_gem_object *obj;
>  	int enable_fbc;
>  
> -	DRM_DEBUG_KMS("\n");
> -
>  	if (!i915_powersave)
>  		return;
>  
>  	if (!I915_HAS_FBC(dev))
>  		return;
>  
> +	DRM_DEBUG_KMS("\n");
> +
>  	/*
>  	 * If FBC is already on, we just have to verify that we can
>  	 * keep it that way...
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 1123 bytes --]

On Wed, 21 Mar 2012 22:33:43 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote:
> > Although internally the MMIO offsets for display regs haven't changed,
> > their visibility through the PCI BAR has been affected by the addition
> > of the Gunit, which occupies the low part of the address space.
> > 
> > Display regs on VLV are offset into the BAR by 0x180000, so we need to
> > add that for any display register offset.
> > 
> > This patch is a hack to do just that, but ultimately we need to split
> > our display and render code more cleanly and add accessor functions for
> > them.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like
> you've proposed + I915_DISPLAY_READ/WRITE like we already have for the
> ring stuff is much better ...

I nearly got violent with the hw guys when they told me...

But yeah I think a display reg wrapper with an offset is probably the
least offensive.

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 22/25] drm/i915: remove some unneeded debug messages

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:36:22PM +0100, Daniel Vetter wrote:
> On Wed, Mar 21, 2012 at 12:48:43PM -0700, Jesse Barnes wrote:
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> So you've achieved the contentless-error-msg nirvana? Luckily for you one
> of these is quality work from China ;-) Patch applied to next, thanks.

Ok, not applied. My brain seems to be somewhere else atm - I've found two
of these in drm/i915 and somehow thought you'd kill these two. But this
patch just moves it. Can you enlighten me as to what's going on here?
-Daniel

> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    4 ++--
> >  1 files changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 58accf5..541c0a6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2075,14 +2075,14 @@ static void intel_update_fbc(struct drm_device *dev)
> >  	struct drm_i915_gem_object *obj;
> >  	int enable_fbc;
> >  
> > -	DRM_DEBUG_KMS("\n");
> > -
> >  	if (!i915_powersave)
> >  		return;
> >  
> >  	if (!I915_HAS_FBC(dev))
> >  		return;
> >  
> > +	DRM_DEBUG_KMS("\n");
> > +
> >  	/*
> >  	 * If FBC is already on, we just have to verify that we can
> >  	 * keep it that way...
> > -- 
> > 1.7.5.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Mail: daniel@ffwll.ch
> Mobile: +41 (0)79 365 57 48

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 23/25] drm/i915: add ValleyView clock gating init

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:44PM -0700, Jesse Barnes wrote:
> Set the same bits as IVB plus a few others.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Minor patch order request: Can you move that to the wm stuff where this
function gets added?
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   18 +++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   41 ++++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index df258ab..4aa6d1d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -638,6 +638,9 @@
>  #define   ECO_GATING_CX_ONLY	(1<<3)
>  #define   ECO_FLIP_DONE		(1<<0)
>  
> +#define CACHE_MODE_1		0x7004 /* IVB+ */
> +#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
> +
>  /* GEN6 interrupt control */
>  #define GEN6_RENDER_HWSTAM	0x2098
>  #define GEN6_RENDER_IMR		0x20a8
> @@ -3255,6 +3258,20 @@
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
>  
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
> +# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
> +
> +#define GEN7_L3CNTLREG1				0xB01C
> +#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
> +
> +#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> +#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +
> +/* WaCatErrorRejectionIssue */
> +#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> +#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> +
>  /* PCH */
>  
>  /* south display engine interrupt */
> @@ -3888,6 +3905,7 @@
>  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
>  
>  #define GEN6_UCGCTL2				0x9404
> +# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
>  # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
>  # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 541c0a6..8668d38 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8939,6 +8939,47 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>  
>  static void valleyview_init_clock_gating(struct drm_device *dev)
>  {
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> +
> +	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
> +
> +	I915_WRITE(WM3_LP_ILK, 0);
> +	I915_WRITE(WM2_LP_ILK, 0);
> +	I915_WRITE(WM1_LP_ILK, 0);
> +
> +	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> +	 * This implements the WaDisableRCZUnitClockGating workaround.
> +	 */
> +	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> +
> +	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
> +
> +	I915_WRITE(IVB_CHICKEN3,
> +		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> +		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> +
> +	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> +	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> +		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> +
> +	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
> +	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> +	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
> +
> +	/* This is required by WaCatErrorRejectionIssue */
> +	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> +		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> +		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> +
> +	for_each_pipe(pipe) {
> +		I915_WRITE(DSPCNTR(pipe),
> +			   I915_READ(DSPCNTR(pipe)) |
> +			   DISPPLANE_TRICKLE_FEED_DISABLE);
> +		intel_flush_display_plane(dev_priv, pipe);
> +	}
> +
>  	return;
>  }
>  
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 24/25] drm/i915: add has_turbo bit to driver info struct

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:45PM -0700, Jesse Barnes wrote:
> Since ValleyView is a gen7 chip but doesn't have the same turbo interface.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Commit headline is imo misleading - effectively the patch disables turbo
on vlv. Then msg body could then elaborate that we do this with a feature
flag. For this specific case where we have just 2 if blocks (you've missed
the disable_rps btw) I don't think it's worth it to add a feature flag.
Normal if cascade like

if (IS_ILK)
else if (IS_VLV)
else if (IS_GEN6 || IS_GEN7)

should do the trick without confusing anyone. And we avoid having to jump
through a few indirections when rechecking the code.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c      |    4 ++++
>  drivers/gpu/drm/i915/i915_drv.h      |    2 ++
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  3 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 48fc5ab..6c92ded 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -220,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.has_llc = 1,
> +	.has_turbo = 1,
>  };
>  
>  static const struct intel_device_info intel_sandybridge_m_info = {
> @@ -229,6 +230,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.has_llc = 1,
> +	.has_turbo = 1,
>  };
>  
>  static const struct intel_device_info intel_ivybridge_d_info = {
> @@ -237,6 +239,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.has_llc = 1,
> +	.has_turbo = 1,
>  };
>  
>  static const struct intel_device_info intel_ivybridge_m_info = {
> @@ -246,6 +249,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.has_llc = 1,
> +	.has_turbo = 1,
>  };
>  
>  static const struct intel_device_info intel_valleyview_m_info = {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 178a955..024f574 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -266,6 +266,7 @@ struct intel_device_info {
>  	u8 has_bsd_ring:1;
>  	u8 has_blt_ring:1;
>  	u8 has_llc:1;
> +	u8 has_turbo:1;
>  };
>  
>  #define I915_PPGTT_PD_ENTRIES 512
> @@ -1025,6 +1026,7 @@ struct drm_i915_file_private {
>  #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
>  #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
>  #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
> +#define HAS_TURBO(dev)		(INTEL_INFO(dev)->has_turbo)
>  #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
>  
>  #define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >=6)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8668d38..dc0ef17 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9715,7 +9715,7 @@ void intel_modeset_init(struct drm_device *dev)
>  		intel_init_emon(dev);
>  	}
>  
> -	if (IS_GEN6(dev) || IS_GEN7(dev)) {
> +	if (HAS_TURBO(dev)) {
>  		gen6_enable_rps(dev_priv);
>  		gen6_update_ring_freq(dev_priv);
>  	}
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 25/25] drm/i915: don't write ring regs until they're set up

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:46PM -0700, Jesse Barnes wrote:
> intel_clear_scanline_wait tries to clear ring wait conditions when we
> turn off pipes, to prevent hanging WAIT_EVENT and similar commands.  But
> we call it early before rings have been setup during initialization and
> shouldn't touch the ring regs yet.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Just a curious question: Does vlv not like this and blow up or is this
just something that poped up in register trace/code reviewing?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dc0ef17..1a8cb30 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3098,6 +3098,10 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
>  
>  	ring = LP_RING(dev_priv);
>  
> +	/* This may be called before rings are initialized */
> +	if (!ring->mmio_base)
> +		return;
> +
>  	tmp = I915_READ_CTL(ring);
>  	if (tmp & RING_WAIT)
>  		I915_WRITE_CTL(ring, tmp);
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 09/25] drm/915: program driain latency regs on ValleyView

[Adam Jackson]

[-- Attachment #1.1: Type: text/plain, Size: 395 bytes --]

On Wed, 2012-03-21 at 22:00 +0100, Daniel Vetter wrote:

> Bikeshed, but imo important: Can we make the unimportant part in these
> function names less noise and instead make the interesting part readable?
> I.e. s/valleyview/vlv/ and s/dl/drain_latency or drain_lat

Honestly I'd be in favor of that globally (ironlake -> ilk) as long as
we kept a glossary in the source too.

- ajax

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 198 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [RFC] ValleyView support

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:21PM -0700, Jesse Barnes wrote:
> In this set, you can see why I was asking about register offsets and
> splitting the display code.  Included are a few cleanups to help me keep
> my sanity, but as I mentioned in my other mail I think we should go
> further.
> 
> Many of these are ok to apply as-is, so let me know what order you'd
> like them in and I can re-post and work on the remainder.

Ok, I've gone through this mainly with a view how it integrates with the
current code. I haven't paid too much attention to the vlv enabling code
itself, but given that it's all new hw (that no one really has yet) I'm ok
as long as the new register definitions are properly reviewed. Even if
there are big opens (like the cacheability stuff) I don't mind to much, as
long as it's contained to vlv code paths.

Patch ordering is fine for me, too, safe for the 2 places I complained
about it.

One thing I've missed though is adding pci ids to intel-gtt.c. But while
reading the patches the integration there is rather hackis, so maybe
that's the reason for it. Wrt intel-gtt.c I think we should hold off with
reorganizing this until basic vlv and hsw code has landed. Yeah, that
means adding pci ids at a few more places :(

Cheers, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 22/25] drm/i915: remove some unneeded debug messages

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 510 bytes --]

On Wed, 21 Mar 2012 22:36:22 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:43PM -0700, Jesse Barnes wrote:
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> So you've achieved the contentless-error-msg nirvana? Luckily for you one
> of these is quality work from China ;-) Patch applied to next, thanks.

Heh looks like I rebased out the actual removal. :)

You can drop this message though...

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

[Adam Jackson]

[-- Attachment #1.1: Type: text/plain, Size: 462 bytes --]

On Wed, 2012-03-21 at 14:32 -0700, Jesse Barnes wrote:

> We need force wake, just not for any parts I've tested yet (the early
> ones had the Punit disabled).
> 
> This code adheres to the spec, but I'll need a part with the Punit
> enabled in order to test & verify.  Until then we can leave it disabled.

Can we consider Gunit and Punit to be roughly the analogues of GPU and
PCH?  Just trying to make sure I know what all the nouns mean.

- ajax

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 198 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 25/25] drm/i915: don't write ring regs until they're set up

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 809 bytes --]

On Wed, 21 Mar 2012 22:46:41 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:46PM -0700, Jesse Barnes wrote:
> > intel_clear_scanline_wait tries to clear ring wait conditions when we
> > turn off pipes, to prevent hanging WAIT_EVENT and similar commands.  But
> > we call it early before rings have been setup during initialization and
> > shouldn't touch the ring regs yet.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Just a curious question: Does vlv not like this and blow up or is this
> just something that poped up in register trace/code reviewing?

Just something that popped up.  No actual harm done afaict aside from
writing some real low register address during init...

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 16/25] drm/i915: add ValleyView specific force wake get/put functions

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 943 bytes --]

On Wed, 21 Mar 2012 17:55:58 -0400
Adam Jackson <ajax@redhat.com> wrote:

> On Wed, 2012-03-21 at 14:32 -0700, Jesse Barnes wrote:
> 
> > We need force wake, just not for any parts I've tested yet (the early
> > ones had the Punit disabled).
> > 
> > This code adheres to the spec, but I'll need a part with the Punit
> > enabled in order to test & verify.  Until then we can leave it disabled.
> 
> Can we consider Gunit and Punit to be roughly the analogues of GPU and
> PCH?  Just trying to make sure I know what all the nouns mean.

No it's really a sub-component, smaller than either of those.  It's
responsible for binding together the GT core, the display, and the
memory interface.  It exposes some regs in the PCI BAR (rudely shoving
aside the display ones) for doing things like forcewake, turbo, and tlb
flushing, along with top level interrupt handling.

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 02/25] drm/i915: add debug message when EDID fetch fails

[Ben Widawsky]

On Wed, 21 Mar 2012 13:53:12 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> On Wed, 21 Mar 2012 17:44:12 -0300
> Eugeni Dodonov <eugeni@dodonov.net> wrote:
> 
> > On Wed, Mar 21, 2012 at 16:48, Jesse Barnes
> > <jbarnes@virtuousgeek.org>wrote:
> > 
> > > +       } else {
> > 
> > +               DRM_DEBUG_KMS("failed to fetch edid\n");
> > >        }
> > >
> > 
> > 
> > Wouldn't it be prettier if we also add some:
> >    ...
> >    err = -ENXIO;
> > 
> > or similar error in that block, to let the caller know that we
> > failed as well?
> > 
> > 
> > >        return ret;
> > >
> > 
> 
> Maybe but I think most callers just check for the EDID later anyway.
> 
> Really this patch can be dropped, but I was wondering exactly where
> the GPIO side of things was failing and added some debug output...
> 

I guess it's not exactly an error if no modes were gotten, so
returning 0 seems right (and initially confusing to me as well). Can you
add some information about the connector and/or adapter. Otherwise I
don't think this is very helpful.

Re: [PATCH 03/25] drm/i915: re-order GT IIR bit definitions

[Ben Widawsky]

On Wed, 21 Mar 2012 12:48:24 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> They were all over the place, order them by position and add a few.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   20 ++++++++++++++------
>  1 files changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 52a06be..af5cd25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3063,18 +3063,26 @@
>  #define DE_PIPEB_VBLANK_IVB		(1<<5)
>  #define DE_PIPEA_VBLANK_IVB		(1<<0)
>  
> +#define MASTER_IER_VLV			0x4400c /* Gunit master IER */
> +#define   MASTER_INTERRUPT_ENABLE	(1<<31)
> +

Seems VLV_MASTER_IER would follow the convention.

>  #define DEISR   0x44000
>  #define DEIMR   0x44004
>  #define DEIIR   0x44008
>  #define DEIER   0x4400c
>  
>  /* GT interrupt */
> -#define GT_PIPE_NOTIFY		(1 << 4)
> -#define GT_SYNC_STATUS          (1 << 2)
> -#define GT_USER_INTERRUPT       (1 << 0)
> -#define GT_BSD_USER_INTERRUPT   (1 << 5)
> -#define GT_GEN6_BSD_USER_INTERRUPT	(1 << 12)
> -#define GT_BLT_USER_INTERRUPT	(1 << 22)
> +#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
> +#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
> +#define GT_BLT_USER_INTERRUPT			(1 << 22)
> +#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
> +#define GT_GEN6_BSD_USER_INTERRUPT		(1 << 12)
> +#define GT_BSD_USER_INTERRUPT			(1 << 5)
> +#define GT_L3_PARITY_ERROR_INTERRUPT		(1 << 5) /* IVB+ */
> +#define GT_PIPE_NOTIFY				(1 << 4)
> +#define GT_RENDER_CS_ERROR_INTERRUPT		(1 << 3)
> +#define GT_SYNC_STATUS				(1 << 2)
> +#define GT_USER_INTERRUPT			(1 << 0)

What about GT_GEN7_L3_PARITY_ERROR_INTERRUPT?

Similarly if GT_BLT_FLUSHDW_NOTIFY_INTERRUPT and
GT_BLT_CS_ERROR_INTERRUPT only apply after a certain generation maybe
add that info... I know this applies directly to your overall pitch to
restructure things, but for now at least try to keep it consistent, and
helpfully named (imho).

>  
>  #define GTISR   0x44010
>  #define GTIMR   0x44014

Re: [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

[Ben Widawsky]

On Wed, 21 Mar 2012 12:48:25 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> From: Rohit Jain <rohit.jain@intel.com>
> 
> Added support for parsing the OEM Customizable Modes Block (#20)
> in the VBIOS table.
> 
> Signed-off-by: Rohit Jain <rohit.jain@intel.com>
> Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Reviewed-by: Vijay A. Purushothaman <vijay.a.purushothaman@intel.com>
> Acked-by: Jesse Barnes <jesse.barnes@intel.com>
> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---

I'll be honest, I haven't read through the whole series yet, but I
really don't see the point of this patch, at least in the next few
patches. Could we modify the commit to describe why we need this (or
drop it)?

Re: [PATCH 05/25] drm/i915: add DPIO read/write functions for ValleyView

[Ben Widawsky]

On Wed, 21 Mar 2012 12:48:26 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> ValleyView and similar hardware (like CedarView) put some display
> related registers like the PLL controls and dividers on a DPIO bus.  Add
> simple indirect register access routines to get to those registers.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |    4 ++
>  drivers/gpu/drm/i915/i915_reg.h      |   55 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   76 ++++++++++++++++++++++++++++++++++
>  3 files changed, 135 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 83ace70..0294330 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -354,6 +354,10 @@ typedef struct drm_i915_private {
>  
>  	/* protects the irq masks */
>  	spinlock_t irq_lock;
> +
> +	/* DPIO indirect register protection */
> +	spinlock_t dpio_lock;
> +
>  	/** Cached value of IMR to avoid reads in updating the bitfield */
>  	u32 pipestat[2];
>  	u32 irq_mask;

I am not convinced we need the dpio_lock. Can't we just use
struct_mutex or the mode.config mutex? I'm not terribly opposed, more
curious than anything else.

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index af5cd25..ad6b5e0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -301,6 +301,61 @@
>  #define  DEBUG_RESET_RENDER		(1<<8)
>  #define  DEBUG_RESET_DISPLAY		(1<<9)
>  
> +/*
> + * DPIO - a special bus for various display related registers to hide behind:
> + *  0x800c: m1, m2, n, p1, p2, k dividers
> + *  0x8014: REF and SFR select
> + *  0x8014: N divider, VCO select
> + *  0x801c/3c: core clock bits
> + *  0x8048/68: low pass filter coefficients
> + *  0x8100: fast clock controls
> + */
> +#define DPIO_PKT			0x2100
> +#define  DPIO_RID			(0<<24)
> +#define  DPIO_OP_WRITE			(1<<16)
> +#define  DPIO_OP_READ			(0<<16)
> +#define  DPIO_PORTID			(0x12<<8)
> +#define  DPIO_BYTE			(0xf<<4)
> +#define  DPIO_BUSY			(1<<0) /* status only */
> +#define DPIO_DATA			0x2104
> +#define DPIO_REG			0x2108
> +#define DPIO_CTL			0x2110
> +#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
> +#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
> +#define  DPIO_SFR_BYPASS		(1<<1)
> +#define  DPIO_RESET			(1<<0)
> +
> +#define _DPIO_DIV_A			0x800c
> +#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
> +#define   DPIO_K_SHIFT			(24) /* 4 bits */
> +#define   DPIO_P1_SHIFT			(21) /* 3 bits */
> +#define   DPIO_P2_SHIFT			(16) /* 5 bits */
> +#define   DPIO_N_SHIFT			(12) /* 4 bits */
> +#define   DPIO_ENABLE_CALIBRATION	(1<<11)
> +#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
> +#define   DPIO_M2DIV_MASK		0xff
> +#define _DPIO_DIV_B			0x802c
> +#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
> +
> +#define _DPIO_REFSFR_A			0x8014
> +#define   DPIO_REFSEL_OVERRIDE		27
> +#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
> +#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
> +#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
> +#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
> +#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
> +#define _DPIO_REFSFR_B			0x8034
> +#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
> +
> +#define _DPIO_CORE_CLK_A		0x801c
> +#define _DPIO_CORE_CLK_B		0x803c
> +#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
> +
> +#define _DPIO_LFP_COEFF_A		0x8048
> +#define _DPIO_LFP_COEFF_B		0x8068
> +#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
> +
> +#define DPIO_FASTCLK_DISABLE		0x8100
>  
>  /*
>   * Fence registers
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index de1ba19..b8daeef 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -360,6 +360,79 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
>  	.find_pll = intel_find_pll_ironlake_dp,
>  };
>  
> +#define wait_for_atomic_us(COND, US) ({ \
> +	int i, ret__ = -ETIMEDOUT;	\
> +	for (i = 0; i < (US); i++) {	\
> +		if ((COND)) {		\
> +			ret__ = 0;	\
> +			break;		\
> +		}			\
> +		udelay(1);		\
> +	}				\
> +	ret__;				\
> +})

It'd be much friendlier if you put this with the other wait_for code in
intel_drv.h

> +
> +#if 0
> +static u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
> +{
> +	unsigned long flags;
> +	u32 val = 0;
> +
> +	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> +		DRM_ERROR("DPIO idle wait timed out\n");
> +		goto out_unlock;
> +	}
> +
> +	I915_WRITE(DPIO_REG, reg);
> +	I915_WRITE(DPIO_PKT, reg);
> +	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
> +		   DPIO_BYTE);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> +		DRM_ERROR("DPIO read wait timed out\n");
> +		goto out_unlock;
> +	}
> +	val = I915_READ(DPIO_DATA);
> +
> +out_unlock:
> +	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
> +	return val;
> +}
> +#endif

I've not read the spec at all, but it looks suspicious that you write
reg to DPIO_PKT, followed by a value presumably overwriting reg. Maybe a
comment to clarify why two back to back writes to the same register
(without a posting read)?

> +
> +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> +			     u32 val)
> +{
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> +		DRM_ERROR("DPIO idle wait timed out\n");
> +		goto out_unlock;
> +	}
> +
> +	I915_WRITE(DPIO_DATA, val);
> +	I915_WRITE(DPIO_REG, reg);
> +	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
> +		   DPIO_BYTE);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
> +		DRM_ERROR("DPIO write wait timed out\n");
> +
> +out_unlock:
> +	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
> +}
> +
> +static void vlv_init_dpio(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* Reset the DPIO config */
> +	I915_WRITE(DPIO_CTL, 0);
> +	POSTING_READ(DPIO_CTL);
> +	I915_WRITE(DPIO_CTL, 1);
> +	POSTING_READ(DPIO_CTL);
> +}
> +
>  static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
>  						int refclk)
>  {
> @@ -9187,6 +9260,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
>  	if (IS_IRONLAKE_M(dev))
>  		ironlake_disable_rc6(dev);
>  
> +	if (IS_VALLEYVIEW(dev))
> +		vlv_init_dpio(dev);
> +
>  	mutex_unlock(&dev->struct_mutex);
>  
>  	/* Disable the irq before mode object teardown, for the irq might

Re: [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions

[Ben Widawsky]

On Wed, 21 Mar 2012 12:48:29 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> 
> Add some VLV limit structures and update the PLL code.
> 
> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |  231 +++++++++++++++++++++++++++++++++-
>  2 files changed, 229 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7d33c49..bb6b49f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -866,6 +866,7 @@
>  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
> +#define   DPLL_LOCK			(1<<15) /* VLV */
>  #define   DPLL_VOLTAGE_LDO		(1<<14)
>  #define   DPLL_INTEGRATED_CLOCK		(1<<13)
>  #define   DPLL_RATE_SWITCH		(1<<8)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f9ac7b7..ea64dc8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -98,6 +98,10 @@ static bool
>  intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
>  			   int target, int refclk, intel_clock_t *match_clock,
>  			   intel_clock_t *best_clock);
> +static bool
> +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
> +			int target, int refclk, intel_clock_t *match_clock,
> +			intel_clock_t *best_clock);
>  
>  static inline u32 /* units of 100MHz */
>  intel_fdi_link_freq(struct drm_device *dev)
> @@ -360,6 +364,48 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
>  	.find_pll = intel_find_pll_ironlake_dp,
>  };
>  
> +static const intel_limit_t intel_limits_vlv_dac = {
> +	.dot = { .min = 25000, .max = 270000 },
> +	.vco = { .min = 4000000, .max = 6000000 },
> +	.n = { .min = 1, .max = 7 },
> +	.m = { .min = 22, .max = 450 }, /* guess */
> +	.m1 = { .min = 2, .max = 3 },
> +	.m2 = { .min = 11, .max = 156 },
> +	.p = { .min = 10, .max = 30 },
> +	.p1 = { .min = 2, .max = 3 },
> +	.p2 = { .dot_limit = 270000,
> +		.p2_slow = 10, .p2_fast = 5 },
> +	.find_pll = intel_vlv_find_best_pll,
> +};
> +
> +static const intel_limit_t intel_limits_vlv_hdmi = {
> +	.dot = { .min = 20000, .max = 165000 },
> +	.vco = { .min = 5994000, .max = 4000000 },
> +	.n = { .min = 1, .max = 7 },
> +	.m = { .min = 60, .max = 300 }, /* guess */
> +	.m1 = { .min = 2, .max = 3 },
> +	.m2 = { .min = 11, .max = 156 },
> +	.p = { .min = 10, .max = 30 },
> +	.p1 = { .min = 2, .max = 3 },
> +	.p2 = { .dot_limit = 270000,
> +		.p2_slow = 10, .p2_fast = 5 },
> +	.find_pll = intel_vlv_find_best_pll,
> +};
> +
> +static const intel_limit_t intel_limits_vlv_dp = {
> +	.dot = { .min = 162000, .max = 270000 },
> +	.vco = { .min = 5994000, .max = 4000000 },
> +	.n = { .min = 1, .max = 7 },
> +	.m = { .min = 60, .max = 300 }, /* guess */
> +	.m1 = { .min = 2, .max = 3 },
> +	.m2 = { .min = 11, .max = 156 },
> +	.p = { .min = 10, .max = 30 },
> +	.p1 = { .min = 2, .max = 3 },
> +	.p2 = { .dot_limit = 270000,
> +		.p2_slow = 10, .p2_fast = 5 },
> +	.find_pll = intel_vlv_find_best_pll,
> +};

is vco.min > vco.max correct? (too lazy to check how it's used).

> +
>  #define wait_for_atomic_us(COND, US) ({ \
>  	int i, ret__ = -ETIMEDOUT;	\
>  	for (i = 0; i < (US); i++) {	\
> @@ -504,6 +550,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
>  			limit = &intel_limits_pineview_lvds;
>  		else
>  			limit = &intel_limits_pineview_sdvo;
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
> +			limit = &intel_limits_vlv_dac;
> +		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> +			limit = &intel_limits_vlv_hdmi;
> +		else
> +			limit = &intel_limits_vlv_dp;
>  	} else if (!IS_GEN2(dev)) {
>  		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
>  			limit = &intel_limits_i9xx_lvds;
> @@ -779,6 +832,84 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
>  	return true;
>  }
>  
> +static bool
> +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
> +			int target, int refclk, intel_clock_t *match_clock,
> +			intel_clock_t *best_clock)
> +{
> +	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
> +	u32 m, n, fastclk, minvco, maxvco;
> +	u32 updrate, minupdate, fracbits, p;
> +	unsigned long bestppm, ppm, absppm;
> +	int dotclk;
> +
> +	dotclk = target * 1000;
> +
> +	bestppm = 1000000;
> +	ppm = 0;
> +	absppm = 0;
> +
> +	fastclk = dotclk / (2*100);
> +	minvco = limit->vco.min;
> +	maxvco = limit->vco.max;
> +	updrate = 0;
> +	minupdate = 19200;
> +	fracbits = 1;
> +
> +	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
> +	bestm1 = bestm2 = bestp1 = bestp2 = 0;
> +
> +	for(n = 1; n <= ((refclk) / minupdate); n++) {
> +		updrate = refclk / n;
> +		for (p1 = 3; p1 > 1; p1--) {
> +			for (p2 = 21; p2 > 0; p2--) {
> +				if (p2 > 10)
> +					p2 = p2 - 1;
> +				p = p1 * p2;
> +
> +				for( m1=2; m1 <= 3; m1++) {
> +					m2 = (((2*(fastclk * p * n / m1 )) +
> +					       refclk) / (2*refclk));
> +					m = m1 * m2;
> +					vco = updrate * m;
> +					if(vco >= minvco && vco < maxvco) {
> +						ppm = 1000000 *((vco / p) -
> +								fastclk) /
> +							fastclk;
> +						absppm = (ppm > 0)? ppm: (-ppm);
> +						if (absppm < 100 &&
> +						    ((p1 * p2) >
> +						     (bestp1 * bestp2))) {
> +							bestppm = 0;
> +							bestn = n;
> +							bestm1 = m1;
> +							bestm2 = m2;
> +							bestp1 = p1;
> +							bestp2 = p2;
> +						}
> +						if (absppm < bestppm - 10) {
> +							bestppm = absppm;
> +							bestn = n;
> +							bestm1 = m1;
> +							bestm2 = m2;
> +							bestp1 = p1;
> +							bestp2 = p2;
> +						}
> +					}
> +				}
> +			} /* Next p2 */
> +		} /* Next p1 */
> +	}/* Next n */
> +
> +	best_clock->n = bestn;
> +	best_clock->m1 = bestm1;
> +	best_clock->m2 = bestm2;
> +	best_clock->p1 = bestp1;
> +	best_clock->p2 = bestp2;
> +
> +	return true;
> +}
> +

I'm not seeing how this ever returns false; And reading this function
hurts my eyes.

>  /**
>   * intel_wait_for_vblank - wait for vblank on a given pipe
>   * @dev: drm device
> @@ -1221,7 +1352,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	u32 val;
>  
>  	/* No really, not for ILK+ */
> -	BUG_ON(dev_priv->info->gen >= 5);
> +	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
>  
>  	/* PLL is protected by panel, make sure we can write it */
>  	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> @@ -2966,6 +3097,7 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
>  		return;
>  
>  	ring = LP_RING(dev_priv);
> +
>  	tmp = I915_READ_CTL(ring);
>  	if (tmp & RING_WAIT)
>  		I915_WRITE_CTL(ring, tmp);
> @@ -5169,14 +5301,38 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
>  	return display_bpc != bpc;
>  }
>  
> +static int vlv_get_refclk(struct drm_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int refclk = 27000; /* for DP & HDMI */
> +
> +	return 100000; /* only one validated so far */
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
> +		refclk = 96000;
> +	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> +		if (intel_panel_use_ssc(dev_priv))
> +			refclk = 100000;
> +		else
> +			refclk = 96000;
> +	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> +		refclk = 100000;
> +	}
> +
> +	return refclk;
> +}
> +
>  static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
>  {
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int refclk;
>  
> -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> -	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> +	if (IS_VALLEYVIEW(dev)) {
> +		refclk = vlv_get_refclk(crtc);
> +	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		   intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
>  		refclk = dev_priv->lvds_ssc_freq * 1000;
>  		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
>  			      refclk / 1000);
> @@ -5301,6 +5457,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
>  	I915_WRITE(LVDS, temp);
>  }
>  
> +static void vlv_update_pll(struct drm_crtc *crtc,
> +			   struct drm_display_mode *mode,
> +			   struct drm_display_mode *adjusted_mode,
> +			   intel_clock_t *clock, intel_clock_t *reduced_clock,
> +			   int refclk, int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll, mdiv, pdiv;
> +	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> +	bool is_hdmi;
> +
> +	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +
> +	bestn = clock->n;
> +	bestm1 = clock->m1;
> +	bestm2 = clock->m2;
> +	bestp1 = clock->p1;
> +	bestp2 = clock->p2;
> +
> +	/* Enable DPIO clock input */
> +	dpll = DPLL_EXT_BUFFER_ENABLE | DPLL_REFA_CLK_ENABLE |
> +		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK;
> +	I915_WRITE(DPLL(pipe), dpll);
> +	POSTING_READ(DPLL(pipe));
> +
> +	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> +	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
> +	mdiv |= ((bestn << DPIO_N_SHIFT));
> +	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
> +	mdiv |= (1 << DPIO_K_SHIFT);
> +	mdiv |= DPIO_ENABLE_CALIBRATION;
> +	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
> +
> +	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
> +
> +	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
> +		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> +		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> +	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
> +
> +	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll);
> +	POSTING_READ(DPLL(pipe));
> +	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK) == DPLL_LOCK), 1))
> +		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> +
> +	if (is_hdmi) {
> +		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> +
> +		if (temp > 1)
> +			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +		else
> +			temp = 0;
> +
> +		I915_WRITE(DPLL_MD(pipe), temp);
> +		POSTING_READ(DPLL_MD(pipe));
> +	}
> +
> +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
> +}
> +
>  static void i9xx_update_pll(struct drm_crtc *crtc,
>  			    struct drm_display_mode *mode,
>  			    struct drm_display_mode *adjusted_mode,
> @@ -5555,6 +5777,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	if (IS_GEN2(dev))
>  		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> +	else if (IS_VALLEYVIEW(dev))
> +		vlv_update_pll(crtc, mode, adjusted_mode, &clock, NULL,
> +			       refclk, num_connectors);
>  	else
>  		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>  				has_reduced_clock ? &reduced_clock : NULL,

Re: [PATCH 08/25] drm/i915: ValleyView mode setting limits and PLL functions

[Purushothaman, Vijay A]

> -----Original Message-----
> From: intel-gfx-
> bounces+vijay.a.purushothaman=intel.com@lists.freedesktop.org [mailto:intel-
> gfx-bounces+vijay.a.purushothaman=intel.com@lists.freedesktop.org] On
> Behalf Of Ben Widawsky
> Sent: Wednesday, March 21, 2012 8:54 PM
> To: Jesse Barnes
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 08/25] drm/i915: ValleyView mode setting limits
> and PLL functions
> 
> On Wed, 21 Mar 2012 12:48:29 -0700
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> >
> > Add some VLV limit structures and update the PLL code.
> >
> > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |    1 +
> >  drivers/gpu/drm/i915/intel_display.c |  231
> > +++++++++++++++++++++++++++++++++-
> >  2 files changed, 229 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 7d33c49..bb6b49f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -866,6 +866,7 @@
> >  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
> >  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
> >  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /*
> Pineview */
> > +#define   DPLL_LOCK			(1<<15) /* VLV */
> >  #define   DPLL_VOLTAGE_LDO		(1<<14)
> >  #define   DPLL_INTEGRATED_CLOCK		(1<<13)
> >  #define   DPLL_RATE_SWITCH		(1<<8)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index f9ac7b7..ea64dc8 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -98,6 +98,10 @@ static bool
> >  intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
> >  			   int target, int refclk, intel_clock_t *match_clock,
> >  			   intel_clock_t *best_clock);
> > +static bool
> > +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
> > +			int target, int refclk, intel_clock_t *match_clock,
> > +			intel_clock_t *best_clock);
> >
> >  static inline u32 /* units of 100MHz */  intel_fdi_link_freq(struct
> > drm_device *dev) @@ -360,6 +364,48 @@ static const intel_limit_t
> > intel_limits_ironlake_display_port = {
> >  	.find_pll = intel_find_pll_ironlake_dp,  };
> >
> > +static const intel_limit_t intel_limits_vlv_dac = {
> > +	.dot = { .min = 25000, .max = 270000 },
> > +	.vco = { .min = 4000000, .max = 6000000 },
> > +	.n = { .min = 1, .max = 7 },
> > +	.m = { .min = 22, .max = 450 }, /* guess */
> > +	.m1 = { .min = 2, .max = 3 },
> > +	.m2 = { .min = 11, .max = 156 },
> > +	.p = { .min = 10, .max = 30 },
> > +	.p1 = { .min = 2, .max = 3 },
> > +	.p2 = { .dot_limit = 270000,
> > +		.p2_slow = 10, .p2_fast = 5 },
> > +	.find_pll = intel_vlv_find_best_pll, };
> > +
> > +static const intel_limit_t intel_limits_vlv_hdmi = {
> > +	.dot = { .min = 20000, .max = 165000 },
> > +	.vco = { .min = 5994000, .max = 4000000 },
> > +	.n = { .min = 1, .max = 7 },
> > +	.m = { .min = 60, .max = 300 }, /* guess */
> > +	.m1 = { .min = 2, .max = 3 },
> > +	.m2 = { .min = 11, .max = 156 },
> > +	.p = { .min = 10, .max = 30 },
> > +	.p1 = { .min = 2, .max = 3 },
> > +	.p2 = { .dot_limit = 270000,
> > +		.p2_slow = 10, .p2_fast = 5 },
> > +	.find_pll = intel_vlv_find_best_pll, };
> > +
> > +static const intel_limit_t intel_limits_vlv_dp = {
> > +	.dot = { .min = 162000, .max = 270000 },
> > +	.vco = { .min = 5994000, .max = 4000000 },
> > +	.n = { .min = 1, .max = 7 },
> > +	.m = { .min = 60, .max = 300 }, /* guess */
> > +	.m1 = { .min = 2, .max = 3 },
> > +	.m2 = { .min = 11, .max = 156 },
> > +	.p = { .min = 10, .max = 30 },
> > +	.p1 = { .min = 2, .max = 3 },
> > +	.p2 = { .dot_limit = 270000,
> > +		.p2_slow = 10, .p2_fast = 5 },
> > +	.find_pll = intel_vlv_find_best_pll, };
> 
> is vco.min > vco.max correct? (too lazy to check how it's used).
> 
> > +
> >  #define wait_for_atomic_us(COND, US) ({ \
> >  	int i, ret__ = -ETIMEDOUT;	\
> >  	for (i = 0; i < (US); i++) {	\
> > @@ -504,6 +550,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc
> *crtc, int refclk)
> >  			limit = &intel_limits_pineview_lvds;
> >  		else
> >  			limit = &intel_limits_pineview_sdvo;
> > +	} else if (IS_VALLEYVIEW(dev)) {
> > +		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
> > +			limit = &intel_limits_vlv_dac;
> > +		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> > +			limit = &intel_limits_vlv_hdmi;
> > +		else
> > +			limit = &intel_limits_vlv_dp;
> >  	} else if (!IS_GEN2(dev)) {
> >  		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> >  			limit = &intel_limits_i9xx_lvds;
> > @@ -779,6 +832,84 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct
> drm_crtc *crtc,
> >  	return true;
> >  }
> >
> > +static bool
> > +intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
> > +			int target, int refclk, intel_clock_t *match_clock,
> > +			intel_clock_t *best_clock)
> > +{
> > +	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
> > +	u32 m, n, fastclk, minvco, maxvco;
> > +	u32 updrate, minupdate, fracbits, p;
> > +	unsigned long bestppm, ppm, absppm;
> > +	int dotclk;
> > +
> > +	dotclk = target * 1000;
> > +
> > +	bestppm = 1000000;
> > +	ppm = 0;
> > +	absppm = 0;
> > +
> > +	fastclk = dotclk / (2*100);
> > +	minvco = limit->vco.min;
> > +	maxvco = limit->vco.max;
> > +	updrate = 0;
> > +	minupdate = 19200;
> > +	fracbits = 1;
> > +
> > +	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
> > +	bestm1 = bestm2 = bestp1 = bestp2 = 0;
> > +
> > +	for(n = 1; n <= ((refclk) / minupdate); n++) {
> > +		updrate = refclk / n;
> > +		for (p1 = 3; p1 > 1; p1--) {
> > +			for (p2 = 21; p2 > 0; p2--) {
> > +				if (p2 > 10)
> > +					p2 = p2 - 1;
> > +				p = p1 * p2;
> > +
> > +				for( m1=2; m1 <= 3; m1++) {
> > +					m2 = (((2*(fastclk * p * n / m1 )) +
> > +					       refclk) / (2*refclk));
> > +					m = m1 * m2;
> > +					vco = updrate * m;
> > +					if(vco >= minvco && vco < maxvco) {
> > +						ppm = 1000000 *((vco / p) -
> > +								fastclk) /
> > +							fastclk;
> > +						absppm = (ppm > 0)? ppm: (-
> ppm);
> > +						if (absppm < 100 &&
> > +						    ((p1 * p2) >
> > +						     (bestp1 * bestp2))) {
> > +							bestppm = 0;
> > +							bestn = n;
> > +							bestm1 = m1;
> > +							bestm2 = m2;
> > +							bestp1 = p1;
> > +							bestp2 = p2;
> > +						}
> > +						if (absppm < bestppm - 10) {
> > +							bestppm = absppm;
> > +							bestn = n;
> > +							bestm1 = m1;
> > +							bestm2 = m2;
> > +							bestp1 = p1;
> > +							bestp2 = p2;
> > +						}
> > +					}
> > +				}
> > +			} /* Next p2 */
> > +		} /* Next p1 */
> > +	}/* Next n */
> > +
> > +	best_clock->n = bestn;
> > +	best_clock->m1 = bestm1;
> > +	best_clock->m2 = bestm2;
> > +	best_clock->p1 = bestp1;
> > +	best_clock->p2 = bestp2;
> > +
> > +	return true;
> > +}
> > +
> 
> I'm not seeing how this ever returns false; And reading this function hurts my
> eyes.
> 

This exact piece of code is used as it is from h/w scripts for initial testing purpose. I will send a revised patch. 


> >  /**
> >   * intel_wait_for_vblank - wait for vblank on a given pipe
> >   * @dev: drm device
> > @@ -1221,7 +1352,7 @@ static void intel_enable_pll(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> >  	u32 val;
> >
> >  	/* No really, not for ILK+ */
> > -	BUG_ON(dev_priv->info->gen >= 5);
> > +	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >=
> 5);
> >
> >  	/* PLL is protected by panel, make sure we can write it */
> >  	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) @@ -2966,6
> > +3097,7 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
> >  		return;
> >
> >  	ring = LP_RING(dev_priv);
> > +
> >  	tmp = I915_READ_CTL(ring);
> >  	if (tmp & RING_WAIT)
> >  		I915_WRITE_CTL(ring, tmp);
> > @@ -5169,14 +5301,38 @@ static bool intel_choose_pipe_bpp_dither(struct
> drm_crtc *crtc,
> >  	return display_bpc != bpc;
> >  }
> >
> > +static int vlv_get_refclk(struct drm_crtc *crtc) {
> > +	struct drm_device *dev = crtc->dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	int refclk = 27000; /* for DP & HDMI */
> > +
> > +	return 100000; /* only one validated so far */
> > +
> > +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
> > +		refclk = 96000;
> > +	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> > +		if (intel_panel_use_ssc(dev_priv))
> > +			refclk = 100000;
> > +		else
> > +			refclk = 96000;
> > +	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
> > +		refclk = 100000;
> > +	}
> > +
> > +	return refclk;
> > +}
> > +
> >  static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
> > {
> >  	struct drm_device *dev = crtc->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	int refclk;
> >
> > -	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> > -	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> > +	if (IS_VALLEYVIEW(dev)) {
> > +		refclk = vlv_get_refclk(crtc);
> > +	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> > +		   intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> >  		refclk = dev_priv->lvds_ssc_freq * 1000;
> >  		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
> >  			      refclk / 1000);
> > @@ -5301,6 +5457,72 @@ static void intel_update_lvds(struct drm_crtc *crtc,
> intel_clock_t *clock,
> >  	I915_WRITE(LVDS, temp);
> >  }
> >
> > +static void vlv_update_pll(struct drm_crtc *crtc,
> > +			   struct drm_display_mode *mode,
> > +			   struct drm_display_mode *adjusted_mode,
> > +			   intel_clock_t *clock, intel_clock_t *reduced_clock,
> > +			   int refclk, int num_connectors) {
> > +	struct drm_device *dev = crtc->dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +	int pipe = intel_crtc->pipe;
> > +	u32 dpll, mdiv, pdiv;
> > +	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> > +	bool is_hdmi;
> > +
> > +	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> > +
> > +	bestn = clock->n;
> > +	bestm1 = clock->m1;
> > +	bestm2 = clock->m2;
> > +	bestp1 = clock->p1;
> > +	bestp2 = clock->p2;
> > +
> > +	/* Enable DPIO clock input */
> > +	dpll = DPLL_EXT_BUFFER_ENABLE | DPLL_REFA_CLK_ENABLE |
> > +		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK;
> > +	I915_WRITE(DPLL(pipe), dpll);
> > +	POSTING_READ(DPLL(pipe));
> > +
> > +	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 &
> DPIO_M2DIV_MASK));
> > +	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
> > +	mdiv |= ((bestn << DPIO_N_SHIFT));
> > +	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
> > +	mdiv |= (1 << DPIO_K_SHIFT);
> > +	mdiv |= DPIO_ENABLE_CALIBRATION;
> > +	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
> > +
> > +	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
> > +
> > +	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
> > +		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> > +		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 <<
> DPIO_CLK_BIAS_CTL_SHIFT);
> > +	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
> > +
> > +	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
> > +
> > +	dpll |= DPLL_VCO_ENABLE;
> > +	I915_WRITE(DPLL(pipe), dpll);
> > +	POSTING_READ(DPLL(pipe));
> > +	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK) == DPLL_LOCK), 1))
> > +		DRM_ERROR("DPLL %d failed to lock\n", pipe);
> > +
> > +	if (is_hdmi) {
> > +		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> > +
> > +		if (temp > 1)
> > +			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> > +		else
> > +			temp = 0;
> > +
> > +		I915_WRITE(DPLL_MD(pipe), temp);
> > +		POSTING_READ(DPLL_MD(pipe));
> > +	}
> > +
> > +	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */ }
> > +
> >  static void i9xx_update_pll(struct drm_crtc *crtc,
> >  			    struct drm_display_mode *mode,
> >  			    struct drm_display_mode *adjusted_mode, @@ -
> 5555,6 +5777,9 @@
> > static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
> >
> >  	if (IS_GEN2(dev))
> >  		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> > +	else if (IS_VALLEYVIEW(dev))
> > +		vlv_update_pll(crtc, mode, adjusted_mode, &clock, NULL,
> > +			       refclk, num_connectors);
> >  	else
> >  		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> >  				has_reduced_clock ? &reduced_clock : NULL,
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 1174 bytes --]

On Wed, 21 Mar 2012 18:30:11 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Wed, 21 Mar 2012 12:48:25 -0700
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > From: Rohit Jain <rohit.jain@intel.com>
> > 
> > Added support for parsing the OEM Customizable Modes Block (#20)
> > in the VBIOS table.
> > 
> > Signed-off-by: Rohit Jain <rohit.jain@intel.com>
> > Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
> > Reviewed-by: Vijay A. Purushothaman <vijay.a.purushothaman@intel.com>
> > Acked-by: Jesse Barnes <jesse.barnes@intel.com>
> > Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> > Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> 
> I'll be honest, I haven't read through the whole series yet, but I
> really don't see the point of this patch, at least in the next few
> patches. Could we modify the commit to describe why we need this (or
> drop it)?

This one is unrelated to VLV, it's just extra VBT gravy.  Obviously it
needs to stuff the mode info somewhere though...

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

[Ben Widawsky]

On Thu, 22 Mar 2012 08:45:32 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> On Wed, 21 Mar 2012 18:30:11 -0700
> Ben Widawsky <ben@bwidawsk.net> wrote:
> 
> > On Wed, 21 Mar 2012 12:48:25 -0700
> > Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > 
> > > From: Rohit Jain <rohit.jain@intel.com>
> > > 
> > > Added support for parsing the OEM Customizable Modes Block (#20)
> > > in the VBIOS table.
> > > 
> > > Signed-off-by: Rohit Jain <rohit.jain@intel.com>
> > > Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
> > > Reviewed-by: Vijay A. Purushothaman
> > > <vijay.a.purushothaman@intel.com> Acked-by: Jesse Barnes
> > > <jesse.barnes@intel.com> Reviewed-by: Eugeni Dodonov
> > > <eugeni.dodonov@intel.com> Signed-off-by: Artem Bityutskiy
> > > <artem.bityutskiy@linux.intel.com> Signed-off-by: Jesse Barnes
> > > <jbarnes@virtuousgeek.org> ---
> > 
> > I'll be honest, I haven't read through the whole series yet, but I
> > really don't see the point of this patch, at least in the next few
> > patches. Could we modify the commit to describe why we need this (or
> > drop it)?
> 
> This one is unrelated to VLV, it's just extra VBT gravy.  Obviously it
> needs to stuff the mode info somewhere though...
> 

THe HW can behave one in two ways, you read the info out and that is
required to advance the internal state machine to get to the next info
you care about. Or, you read the info out and nobody knows or cares. I
truly don't know how this HW works yet, but I'd say if it's the former
it should be added as a comment to the code. If it's the latter, we
should drop the patch.

$.02

Re: [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 2415 bytes --]

On Thu, 22 Mar 2012 09:11:37 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Thu, 22 Mar 2012 08:45:32 -0700
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > On Wed, 21 Mar 2012 18:30:11 -0700
> > Ben Widawsky <ben@bwidawsk.net> wrote:
> > 
> > > On Wed, 21 Mar 2012 12:48:25 -0700
> > > Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > > 
> > > > From: Rohit Jain <rohit.jain@intel.com>
> > > > 
> > > > Added support for parsing the OEM Customizable Modes Block (#20)
> > > > in the VBIOS table.
> > > > 
> > > > Signed-off-by: Rohit Jain <rohit.jain@intel.com>
> > > > Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
> > > > Reviewed-by: Vijay A. Purushothaman
> > > > <vijay.a.purushothaman@intel.com> Acked-by: Jesse Barnes
> > > > <jesse.barnes@intel.com> Reviewed-by: Eugeni Dodonov
> > > > <eugeni.dodonov@intel.com> Signed-off-by: Artem Bityutskiy
> > > > <artem.bityutskiy@linux.intel.com> Signed-off-by: Jesse Barnes
> > > > <jbarnes@virtuousgeek.org> ---
> > > 
> > > I'll be honest, I haven't read through the whole series yet, but I
> > > really don't see the point of this patch, at least in the next few
> > > patches. Could we modify the commit to describe why we need this (or
> > > drop it)?
> > 
> > This one is unrelated to VLV, it's just extra VBT gravy.  Obviously it
> > needs to stuff the mode info somewhere though...
> > 
> 
> THe HW can behave one in two ways, you read the info out and that is
> required to advance the internal state machine to get to the next info
> you care about. Or, you read the info out and nobody knows or cares. I
> truly don't know how this HW works yet, but I'd say if it's the former
> it should be added as a comment to the code. If it's the latter, we
> should drop the patch.

As I said, it doesn't belong in the VLV patchset.  It has nothing to do
with touch hw though; it's just a way for us to get any OEM custom
modes out of the VBT.  For example on a given platform the VBT panel
data may have a certain timing, but an additional timing may also be
preferred, which might be specified in this block.

So we should parse it, and add it to the appropriate connector's mode
list.  This patch only does the parsing, but doesn't add it to the mode
list, so isn't useful by itself.

At any rate, I'll drop it from this series.

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 10/25] drm/i915: Enable DP panel power sequencing for ValleyView

[Ben Widawsky]

On Wed, 21 Mar 2012 12:48:31 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> VLV supports two dp panels, there are two set of panel power sequence
> registers which needed to be programmed based on the configured
> pipe. This patch add supports for the same
> 
> Signed-off-by: Beeresh G <beeresh.g@intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 03/25] drm/i915: re-order GT IIR bit definitions

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 2526 bytes --]

On Wed, 21 Mar 2012 18:10:36 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Wed, 21 Mar 2012 12:48:24 -0700
> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> 
> > They were all over the place, order them by position and add a few.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |   20 ++++++++++++++------
> >  1 files changed, 14 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 52a06be..af5cd25 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3063,18 +3063,26 @@
> >  #define DE_PIPEB_VBLANK_IVB		(1<<5)
> >  #define DE_PIPEA_VBLANK_IVB		(1<<0)
> >  
> > +#define MASTER_IER_VLV			0x4400c /* Gunit master IER */
> > +#define   MASTER_INTERRUPT_ENABLE	(1<<31)
> > +
> 
> Seems VLV_MASTER_IER would follow the convention.
> 
> >  #define DEISR   0x44000
> >  #define DEIMR   0x44004
> >  #define DEIIR   0x44008
> >  #define DEIER   0x4400c
> >  
> >  /* GT interrupt */
> > -#define GT_PIPE_NOTIFY		(1 << 4)
> > -#define GT_SYNC_STATUS          (1 << 2)
> > -#define GT_USER_INTERRUPT       (1 << 0)
> > -#define GT_BSD_USER_INTERRUPT   (1 << 5)
> > -#define GT_GEN6_BSD_USER_INTERRUPT	(1 << 12)
> > -#define GT_BLT_USER_INTERRUPT	(1 << 22)
> > +#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT		(1 << 26)
> > +#define GT_BLT_CS_ERROR_INTERRUPT		(1 << 25)
> > +#define GT_BLT_USER_INTERRUPT			(1 << 22)
> > +#define GT_BSD_CS_ERROR_INTERRUPT		(1 << 15)
> > +#define GT_GEN6_BSD_USER_INTERRUPT		(1 << 12)
> > +#define GT_BSD_USER_INTERRUPT			(1 << 5)
> > +#define GT_L3_PARITY_ERROR_INTERRUPT		(1 << 5) /* IVB+ */
> > +#define GT_PIPE_NOTIFY				(1 << 4)
> > +#define GT_RENDER_CS_ERROR_INTERRUPT		(1 << 3)
> > +#define GT_SYNC_STATUS				(1 << 2)
> > +#define GT_USER_INTERRUPT			(1 << 0)
> 
> What about GT_GEN7_L3_PARITY_ERROR_INTERRUPT?

Yeah it's gen7+ you're right.

> Similarly if GT_BLT_FLUSHDW_NOTIFY_INTERRUPT and
> GT_BLT_CS_ERROR_INTERRUPT only apply after a certain generation maybe
> add that info... I know this applies directly to your overall pitch to
> restructure things, but for now at least try to keep it consistent, and
> helpfully named (imho).

Docs aren't very helpful here; the ILK ones say they're the same but
I'm suspicious...

I'll gen6 the new ones though; we don't use them yet anyway.
-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

[Jesse Barnes]

[-- Attachment #1.1: Type: text/plain, Size: 1796 bytes --]

On Wed, 21 Mar 2012 14:36:47 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> On Wed, 21 Mar 2012 22:33:43 +0100
> Daniel Vetter <daniel@ffwll.ch> wrote:
> 
> > On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote:
> > > Although internally the MMIO offsets for display regs haven't changed,
> > > their visibility through the PCI BAR has been affected by the addition
> > > of the Gunit, which occupies the low part of the address space.
> > > 
> > > Display regs on VLV are offset into the BAR by 0x180000, so we need to
> > > add that for any display register offset.
> > > 
> > > This patch is a hack to do just that, but ultimately we need to split
> > > our display and render code more cleanly and add accessor functions for
> > > them.
> > > 
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > 
> > Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like
> > you've proposed + I915_DISPLAY_READ/WRITE like we already have for the
> > ring stuff is much better ...
> 
> I nearly got violent with the hw guys when they told me...
> 
> But yeah I think a display reg wrapper with an offset is probably the
> least offensive.

Ok started on this but quickly got frustrated.  Should we apply this
everywhere, even to PCH and ilk+ stuff?  If not, it'll get
inconsistent, if we do, it'll be confusing.

I wonder if we should split intel_display.c first, and only apply the
new macro to the gmch code?  But that still leaves the various port
files and gpio/gmbus... but those have pretty clear PCH splits too
right?

Suggestions welcome, but there may be no way to avoid a complete audit
of every single read/write to see if it should be converted (ugg).

-- 
Jesse Barnes, Intel Open Source Technology Center

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 11/25] drm/i915: Enable HDMI on ValleyView

[Shobhit Kumar]

On Thursday 22 March 2012 02:32 AM, Daniel Vetter wrote:
> On Wed, Mar 21, 2012 at 12:48:32PM -0700, Jesse Barnes wrote:
>> From: Shobhit Kumar<shobhit.kumar@intel.com>
>>
>> HDMI register offsets are different in Valleyview. Add support for the
>> same.
>>
>> Signed-off-by: Beeresh G<beeresh.g@intel.com>
>> Signed-off-by: Shobhit Kumar<shobhit.kumar@intel.com>
>> Reviewed-by: Vijay Purushothaman<vijay.a.purushothaman@intel.com>
>> Reviewed-by: Jesse Barnes<jesse.barnes@intel.com>
>> Signed-off-by: Jesse Barnes<jbarnes@virtuousgeek.org>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h   |   16 +++++++++++++++
>>   drivers/gpu/drm/i915/intel_hdmi.c |   39 ++++++++++++++++++++++++++++++++++++-
>>   2 files changed, 54 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c187398..f04bfbf 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3452,6 +3452,21 @@
>>   #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>>   #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>>
>> +#define VLV_VIDEO_DIP_CTL_A		0x60220
>> +#define VLV_VIDEO_DIP_DATA_A		0x60208
>> +#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
>> +
>> +#define VLV_VIDEO_DIP_CTL_B		0x61170
>> +#define VLV_VIDEO_DIP_DATA_B		0x61174
>> +#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
>> +
>> +#define VLV_TVIDEO_DIP_CTL(pipe) \
>> +	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
>> +#define VLV_TVIDEO_DIP_DATA(pipe) \
>> +	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
>> +#define VLV_TVIDEO_DIP_GCP(pipe) \
>> +	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
>> +
>>   #define _TRANS_HTOTAL_B          0xe1000
>>   #define _TRANS_HBLANK_B          0xe1004
>>   #define _TRANS_HSYNC_B           0xe1008
>> @@ -3672,6 +3687,7 @@
>>   #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
>>
>>   /* or SDVOB */
>> +#define VLV_HDMIB 0x61140
>>   #define HDMIB   0xe1140
>>   #define  PORT_ENABLE    (1<<  31)
>>   #define  TRANSCODER(pipe)       ((pipe)<<  30)
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index cae3e5f..3f4a2d2 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -177,6 +177,37 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
>>
>>   	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>>   }
>> +
>> +static void vlv_write_infoframe(struct drm_encoder *encoder,
>> +				     struct dip_infoframe *frame)
>> +{
>> +	uint32_t *data = (uint32_t *)frame;
>> +	struct drm_device *dev = encoder->dev;
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +	struct drm_crtc *crtc = encoder->crtc;
>> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>> +	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
>> +	unsigned i, len = DIP_HEADER_SIZE + frame->len;
>> +	u32 flags, val = I915_READ(reg);
>> +
>> +	intel_wait_for_vblank(dev, intel_crtc->pipe);
>> +
>> +	flags = intel_infoframe_index(frame);
>> +
>> +	val&= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
>> +
>> +	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>> +
>> +	for (i = 0; i<  len; i += 4) {
>> +		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
>> +		data++;
>> +	}
>> +
>> +	flags |= intel_infoframe_flags(frame);
>> +
>> +	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
>> +}
>> +
>>   static void intel_set_infoframe(struct drm_encoder *encoder,
>>   				struct dip_infoframe *frame)
>>   {
>> @@ -522,10 +553,12 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
>>   	intel_encoder->crtc_mask = (1<<  0) | (1<<  1) | (1<<  2);
>>
>>   	/* Set up the DDC bus. */
>> +	/* For VLV SDVOB == HDMIB */
>>   	if (sdvox_reg == SDVOB) {
>>   		intel_encoder->clone_mask = (1<<  INTEL_HDMIB_CLONE_BIT);
>>   		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
>>   		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
>> +	/* For VLV SDVOC == HDMIC */
> I'm a bit confused about these two comments here. Afaict the code already
> works that way, not just on vlv. Can we just drop this hunk?
Yes we should drop this. Just couple of informational comments which I 
missed to remove.

Regards
Shobhit

Re: [PATCH 04/25] drm/i915: Add basic support for parsing of VBT OEM Custom Block

[Rodrigo Vivi]

I was also waiting for the patch that really does some parse as well,
but I think this patch will be useful for one case that I'm currently
working on...

anyway:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Thu, Mar 22, 2012 at 2:00 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> On Thu, 22 Mar 2012 09:11:37 -0700
> Ben Widawsky <ben@bwidawsk.net> wrote:
>
>> On Thu, 22 Mar 2012 08:45:32 -0700
>> Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>>
>> > On Wed, 21 Mar 2012 18:30:11 -0700
>> > Ben Widawsky <ben@bwidawsk.net> wrote:
>> >
>> > > On Wed, 21 Mar 2012 12:48:25 -0700
>> > > Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>> > >
>> > > > From: Rohit Jain <rohit.jain@intel.com>
>> > > >
>> > > > Added support for parsing the OEM Customizable Modes Block (#20)
>> > > > in the VBIOS table.
>> > > >
>> > > > Signed-off-by: Rohit Jain <rohit.jain@intel.com>
>> > > > Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
>> > > > Reviewed-by: Vijay A. Purushothaman
>> > > > <vijay.a.purushothaman@intel.com> Acked-by: Jesse Barnes
>> > > > <jesse.barnes@intel.com> Reviewed-by: Eugeni Dodonov
>> > > > <eugeni.dodonov@intel.com> Signed-off-by: Artem Bityutskiy
>> > > > <artem.bityutskiy@linux.intel.com> Signed-off-by: Jesse Barnes
>> > > > <jbarnes@virtuousgeek.org> ---
>> > >
>> > > I'll be honest, I haven't read through the whole series yet, but I
>> > > really don't see the point of this patch, at least in the next few
>> > > patches. Could we modify the commit to describe why we need this (or
>> > > drop it)?
>> >
>> > This one is unrelated to VLV, it's just extra VBT gravy.  Obviously it
>> > needs to stuff the mode info somewhere though...
>> >
>>
>> THe HW can behave one in two ways, you read the info out and that is
>> required to advance the internal state machine to get to the next info
>> you care about. Or, you read the info out and nobody knows or cares. I
>> truly don't know how this HW works yet, but I'd say if it's the former
>> it should be added as a comment to the code. If it's the latter, we
>> should drop the patch.
>
> As I said, it doesn't belong in the VLV patchset.  It has nothing to do
> with touch hw though; it's just a way for us to get any OEM custom
> modes out of the VBT.  For example on a given platform the VBT panel
> data may have a certain timing, but an additional timing may also be
> preferred, which might be specified in this block.
>
> So we should parse it, and add it to the appropriate connector's mode
> list.  This patch only does the parsing, but doesn't add it to the mode
> list, so isn't useful by itself.
>
> At any rate, I'll drop it from this series.
>
> --
> Jesse Barnes, Intel Open Source Technology Center
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net