* [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:32 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
` (27 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers
for 32 and 64 bit POWERPC. We are going to support 64bit versions too so
let's rename 32bit ones to avoid confusion.
This is a mechanical patch so it does not fix obvious mistake with these
registers in POWER7 yet, this will be fixed later.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 40 +++++++++---------
target-ppc/translate_init.c | 98 ++++++++++++++++++++++-----------------------
2 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 406a406..04dc856 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1566,24 +1566,24 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_BOOKE_DCDBTRH (0x39D)
#define SPR_BOOKE_ICDBTRL (0x39E)
#define SPR_BOOKE_ICDBTRH (0x39F)
-#define SPR_UMMCR2 (0x3A0)
-#define SPR_UPMC5 (0x3A1)
-#define SPR_UPMC6 (0x3A2)
+#define SPR_74XX_UMMCR2 (0x3A0)
+#define SPR_7XX_UPMC5 (0x3A1)
+#define SPR_7XX_UPMC6 (0x3A2)
#define SPR_UBAMR (0x3A7)
-#define SPR_UMMCR0 (0x3A8)
-#define SPR_UPMC1 (0x3A9)
-#define SPR_UPMC2 (0x3AA)
-#define SPR_USIAR (0x3AB)
-#define SPR_UMMCR1 (0x3AC)
-#define SPR_UPMC3 (0x3AD)
-#define SPR_UPMC4 (0x3AE)
+#define SPR_7XX_UMMCR0 (0x3A8)
+#define SPR_7XX_UPMC1 (0x3A9)
+#define SPR_7XX_UPMC2 (0x3AA)
+#define SPR_7XX_USIAR (0x3AB)
+#define SPR_7XX_UMMCR1 (0x3AC)
+#define SPR_7XX_UPMC3 (0x3AD)
+#define SPR_7XX_UPMC4 (0x3AE)
#define SPR_USDA (0x3AF)
#define SPR_40x_ZPR (0x3B0)
#define SPR_BOOKE_MAS7 (0x3B0)
-#define SPR_MMCR2 (0x3B0)
-#define SPR_PMC5 (0x3B1)
+#define SPR_74XX_MMCR2 (0x3B0)
+#define SPR_7XX_PMC5 (0x3B1)
#define SPR_40x_PID (0x3B1)
-#define SPR_PMC6 (0x3B2)
+#define SPR_7XX_PMC6 (0x3B2)
#define SPR_440_MMUCR (0x3B2)
#define SPR_4xx_CCR0 (0x3B3)
#define SPR_BOOKE_EPLC (0x3B3)
@@ -1593,19 +1593,19 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_405_DVC1 (0x3B6)
#define SPR_405_DVC2 (0x3B7)
#define SPR_BAMR (0x3B7)
-#define SPR_MMCR0 (0x3B8)
-#define SPR_PMC1 (0x3B9)
+#define SPR_7XX_MMCR0 (0x3B8)
+#define SPR_7XX_PMC1 (0x3B9)
#define SPR_40x_SGR (0x3B9)
-#define SPR_PMC2 (0x3BA)
+#define SPR_7XX_PMC2 (0x3BA)
#define SPR_40x_DCWR (0x3BA)
-#define SPR_SIAR (0x3BB)
+#define SPR_7XX_SIAR (0x3BB)
#define SPR_405_SLER (0x3BB)
-#define SPR_MMCR1 (0x3BC)
+#define SPR_7XX_MMCR1 (0x3BC)
#define SPR_405_SU0R (0x3BC)
#define SPR_401_SKR (0x3BC)
-#define SPR_PMC3 (0x3BD)
+#define SPR_7XX_PMC3 (0x3BD)
#define SPR_405_DBCR1 (0x3BD)
-#define SPR_PMC4 (0x3BE)
+#define SPR_7XX_PMC4 (0x3BE)
#define SPR_SDA (0x3BF)
#define SPR_403_VTBL (0x3CC)
#define SPR_403_VTBU (0x3CD)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d764bbd..fa137af 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -953,72 +953,72 @@ static void gen_spr_7xx (CPUPPCState *env)
0x00000000);
/* Performance monitors */
/* XXX : not implemented */
- spr_register(env, SPR_MMCR0, "MMCR0",
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC1, "PMC1",
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC2, "PMC2",
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC3, "PMC3",
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC4, "PMC4",
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_SIAR, "SIAR",
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR0, "UMMCR0",
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR1, "UMMCR1",
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC1, "UPMC1",
+ spr_register(env, SPR_7XX_UPMC1, "UPMC1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC2, "UPMC2",
+ spr_register(env, SPR_7XX_UPMC2, "UPMC2",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC3, "UPMC3",
+ spr_register(env, SPR_7XX_UPMC3, "UPMC3",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC4, "UPMC4",
+ spr_register(env, SPR_7XX_UPMC4, "UPMC4",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_USIAR, "USIAR",
+ spr_register(env, SPR_7XX_USIAR, "USIAR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -1119,22 +1119,22 @@ static void gen_spr_604 (CPUPPCState *env)
KVM_REG_PPC_DABR, 0x00000000);
/* Performance counters */
/* XXX : not implemented */
- spr_register(env, SPR_MMCR0, "MMCR0",
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC1, "PMC1",
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC2, "PMC2",
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_SIAR, "SIAR",
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
@@ -1354,12 +1354,12 @@ static void gen_spr_74xx (CPUPPCState *env)
&spr_read_generic, &spr_write_pir,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR2, "MMCR2",
+ spr_register(env, SPR_74XX_MMCR2, "MMCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UMMCR2, "UMMCR2",
+ spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -5436,17 +5436,17 @@ static void init_proc_604E (CPUPPCState *env)
gen_spr_ne_601(env);
gen_spr_604(env);
/* XXX : not implemented */
- spr_register(env, SPR_MMCR1, "MMCR1",
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC3, "PMC3",
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC4, "PMC4",
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -6475,22 +6475,22 @@ static void init_proc_7440 (CPUPPCState *env)
0x00000000);
/* PMC */
/* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -6608,22 +6608,22 @@ static void init_proc_7450 (CPUPPCState *env)
0x00000000);
/* PMC */
/* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -6710,22 +6710,22 @@ static void init_proc_7445 (CPUPPCState *env)
0x00000000);
/* PMC */
/* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -6848,22 +6848,22 @@ static void init_proc_7455 (CPUPPCState *env)
0x00000000);
/* PMC */
/* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -7010,22 +7010,22 @@ static void init_proc_7457 (CPUPPCState *env)
0x00000000);
/* PMC */
/* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -7147,22 +7147,22 @@ static void init_proc_e600 (CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC5, "PMC5",
+ spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC5, "UPMC5",
+ spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_PMC6, "PMC6",
+ spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_UPMC6, "UPMC6",
+ spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
@@ -7783,11 +7783,11 @@ static void init_proc_POWER7 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_MMCRA, 0x00000000);
- spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
+ spr_register_kvm(env, SPR_7XX_PMC5, "SPR_7XX_PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC5, 0x00000000);
- spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
+ spr_register_kvm(env, SPR_7XX_PMC6, "SPR_7XX_PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC6, 0x00000000);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
@ 2014-06-03 16:32 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:32 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers
> for 32 and 64 bit POWERPC. We are going to support 64bit versions too so
> let's rename 32bit ones to avoid confusion.
>
> This is a mechanical patch so it does not fix obvious mistake with these
> registers in POWER7 yet, this will be fixed later.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 15:40 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2014-06-03 16:25 ` [Qemu-devel] " Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 03/29] target-ppc: Refactor PPC970 Alexey Kardashevskiy
` (26 subsequent siblings)
28 siblings, 2 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
The differences between classes were:
1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
2. check_pow() callback, HID0 format is the same so should be the same
0x01C00000 which means "deep nap", "doze" and "nap" bits set;
3. LPCR - 970 does not have it but 970MP had one (by mistake).
This fixes wrong differences and makes one 970 class.
This fixes wrong registration of LPCR which is not present on 970.
This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to
970 class as we do not emulate hypervisor in QEMU anyway.
This does not remove check_pow_970FX now as it is still used by POWER5+
class, this will be addressed later.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu-models.c | 14 +--
target-ppc/translate_init.c | 222 ++++----------------------------------------
2 files changed, 23 insertions(+), 213 deletions(-)
diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
index 9a66c03..97a81d8 100644
--- a/target-ppc/cpu-models.c
+++ b/target-ppc/cpu-models.c
@@ -1142,19 +1142,19 @@
"POWER8 v1.0")
POWERPC_DEF("970", CPU_POWERPC_970, 970,
"PowerPC 970")
- POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
+ POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
"PowerPC 970FX v1.0 (G5)")
- POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
+ POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970,
"PowerPC 970FX v2.0 (G5)")
- POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
+ POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970,
"PowerPC 970FX v2.1 (G5)")
- POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
+ POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970,
"PowerPC 970FX v3.0 (G5)")
- POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
+ POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970,
"PowerPC 970FX v3.1 (G5)")
- POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
+ POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970,
"PowerPC 970MP v1.0")
- POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
+ POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
"PowerPC 970MP v1.1")
#if defined(TODO)
POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index fa137af..2f40d0d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7268,8 +7268,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
static int check_pow_970 (CPUPPCState *env)
{
- if (env->spr[SPR_HID0] & 0x00600000)
+ if (env->spr[SPR_HID0] & 0x01C00000) {
return 1;
+ }
return 0;
}
@@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_hior, &spr_write_hior,
0x00000000);
+
+ spr_register(env, SPR_CTRL, "SPR_CTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
+ env->slb_nr = 64;
#endif
init_excp_970(env);
env->dcache_line_size = 128;
@@ -7334,7 +7348,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_SHV) |
(1ull << MSR_VR) |
(1ull << MSR_POW) |
(1ull << MSR_EE) |
@@ -7371,209 +7384,6 @@ static int check_pow_970FX (CPUPPCState *env)
return 0;
}
-static void init_proc_970FX (CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x60000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
- /* Memory management */
- /* XXX: not correct */
- gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x00000000);
- spr_register(env, SPR_CTRL, "SPR_CTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 64;
-#endif
- init_excp_970(env);
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
- /* Allocate hardware IRQ controller */
- ppc970_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
-}
-
-POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 970FX (aka G5)";
- pcc->init_proc = init_proc_970FX;
- pcc->check_pow = check_pow_970FX;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI);
- pcc->mmu_model = POWERPC_MMU_64B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_970;
- pcc->bus_model = PPC_FLAGS_INPUT_970;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x10000;
-}
-
-static int check_pow_970MP (CPUPPCState *env)
-{
- if (env->spr[SPR_HID0] & 0x01C00000)
- return 1;
-
- return 0;
-}
-
-static void init_proc_970MP (CPUPPCState *env)
-{
- gen_spr_ne_601(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x60000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
- /* XXX : not implemented */
- /* Memory management */
- /* XXX: not correct */
- gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x00000000);
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif
- init_excp_970(env);
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
- /* Allocate hardware IRQ controller */
- ppc970_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
-}
-
-POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 970 MP";
- pcc->init_proc = init_proc_970MP;
- pcc->check_pow = check_pow_970MP;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
- PPC_64B | PPC_ALTIVEC |
- PPC_SEGMENT_64B | PPC_SLBI;
- pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_SHV) |
- (1ull << MSR_VR) |
- (1ull << MSR_POW) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_PMM) |
- (1ull << MSR_RI);
- pcc->mmu_model = POWERPC_MMU_64B;
-#if defined(CONFIG_SOFTMMU)
- pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
-#endif
- pcc->excp_model = POWERPC_EXCP_970;
- pcc->bus_model = PPC_FLAGS_INPUT_970;
- pcc->bfd_mach = bfd_mach_ppc64;
- pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
- POWERPC_FLAG_BUS_CLK;
- pcc->l1_dcache_size = 0x8000;
- pcc->l1_icache_size = 0x10000;
-}
-
static void init_proc_power5plus(CPUPPCState *env)
{
gen_spr_ne_601(env);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
@ 2014-06-03 15:40 ` Greg Kurz
2014-06-03 16:11 ` Alexander Graf
2014-06-03 16:25 ` [Qemu-devel] " Tom Musta
1 sibling, 1 reply; 74+ messages in thread
From: Greg Kurz @ 2014-06-03 15:40 UTC (permalink / raw)
To: Alexey Kardashevskiy; +Cc: Tom Musta, qemu-ppc, qemu-devel
On Tue, 3 Jun 2014 19:27:37 +1000
Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
> The differences between classes were:
> 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
> 2. check_pow() callback, HID0 format is the same so should be the same
> 0x01C00000 which means "deep nap", "doze" and "nap" bits set;
> 3. LPCR - 970 does not have it but 970MP had one (by mistake).
>
> This fixes wrong differences and makes one 970 class.
>
> This fixes wrong registration of LPCR which is not present on 970.
>
> This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to
> 970 class as we do not emulate hypervisor in QEMU anyway.
>
> This does not remove check_pow_970FX now as it is still used by POWER5+
> class, this will be addressed later.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu-models.c | 14 +--
> target-ppc/translate_init.c | 222 ++++----------------------------------------
> 2 files changed, 23 insertions(+), 213 deletions(-)
>
> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
> index 9a66c03..97a81d8 100644
> --- a/target-ppc/cpu-models.c
> +++ b/target-ppc/cpu-models.c
> @@ -1142,19 +1142,19 @@
> "POWER8 v1.0")
> POWERPC_DEF("970", CPU_POWERPC_970, 970,
> "PowerPC 970")
> - POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
> + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
> "PowerPC 970FX v1.0 (G5)")
> - POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
> + POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970,
> "PowerPC 970FX v2.0 (G5)")
> - POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
> + POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970,
> "PowerPC 970FX v2.1 (G5)")
> - POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
> + POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970,
> "PowerPC 970FX v3.0 (G5)")
> - POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
> + POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970,
> "PowerPC 970FX v3.1 (G5)")
> - POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
> + POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970,
> "PowerPC 970MP v1.0")
> - POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
> + POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
> "PowerPC 970MP v1.1")
> #if defined(TODO)
> POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index fa137af..2f40d0d 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7268,8 +7268,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
>
> static int check_pow_970 (CPUPPCState *env)
> {
> - if (env->spr[SPR_HID0] & 0x00600000)
> + if (env->spr[SPR_HID0] & 0x01C00000) {
What about killing magic numbers with something like:
#define HID0_DEEPNAP (1<<24)
#define HID0_DOZE (1<<23)
#define HID0_NAP (1<<22)
> return 1;
> + }
>
> return 0;
> }
> @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_hior, &spr_write_hior,
> 0x00000000);
> +
> + spr_register(env, SPR_CTRL, "SPR_CTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_UCTRL, "SPR_UCTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> #if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> + env->slb_nr = 64;
> #endif
> init_excp_970(env);
> env->dcache_line_size = 128;
> @@ -7334,7 +7348,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> PPC_64B | PPC_ALTIVEC |
> PPC_SEGMENT_64B | PPC_SLBI;
> pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> (1ull << MSR_VR) |
> (1ull << MSR_POW) |
> (1ull << MSR_EE) |
> @@ -7371,209 +7384,6 @@ static int check_pow_970FX (CPUPPCState *env)
> return 0;
> }
>
> -static void init_proc_970FX (CPUPPCState *env)
> -{
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> - /* Memory management */
> - /* XXX: not correct */
> - gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> - spr_register(env, SPR_CTRL, "SPR_CTRL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, &spr_write_generic,
> - 0x00000000);
> - spr_register(env, SPR_UCTRL, "SPR_UCTRL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, SPR_NOACCESS,
> - 0x00000000);
> - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 64;
> -#endif
> - init_excp_970(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> - /* Allocate hardware IRQ controller */
> - ppc970_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> -}
> -
> -POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "PowerPC 970FX (aka G5)";
> - pcc->init_proc = init_proc_970FX;
> - pcc->check_pow = check_pow_970FX;
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> - PPC_FLOAT_STFIWX |
> - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> - PPC_MEM_SYNC | PPC_MEM_EIEIO |
> - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_64B | PPC_ALTIVEC |
> - PPC_SEGMENT_64B | PPC_SLBI;
> - pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_VR) |
> - (1ull << MSR_POW) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_SE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR) |
> - (1ull << MSR_PMM) |
> - (1ull << MSR_RI);
> - pcc->mmu_model = POWERPC_MMU_64B;
> -#if defined(CONFIG_SOFTMMU)
> - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> -#endif
> - pcc->excp_model = POWERPC_EXCP_970;
> - pcc->bus_model = PPC_FLAGS_INPUT_970;
> - pcc->bfd_mach = bfd_mach_ppc64;
> - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> - POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> - POWERPC_FLAG_BUS_CLK;
> - pcc->l1_dcache_size = 0x8000;
> - pcc->l1_icache_size = 0x10000;
> -}
> -
> -static int check_pow_970MP (CPUPPCState *env)
> -{
> - if (env->spr[SPR_HID0] & 0x01C00000)
> - return 1;
> -
> - return 0;
> -}
> -
> -static void init_proc_970MP (CPUPPCState *env)
> -{
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> - /* XXX : not implemented */
> - /* Memory management */
> - /* XXX: not correct */
> - gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> - /* Logical partitionning */
> - spr_register_kvm(env, SPR_LPCR, "LPCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_LPCR, 0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> -#endif
> - init_excp_970(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> - /* Allocate hardware IRQ controller */
> - ppc970_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> -}
> -
> -POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> -
> - dc->desc = "PowerPC 970 MP";
> - pcc->init_proc = init_proc_970MP;
> - pcc->check_pow = check_pow_970MP;
> - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> - PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> - PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
> - PPC_FLOAT_STFIWX |
> - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
> - PPC_MEM_SYNC | PPC_MEM_EIEIO |
> - PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_64B | PPC_ALTIVEC |
> - PPC_SEGMENT_64B | PPC_SLBI;
> - pcc->msr_mask = (1ull << MSR_SF) |
> - (1ull << MSR_SHV) |
> - (1ull << MSR_VR) |
> - (1ull << MSR_POW) |
> - (1ull << MSR_EE) |
> - (1ull << MSR_PR) |
> - (1ull << MSR_FP) |
> - (1ull << MSR_ME) |
> - (1ull << MSR_FE0) |
> - (1ull << MSR_SE) |
> - (1ull << MSR_DE) |
> - (1ull << MSR_FE1) |
> - (1ull << MSR_IR) |
> - (1ull << MSR_DR) |
> - (1ull << MSR_PMM) |
> - (1ull << MSR_RI);
> - pcc->mmu_model = POWERPC_MMU_64B;
> -#if defined(CONFIG_SOFTMMU)
> - pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> -#endif
> - pcc->excp_model = POWERPC_EXCP_970;
> - pcc->bus_model = PPC_FLAGS_INPUT_970;
> - pcc->bfd_mach = bfd_mach_ppc64;
> - pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
> - POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
> - POWERPC_FLAG_BUS_CLK;
> - pcc->l1_dcache_size = 0x8000;
> - pcc->l1_icache_size = 0x10000;
> -}
> -
> static void init_proc_power5plus(CPUPPCState *env)
> {
> gen_spr_ne_601(env);
--
Gregory Kurz kurzgreg@fr.ibm.com
gkurz@linux.vnet.ibm.com
Software Engineer @ IBM/Meiosys http://www.ibm.com
Tel +33 (0)562 165 496
"Anarchy is about taking complete responsibility for yourself."
Alan Moore.
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class
2014-06-03 15:40 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
@ 2014-06-03 16:11 ` Alexander Graf
0 siblings, 0 replies; 74+ messages in thread
From: Alexander Graf @ 2014-06-03 16:11 UTC (permalink / raw)
To: Greg Kurz; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, qemu-devel
On 06/03/2014 05:40 PM, Greg Kurz wrote:
> On Tue, 3 Jun 2014 19:27:37 +1000
> Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
>
>> The differences between classes were:
>> 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
>> 2. check_pow() callback, HID0 format is the same so should be the same
>> 0x01C00000 which means "deep nap", "doze" and "nap" bits set;
>> 3. LPCR - 970 does not have it but 970MP had one (by mistake).
>>
>> This fixes wrong differences and makes one 970 class.
>>
>> This fixes wrong registration of LPCR which is not present on 970.
>>
>> This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to
>> 970 class as we do not emulate hypervisor in QEMU anyway.
>>
>> This does not remove check_pow_970FX now as it is still used by POWER5+
>> class, this will be addressed later.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/cpu-models.c | 14 +--
>> target-ppc/translate_init.c | 222 ++++----------------------------------------
>> 2 files changed, 23 insertions(+), 213 deletions(-)
>>
>> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c
>> index 9a66c03..97a81d8 100644
>> --- a/target-ppc/cpu-models.c
>> +++ b/target-ppc/cpu-models.c
>> @@ -1142,19 +1142,19 @@
>> "POWER8 v1.0")
>> POWERPC_DEF("970", CPU_POWERPC_970, 970,
>> "PowerPC 970")
>> - POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX,
>> + POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970,
>> "PowerPC 970FX v1.0 (G5)")
>> - POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX,
>> + POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970,
>> "PowerPC 970FX v2.0 (G5)")
>> - POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX,
>> + POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970,
>> "PowerPC 970FX v2.1 (G5)")
>> - POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX,
>> + POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970,
>> "PowerPC 970FX v3.0 (G5)")
>> - POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX,
>> + POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970,
>> "PowerPC 970FX v3.1 (G5)")
>> - POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP,
>> + POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970,
>> "PowerPC 970MP v1.0")
>> - POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP,
>> + POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970,
>> "PowerPC 970MP v1.1")
>> #if defined(TODO)
>> POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970,
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index fa137af..2f40d0d 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7268,8 +7268,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
>>
>> static int check_pow_970 (CPUPPCState *env)
>> {
>> - if (env->spr[SPR_HID0] & 0x00600000)
>> + if (env->spr[SPR_HID0] & 0x01C00000) {
> What about killing magic numbers with something like:
>
> #define HID0_DEEPNAP (1<<24)
> #define HID0_DOZE (1<<23)
> #define HID0_NAP (1<<22)
I like the idea. But IMHO this can easily come as a follow-up patch if
that's the only nit on this patch set :).
Alex
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
2014-06-03 15:40 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
@ 2014-06-03 16:25 ` Tom Musta
2014-06-04 4:48 ` Alexey Kardashevskiy
1 sibling, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:25 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_hior, &spr_write_hior,
> 0x00000000);
> +
> + spr_register(env, SPR_CTRL, "SPR_CTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_UCTRL, "SPR_UCTRL",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
This doesn't look quite right .... UCTRL is readable also from both user & supervisor mode.
And UCTRL should alias CTRL (a la your read_ureg helper).
But you've only re-arranged existing code ... not regressed anything. This should be fixed in
a follow up patch.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class
2014-06-03 16:25 ` [Qemu-devel] " Tom Musta
@ 2014-06-04 4:48 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 4:48 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:25 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> @@ -7303,8 +7304,21 @@ static void init_proc_970 (CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_hior, &spr_write_hior,
>> 0x00000000);
>> +
>> + spr_register(env, SPR_CTRL, "SPR_CTRL",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, &spr_write_generic,
>> + 0x00000000);
>> + spr_register(env, SPR_UCTRL, "SPR_UCTRL",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, SPR_NOACCESS,
>> + 0x00000000);
>
> This doesn't look quite right .... UCTRL is readable also from both user & supervisor mode.
>
> And UCTRL should alias CTRL (a la your read_ureg helper).
>
> But you've only re-arranged existing code ... not regressed anything. This should be fixed in
> a follow up patch.
I will add it as a separate patch in v5.
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 03/29] target-ppc: Refactor PPC970
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 01/29] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 02/29] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
` (25 subsequent siblings)
28 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This splits one init_proc_970() into a set of small helpers. Later
init_proc_970() will be generalized and will call different set of helpers
depending on the current CPU class.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 97 +++++++++++++++++++++++++++------------------
1 file changed, 58 insertions(+), 39 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 2f40d0d..496241e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7275,48 +7275,70 @@ static int check_pow_970 (CPUPPCState *env)
return 0;
}
+static void gen_spr_970_hid(CPUPPCState *env)
+{
+ /* Hardware implementation registers */
+ /* XXX : not implemented */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_clear,
+ 0x60000000);
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_970_HID5, "HID5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ POWERPC970_HID5_INIT);
+}
+
+static void gen_spr_970_hior(CPUPPCState *env)
+{
+ spr_register(env, SPR_HIOR, "SPR_HIOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_hior, &spr_write_hior,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_common(CPUPPCState *env)
+{
+ spr_register(env, SPR_CTRL, "SPR_CTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_altivec(CPUPPCState *env)
+{
+ if (!(env->insns_flags & PPC_ALTIVEC)) {
+ return;
+ }
+
+ spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ /* Can't find information on what this should be on reset. This
+ * value is the one used by 74xx processors. */
+ vscr_init(env, 0x00010000);
+}
+
static void init_proc_970 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
- /* Time base */
gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x60000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
- /* Memory management */
- /* XXX: not correct */
+ gen_spr_book3s_altivec(env);
+ gen_spr_970_hid(env);
+ gen_spr_970_hior(env);
gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x00000000);
-
- spr_register(env, SPR_CTRL, "SPR_CTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ gen_spr_book3s_common(env);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 64;
#endif
@@ -7325,9 +7347,6 @@ static void init_proc_970 (CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
ppc970_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
}
POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (2 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 03/29] target-ppc: Refactor PPC970 Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:32 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
` (24 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This stops using 7xx common SPRs init function and adds separate set
of helpers for 970.
This does not copy ICTC SPR as neither 970 manual nor PowerISA mention it.
This defines 970/book3s PMU SPRs constants as they differs from the ones
used for 7XX.
This creates 2 helpers for PMU SPRs, one for hypv privileged SPRs and one
for user privileged SPRs as "hypv" versions can be shared across the family
while "user" versions will behave different starting POWER8 (which will be
addressed later).
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 20 +++++++++
target-ppc/translate_init.c | 99 ++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 04dc856..781e4fa 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1470,15 +1470,21 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERF3 (0x303)
#define SPR_RCPU_MI_RBA3 (0x303)
#define SPR_MPC_MI_EPN (0x303)
+#define SPR_POWER_UPMC1 (0x303)
#define SPR_PERF4 (0x304)
+#define SPR_POWER_UPMC2 (0x304)
#define SPR_PERF5 (0x305)
#define SPR_MPC_MI_TWC (0x305)
+#define SPR_POWER_UPMC3 (0x305)
#define SPR_PERF6 (0x306)
#define SPR_MPC_MI_RPN (0x306)
+#define SPR_POWER_UPMC4 (0x306)
#define SPR_PERF7 (0x307)
+#define SPR_POWER_UPMC5 (0x307)
#define SPR_PERF8 (0x308)
#define SPR_RCPU_L2U_RBA0 (0x308)
#define SPR_MPC_MD_CTR (0x308)
+#define SPR_POWER_UPMC6 (0x308)
#define SPR_PERF9 (0x309)
#define SPR_RCPU_L2U_RBA1 (0x309)
#define SPR_MPC_MD_CASID (0x309)
@@ -1488,29 +1494,43 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERFB (0x30B)
#define SPR_RCPU_L2U_RBA3 (0x30B)
#define SPR_MPC_MD_EPN (0x30B)
+#define SPR_POWER_UMMCR0 (0X30B)
#define SPR_PERFC (0x30C)
#define SPR_MPC_MD_TWB (0x30C)
+#define SPR_POWER_USIAR (0X30C)
#define SPR_PERFD (0x30D)
#define SPR_MPC_MD_TWC (0x30D)
+#define SPR_POWER_USDAR (0X30D)
#define SPR_PERFE (0x30E)
#define SPR_MPC_MD_RPN (0x30E)
+#define SPR_POWER_UMMCR1 (0X30E)
#define SPR_PERFF (0x30F)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_UPERF3 (0x313)
+#define SPR_POWER_PMC1 (0X313)
#define SPR_UPERF4 (0x314)
+#define SPR_POWER_PMC2 (0X314)
#define SPR_UPERF5 (0x315)
+#define SPR_POWER_PMC3 (0X315)
#define SPR_UPERF6 (0x316)
+#define SPR_POWER_PMC4 (0X316)
#define SPR_UPERF7 (0x317)
+#define SPR_POWER_PMC5 (0X317)
#define SPR_UPERF8 (0x318)
+#define SPR_POWER_PMC6 (0X318)
#define SPR_UPERF9 (0x319)
#define SPR_UPERFA (0x31A)
#define SPR_UPERFB (0x31B)
+#define SPR_POWER_MMCR0 (0X31B)
#define SPR_UPERFC (0x31C)
+#define SPR_POWER_SIAR (0X31C)
#define SPR_UPERFD (0x31D)
+#define SPR_POWER_SDAR (0X31D)
#define SPR_UPERFE (0x31E)
+#define SPR_POWER_MMCR1 (0X31E)
#define SPR_UPERFF (0x31F)
#define SPR_RCPU_MI_RA0 (0x320)
#define SPR_MPC_MI_DBCAM (0x320)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 496241e..1192a8f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7329,16 +7329,113 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
vscr_init(env, 0x00010000);
}
+static void gen_spr_book3s_dbg(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+}
+
+static void gen_spr_970_dbg(CPUPPCState *env)
+{
+ /* Breakpoints */
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC1, "UPMC1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC2, "UPMC2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC3, "UPMC3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC4, "UPMC4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_USIAR, "USIAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
+static void gen_spr_power5p_ear(CPUPPCState *env)
+{
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void init_proc_970 (CPUPPCState *env)
{
gen_spr_ne_601(env);
- gen_spr_7xx(env);
gen_tbl(env);
gen_spr_book3s_altivec(env);
+ gen_spr_book3s_pmu_hypv(env);
+ gen_spr_book3s_pmu_user(env);
+ gen_spr_book3s_dbg(env);
+
gen_spr_970_hid(env);
gen_spr_970_hior(env);
gen_low_BATs(env);
gen_spr_book3s_common(env);
+
+ gen_spr_power5p_ear(env);
+
+ gen_spr_970_dbg(env);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 64;
#endif
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
@ 2014-06-03 16:32 ` Tom Musta
2014-06-04 5:09 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:32 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> +static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> +{
> + spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UPMC1, "UPMC1",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UPMC2, "UPMC2",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UPMC3, "UPMC3",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UPMC4, "UPMC4",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_USIAR, "USIAR",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +}
The Uxxxx regs are writeable from supervisor state, aren't they? (similar comment as UCTRL).
There is also this complicating factor in ISA 2.07 (P8) whereby the PMU Uxxxx SPRs are
readable/writeable based on the state of MMCR0[PMCC] (ick!).
I think either of these can be handled in follow up patches. I am also not sure that I see a
compelling reason to model the MMCR0[PMCC] accessibility unless we actually start modeling the
PMU (hard).
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970
2014-06-03 16:32 ` Tom Musta
@ 2014-06-04 5:09 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 5:09 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:32 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> +static void gen_spr_book3s_pmu_user(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC1, "UPMC1",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC2, "UPMC2",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC3, "UPMC3",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_UPMC4, "UPMC4",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_POWER_USIAR, "USIAR",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> +}
>
> The Uxxxx regs are writeable from supervisor state, aren't they? (similar comment as UCTRL).
Yes, they are. Will fix it.
However I did not understand the "similar comment as UCTRL" comment. UCTRL
is not writable at all.
> There is also this complicating factor in ISA 2.07 (P8) whereby the PMU Uxxxx SPRs are
> readable/writeable based on the state of MMCR0[PMCC] (ick!).
I'll enable writes to Uxxxx for supermode in v5 of this patch.
> I think either of these can be handled in follow up patches. I am also not sure that I see a
> compelling reason to model the MMCR0[PMCC] accessibility unless we actually start modeling the
> PMU (hard).
>
> Reviewed-by: Tom Musta <tommusta@gmail.com>
>
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (3 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 04/29] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:35 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
` (23 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish
the transition and fix MMCRA and define a hypv version of it.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 3 ++-
target-ppc/translate_init.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 781e4fa..21eec1b 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1466,7 +1466,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
-#define SPR_MMCRA (0x302)
+#define SPR_POWER_UMMCRA (0x302)
#define SPR_PERF3 (0x303)
#define SPR_RCPU_MI_RBA3 (0x303)
#define SPR_MPC_MI_EPN (0x303)
@@ -1509,6 +1509,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
#define SPR_UPERF2 (0x312)
+#define SPR_POWER_MMCRA (0X312)
#define SPR_UPERF3 (0x313)
#define SPR_POWER_PMC1 (0X313)
#define SPR_UPERF4 (0x314)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1192a8f..f7fe549 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7705,7 +7705,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DSCR, 0x00000000);
- spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+ spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_MMCRA, 0x00000000);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
@ 2014-06-03 16:35 ` Tom Musta
2014-06-04 1:36 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:35 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish
> the transition and fix MMCRA and define a hypv version of it.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
I'm still not a fan of "SPR_POWER_*" since these are now in the ISA (the "_POWER_" seems redundant).
Aside from that ...
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers
2014-06-03 16:35 ` Tom Musta
@ 2014-06-04 1:36 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 1:36 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:35 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish
>> the transition and fix MMCRA and define a hypv version of it.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> I'm still not a fan of "SPR_POWER_*" since these are now in the ISA (the "_POWER_" seems redundant).
And I am still a fan of having specific name in a macro if there is chance
that SPR with the same name can have different numbers on different
platforms :)
Alex, judge please :)
> Aside from that ...
>
> Reviewed-by: Tom Musta <tommusta@gmail.com>
Yup, thanks, putting it into my git tree to have them all in v5!
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (4 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 05/29] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:36 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
` (22 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA
CPUs. Since we are building common infrastructure for SPRs intialization
to share it between 970 and POWER5+/7/..., let's add missing SPRs to
the 970 family. Later rework of CPU class initialization will use those
for all PowerISA CPUs.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index f7fe549..e4c9a4c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7356,6 +7356,10 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_POWER_MMCRA, "MMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
spr_register(env, SPR_POWER_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -7372,10 +7376,22 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_POWER_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_POWER_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
spr_register(env, SPR_POWER_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
+ spr_register(env, SPR_POWER_SDAR, "SDAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
}
static void gen_spr_book3s_pmu_user(CPUPPCState *env)
@@ -7388,6 +7404,10 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
+ spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
spr_register(env, SPR_POWER_UPMC1, "UPMC1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -7404,10 +7424,22 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
+ spr_register(env, SPR_POWER_UPMC5, "UPMC5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_POWER_UPMC6, "UPMC6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
spr_register(env, SPR_POWER_USIAR, "USIAR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
+ spr_register(env, SPR_POWER_USDAR, "USDAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
}
static void gen_spr_power5p_ear(CPUPPCState *env)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
@ 2014-06-03 16:36 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:36 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA
> CPUs. Since we are building common infrastructure for SPRs intialization
> to share it between 970 and POWER5+/7/..., let's add missing SPRs to
> the 970 family. Later rework of CPU class initialization will use those
> for all PowerISA CPUs.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f7fe549..e4c9a4c 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7356,6 +7356,10 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> + spr_register(env, SPR_POWER_MMCRA, "MMCRA",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> spr_register(env, SPR_POWER_PMC1, "PMC1",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> @@ -7372,10 +7376,22 @@ static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> + spr_register(env, SPR_POWER_PMC5, "PMC5",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_POWER_PMC6, "PMC6",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> spr_register(env, SPR_POWER_SIAR, "SIAR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_SDAR, "SDAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> }
>
> static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> @@ -7388,6 +7404,10 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> spr_register(env, SPR_POWER_UPMC1, "UPMC1",
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> @@ -7404,10 +7424,22 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_UPMC5, "UPMC5",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_POWER_UPMC6, "UPMC6",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> spr_register(env, SPR_POWER_USIAR, "USIAR",
> &spr_read_ureg, SPR_NOACCESS,
> &spr_read_ureg, SPR_NOACCESS,
> 0x00000000);
> + spr_register(env, SPR_POWER_USDAR, "USDAR",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> }
>
> static void gen_spr_power5p_ear(CPUPPCState *env)
>
Similar comments on the Uxxxx SPRs as I made for patch 4. Still OK with addressing this later.
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (5 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 06/29] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:37 ` Tom Musta
2014-06-03 16:42 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
` (21 subsequent siblings)
28 siblings, 2 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
Compared to PowerISA-compliant CPUs, 970 family has most of them plus
PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
Since we are changing SPRs for Book3s/970 families, let's add them too.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 4 ++++
target-ppc/translate_init.c | 26 ++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 21eec1b..fc09087 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1488,9 +1488,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_PERF9 (0x309)
#define SPR_RCPU_L2U_RBA1 (0x309)
#define SPR_MPC_MD_CASID (0x309)
+#define SPR_970_UPMC7 (0X309)
#define SPR_PERFA (0x30A)
#define SPR_RCPU_L2U_RBA2 (0x30A)
#define SPR_MPC_MD_AP (0x30A)
+#define SPR_970_UPMC8 (0X30A)
#define SPR_PERFB (0x30B)
#define SPR_RCPU_L2U_RBA3 (0x30B)
#define SPR_MPC_MD_EPN (0x30B)
@@ -1523,7 +1525,9 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPERF8 (0x318)
#define SPR_POWER_PMC6 (0X318)
#define SPR_UPERF9 (0x319)
+#define SPR_970_PMC7 (0X319)
#define SPR_UPERFA (0x31A)
+#define SPR_970_PMC8 (0X31A)
#define SPR_UPERFB (0x31B)
#define SPR_POWER_MMCR0 (0X31B)
#define SPR_UPERFC (0x31C)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e4c9a4c..0fcf918 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7442,6 +7442,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_970_pmu_hypv(CPUPPCState *env)
+{
+ spr_register(env, SPR_970_PMC7, "PMC7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_970_PMC8, "PMC8",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_970_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_970_UPMC7, "UPMC7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_970_UPMC8, "UPMC8",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
static void gen_spr_power5p_ear(CPUPPCState *env)
{
/* External access control */
@@ -7464,6 +7488,8 @@ static void init_proc_970 (CPUPPCState *env)
gen_spr_970_hior(env);
gen_low_BATs(env);
gen_spr_book3s_common(env);
+ gen_spr_970_pmu_hypv(env);
+ gen_spr_970_pmu_user(env);
gen_spr_power5p_ear(env);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
@ 2014-06-03 16:37 ` Tom Musta
2014-06-03 16:42 ` Tom Musta
1 sibling, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:37 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>
> Since we are changing SPRs for Book3s/970 families, let's add them too.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 4 ++++
> target-ppc/translate_init.c | 26 ++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 21eec1b..fc09087 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1488,9 +1488,11 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_PERF9 (0x309)
> #define SPR_RCPU_L2U_RBA1 (0x309)
> #define SPR_MPC_MD_CASID (0x309)
> +#define SPR_970_UPMC7 (0X309)
> #define SPR_PERFA (0x30A)
> #define SPR_RCPU_L2U_RBA2 (0x30A)
> #define SPR_MPC_MD_AP (0x30A)
> +#define SPR_970_UPMC8 (0X30A)
> #define SPR_PERFB (0x30B)
> #define SPR_RCPU_L2U_RBA3 (0x30B)
> #define SPR_MPC_MD_EPN (0x30B)
> @@ -1523,7 +1525,9 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_UPERF8 (0x318)
> #define SPR_POWER_PMC6 (0X318)
> #define SPR_UPERF9 (0x319)
> +#define SPR_970_PMC7 (0X319)
> #define SPR_UPERFA (0x31A)
> +#define SPR_970_PMC8 (0X31A)
> #define SPR_UPERFB (0x31B)
> #define SPR_POWER_MMCR0 (0X31B)
> #define SPR_UPERFC (0x31C)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e4c9a4c..0fcf918 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7442,6 +7442,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void gen_spr_970_pmu_hypv(CPUPPCState *env)
> +{
> + spr_register(env, SPR_970_PMC7, "PMC7",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_970_PMC8, "PMC8",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +}
> +
> +static void gen_spr_970_pmu_user(CPUPPCState *env)
> +{
> + spr_register(env, SPR_970_UPMC7, "UPMC7",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_970_UPMC8, "UPMC8",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +}
> +
> static void gen_spr_power5p_ear(CPUPPCState *env)
> {
> /* External access control */
> @@ -7464,6 +7488,8 @@ static void init_proc_970 (CPUPPCState *env)
> gen_spr_970_hior(env);
> gen_low_BATs(env);
> gen_spr_book3s_common(env);
> + gen_spr_970_pmu_hypv(env);
> + gen_spr_970_pmu_user(env);
>
> gen_spr_power5p_ear(env);
>
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
2014-06-03 16:37 ` Tom Musta
@ 2014-06-03 16:42 ` Tom Musta
2014-06-04 5:25 ` Alexey Kardashevskiy
1 sibling, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:42 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>
> Since we are changing SPRs for Book3s/970 families, let's add them too.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 4 ++++
> target-ppc/translate_init.c | 26 ++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
[ ... ]
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e4c9a4c..0fcf918 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7442,6 +7442,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void gen_spr_970_pmu_hypv(CPUPPCState *env)
> +{
> + spr_register(env, SPR_970_PMC7, "PMC7",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_970_PMC8, "PMC8",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +}
> +
Sorry ... forgot my comments: Shouldn't this be named "gen_spr_970_pm_sup" ? These are supervisor SPRs, not hypervisor SPRs.
> +static void gen_spr_970_pmu_user(CPUPPCState *env)
> +{
> + spr_register(env, SPR_970_UPMC7, "UPMC7",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + spr_register(env, SPR_970_UPMC8, "UPMC8",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +}
> +
Are UPMC7/8 writeable from supervisor state? (the 970 UM is not crystal clear here).
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class
2014-06-03 16:42 ` Tom Musta
@ 2014-06-04 5:25 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 5:25 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:42 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> Compared to PowerISA-compliant CPUs, 970 family has most of them plus
>> PMC7/8 which are only present on 970 but not on POWER5 and later CPUs.
>>
>> Since we are changing SPRs for Book3s/970 families, let's add them too.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/cpu.h | 4 ++++
>> target-ppc/translate_init.c | 26 ++++++++++++++++++++++++++
>> 2 files changed, 30 insertions(+)
>>
>
> [ ... ]
>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index e4c9a4c..0fcf918 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7442,6 +7442,30 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
>> 0x00000000);
>> }
>>
>> +static void gen_spr_970_pmu_hypv(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_970_PMC7, "PMC7",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + 0x00000000);
>> + spr_register(env, SPR_970_PMC8, "PMC8",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + 0x00000000);
>> +}
>> +
>
> Sorry ... forgot my comments: Shouldn't this be named "gen_spr_970_pm_sup" ? These are supervisor SPRs, not hypervisor SPRs.
Will be fixed in v5.
>> +static void gen_spr_970_pmu_user(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_970_UPMC7, "UPMC7",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> + spr_register(env, SPR_970_UPMC8, "UPMC8",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, SPR_NOACCESS,
>> + 0x00000000);
>> +}
>> +
>
> Are UPMC7/8 writeable from supervisor state? (the 970 UM is not crystal clear here).
No idea either. I suggest enabling writes there and get back to the topic
when/if we decide to model them correctly. Ok?
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (6 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 07/29] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:43 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
` (20 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
Previously LPCR was registered for the 970 class which was wrong as
it does not have LPCR. Instead, HID4 is used which this patch registers.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 11 +++++++++++
2 files changed, 12 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fc09087..97f01ca 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1683,6 +1683,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_750_TDCL (0x3F4)
#define SPR_40x_IAC1 (0x3F4)
#define SPR_MMUCSR0 (0x3F4)
+#define SPR_970_HID4 (0x3F4)
#define SPR_DABR (0x3F5)
#define DABR_MASK (~(target_ulong)0x7)
#define SPR_Exxx_BUCSR (0x3F5)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 0fcf918..de920a0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7301,6 +7301,16 @@ static void gen_spr_970_hior(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_970_lpar(CPUPPCState *env)
+{
+ /* Logical partitionning */
+ /* PPC970: HID4 is effectively the LPCR */
+ spr_register(env, SPR_970_HID4, "HID4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void gen_spr_book3s_common(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
@@ -7490,6 +7500,7 @@ static void init_proc_970 (CPUPPCState *env)
gen_spr_book3s_common(env);
gen_spr_970_pmu_hypv(env);
gen_spr_970_pmu_user(env);
+ gen_spr_970_lpar(env);
gen_spr_power5p_ear(env);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
@ 2014-06-03 16:43 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:43 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> Previously LPCR was registered for the 970 class which was wrong as
> it does not have LPCR. Instead, HID4 is used which this patch registers.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 11 +++++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index fc09087..97f01ca 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1683,6 +1683,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_750_TDCL (0x3F4)
> #define SPR_40x_IAC1 (0x3F4)
> #define SPR_MMUCSR0 (0x3F4)
> +#define SPR_970_HID4 (0x3F4)
> #define SPR_DABR (0x3F5)
> #define DABR_MASK (~(target_ulong)0x7)
> #define SPR_Exxx_BUCSR (0x3F5)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 0fcf918..de920a0 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7301,6 +7301,16 @@ static void gen_spr_970_hior(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void gen_spr_970_lpar(CPUPPCState *env)
> +{
> + /* Logical partitionning */
> + /* PPC970: HID4 is effectively the LPCR */
> + spr_register(env, SPR_970_HID4, "HID4",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +}
> +
> static void gen_spr_book3s_common(CPUPPCState *env)
> {
> spr_register(env, SPR_CTRL, "SPR_CTRL",
> @@ -7490,6 +7500,7 @@ static void init_proc_970 (CPUPPCState *env)
> gen_spr_book3s_common(env);
> gen_spr_970_pmu_hypv(env);
> gen_spr_970_pmu_user(env);
> + gen_spr_970_lpar(env);
>
> gen_spr_power5p_ear(env);
>
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64()
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (7 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 08/29] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:45 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
` (19 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
At the moment every POWER CPU family has its own init_proc_POWERX function.
E500 already has common init function so we try to do the same thing.
This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+.
This introduces generalized init_proc_book3s_64() which accepts a CPU type
as a parameter.
This uses new init function for 970 and POWER5+ CPU classes.
970 and POWER5+ use the same CPU class initialization except 3 things:
1. logical partitioning is controlled by LPCR (POWER5+) and HID4 (970)
SPRs;
2. 970 does not have EAR (External Access Register) SPR and PowerISA 2.03
defines one so keep it only for POWER5+;
3. POWER5+ does not have ALTIVEC so insns_flags does not have PPC_ALTIVEC
flag set and gen_spr_book3s_altivec() won't init ALTIVEC for POWER5+.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 85 ++++++++++++++-------------------------------
1 file changed, 27 insertions(+), 58 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index de920a0..301f5ff 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7266,6 +7266,11 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
#define POWERPC970_HID5_INIT 0x00000000
#endif
+enum BOOK3S_CPU_TYPE {
+ BOOK3S_CPU_970,
+ BOOK3S_CPU_POWER5PLUS,
+};
+
static int check_pow_970 (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000) {
@@ -7485,7 +7490,16 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
0x00000000);
}
-static void init_proc_970 (CPUPPCState *env)
+static void gen_spr_power5p_lpar(CPUPPCState *env)
+{
+ /* Logical partitionning */
+ spr_register_kvm(env, SPR_LPCR, "LPCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_LPCR, 0x00000000);
+}
+
+static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
gen_tbl(env);
@@ -7500,9 +7514,13 @@ static void init_proc_970 (CPUPPCState *env)
gen_spr_book3s_common(env);
gen_spr_970_pmu_hypv(env);
gen_spr_970_pmu_user(env);
- gen_spr_970_lpar(env);
- gen_spr_power5p_ear(env);
+ if (version >= BOOK3S_CPU_POWER5PLUS) {
+ gen_spr_power5p_lpar(env);
+ gen_spr_power5p_ear(env);
+ } else {
+ gen_spr_970_lpar(env);
+ }
gen_spr_970_dbg(env);
#if !defined(CONFIG_USER_ONLY)
@@ -7515,6 +7533,11 @@ static void init_proc_970 (CPUPPCState *env)
ppc970_irq_init(env);
}
+static void init_proc_970(CPUPPCState *env)
+{
+ init_proc_book3s_64(env, BOOK3S_CPU_970);
+}
+
POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -7571,61 +7594,7 @@ static int check_pow_970FX (CPUPPCState *env)
static void init_proc_power5plus(CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_7xx(env);
- /* Time base */
- gen_tbl(env);
- /* Hardware implementation registers */
- /* XXX : not implemented */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_clear,
- 0x60000000);
- /* XXX : not implemented */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_970_HID5, "HID5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- POWERPC970_HID5_INIT);
- /* Memory management */
- /* XXX: not correct */
- gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_hior, &spr_write_hior,
- 0x00000000);
- spr_register(env, SPR_CTRL, "SPR_CTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 64;
-#endif
- init_excp_970(env);
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
- /* Allocate hardware IRQ controller */
- ppc970_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
+ init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
}
POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64()
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
@ 2014-06-03 16:45 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:45 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> At the moment every POWER CPU family has its own init_proc_POWERX function.
> E500 already has common init function so we try to do the same thing.
>
> This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+.
>
> This introduces generalized init_proc_book3s_64() which accepts a CPU type
> as a parameter.
>
> This uses new init function for 970 and POWER5+ CPU classes.
>
> 970 and POWER5+ use the same CPU class initialization except 3 things:
> 1. logical partitioning is controlled by LPCR (POWER5+) and HID4 (970)
> SPRs;
> 2. 970 does not have EAR (External Access Register) SPR and PowerISA 2.03
> defines one so keep it only for POWER5+;
> 3. POWER5+ does not have ALTIVEC so insns_flags does not have PPC_ALTIVEC
> flag set and gen_spr_book3s_altivec() won't init ALTIVEC for POWER5+.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 85 ++++++++++++++-------------------------------
> 1 file changed, 27 insertions(+), 58 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index de920a0..301f5ff 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7266,6 +7266,11 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
> #define POWERPC970_HID5_INIT 0x00000000
> #endif
>
> +enum BOOK3S_CPU_TYPE {
> + BOOK3S_CPU_970,
> + BOOK3S_CPU_POWER5PLUS,
> +};
> +
> static int check_pow_970 (CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & 0x01C00000) {
> @@ -7485,7 +7490,16 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
> 0x00000000);
> }
>
> -static void init_proc_970 (CPUPPCState *env)
> +static void gen_spr_power5p_lpar(CPUPPCState *env)
> +{
> + /* Logical partitionning */
> + spr_register_kvm(env, SPR_LPCR, "LPCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_LPCR, 0x00000000);
> +}
> +
> +static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> gen_tbl(env);
> @@ -7500,9 +7514,13 @@ static void init_proc_970 (CPUPPCState *env)
> gen_spr_book3s_common(env);
> gen_spr_970_pmu_hypv(env);
> gen_spr_970_pmu_user(env);
> - gen_spr_970_lpar(env);
>
> - gen_spr_power5p_ear(env);
> + if (version >= BOOK3S_CPU_POWER5PLUS) {
> + gen_spr_power5p_lpar(env);
> + gen_spr_power5p_ear(env);
> + } else {
> + gen_spr_970_lpar(env);
> + }
>
> gen_spr_970_dbg(env);
> #if !defined(CONFIG_USER_ONLY)
> @@ -7515,6 +7533,11 @@ static void init_proc_970 (CPUPPCState *env)
> ppc970_irq_init(env);
> }
>
> +static void init_proc_970(CPUPPCState *env)
> +{
> + init_proc_book3s_64(env, BOOK3S_CPU_970);
> +}
> +
> POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -7571,61 +7594,7 @@ static int check_pow_970FX (CPUPPCState *env)
>
> static void init_proc_power5plus(CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> - /* Time base */
> - gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> - /* Memory management */
> - /* XXX: not correct */
> - gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> - spr_register(env, SPR_CTRL, "SPR_CTRL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, &spr_write_generic,
> - 0x00000000);
> - spr_register(env, SPR_UCTRL, "SPR_UCTRL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, SPR_NOACCESS,
> - 0x00000000);
> - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* Logical partitionning */
> - spr_register_kvm(env, SPR_LPCR, "LPCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_LPCR, 0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 64;
> -#endif
> - init_excp_970(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> - /* Allocate hardware IRQ controller */
> - ppc970_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> + init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
> }
>
> POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (8 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 09/29] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:45 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
` (18 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
After merging 970s into one class, check_pow_970() is used for all of them.
Since POWER5+ is no different in the matter of supported power modes,
let's use the same check_pow() callback for POWER5+ too,
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 301f5ff..b372a64 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7584,14 +7584,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x10000;
}
-static int check_pow_970FX (CPUPPCState *env)
-{
- if (env->spr[SPR_HID0] & 0x00600000)
- return 1;
-
- return 0;
-}
-
static void init_proc_power5plus(CPUPPCState *env)
{
init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
@@ -7605,7 +7597,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER5";
dc->desc = "POWER5+";
pcc->init_proc = init_proc_power5plus;
- pcc->check_pow = check_pow_970FX;
+ pcc->check_pow = check_pow_970;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
@ 2014-06-03 16:45 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:45 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> After merging 970s into one class, check_pow_970() is used for all of them.
> Since POWER5+ is no different in the matter of supported power modes,
> let's use the same check_pow() callback for POWER5+ too,
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 10 +---------
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 301f5ff..b372a64 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7584,14 +7584,6 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> pcc->l1_icache_size = 0x10000;
> }
>
> -static int check_pow_970FX (CPUPPCState *env)
> -{
> - if (env->spr[SPR_HID0] & 0x00600000)
> - return 1;
> -
> - return 0;
> -}
> -
> static void init_proc_power5plus(CPUPPCState *env)
> {
> init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
> @@ -7605,7 +7597,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> dc->fw_name = "PowerPC,POWER5";
> dc->desc = "POWER5+";
> pcc->init_proc = init_proc_power5plus;
> - pcc->check_pow = check_pow_970FX;
> + pcc->check_pow = check_pow_970;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (9 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 10/29] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:47 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
` (17 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This enabled PMU SPRs migration by hooking hypv privileged versions with
"KVM one reg" IDs.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 104 ++++++++++++++++++++++----------------------
1 file changed, 52 insertions(+), 52 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b372a64..3445b17 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7363,50 +7363,50 @@ static void gen_spr_970_dbg(CPUPPCState *env)
static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
{
- spr_register(env, SPR_POWER_MMCR0, "MMCR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_MMCRA, "MMCRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_PMC1, "PMC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_PMC2, "PMC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_PMC5, "PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_PMC6, "PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_POWER_SIAR, "SIAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_POWER_SDAR, "SDAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR0, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR1, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRA, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC1, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC3, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC4, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC5, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC6, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ KVM_REG_PPC_SIAR, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ KVM_REG_PPC_SDAR, 0x00000000);
}
static void gen_spr_book3s_pmu_user(CPUPPCState *env)
@@ -7459,14 +7459,14 @@ static void gen_spr_book3s_pmu_user(CPUPPCState *env)
static void gen_spr_970_pmu_hypv(CPUPPCState *env)
{
- spr_register(env, SPR_970_PMC7, "PMC7",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_970_PMC8, "PMC8",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_970_PMC7, "PMC7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC7, 0x00000000);
+ spr_register_kvm(env, SPR_970_PMC8, "PMC8",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC8, 0x00000000);
}
static void gen_spr_970_pmu_user(CPUPPCState *env)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
@ 2014-06-03 16:47 ` Tom Musta
2014-06-04 1:46 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:47 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This enabled PMU SPRs migration by hooking hypv privileged versions with
> "KVM one reg" IDs.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 104 ++++++++++++++++++++++----------------------
> 1 file changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index b372a64..3445b17 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7363,50 +7363,50 @@ static void gen_spr_970_dbg(CPUPPCState *env)
>
> static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
Supervisor?
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration
2014-06-03 16:47 ` Tom Musta
@ 2014-06-04 1:46 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 1:46 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:47 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This enabled PMU SPRs migration by hooking hypv privileged versions with
>> "KVM one reg" IDs.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/translate_init.c | 104 ++++++++++++++++++++++----------------------
>> 1 file changed, 52 insertions(+), 52 deletions(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index b372a64..3445b17 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7363,50 +7363,50 @@ static void gen_spr_970_dbg(CPUPPCState *env)
>>
>> static void gen_spr_book3s_pmu_hypv(CPUPPCState *env)
>
> Supervisor?
Yes. Changing this in the whole series. No "hypv" in QEMU today.
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (10 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 11/29] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:48 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
` (16 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be
called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 40 ++++++++++++++++++++++++++--------------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3445b17..aa88727 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7499,6 +7499,30 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
KVM_REG_PPC_LPCR, 0x00000000);
}
+static void gen_spr_book3s_ids(CPUPPCState *env)
+{
+ /* Processor identification */
+ spr_register(env, SPR_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+}
+
+static void gen_spr_book3s_purr(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
+ spr_register_kvm(env, SPR_PURR, "PURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ KVM_REG_PPC_PURR, 0x00000000);
+ spr_register_kvm(env, SPR_SPURR, "SPURR",
+ &spr_read_purr, SPR_NOACCESS,
+ &spr_read_purr, SPR_NOACCESS,
+ KVM_REG_PPC_SPURR, 0x00000000);
+#endif
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7712,21 +7736,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
gen_spr_7xx(env);
/* Time base */
gen_tbl(env);
- /* Processor identification */
- spr_register(env, SPR_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
#if !defined(CONFIG_USER_ONLY)
- /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
- spr_register_kvm(env, SPR_PURR, "PURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_PURR, 0x00000000);
- spr_register_kvm(env, SPR_SPURR, "SPURR",
- &spr_read_purr, SPR_NOACCESS,
- &spr_read_purr, SPR_NOACCESS,
- KVM_REG_PPC_SPURR, 0x00000000);
spr_register(env, SPR_CFAR, "SPR_CFAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
@@ -7748,6 +7758,8 @@ static void init_proc_POWER7 (CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC6, 0x00000000);
#endif /* !CONFIG_USER_ONLY */
+ gen_spr_book3s_ids(env);
+ gen_spr_book3s_purr(env);
gen_spr_amr(env);
/* XXX : not implemented */
spr_register(env, SPR_CTRL, "SPR_CTRLT",
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
@ 2014-06-03 16:48 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:48 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be
> called from generalized init_proc_book3s_64().
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 40 ++++++++++++++++++++++++++--------------
> 1 file changed, 26 insertions(+), 14 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 3445b17..aa88727 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7499,6 +7499,30 @@ static void gen_spr_power5p_lpar(CPUPPCState *env)
> KVM_REG_PPC_LPCR, 0x00000000);
> }
>
> +static void gen_spr_book3s_ids(CPUPPCState *env)
> +{
> + /* Processor identification */
> + spr_register(env, SPR_PIR, "PIR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_pir,
> + 0x00000000);
> +}
> +
> +static void gen_spr_book3s_purr(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> + spr_register_kvm(env, SPR_PURR, "PURR",
> + &spr_read_purr, SPR_NOACCESS,
> + &spr_read_purr, SPR_NOACCESS,
> + KVM_REG_PPC_PURR, 0x00000000);
> + spr_register_kvm(env, SPR_SPURR, "SPURR",
> + &spr_read_purr, SPR_NOACCESS,
> + &spr_read_purr, SPR_NOACCESS,
> + KVM_REG_PPC_SPURR, 0x00000000);
> +#endif
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -7712,21 +7736,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
> gen_spr_7xx(env);
> /* Time base */
> gen_tbl(env);
> - /* Processor identification */
> - spr_register(env, SPR_PIR, "PIR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_pir,
> - 0x00000000);
> #if !defined(CONFIG_USER_ONLY)
> - /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
> - spr_register_kvm(env, SPR_PURR, "PURR",
> - &spr_read_purr, SPR_NOACCESS,
> - &spr_read_purr, SPR_NOACCESS,
> - KVM_REG_PPC_PURR, 0x00000000);
> - spr_register_kvm(env, SPR_SPURR, "SPURR",
> - &spr_read_purr, SPR_NOACCESS,
> - &spr_read_purr, SPR_NOACCESS,
> - KVM_REG_PPC_SPURR, 0x00000000);
> spr_register(env, SPR_CFAR, "SPR_CFAR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_cfar, &spr_write_cfar,
> @@ -7748,6 +7758,8 @@ static void init_proc_POWER7 (CPUPPCState *env)
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_PMC6, 0x00000000);
> #endif /* !CONFIG_USER_ONLY */
> + gen_spr_book3s_ids(env);
> + gen_spr_book3s_purr(env);
> gen_spr_amr(env);
> /* XXX : not implemented */
> spr_register(env, SPR_CTRL, "SPR_CTRLT",
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (11 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 12/29] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:48 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
` (15 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This moves TAR SPR to a helper. Later this helper will be
called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index aa88727..d6557f2 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7523,6 +7523,14 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
#endif
}
+static void gen_spr_power8_tce_address_control(CPUPPCState *env)
+{
+ spr_register(env, SPR_TAR, "TAR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7933,11 +7941,7 @@ static void init_proc_POWER8(CPUPPCState *env)
/* inherit P7 */
init_proc_POWER7(env);
- /* P8 supports the TAR */
- spr_register(env, SPR_TAR, "TAR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ gen_spr_power8_tce_address_control(env);
}
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
@ 2014-06-03 16:48 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:48 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This moves TAR SPR to a helper. Later this helper will be
> called from generalized init_proc_book3s_64().
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index aa88727..d6557f2 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7523,6 +7523,14 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> +{
> + spr_register(env, SPR_TAR, "TAR",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +}
> +
> static void init_proc_book3s_64(CPUPPCState *env, int version)
> {
> gen_spr_ne_601(env);
> @@ -7933,11 +7941,7 @@ static void init_proc_POWER8(CPUPPCState *env)
> /* inherit P7 */
> init_proc_POWER7(env);
>
> - /* P8 supports the TAR */
> - spr_register(env, SPR_TAR, "TAR",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> + gen_spr_power8_tce_address_control(env);
> }
>
> POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (12 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 13/29] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:54 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
` (14 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
will be called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 70 ++++++++++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 30 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d6557f2..576056c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7523,6 +7523,42 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
#endif
}
+static void gen_spr_power6_dbg(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_CFAR, "SPR_CFAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_cfar, &spr_write_cfar,
+ 0x00000000);
+#endif
+}
+
+static void gen_spr_power5p_common(CPUPPCState *env)
+{
+ spr_register(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
+static void gen_spr_power6_common(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSCR, 0x00000000);
+#endif
+ /*
+ * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
+ * POWERPC_EXCP_INVAL_SPR.
+ */
+ spr_register(env, SPR_PCR, "PCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ 0x00000000);
+}
+
static void gen_spr_power8_tce_address_control(CPUPPCState *env)
{
spr_register(env, SPR_TAR, "TAR",
@@ -7745,14 +7781,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
/* Time base */
gen_tbl(env);
#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_CFAR, "SPR_CFAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_cfar, &spr_write_cfar,
- 0x00000000);
- spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSCR, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -7768,24 +7796,15 @@ static void init_proc_POWER7 (CPUPPCState *env)
#endif /* !CONFIG_USER_ONLY */
gen_spr_book3s_ids(env);
gen_spr_book3s_purr(env);
+ gen_spr_book3s_common(env);
+ gen_spr_power5p_common(env);
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
gen_spr_amr(env);
- /* XXX : not implemented */
- spr_register(env, SPR_CTRL, "SPR_CTRLT",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
- 0x80800000);
- spr_register(env, SPR_UCTRL, "SPR_CTRLF",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x80800000);
spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_PPR, "PPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Logical partitionning */
spr_register_kvm(env, SPR_LPCR, "LPCR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7803,15 +7822,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
/* Can't find information on what this should be on reset. This
* value is the one used by 74xx processors. */
vscr_init(env, 0x00010000);
-
- /*
- * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
- * POWERPC_EXCP_INVAL_SPR.
- */
- spr_register(env, SPR_PCR, "PCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- 0x00000000);
}
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
@ 2014-06-03 16:54 ` Tom Musta
2014-06-04 2:02 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:54 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
> will be called from generalized init_proc_book3s_64().
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 70 ++++++++++++++++++++++++++-------------------
> 1 file changed, 40 insertions(+), 30 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index d6557f2..576056c 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7523,6 +7523,42 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power6_dbg(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register(env, SPR_CFAR, "SPR_CFAR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_cfar, &spr_write_cfar,
> + 0x00000000);
> +#endif
> +}
> +
> +static void gen_spr_power5p_common(CPUPPCState *env)
> +{
> + spr_register(env, SPR_PPR, "PPR",
> + &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> +}
> +
> +static void gen_spr_power6_common(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_DSCR, 0x00000000);
> +#endif
> + /*
> + * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
> + * POWERPC_EXCP_INVAL_SPR.
> + */
> + spr_register(env, SPR_PCR, "PCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + 0x00000000);
> +}
> +
> static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> {
> spr_register(env, SPR_TAR, "TAR",
> @@ -7745,14 +7781,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
> /* Time base */
> gen_tbl(env);
> #if !defined(CONFIG_USER_ONLY)
> - spr_register(env, SPR_CFAR, "SPR_CFAR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_cfar, &spr_write_cfar,
> - 0x00000000);
> - spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_DSCR, 0x00000000);
> spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> @@ -7768,24 +7796,15 @@ static void init_proc_POWER7 (CPUPPCState *env)
> #endif /* !CONFIG_USER_ONLY */
> gen_spr_book3s_ids(env);
> gen_spr_book3s_purr(env);
> + gen_spr_book3s_common(env);
> + gen_spr_power5p_common(env);
> + gen_spr_power6_common(env);
> + gen_spr_power6_dbg(env);
> gen_spr_amr(env);
> - /* XXX : not implemented */
> - spr_register(env, SPR_CTRL, "SPR_CTRLT",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, &spr_write_generic,
> - 0x80800000);
> - spr_register(env, SPR_UCTRL, "SPR_CTRLF",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, SPR_NOACCESS,
> - 0x80800000);
Note that by switching to using gen_spr_book3s_common, there is an implicit change in the register names
("SPR_CTRLT" --> "SPR_CTRL" and "SPR_CTLRF -> "SPR_UCTRL"). I am not completely sure of the impact of
this (change in what is seen in the monitor?) .... But I like your new names better than the old ones :)
> - /*
> - * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
> - * POWERPC_EXCP_INVAL_SPR.
> - */
> - spr_register(env, SPR_PCR, "PCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, SPR_NOACCESS,
> - 0x00000000);
> }
>
We probably have quite a few hypervisor SPRs that should also be handled this way ????
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers
2014-06-03 16:54 ` Tom Musta
@ 2014-06-04 2:02 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 2:02 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:54 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
>> will be called from generalized init_proc_book3s_64().
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/translate_init.c | 70 ++++++++++++++++++++++++++-------------------
>> 1 file changed, 40 insertions(+), 30 deletions(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index d6557f2..576056c 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7523,6 +7523,42 @@ static void gen_spr_book3s_purr(CPUPPCState *env)
>> #endif
>> }
>>
>> +static void gen_spr_power6_dbg(CPUPPCState *env)
>> +{
>> +#if !defined(CONFIG_USER_ONLY)
>> + spr_register(env, SPR_CFAR, "SPR_CFAR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_cfar, &spr_write_cfar,
>> + 0x00000000);
>> +#endif
>> +}
>> +
>> +static void gen_spr_power5p_common(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_PPR, "PPR",
>> + &spr_read_generic, &spr_write_generic,
>> + &spr_read_generic, &spr_write_generic,
>> + 0x00000000);
>> +}
>> +
>> +static void gen_spr_power6_common(CPUPPCState *env)
>> +{
>> +#if !defined(CONFIG_USER_ONLY)
>> + spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + KVM_REG_PPC_DSCR, 0x00000000);
>> +#endif
>> + /*
>> + * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
>> + * POWERPC_EXCP_INVAL_SPR.
>> + */
>> + spr_register(env, SPR_PCR, "PCR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + 0x00000000);
>> +}
>> +
>> static void gen_spr_power8_tce_address_control(CPUPPCState *env)
>> {
>> spr_register(env, SPR_TAR, "TAR",
>> @@ -7745,14 +7781,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
>> /* Time base */
>> gen_tbl(env);
>> #if !defined(CONFIG_USER_ONLY)
>> - spr_register(env, SPR_CFAR, "SPR_CFAR",
>> - SPR_NOACCESS, SPR_NOACCESS,
>> - &spr_read_cfar, &spr_write_cfar,
>> - 0x00000000);
>> - spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
>> - SPR_NOACCESS, SPR_NOACCESS,
>> - &spr_read_generic, &spr_write_generic,
>> - KVM_REG_PPC_DSCR, 0x00000000);
>> spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_generic, &spr_write_generic,
>> @@ -7768,24 +7796,15 @@ static void init_proc_POWER7 (CPUPPCState *env)
>> #endif /* !CONFIG_USER_ONLY */
>> gen_spr_book3s_ids(env);
>> gen_spr_book3s_purr(env);
>> + gen_spr_book3s_common(env);
>> + gen_spr_power5p_common(env);
>> + gen_spr_power6_common(env);
>> + gen_spr_power6_dbg(env);
>> gen_spr_amr(env);
>> - /* XXX : not implemented */
>> - spr_register(env, SPR_CTRL, "SPR_CTRLT",
>> - SPR_NOACCESS, SPR_NOACCESS,
>> - SPR_NOACCESS, &spr_write_generic,
>> - 0x80800000);
>> - spr_register(env, SPR_UCTRL, "SPR_CTRLF",
>> - SPR_NOACCESS, SPR_NOACCESS,
>> - &spr_read_generic, SPR_NOACCESS,
>> - 0x80800000);
>
>
> Note that by switching to using gen_spr_book3s_common, there is an implicit change in the register names
> ("SPR_CTRLT" --> "SPR_CTRL" and "SPR_CTLRF -> "SPR_UCTRL"). I am not completely sure of the impact of
> this (change in what is seen in the monitor?) ....
Well, "info registers"/ppc_cpu_dump_state() does not use these names, so I
am not sure if the change will be visible at all.
> But I like your new names better than the old ones :)
Good :)
>
>
>
>> - /*
>> - * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
>> - * POWERPC_EXCP_INVAL_SPR.
>> - */
>> - spr_register(env, SPR_PCR, "PCR",
>> - SPR_NOACCESS, SPR_NOACCESS,
>> - SPR_NOACCESS, SPR_NOACCESS,
>> - 0x00000000);
>> }
>>
>
> We probably have quite a few hypervisor SPRs that should also be handled this way ????
This is definitely not today.
> Reviewed-by: Tom Musta <tommusta@gmail.com>
got it, thanks!
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (13 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 14/29] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:54 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() " Alexey Kardashevskiy
` (13 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This replaces VRSAVE registration and vscr_init() call with
gen_spr_book3s_altivec() which is generic and does the same thing if
insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set).
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Here is the function for the reference:
static void gen_spr_book3s_altivec(CPUPPCState *env)
{
if (!(env->insns_flags & PPC_ALTIVEC)) {
return;
}
spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Can't find information on what this should be on reset. This
* value is the one used by 74xx processors. */
vscr_init(env, 0x00010000);
}
---
target-ppc/translate_init.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 576056c..40c8ce1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7778,6 +7778,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_spr_7xx(env);
+ gen_spr_book3s_altivec(env);
/* Time base */
gen_tbl(env);
#if !defined(CONFIG_USER_ONLY)
@@ -7801,10 +7802,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_amr(env);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Logical partitionning */
spr_register_kvm(env, SPR_LPCR, "LPCR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7819,9 +7816,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
/* Allocate hardware IRQ controller */
ppcPOWER7_irq_init(env);
- /* Can't find information on what this should be on reset. This
- * value is the one used by 74xx processors. */
- vscr_init(env, 0x00010000);
}
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
@ 2014-06-03 16:54 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:54 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This replaces VRSAVE registration and vscr_init() call with
> gen_spr_book3s_altivec() which is generic and does the same thing if
> insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set).
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
>
> Here is the function for the reference:
>
> static void gen_spr_book3s_altivec(CPUPPCState *env)
> {
> if (!(env->insns_flags & PPC_ALTIVEC)) {
> return;
> }
>
> spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> &spr_read_generic, &spr_write_generic,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
>
> /* Can't find information on what this should be on reset. This
> * value is the one used by 74xx processors. */
> vscr_init(env, 0x00010000);
> }
> ---
> target-ppc/translate_init.c | 8 +-------
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 576056c..40c8ce1 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7778,6 +7778,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
> {
> gen_spr_ne_601(env);
> gen_spr_7xx(env);
> + gen_spr_book3s_altivec(env);
> /* Time base */
> gen_tbl(env);
> #if !defined(CONFIG_USER_ONLY)
> @@ -7801,10 +7802,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
> gen_spr_power6_common(env);
> gen_spr_power6_dbg(env);
> gen_spr_amr(env);
> - spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
> - &spr_read_generic, &spr_write_generic,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> /* Logical partitionning */
> spr_register_kvm(env, SPR_LPCR, "LPCR",
> SPR_NOACCESS, SPR_NOACCESS,
> @@ -7819,9 +7816,6 @@ static void init_proc_POWER7 (CPUPPCState *env)
>
> /* Allocate hardware IRQ controller */
> ppcPOWER7_irq_init(env);
> - /* Can't find information on what this should be on reset. This
> - * value is the one used by 74xx processors. */
> - vscr_init(env, 0x00010000);
> }
>
> POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (14 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 15/29] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:54 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
` (12 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This makes use of generic gen_spr_book3s_lpar() which registers LPCR SPR.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 40c8ce1..bc68adb 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7800,13 +7800,9 @@ static void init_proc_POWER7 (CPUPPCState *env)
gen_spr_book3s_common(env);
gen_spr_power5p_common(env);
gen_spr_power6_common(env);
+ gen_spr_book3s_lpar(env);
gen_spr_power6_dbg(env);
gen_spr_amr(env);
- /* Logical partitionning */
- spr_register_kvm(env, SPR_LPCR, "LPCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_LPCR, 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() for POWER7/8
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() " Alexey Kardashevskiy
@ 2014-06-03 16:54 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:54 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This makes use of generic gen_spr_book3s_lpar() which registers LPCR SPR.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 40c8ce1..bc68adb 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7800,13 +7800,9 @@ static void init_proc_POWER7 (CPUPPCState *env)
> gen_spr_book3s_common(env);
> gen_spr_power5p_common(env);
> gen_spr_power6_common(env);
> + gen_spr_book3s_lpar(env);
> gen_spr_power6_dbg(env);
> gen_spr_amr(env);
> - /* Logical partitionning */
> - spr_register_kvm(env, SPR_LPCR, "LPCR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_LPCR, 0x00000000);
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (15 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 16/29] target-ppc: Make use of gen_spr_book3s_lpar() " Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:55 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
` (11 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This replaces gen_spr_7xx() call (which registers 32bit SPRs) with
gen_spr_book3s_pmu() call.
This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu()
already registers correct PMC5/6 SPRs.
This removes explicit MMCRA registration as gen_spr_book3s_pmu() does it
anyway.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bc68adb..b1288f4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7777,29 +7777,16 @@ static Property powerpc_servercpu_properties[] = {
static void init_proc_POWER7 (CPUPPCState *env)
{
gen_spr_ne_601(env);
- gen_spr_7xx(env);
gen_spr_book3s_altivec(env);
/* Time base */
gen_tbl(env);
-#if !defined(CONFIG_USER_ONLY)
- spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_MMCRA, 0x00000000);
- spr_register_kvm(env, SPR_7XX_PMC5, "SPR_7XX_PMC5",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC5, 0x00000000);
- spr_register_kvm(env, SPR_7XX_PMC6, "SPR_7XX_PMC6",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_PMC6, 0x00000000);
-#endif /* !CONFIG_USER_ONLY */
gen_spr_book3s_ids(env);
gen_spr_book3s_purr(env);
gen_spr_book3s_common(env);
gen_spr_power5p_common(env);
gen_spr_power6_common(env);
+ gen_spr_book3s_pmu_hypv(env);
+ gen_spr_book3s_pmu_user(env);
gen_spr_book3s_lpar(env);
gen_spr_power6_dbg(env);
gen_spr_amr(env);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
@ 2014-06-03 16:55 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:55 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This replaces gen_spr_7xx() call (which registers 32bit SPRs) with
> gen_spr_book3s_pmu() call.
>
> This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu()
> already registers correct PMC5/6 SPRs.
>
> This removes explicit MMCRA registration as gen_spr_book3s_pmu() does it
> anyway.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 17 ++---------------
> 1 file changed, 2 insertions(+), 15 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index bc68adb..b1288f4 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7777,29 +7777,16 @@ static Property powerpc_servercpu_properties[] = {
> static void init_proc_POWER7 (CPUPPCState *env)
> {
> gen_spr_ne_601(env);
> - gen_spr_7xx(env);
> gen_spr_book3s_altivec(env);
> /* Time base */
> gen_tbl(env);
> -#if !defined(CONFIG_USER_ONLY)
> - spr_register_kvm(env, SPR_POWER_MMCRA, "SPR_MMCRA",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_MMCRA, 0x00000000);
> - spr_register_kvm(env, SPR_7XX_PMC5, "SPR_7XX_PMC5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_PMC5, 0x00000000);
> - spr_register_kvm(env, SPR_7XX_PMC6, "SPR_7XX_PMC6",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_PMC6, 0x00000000);
> -#endif /* !CONFIG_USER_ONLY */
> gen_spr_book3s_ids(env);
> gen_spr_book3s_purr(env);
> gen_spr_book3s_common(env);
> gen_spr_power5p_common(env);
> gen_spr_power6_common(env);
> + gen_spr_book3s_pmu_hypv(env);
> + gen_spr_book3s_pmu_user(env);
> gen_spr_book3s_lpar(env);
> gen_spr_power6_dbg(env);
> gen_spr_amr(env);
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (16 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 17/29] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:57 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR Alexey Kardashevskiy
` (10 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This extends init_proc_book3s_64 to support POWER7 and POWER8.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v4:
* added g_assert_not_reached() to default path to catch errors earlier
---
target-ppc/translate_init.c | 100 +++++++++++++++++++++++++++-----------------
1 file changed, 61 insertions(+), 39 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b1288f4..17163e7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7269,6 +7269,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
enum BOOK3S_CPU_TYPE {
BOOK3S_CPU_970,
BOOK3S_CPU_POWER5PLUS,
+ BOOK3S_CPU_POWER6,
+ BOOK3S_CPU_POWER7,
+ BOOK3S_CPU_POWER8
};
static int check_pow_970 (CPUPPCState *env)
@@ -7575,30 +7578,74 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_book3s_pmu_hypv(env);
gen_spr_book3s_pmu_user(env);
gen_spr_book3s_dbg(env);
-
- gen_spr_970_hid(env);
- gen_spr_970_hior(env);
- gen_low_BATs(env);
gen_spr_book3s_common(env);
- gen_spr_970_pmu_hypv(env);
- gen_spr_970_pmu_user(env);
+ switch (version) {
+ case BOOK3S_CPU_970:
+ case BOOK3S_CPU_POWER5PLUS:
+ gen_spr_970_hid(env);
+ gen_spr_970_hior(env);
+ gen_low_BATs(env);
+ gen_spr_970_pmu_hypv(env);
+ gen_spr_970_pmu_user(env);
+ break;
+ case BOOK3S_CPU_POWER7:
+ case BOOK3S_CPU_POWER8:
+ gen_spr_book3s_ids(env);
+ gen_spr_amr(env);
+ gen_spr_book3s_purr(env);
+ break;
+ default:
+ g_assert_not_reached();
+ }
if (version >= BOOK3S_CPU_POWER5PLUS) {
+ gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
} else {
gen_spr_970_lpar(env);
}
-
- gen_spr_970_dbg(env);
+ if (version == BOOK3S_CPU_970) {
+ gen_spr_970_dbg(env);
+ }
+ if (version >= BOOK3S_CPU_POWER6) {
+ gen_spr_power6_common(env);
+ gen_spr_power6_dbg(env);
+ }
+ if (version >= BOOK3S_CPU_POWER8) {
+ gen_spr_power8_tce_address_control(env);
+ }
#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 64;
+ switch (version) {
+ case BOOK3S_CPU_970:
+ case BOOK3S_CPU_POWER5PLUS:
+ env->slb_nr = 64;
+ break;
+ case BOOK3S_CPU_POWER7:
+ case BOOK3S_CPU_POWER8:
+ default:
+ env->slb_nr = 32;
+ break;
+ }
#endif
- init_excp_970(env);
+ /* Allocate hardware IRQ controller */
+ switch (version) {
+ case BOOK3S_CPU_970:
+ case BOOK3S_CPU_POWER5PLUS:
+ init_excp_970(env);
+ ppc970_irq_init(env);
+ break;
+ case BOOK3S_CPU_POWER7:
+ case BOOK3S_CPU_POWER8:
+ init_excp_POWER7(env);
+ ppcPOWER7_irq_init(env);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
env->dcache_line_size = 128;
env->icache_line_size = 128;
- /* Allocate hardware IRQ controller */
- ppc970_irq_init(env);
}
static void init_proc_970(CPUPPCState *env)
@@ -7776,29 +7823,7 @@ static Property powerpc_servercpu_properties[] = {
static void init_proc_POWER7 (CPUPPCState *env)
{
- gen_spr_ne_601(env);
- gen_spr_book3s_altivec(env);
- /* Time base */
- gen_tbl(env);
- gen_spr_book3s_ids(env);
- gen_spr_book3s_purr(env);
- gen_spr_book3s_common(env);
- gen_spr_power5p_common(env);
- gen_spr_power6_common(env);
- gen_spr_book3s_pmu_hypv(env);
- gen_spr_book3s_pmu_user(env);
- gen_spr_book3s_lpar(env);
- gen_spr_power6_dbg(env);
- gen_spr_amr(env);
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif
- init_excp_POWER7(env);
- env->dcache_line_size = 128;
- env->icache_line_size = 128;
-
- /* Allocate hardware IRQ controller */
- ppcPOWER7_irq_init(env);
+ init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
}
POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
@@ -7925,10 +7950,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
static void init_proc_POWER8(CPUPPCState *env)
{
- /* inherit P7 */
- init_proc_POWER7(env);
-
- gen_spr_power8_tce_address_control(env);
+ init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
}
POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
@ 2014-06-03 16:57 ` Tom Musta
2014-06-04 2:09 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:57 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This extends init_proc_book3s_64 to support POWER7 and POWER8.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v4:
> * added g_assert_not_reached() to default path to catch errors earlier
> ---
> target-ppc/translate_init.c | 100 +++++++++++++++++++++++++++-----------------
> 1 file changed, 61 insertions(+), 39 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index b1288f4..17163e7 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7269,6 +7269,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
> enum BOOK3S_CPU_TYPE {
> BOOK3S_CPU_970,
> BOOK3S_CPU_POWER5PLUS,
> + BOOK3S_CPU_POWER6,
> + BOOK3S_CPU_POWER7,
> + BOOK3S_CPU_POWER8
> };
>
> static int check_pow_970 (CPUPPCState *env)
> @@ -7575,30 +7578,74 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_book3s_pmu_hypv(env);
> gen_spr_book3s_pmu_user(env);
> gen_spr_book3s_dbg(env);
> -
> - gen_spr_970_hid(env);
> - gen_spr_970_hior(env);
> - gen_low_BATs(env);
> gen_spr_book3s_common(env);
> - gen_spr_970_pmu_hypv(env);
> - gen_spr_970_pmu_user(env);
>
> + switch (version) {
> + case BOOK3S_CPU_970:
> + case BOOK3S_CPU_POWER5PLUS:
> + gen_spr_970_hid(env);
> + gen_spr_970_hior(env);
> + gen_low_BATs(env);
> + gen_spr_970_pmu_hypv(env);
> + gen_spr_970_pmu_user(env);
> + break;
It appears the 970/P5+ models now have both the old and the new PMU SPR numbers .... intentional?
> + case BOOK3S_CPU_POWER7:
> + case BOOK3S_CPU_POWER8:
> + gen_spr_book3s_ids(env);
> + gen_spr_amr(env);
> + gen_spr_book3s_purr(env);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> if (version >= BOOK3S_CPU_POWER5PLUS) {
> + gen_spr_power5p_common(env);
> gen_spr_power5p_lpar(env);
> gen_spr_power5p_ear(env);
> } else {
> gen_spr_970_lpar(env);
> }
> -
> - gen_spr_970_dbg(env);
> + if (version == BOOK3S_CPU_970) {
> + gen_spr_970_dbg(env);
> + }
> + if (version >= BOOK3S_CPU_POWER6) {
> + gen_spr_power6_common(env);
> + gen_spr_power6_dbg(env);
> + }
> + if (version >= BOOK3S_CPU_POWER8) {
> + gen_spr_power8_tce_address_control(env);
> + }
> #if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 64;
> + switch (version) {
> + case BOOK3S_CPU_970:
> + case BOOK3S_CPU_POWER5PLUS:
> + env->slb_nr = 64;
> + break;
> + case BOOK3S_CPU_POWER7:
> + case BOOK3S_CPU_POWER8:
> + default:
> + env->slb_nr = 32;
> + break;
> + }
> #endif
> - init_excp_970(env);
> + /* Allocate hardware IRQ controller */
> + switch (version) {
> + case BOOK3S_CPU_970:
> + case BOOK3S_CPU_POWER5PLUS:
> + init_excp_970(env);
> + ppc970_irq_init(env);
> + break;
> + case BOOK3S_CPU_POWER7:
> + case BOOK3S_CPU_POWER8:
> + init_excp_POWER7(env);
> + ppcPOWER7_irq_init(env);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> env->dcache_line_size = 128;
> env->icache_line_size = 128;
> - /* Allocate hardware IRQ controller */
> - ppc970_irq_init(env);
> }
>
> static void init_proc_970(CPUPPCState *env)
> @@ -7776,29 +7823,7 @@ static Property powerpc_servercpu_properties[] = {
>
> static void init_proc_POWER7 (CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_book3s_altivec(env);
> - /* Time base */
> - gen_tbl(env);
> - gen_spr_book3s_ids(env);
> - gen_spr_book3s_purr(env);
> - gen_spr_book3s_common(env);
> - gen_spr_power5p_common(env);
> - gen_spr_power6_common(env);
> - gen_spr_book3s_pmu_hypv(env);
> - gen_spr_book3s_pmu_user(env);
> - gen_spr_book3s_lpar(env);
> - gen_spr_power6_dbg(env);
> - gen_spr_amr(env);
> -#if !defined(CONFIG_USER_ONLY)
> - env->slb_nr = 32;
> -#endif
> - init_excp_POWER7(env);
> - env->dcache_line_size = 128;
> - env->icache_line_size = 128;
> -
> - /* Allocate hardware IRQ controller */
> - ppcPOWER7_irq_init(env);
> + init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
> }
>
> POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
> @@ -7925,10 +7950,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
>
> static void init_proc_POWER8(CPUPPCState *env)
> {
> - /* inherit P7 */
> - init_proc_POWER7(env);
> -
> - gen_spr_power8_tce_address_control(env);
> + init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
> }
>
> POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8
2014-06-03 16:57 ` Tom Musta
@ 2014-06-04 2:09 ` Alexey Kardashevskiy
2014-06-04 12:24 ` Tom Musta
0 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 2:09 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:57 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This extends init_proc_book3s_64 to support POWER7 and POWER8.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> Changes:
>> v4:
>> * added g_assert_not_reached() to default path to catch errors earlier
>> ---
>> target-ppc/translate_init.c | 100 +++++++++++++++++++++++++++-----------------
>> 1 file changed, 61 insertions(+), 39 deletions(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index b1288f4..17163e7 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7269,6 +7269,9 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
>> enum BOOK3S_CPU_TYPE {
>> BOOK3S_CPU_970,
>> BOOK3S_CPU_POWER5PLUS,
>> + BOOK3S_CPU_POWER6,
>> + BOOK3S_CPU_POWER7,
>> + BOOK3S_CPU_POWER8
>> };
>>
>> static int check_pow_970 (CPUPPCState *env)
>> @@ -7575,30 +7578,74 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> gen_spr_book3s_pmu_hypv(env);
>> gen_spr_book3s_pmu_user(env);
>> gen_spr_book3s_dbg(env);
>> -
>> - gen_spr_970_hid(env);
>> - gen_spr_970_hior(env);
>> - gen_low_BATs(env);
>> gen_spr_book3s_common(env);
>> - gen_spr_970_pmu_hypv(env);
>> - gen_spr_970_pmu_user(env);
>>
>> + switch (version) {
>> + case BOOK3S_CPU_970:
>> + case BOOK3S_CPU_POWER5PLUS:
>> + gen_spr_970_hid(env);
>> + gen_spr_970_hior(env);
>> + gen_low_BATs(env);
>> + gen_spr_970_pmu_hypv(env);
>> + gen_spr_970_pmu_user(env);
>> + break;
>
>
> It appears the 970/P5+ models now have both the old and the new PMU SPR numbers .... intentional?
How so?
gen_spr_book3s_pmu_xxx add PCM1..6, gen_spr_970_pmu_xxx add PMC7-8.
Since patch #4, 970/p5+ do not use old PMU SPRs.
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8
2014-06-04 2:09 ` Alexey Kardashevskiy
@ 2014-06-04 12:24 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-04 12:24 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 9:09 PM, Alexey Kardashevskiy wrote:
> How so?
>
> gen_spr_book3s_pmu_xxx add PCM1..6, gen_spr_970_pmu_xxx add PMC7-8.
>
> Since patch #4, 970/p5+ do not use old PMU SPRs.
>
Alexey: You are correct ... I misread the code.
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (17 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 18/29] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 16:59 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
` (9 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds TIR (Thread Identification Register) SPR first defined in
PowerISA 2.05.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v4:
* disabled reading it from user space
---
target-ppc/cpu.h | 1 +
target-ppc/translate_init.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 97f01ca..8f43b37 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_BOOKE_GIVOR8 (0x1BB)
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
+#define SPR_TIR (0x1BE)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 17163e7..c41d289 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7509,6 +7509,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
+
+ spr_register(env, SPR_TIR, "TIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
}
static void gen_spr_book3s_purr(CPUPPCState *env)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR Alexey Kardashevskiy
@ 2014-06-03 16:59 ` Tom Musta
2014-06-04 2:14 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 16:59 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TIR (Thread Identification Register) SPR first defined in
> PowerISA 2.05.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v4:
> * disabled reading it from user space
> ---
> target-ppc/cpu.h | 1 +
> target-ppc/translate_init.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 97f01ca..8f43b37 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_BOOKE_GIVOR8 (0x1BB)
> #define SPR_BOOKE_GIVOR13 (0x1BC)
> #define SPR_BOOKE_GIVOR14 (0x1BD)
> +#define SPR_TIR (0x1BE)
> #define SPR_BOOKE_SPEFSCR (0x200)
> #define SPR_Exxx_BBEAR (0x201)
> #define SPR_Exxx_BBTAR (0x202)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 17163e7..c41d289 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7509,6 +7509,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_pir,
> 0x00000000);
> +
> + spr_register(env, SPR_TIR, "TIR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> + 0x00000000);
> }
>
> static void gen_spr_book3s_purr(CPUPPCState *env)
>
It looks like TIR gets added to both P7 and P8. Intentional? (TIR was added in ISA 2.07 ... not sure if it existed in P7 implementations or not).
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR
2014-06-03 16:59 ` Tom Musta
@ 2014-06-04 2:14 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 2:14 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 02:59 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds TIR (Thread Identification Register) SPR first defined in
>> PowerISA 2.05.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> Changes:
>> v4:
>> * disabled reading it from user space
>> ---
>> target-ppc/cpu.h | 1 +
>> target-ppc/translate_init.c | 5 +++++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 97f01ca..8f43b37 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1374,6 +1374,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>> #define SPR_BOOKE_GIVOR8 (0x1BB)
>> #define SPR_BOOKE_GIVOR13 (0x1BC)
>> #define SPR_BOOKE_GIVOR14 (0x1BD)
>> +#define SPR_TIR (0x1BE)
>> #define SPR_BOOKE_SPEFSCR (0x200)
>> #define SPR_Exxx_BBEAR (0x201)
>> #define SPR_Exxx_BBTAR (0x202)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 17163e7..c41d289 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7509,6 +7509,11 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_generic, &spr_write_pir,
>> 0x00000000);
>> +
>> + spr_register(env, SPR_TIR, "TIR",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, SPR_NOACCESS,
>> + 0x00000000);
>> }
>>
>> static void gen_spr_book3s_purr(CPUPPCState *env)
>>
>
> It looks like TIR gets added to both P7 and P8. Intentional? (TIR was
> added in ISA 2.07 ... not sure if it existed in P7 implementations or
> not).
Oh. I see. It is defined on 2.06 but for embedded only, servers have it
from 2.07. Will fix it.
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (18 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 19/29] target-ppc: Add POWER7's TIR SPR Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
` (8 subsequent siblings)
28 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds an FSCR (Facility Status and Control Register) SPR. This defines
names for FSCR bits.
This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU).
This registers an interrupt vector for it at 0xF60 as PowerISA defines.
This adds a TCG helper_fscr_facility_check() helper to raise an exception
if the facility is not enabled. It updates the interrupt cause field
in FSCR. This adds a TCG translation block generation code. The helper
may be used for HFSCR too as it has the same format.
The helper raising FU exceptions is not used by this patch but will be
in the next ones.
This adds gen_update_current_nip() to update NIP in DisasContext.
This helper is not used now and will be called before checking for
a condition for throwing an FU exception.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v4:
* added gen_update_current_nip()
* it is gen_spr_power8_fscr() now instead of gen_spr_power8_common()
* added "facility unavailable" exception vector at 0xF60
---
target-ppc/cpu.h | 16 ++++++++++++++++
target-ppc/excp_helper.c | 5 +++++
target-ppc/helper.h | 1 +
target-ppc/misc_helper.c | 27 +++++++++++++++++++++++++++
target-ppc/translate.c | 7 +++++++
target-ppc/translate_init.c | 10 ++++++++++
6 files changed, 66 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8f43b37..32fadcd 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -238,6 +238,7 @@ enum {
POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
/* VSX Unavailable (Power ISA 2.06 and later) */
POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
+ POWERPC_EXCP_FU = 95, /* Facility Unavailable */
/* EOL */
POWERPC_EXCP_NB = 96,
/* QEMU exceptions: used internally during code translation */
@@ -516,6 +517,19 @@ struct ppc_slb_t {
#endif
#endif
+/* Facility Status and Control (FSCR) bits */
+#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
+#define FSCR_TAR (63 - 55) /* Target Address Register */
+/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
+#define FSCR_IC_MASK (0xFFULL)
+#define FSCR_IC_POS (63 - 7)
+#define FSCR_IC_DSCR_SPR3 2
+#define FSCR_IC_PMU 3
+#define FSCR_IC_BHRB 4
+#define FSCR_IC_TM 5
+#define FSCR_IC_EBB 7
+#define FSCR_IC_TAR 8
+
/* Exception state register bits definition */
#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
@@ -1104,6 +1118,7 @@ do { \
/*****************************************************************************/
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
void ppc_translate_init(void);
+void gen_update_current_nip(void *opaque);
int cpu_ppc_exec (CPUPPCState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
@@ -1272,6 +1287,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_CTRL (0x098)
#define SPR_MPC_CMPE (0x098)
#define SPR_MPC_CMPF (0x099)
+#define SPR_FSCR (0x099)
#define SPR_MPC_CMPG (0x09A)
#define SPR_MPC_CMPH (0x09B)
#define SPR_MPC_LCTRL1 (0x09C)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 4fa297d..fd89d99 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -398,6 +398,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
goto store_current;
+ case POWERPC_EXCP_FU: /* Facility unavailable exception */
+ if (lpes1 == 0) {
+ new_msr |= (target_ulong)MSR_HVB;
+ }
+ goto store_current;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
LOG_EXCP("PIT exception\n");
goto store_next;
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 4c795f2..9041ba0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -579,6 +579,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
DEF_HELPER_2(load_dump_spr, void, env, i32)
DEF_HELPER_2(store_dump_spr, void, env, i32)
+DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
DEF_HELPER_1(load_tbl, tl, env)
DEF_HELPER_1(load_tbu, tl, env)
DEF_HELPER_1(load_atbl, tl, env)
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index 2eb2fa6..9ef18c4 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -34,6 +34,33 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
+
+#ifdef TARGET_PPC64
+static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
+ uint32_t sprn, uint32_t cause)
+{
+ qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
+
+ env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
+ cause &= FSCR_IC_MASK;
+ env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
+
+ helper_raise_exception_err(env, POWERPC_EXCP_FU, 0);
+}
+#endif
+
+void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
+ uint32_t sprn, uint32_t cause)
+{
+#ifdef TARGET_PPC64
+ if (env->spr[SPR_FSCR] & (1ULL << bit)) {
+ /* Facility is enabled, continue */
+ return;
+ }
+ raise_fu_exception(env, bit, sprn, cause);
+#endif
+}
+
#if !defined(CONFIG_USER_ONLY)
void helper_store_sdr1(CPUPPCState *env, target_ulong val)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fb2b18b..f330a13 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -290,6 +290,13 @@ static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
tcg_gen_movi_tl(cpu_nip, nip);
}
+void gen_update_current_nip(void *opaque)
+{
+ DisasContext *ctx = opaque;
+
+ tcg_gen_movi_tl(cpu_nip, ctx->nip);
+}
+
static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
{
TCGv_i32 t0, t1;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c41d289..6f0c36b 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3073,6 +3073,7 @@ static void init_excp_POWER7 (CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
+ env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
@@ -7575,6 +7576,14 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_power8_fscr(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_FSCR, "FSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_FSCR, 0x00000000);
+}
+
static void init_proc_book3s_64(CPUPPCState *env, int version)
{
gen_spr_ne_601(env);
@@ -7619,6 +7628,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
}
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_tce_address_control(env);
+ gen_spr_power8_fscr(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (19 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 20/29] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 17:08 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
` (7 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This makes user-privileged read/write fail if TAR facility is not enabled
in FSCR.
Since this is the very first check for enabled in FSCR facility,
this also adds gen_fscr_facility_check() for using in spr_write_tar()/
spr_read_tar().
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6f0c36b..9b83d56 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE {
BOOK3S_CPU_POWER8
};
+static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
+ int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_update_current_nip(opaque);
+ gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
static int check_pow_970 (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000) {
@@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env)
0x00000000);
}
+static void spr_read_tar(void *opaque, int gprn, int sprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_read_generic(opaque, gprn, sprn);
+}
+
+static void spr_write_tar(void *opaque, int sprn, int gprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
+ spr_write_generic(opaque, sprn, gprn);
+}
+
static void gen_spr_power8_tce_address_control(CPUPPCState *env)
{
spr_register(env, SPR_TAR, "TAR",
- &spr_read_generic, &spr_write_generic,
+ &spr_read_tar, &spr_write_tar,
&spr_read_generic, &spr_write_generic,
0x00000000);
}
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
@ 2014-06-03 17:08 ` Tom Musta
2014-06-04 2:37 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 17:08 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This makes user-privileged read/write fail if TAR facility is not enabled
> in FSCR.
>
> Since this is the very first check for enabled in FSCR facility,
> this also adds gen_fscr_facility_check() for using in spr_write_tar()/
> spr_read_tar().
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++-
> 1 file changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 6f0c36b..9b83d56 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE {
> BOOK3S_CPU_POWER8
> };
>
> +static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
> + int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_update_current_nip(opaque);
> + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> static int check_pow_970 (CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & 0x01C00000) {
> @@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void spr_read_tar(void *opaque, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_read_generic(opaque, gprn, sprn);
> +}
> +
> +static void spr_write_tar(void *opaque, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
> + spr_write_generic(opaque, sprn, gprn);
> +}
> +
> static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> {
> spr_register(env, SPR_TAR, "TAR",
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_tar, &spr_write_tar,
> &spr_read_generic, &spr_write_generic,
> 0x00000000);
> }
>
There are potential impacts to user mode here. If I am reading correctly, TAR would not be accessible
in user mode.
An obvious fix would be to initialize FSCR to enable TAR access in the user mode build targets.
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR
2014-06-03 17:08 ` Tom Musta
@ 2014-06-04 2:37 ` Alexey Kardashevskiy
2014-06-04 12:25 ` Tom Musta
0 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 2:37 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 03:08 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This makes user-privileged read/write fail if TAR facility is not enabled
>> in FSCR.
>>
>> Since this is the very first check for enabled in FSCR facility,
>> this also adds gen_fscr_facility_check() for using in spr_write_tar()/
>> spr_read_tar().
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/translate_init.c | 29 ++++++++++++++++++++++++++++-
>> 1 file changed, 28 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 6f0c36b..9b83d56 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7275,6 +7275,21 @@ enum BOOK3S_CPU_TYPE {
>> BOOK3S_CPU_POWER8
>> };
>>
>> +static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
>> + int sprn, int cause)
>> +{
>> + TCGv_i32 t1 = tcg_const_i32(bit);
>> + TCGv_i32 t2 = tcg_const_i32(sprn);
>> + TCGv_i32 t3 = tcg_const_i32(cause);
>> +
>> + gen_update_current_nip(opaque);
>> + gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
>> +
>> + tcg_temp_free_i32(t3);
>> + tcg_temp_free_i32(t2);
>> + tcg_temp_free_i32(t1);
>> +}
>> +
>> static int check_pow_970 (CPUPPCState *env)
>> {
>> if (env->spr[SPR_HID0] & 0x01C00000) {
>> @@ -7568,10 +7583,22 @@ static void gen_spr_power6_common(CPUPPCState *env)
>> 0x00000000);
>> }
>>
>> +static void spr_read_tar(void *opaque, int gprn, int sprn)
>> +{
>> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
>> + spr_read_generic(opaque, gprn, sprn);
>> +}
>> +
>> +static void spr_write_tar(void *opaque, int sprn, int gprn)
>> +{
>> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
>> + spr_write_generic(opaque, sprn, gprn);
>> +}
>> +
>> static void gen_spr_power8_tce_address_control(CPUPPCState *env)
>> {
>> spr_register(env, SPR_TAR, "TAR",
>> - &spr_read_generic, &spr_write_generic,
>> + &spr_read_tar, &spr_write_tar,
>> &spr_read_generic, &spr_write_generic,
>> 0x00000000);
>> }
>>
>
> There are potential impacts to user mode here. If I am reading correctly, TAR would not be accessible
> in user mode.
And this is bad why exactly? I definitely need to learn about linux-user
more...
> An obvious fix would be to initialize FSCR to enable TAR access in the user mode build targets.
Like that?
static void gen_spr_power8_fscr(CPUPPCState *env)
{
+#if defined(CONFIG_USER_ONLY)
+ target_ulong initval = 1ULL << FSCR_TAR;
+#else
+ target_ulong initval = 0;
+#endif
spr_register_kvm(env, SPR_FSCR, "FSCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_FSCR, 0x00000000);
+ KVM_REG_PPC_FSCR, initval);
}
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR
2014-06-04 2:37 ` Alexey Kardashevskiy
@ 2014-06-04 12:25 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-04 12:25 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 9:37 PM, Alexey Kardashevskiy wrote:
> On 06/04/2014 03:08 AM, Tom Musta wrote:
>> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>>> This makes user-privileged read/write fail if TAR facility is not enabled
>>> in FSCR.
[ ...]
>>>
>>
>> There are potential impacts to user mode here. If I am reading correctly, TAR would not be accessible
>> in user mode.
>
>
> And this is bad why exactly? I definitely need to learn about linux-user
> more...
>
Because TAR and bctar are Book I additions to ISA 2.07 and thus we can expect them to show up in applications.
Since FSCR is not user-writeable, if FSCR[TAR] is initially zero, there is no means to enable access. Any
application using bctar would not run.
>
>> An obvious fix would be to initialize FSCR to enable TAR access in the user mode build targets.
>
>
> Like that?
>
> static void gen_spr_power8_fscr(CPUPPCState *env)
> {
> +#if defined(CONFIG_USER_ONLY)
> + target_ulong initval = 1ULL << FSCR_TAR;
> +#else
> + target_ulong initval = 0;
> +#endif
> spr_register_kvm(env, SPR_FSCR, "FSCR",
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> - KVM_REG_PPC_FSCR, 0x00000000);
> + KVM_REG_PPC_FSCR, initval);
> }
>
>
Yes. I believe that would work.
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (20 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 21/29] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 17:10 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
` (6 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
it is accessed via its user-privileged mirror. A spr_read_ureg() is
already there. Since the new helper is only used by book3s CPUs, it is
limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v4:
* disabled write_ureg for user mode, privileged mode is still needed for
recent guest kernels to boot on POWER8
---
target-ppc/cpu.h | 3 +++
target-ppc/translate_init.c | 29 +++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 32fadcd..cf1ccad 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MI_CTR (0x300)
#define SPR_PERF1 (0x301)
#define SPR_RCPU_MI_RBA1 (0x301)
+#define SPR_POWER_UMMCR2 (0x301)
#define SPR_PERF2 (0x302)
#define SPR_RCPU_MI_RBA2 (0x302)
#define SPR_MPC_MI_AP (0x302)
@@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_MD_TW (0x30F)
#define SPR_UPERF0 (0x310)
#define SPR_UPERF1 (0x311)
+#define SPR_POWER_MMCR2 (0x311)
#define SPR_UPERF2 (0x312)
#define SPR_POWER_MMCRA (0X312)
#define SPR_UPERF3 (0x313)
@@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_440_ITV3 (0x377)
#define SPR_440_CCR1 (0x378)
#define SPR_DCRIPR (0x37B)
+#define SPR_POWER_MMCRS (0x37E)
#define SPR_PPR (0x380)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9b83d56..6bb0788 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -175,6 +175,13 @@ static void spr_read_ureg (void *opaque, int gprn, int sprn)
gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
}
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static void spr_write_ureg(void *opaque, int sprn, int gprn)
+{
+ gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
+}
+#endif
+
/* SPR common to all non-embedded PowerPC */
/* DECR */
#if !defined(CONFIG_USER_ONLY)
@@ -7500,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_power8_pmu_hypv(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCR2, 0x00000000);
+ spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRS, 0x00000000);
+}
+
+static void gen_spr_power8_pmu_user(CPUPPCState *env)
+{
+ spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, &spr_write_ureg,
+ 0x00000000);
+}
+
static void gen_spr_power5p_ear(CPUPPCState *env)
{
/* External access control */
@@ -7656,6 +7683,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_tce_address_control(env);
gen_spr_power8_fscr(env);
+ gen_spr_power8_pmu_hypv(env);
+ gen_spr_power8_pmu_user(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
@ 2014-06-03 17:10 ` Tom Musta
2014-06-03 23:42 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 17:10 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
>
> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
> it is accessed via its user-privileged mirror. A spr_read_ureg() is
> already there. Since the new helper is only used by book3s CPUs, it is
> limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v4:
> * disabled write_ureg for user mode, privileged mode is still needed for
> recent guest kernels to boot on POWER8
> ---
> target-ppc/cpu.h | 3 +++
> target-ppc/translate_init.c | 29 +++++++++++++++++++++++++++++
> 2 files changed, 32 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 32fadcd..cf1ccad 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_MI_CTR (0x300)
> #define SPR_PERF1 (0x301)
> #define SPR_RCPU_MI_RBA1 (0x301)
> +#define SPR_POWER_UMMCR2 (0x301)
> #define SPR_PERF2 (0x302)
> #define SPR_RCPU_MI_RBA2 (0x302)
> #define SPR_MPC_MI_AP (0x302)
> @@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_MD_TW (0x30F)
> #define SPR_UPERF0 (0x310)
> #define SPR_UPERF1 (0x311)
> +#define SPR_POWER_MMCR2 (0x311)
> #define SPR_UPERF2 (0x312)
> #define SPR_POWER_MMCRA (0X312)
> #define SPR_UPERF3 (0x313)
> @@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_440_ITV3 (0x377)
> #define SPR_440_CCR1 (0x378)
> #define SPR_DCRIPR (0x37B)
> +#define SPR_POWER_MMCRS (0x37E)
> #define SPR_PPR (0x380)
> #define SPR_750_GQR0 (0x390)
> #define SPR_440_DNV0 (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 9b83d56..6bb0788 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -175,6 +175,13 @@ static void spr_read_ureg (void *opaque, int gprn, int sprn)
> gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
> }
>
> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> +static void spr_write_ureg(void *opaque, int sprn, int gprn)
> +{
> + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
> +}
> +#endif
> +
> /* SPR common to all non-embedded PowerPC */
> /* DECR */
> #if !defined(CONFIG_USER_ONLY)
> @@ -7500,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void gen_spr_power8_pmu_hypv(CPUPPCState *env)
> +{
> + spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCR2, 0x00000000);
> + spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_MMCRS, 0x00000000);
> +}
Supervisor.
> +
> +static void gen_spr_power8_pmu_user(CPUPPCState *env)
> +{
> + spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, &spr_write_ureg,
> + 0x00000000);
> +}
> +
The write_ureg should probably also be applied to the other PMU Uxxxx SPRs, no?
> static void gen_spr_power5p_ear(CPUPPCState *env)
> {
> /* External access control */
> @@ -7656,6 +7683,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> if (version >= BOOK3S_CPU_POWER8) {
> gen_spr_power8_tce_address_control(env);
> gen_spr_power8_fscr(env);
> + gen_spr_power8_pmu_hypv(env);
> + gen_spr_power8_pmu_user(env);
> }
> #if !defined(CONFIG_USER_ONLY)
> switch (version) {
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs
2014-06-03 17:10 ` Tom Musta
@ 2014-06-03 23:42 ` Alexey Kardashevskiy
2014-06-04 5:26 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 23:42 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 03:10 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
>>
>> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
>> it is accessed via its user-privileged mirror. A spr_read_ureg() is
>> already there. Since the new helper is only used by book3s CPUs, it is
>> limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> Changes:
>> v4:
>> * disabled write_ureg for user mode, privileged mode is still needed for
>> recent guest kernels to boot on POWER8
>> ---
>> target-ppc/cpu.h | 3 +++
>> target-ppc/translate_init.c | 29 +++++++++++++++++++++++++++++
>> 2 files changed, 32 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 32fadcd..cf1ccad 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>> #define SPR_MPC_MI_CTR (0x300)
>> #define SPR_PERF1 (0x301)
>> #define SPR_RCPU_MI_RBA1 (0x301)
>> +#define SPR_POWER_UMMCR2 (0x301)
>> #define SPR_PERF2 (0x302)
>> #define SPR_RCPU_MI_RBA2 (0x302)
>> #define SPR_MPC_MI_AP (0x302)
>> @@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>> #define SPR_MPC_MD_TW (0x30F)
>> #define SPR_UPERF0 (0x310)
>> #define SPR_UPERF1 (0x311)
>> +#define SPR_POWER_MMCR2 (0x311)
>> #define SPR_UPERF2 (0x312)
>> #define SPR_POWER_MMCRA (0X312)
>> #define SPR_UPERF3 (0x313)
>> @@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>> #define SPR_440_ITV3 (0x377)
>> #define SPR_440_CCR1 (0x378)
>> #define SPR_DCRIPR (0x37B)
>> +#define SPR_POWER_MMCRS (0x37E)
>> #define SPR_PPR (0x380)
>> #define SPR_750_GQR0 (0x390)
>> #define SPR_440_DNV0 (0x390)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 9b83d56..6bb0788 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -175,6 +175,13 @@ static void spr_read_ureg (void *opaque, int gprn, int sprn)
>> gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
>> }
>>
>> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
>> +static void spr_write_ureg(void *opaque, int sprn, int gprn)
>> +{
>> + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
>> +}
>> +#endif
>> +
>> /* SPR common to all non-embedded PowerPC */
>> /* DECR */
>> #if !defined(CONFIG_USER_ONLY)
>> @@ -7500,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
>> 0x00000000);
>> }
>>
>> +static void gen_spr_power8_pmu_hypv(CPUPPCState *env)
>> +{
>> + spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + KVM_REG_PPC_MMCR2, 0x00000000);
>> + spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + &spr_read_generic, &spr_write_generic,
>> + KVM_REG_PPC_MMCRS, 0x00000000);
>> +}
>
>
> Supervisor.
>
>> +
>> +static void gen_spr_power8_pmu_user(CPUPPCState *env)
>> +{
>> + spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
>> + &spr_read_ureg, SPR_NOACCESS,
>> + &spr_read_ureg, &spr_write_ureg,
>> + 0x00000000);
>> +}
>> +
>
> The write_ureg should probably also be applied to the other PMU Uxxxx SPRs, no?
We do not support EBB and without that there should be no write_ureg at
all. Your comment in patch #4 is about that, right? But UMMCR2 is still
accessed by fresh guests, this is the only reason why I enabled this one.
So what does make sense to do with all of them?
>
>> static void gen_spr_power5p_ear(CPUPPCState *env)
>> {
>> /* External access control */
>> @@ -7656,6 +7683,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> if (version >= BOOK3S_CPU_POWER8) {
>> gen_spr_power8_tce_address_control(env);
>> gen_spr_power8_fscr(env);
>> + gen_spr_power8_pmu_hypv(env);
>> + gen_spr_power8_pmu_user(env);
>> }
>> #if !defined(CONFIG_USER_ONLY)
>> switch (version) {
>>
>
> Reviewed-by: Tom Musta <tommusta@gmail.com>
>
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs
2014-06-03 23:42 ` Alexey Kardashevskiy
@ 2014-06-04 5:26 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 5:26 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 09:42 AM, Alexey Kardashevskiy wrote:
> On 06/04/2014 03:10 AM, Tom Musta wrote:
>> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>>> This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
>>>
>>> This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
>>> it is accessed via its user-privileged mirror. A spr_read_ureg() is
>>> already there. Since the new helper is only used by book3s CPUs, it is
>>> limited to TARGET_PPC64 to make gcc happy when QEMU is compiled for 32 bit.
>>>
>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>> ---
>>> Changes:
>>> v4:
>>> * disabled write_ureg for user mode, privileged mode is still needed for
>>> recent guest kernels to boot on POWER8
>>> ---
>>> target-ppc/cpu.h | 3 +++
>>> target-ppc/translate_init.c | 29 +++++++++++++++++++++++++++++
>>> 2 files changed, 32 insertions(+)
>>>
>>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>>> index 32fadcd..cf1ccad 100644
>>> --- a/target-ppc/cpu.h
>>> +++ b/target-ppc/cpu.h
>>> @@ -1480,6 +1480,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>>> #define SPR_MPC_MI_CTR (0x300)
>>> #define SPR_PERF1 (0x301)
>>> #define SPR_RCPU_MI_RBA1 (0x301)
>>> +#define SPR_POWER_UMMCR2 (0x301)
>>> #define SPR_PERF2 (0x302)
>>> #define SPR_RCPU_MI_RBA2 (0x302)
>>> #define SPR_MPC_MI_AP (0x302)
>>> @@ -1527,6 +1528,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>>> #define SPR_MPC_MD_TW (0x30F)
>>> #define SPR_UPERF0 (0x310)
>>> #define SPR_UPERF1 (0x311)
>>> +#define SPR_POWER_MMCR2 (0x311)
>>> #define SPR_UPERF2 (0x312)
>>> #define SPR_POWER_MMCRA (0X312)
>>> #define SPR_UPERF3 (0x313)
>>> @@ -1579,6 +1581,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>>> #define SPR_440_ITV3 (0x377)
>>> #define SPR_440_CCR1 (0x378)
>>> #define SPR_DCRIPR (0x37B)
>>> +#define SPR_POWER_MMCRS (0x37E)
>>> #define SPR_PPR (0x380)
>>> #define SPR_750_GQR0 (0x390)
>>> #define SPR_440_DNV0 (0x390)
>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>> index 9b83d56..6bb0788 100644
>>> --- a/target-ppc/translate_init.c
>>> +++ b/target-ppc/translate_init.c
>>> @@ -175,6 +175,13 @@ static void spr_read_ureg (void *opaque, int gprn, int sprn)
>>> gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
>>> }
>>>
>>> +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
>>> +static void spr_write_ureg(void *opaque, int sprn, int gprn)
>>> +{
>>> + gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
>>> +}
>>> +#endif
>>> +
>>> /* SPR common to all non-embedded PowerPC */
>>> /* DECR */
>>> #if !defined(CONFIG_USER_ONLY)
>>> @@ -7500,6 +7507,26 @@ static void gen_spr_970_pmu_user(CPUPPCState *env)
>>> 0x00000000);
>>> }
>>>
>>> +static void gen_spr_power8_pmu_hypv(CPUPPCState *env)
>>> +{
>>> + spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + &spr_read_generic, &spr_write_generic,
>>> + KVM_REG_PPC_MMCR2, 0x00000000);
>>> + spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
>>> + SPR_NOACCESS, SPR_NOACCESS,
>>> + &spr_read_generic, &spr_write_generic,
>>> + KVM_REG_PPC_MMCRS, 0x00000000);
>>> +}
>>
>>
>> Supervisor.
>>
>>> +
>>> +static void gen_spr_power8_pmu_user(CPUPPCState *env)
>>> +{
>>> + spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
>>> + &spr_read_ureg, SPR_NOACCESS,
>>> + &spr_read_ureg, &spr_write_ureg,
>>> + 0x00000000);
>>> +}
>>> +
>>
>> The write_ureg should probably also be applied to the other PMU Uxxxx SPRs, no?
>
>
> We do not support EBB and without that there should be no write_ureg at
> all. Your comment in patch #4 is about that, right? But UMMCR2 is still
> accessed by fresh guests, this is the only reason why I enabled this one.
>
> So what does make sense to do with all of them?
Ah, applied spr_write_ureg() to all of them for now so disregard this comment.
>
>
>>
>>> static void gen_spr_power5p_ear(CPUPPCState *env)
>>> {
>>> /* External access control */
>>> @@ -7656,6 +7683,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>>> if (version >= BOOK3S_CPU_POWER8) {
>>> gen_spr_power8_tce_address_control(env);
>>> gen_spr_power8_fscr(env);
>>> + gen_spr_power8_pmu_hypv(env);
>>> + gen_spr_power8_pmu_user(env);
>>> }
>>> #if !defined(CONFIG_USER_ONLY)
>>> switch (version) {
>>>
>>
>> Reviewed-by: Tom Musta <tommusta@gmail.com>
>>
>
>
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (21 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 22/29] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 17:58 ` Tom Musta
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 24/29] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
` (5 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds TM (Transactional Memory) SPRs.
This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the helpers.
This adds a gen_msr_facility_check() helper which purpose is to generate
the Facility Unavailable exception if the facility is disabled.
It is a copy of gen_fscr_facility_check() but it checks for enabled
facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
in FSCR/HFSCR (whichever is passed to the helper).
This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
which are used for TM SPRs.
This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class'
msr_mask.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v4:
* enable MSR_TM in msr_mask
* tested compile with --enable-tcg-debug and ppc-softmmu
* re-implemented spr_(read|write)_prev_upper32 using TCGv types (not i32 or i64)
---
target-ppc/cpu.h | 10 ++++++
target-ppc/helper.h | 1 +
target-ppc/misc_helper.c | 12 +++++++
target-ppc/translate_init.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 108 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index cf1ccad..8ea471c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -427,6 +427,9 @@ struct ppc_slb_t {
#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_SHV 60 /* hypervisor state hflags */
+#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
+#define MSR_TS1 33
+#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define MSR_ICM 30 /* Interrupt computation mode for BookE */
#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
@@ -503,6 +506,9 @@ struct ppc_slb_t {
#define msr_pmm ((env->msr >> MSR_PMM) & 1)
#define msr_ri ((env->msr >> MSR_RI) & 1)
#define msr_le ((env->msr >> MSR_LE) & 1)
+#define msr_ts ((env->msr >> MSR_TS1) & 3)
+#define msr_tm ((env->msr >> MSR_TM) & 1)
+
/* Hypervisor bit is more specific */
#if defined(TARGET_PPC64)
#define MSR_HVB (1ULL << MSR_SHV)
@@ -1275,6 +1281,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_MPC_EIE (0x050)
#define SPR_MPC_EID (0x051)
#define SPR_MPC_NRI (0x052)
+#define SPR_TFHAR (0x080)
+#define SPR_TFIAR (0x081)
+#define SPR_TEXASR (0x082)
+#define SPR_TEXASRU (0x083)
#define SPR_UCTRL (0x088)
#define SPR_MPC_CMPA (0x090)
#define SPR_MPC_CMPB (0x091)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9041ba0..4c211b8 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -580,6 +580,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
DEF_HELPER_2(load_dump_spr, void, env, i32)
DEF_HELPER_2(store_dump_spr, void, env, i32)
DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
+DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32)
DEF_HELPER_1(load_tbl, tl, env)
DEF_HELPER_1(load_tbu, tl, env)
DEF_HELPER_1(load_atbl, tl, env)
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index 9ef18c4..409deb6 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -61,6 +61,18 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
#endif
}
+void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
+ uint32_t sprn, uint32_t cause)
+{
+#ifdef TARGET_PPC64
+ if (env->msr & (1ULL << bit)) {
+ /* Facility is enabled, continue */
+ return;
+ }
+ raise_fu_exception(env, bit, sprn, cause);
+#endif
+}
+
#if !defined(CONFIG_USER_ONLY)
void helper_store_sdr1(CPUPPCState *env, target_ulong val)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6bb0788..bb4201c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7297,6 +7297,45 @@ static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
tcg_temp_free_i32(t1);
}
+static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit,
+ int sprn, int cause)
+{
+ TCGv_i32 t1 = tcg_const_i32(bit);
+ TCGv_i32 t2 = tcg_const_i32(sprn);
+ TCGv_i32 t3 = tcg_const_i32(cause);
+
+ gen_update_current_nip(opaque);
+ gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
+
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+}
+
+static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
+{
+ TCGv spr_up = tcg_temp_new();
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_shri_tl(spr_up, spr, 32);
+ tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
+
+ tcg_temp_free(spr);
+ tcg_temp_free(spr_up);
+}
+
+static void spr_write_prev_upper32(void *opaque, int sprn, int gprn)
+{
+ TCGv spr = tcg_temp_new();
+
+ gen_load_spr(spr, sprn - 1);
+ tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
+ gen_store_spr(sprn - 1, spr);
+
+ tcg_temp_free(spr);
+}
+
static int check_pow_970 (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000) {
@@ -7630,6 +7669,50 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
0x00000000);
}
+static void spr_read_tm(void *opaque, int gprn, int sprn)
+{
+ gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_generic(opaque, gprn, sprn);
+}
+
+static void spr_write_tm(void *opaque, int sprn, int gprn)
+{
+ gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_generic(opaque, sprn, gprn);
+}
+
+static void spr_read_tm_upper32(void *opaque, int gprn, int sprn)
+{
+ gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_read_prev_upper32(opaque, gprn, sprn);
+}
+
+static void spr_write_tm_upper32(void *opaque, int sprn, int gprn)
+{
+ gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
+ spr_write_prev_upper32(opaque, sprn, gprn);
+}
+
+static void gen_spr_power8_tm(CPUPPCState *env)
+{
+ spr_register_kvm(env, SPR_TFHAR, "TFHAR",
+ &spr_read_tm, &spr_write_tm,
+ &spr_read_tm, &spr_write_tm,
+ KVM_REG_PPC_TFHAR, 0x00000000);
+ spr_register_kvm(env, SPR_TFIAR, "TFIAR",
+ &spr_read_tm, &spr_write_tm,
+ &spr_read_tm, &spr_write_tm,
+ KVM_REG_PPC_TFIAR, 0x00000000);
+ spr_register_kvm(env, SPR_TEXASR, "TEXASR",
+ &spr_read_tm, &spr_write_tm,
+ &spr_read_tm, &spr_write_tm,
+ KVM_REG_PPC_TEXASR, 0x00000000);
+ spr_register(env, SPR_TEXASRU, "TEXASRU",
+ &spr_read_tm_upper32, &spr_write_tm_upper32,
+ &spr_read_tm_upper32, &spr_write_tm_upper32,
+ 0x00000000);
+}
+
static void gen_spr_power8_fscr(CPUPPCState *env)
{
spr_register_kvm(env, SPR_FSCR, "FSCR",
@@ -7685,6 +7768,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_fscr(env);
gen_spr_power8_pmu_hypv(env);
gen_spr_power8_pmu_user(env);
+ gen_spr_power8_tm(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
@@ -8056,6 +8140,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S;
pcc->msr_mask = (1ull << MSR_SF) |
+ (1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
(1ull << MSR_EE) |
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
@ 2014-06-03 17:58 ` Tom Musta
2014-06-04 2:54 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 17:58 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TM (Transactional Memory) SPRs.
>
> This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
> handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
> Since this is not the only register like that and their numbers go
> consequently, it makes sense to generalize the helpers.
>
> This adds a gen_msr_facility_check() helper which purpose is to generate
> the Facility Unavailable exception if the facility is disabled.
> It is a copy of gen_fscr_facility_check() but it checks for enabled
> facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
> in FSCR/HFSCR (whichever is passed to the helper).
>
> This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
> which are used for TM SPRs.
>
> This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class'
> msr_mask.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v4:
> * enable MSR_TM in msr_mask
> * tested compile with --enable-tcg-debug and ppc-softmmu
> * re-implemented spr_(read|write)_prev_upper32 using TCGv types (not i32 or i64)
> ---
> target-ppc/cpu.h | 10 ++++++
> target-ppc/helper.h | 1 +
> target-ppc/misc_helper.c | 12 +++++++
> target-ppc/translate_init.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 108 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index cf1ccad..8ea471c 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -427,6 +427,9 @@ struct ppc_slb_t {
> #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
> #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
> #define MSR_SHV 60 /* hypervisor state hflags */
> +#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
> +#define MSR_TS1 33
> +#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
> #define MSR_CM 31 /* Computation mode for BookE hflags */
> #define MSR_ICM 30 /* Interrupt computation mode for BookE */
> #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
> @@ -503,6 +506,9 @@ struct ppc_slb_t {
> #define msr_pmm ((env->msr >> MSR_PMM) & 1)
> #define msr_ri ((env->msr >> MSR_RI) & 1)
> #define msr_le ((env->msr >> MSR_LE) & 1)
> +#define msr_ts ((env->msr >> MSR_TS1) & 3)
> +#define msr_tm ((env->msr >> MSR_TM) & 1)
> +
> /* Hypervisor bit is more specific */
> #if defined(TARGET_PPC64)
> #define MSR_HVB (1ULL << MSR_SHV)
> @@ -1275,6 +1281,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_MPC_EIE (0x050)
> #define SPR_MPC_EID (0x051)
> #define SPR_MPC_NRI (0x052)
> +#define SPR_TFHAR (0x080)
> +#define SPR_TFIAR (0x081)
> +#define SPR_TEXASR (0x082)
> +#define SPR_TEXASRU (0x083)
> #define SPR_UCTRL (0x088)
> #define SPR_MPC_CMPA (0x090)
> #define SPR_MPC_CMPB (0x091)
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9041ba0..4c211b8 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -580,6 +580,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
> DEF_HELPER_2(load_dump_spr, void, env, i32)
> DEF_HELPER_2(store_dump_spr, void, env, i32)
> DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
> +DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32)
> DEF_HELPER_1(load_tbl, tl, env)
> DEF_HELPER_1(load_tbu, tl, env)
> DEF_HELPER_1(load_atbl, tl, env)
> diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
> index 9ef18c4..409deb6 100644
> --- a/target-ppc/misc_helper.c
> +++ b/target-ppc/misc_helper.c
> @@ -61,6 +61,18 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
> #endif
> }
>
> +void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
> + uint32_t sprn, uint32_t cause)
> +{
> +#ifdef TARGET_PPC64
> + if (env->msr & (1ULL << bit)) {
> + /* Facility is enabled, continue */
> + return;
> + }
> + raise_fu_exception(env, bit, sprn, cause);
> +#endif
> +}
> +
> #if !defined(CONFIG_USER_ONLY)
>
> void helper_store_sdr1(CPUPPCState *env, target_ulong val)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 6bb0788..bb4201c 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7297,6 +7297,45 @@ static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
> tcg_temp_free_i32(t1);
> }
>
> +static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit,
> + int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_update_current_nip(opaque);
> + gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> +static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
> +{
> + TCGv spr_up = tcg_temp_new();
> + TCGv spr = tcg_temp_new();
> +
> + gen_load_spr(spr, sprn - 1);
> + tcg_gen_shri_tl(spr_up, spr, 32);
> + tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
> +
> + tcg_temp_free(spr);
> + tcg_temp_free(spr_up);
> +}
> +
> +static void spr_write_prev_upper32(void *opaque, int sprn, int gprn)
> +{
> + TCGv spr = tcg_temp_new();
> +
> + gen_load_spr(spr, sprn - 1);
> + tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
> + gen_store_spr(sprn - 1, spr);
> +
> + tcg_temp_free(spr);
> +}
> +
> static int check_pow_970 (CPUPPCState *env)
> {
> if (env->spr[SPR_HID0] & 0x01C00000) {
> @@ -7630,6 +7669,50 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void spr_read_tm(void *opaque, int gprn, int sprn)
> +{
> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_read_generic(opaque, gprn, sprn);
> +}
> +
> +static void spr_write_tm(void *opaque, int sprn, int gprn)
> +{
> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_write_generic(opaque, sprn, gprn);
> +}
> +
> +static void spr_read_tm_upper32(void *opaque, int gprn, int sprn)
> +{
> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_read_prev_upper32(opaque, gprn, sprn);
> +}
> +
> +static void spr_write_tm_upper32(void *opaque, int sprn, int gprn)
> +{
> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
> + spr_write_prev_upper32(opaque, sprn, gprn);
> +}
> +
> +static void gen_spr_power8_tm(CPUPPCState *env)
> +{
> + spr_register_kvm(env, SPR_TFHAR, "TFHAR",
> + &spr_read_tm, &spr_write_tm,
> + &spr_read_tm, &spr_write_tm,
> + KVM_REG_PPC_TFHAR, 0x00000000);
> + spr_register_kvm(env, SPR_TFIAR, "TFIAR",
> + &spr_read_tm, &spr_write_tm,
> + &spr_read_tm, &spr_write_tm,
> + KVM_REG_PPC_TFIAR, 0x00000000);
> + spr_register_kvm(env, SPR_TEXASR, "TEXASR",
> + &spr_read_tm, &spr_write_tm,
> + &spr_read_tm, &spr_write_tm,
> + KVM_REG_PPC_TEXASR, 0x00000000);
> + spr_register(env, SPR_TEXASRU, "TEXASRU",
> + &spr_read_tm_upper32, &spr_write_tm_upper32,
> + &spr_read_tm_upper32, &spr_write_tm_upper32,
> + 0x00000000);
> +}
> +
> static void gen_spr_power8_fscr(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_FSCR, "FSCR",
> @@ -7685,6 +7768,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_power8_fscr(env);
> gen_spr_power8_pmu_hypv(env);
> gen_spr_power8_pmu_user(env);
> + gen_spr_power8_tm(env);
> }
> #if !defined(CONFIG_USER_ONLY)
> switch (version) {
> @@ -8056,6 +8140,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> PPC2_ISA205 | PPC2_ISA207S;
> pcc->msr_mask = (1ull << MSR_SF) |
> + (1ull << MSR_TM) |
> (1ull << MSR_VR) |
> (1ull << MSR_VSX) |
> (1ull << MSR_EE) |
>
There are user-mode impacts here as well .... although I think we are a long way off from doing anything with TM.
The typical pattern is to default MSR enable bits to 1 ... see translate_init.c/ppc_cpu_reset:
9490 /* CPUClass::reset() */
9491 static void ppc_cpu_reset(CPUState *s)
9492 {
9493 PowerPCCPU *cpu = POWERPC_CPU(s);
9494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9495 CPUPPCState *env = &cpu->env;
9496 target_ulong msr;
9497 int i;
9498
9499 pcc->parent_reset(s);
9500
9501 msr = (target_ulong)0;
9502 if (0) {
9503 /* XXX: find a suitable condition to enable the hypervisor mode */
9504 msr |= (target_ulong)MSR_HVB;
9505 }
9506 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9507 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9508 msr |= (target_ulong)1 << MSR_EP;
9509 #if defined(DO_SINGLE_STEP) && 0
9510 /* Single step trace mode */
9511 msr |= (target_ulong)1 << MSR_SE;
9512 msr |= (target_ulong)1 << MSR_BE;
9513 #endif
9514 #if defined(CONFIG_USER_ONLY)
9515 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9516 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9517 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9518 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9519 msr |= (target_ulong)1 << MSR_PR;
9520 #if !defined(TARGET_WORDS_BIGENDIAN)
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs
2014-06-03 17:58 ` Tom Musta
@ 2014-06-04 2:54 ` Alexey Kardashevskiy
2014-06-04 12:30 ` Tom Musta
0 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 2:54 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 03:58 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds TM (Transactional Memory) SPRs.
>>
>> This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
>> handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
>> Since this is not the only register like that and their numbers go
>> consequently, it makes sense to generalize the helpers.
>>
>> This adds a gen_msr_facility_check() helper which purpose is to generate
>> the Facility Unavailable exception if the facility is disabled.
>> It is a copy of gen_fscr_facility_check() but it checks for enabled
>> facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause
>> in FSCR/HFSCR (whichever is passed to the helper).
>>
>> This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32
>> which are used for TM SPRs.
>>
>> This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class'
>> msr_mask.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> Changes:
>> v4:
>> * enable MSR_TM in msr_mask
>> * tested compile with --enable-tcg-debug and ppc-softmmu
>> * re-implemented spr_(read|write)_prev_upper32 using TCGv types (not i32 or i64)
>> ---
>> target-ppc/cpu.h | 10 ++++++
>> target-ppc/helper.h | 1 +
>> target-ppc/misc_helper.c | 12 +++++++
>> target-ppc/translate_init.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 108 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index cf1ccad..8ea471c 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -427,6 +427,9 @@ struct ppc_slb_t {
>> #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
>> #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
>> #define MSR_SHV 60 /* hypervisor state hflags */
>> +#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
>> +#define MSR_TS1 33
>> +#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
>> #define MSR_CM 31 /* Computation mode for BookE hflags */
>> #define MSR_ICM 30 /* Interrupt computation mode for BookE */
>> #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
>> @@ -503,6 +506,9 @@ struct ppc_slb_t {
>> #define msr_pmm ((env->msr >> MSR_PMM) & 1)
>> #define msr_ri ((env->msr >> MSR_RI) & 1)
>> #define msr_le ((env->msr >> MSR_LE) & 1)
>> +#define msr_ts ((env->msr >> MSR_TS1) & 3)
>> +#define msr_tm ((env->msr >> MSR_TM) & 1)
>> +
>> /* Hypervisor bit is more specific */
>> #if defined(TARGET_PPC64)
>> #define MSR_HVB (1ULL << MSR_SHV)
>> @@ -1275,6 +1281,10 @@ static inline int cpu_mmu_index (CPUPPCState *env)
>> #define SPR_MPC_EIE (0x050)
>> #define SPR_MPC_EID (0x051)
>> #define SPR_MPC_NRI (0x052)
>> +#define SPR_TFHAR (0x080)
>> +#define SPR_TFIAR (0x081)
>> +#define SPR_TEXASR (0x082)
>> +#define SPR_TEXASRU (0x083)
>> #define SPR_UCTRL (0x088)
>> #define SPR_MPC_CMPA (0x090)
>> #define SPR_MPC_CMPB (0x091)
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index 9041ba0..4c211b8 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -580,6 +580,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
>> DEF_HELPER_2(load_dump_spr, void, env, i32)
>> DEF_HELPER_2(store_dump_spr, void, env, i32)
>> DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
>> +DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32)
>> DEF_HELPER_1(load_tbl, tl, env)
>> DEF_HELPER_1(load_tbu, tl, env)
>> DEF_HELPER_1(load_atbl, tl, env)
>> diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
>> index 9ef18c4..409deb6 100644
>> --- a/target-ppc/misc_helper.c
>> +++ b/target-ppc/misc_helper.c
>> @@ -61,6 +61,18 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
>> #endif
>> }
>>
>> +void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
>> + uint32_t sprn, uint32_t cause)
>> +{
>> +#ifdef TARGET_PPC64
>> + if (env->msr & (1ULL << bit)) {
>> + /* Facility is enabled, continue */
>> + return;
>> + }
>> + raise_fu_exception(env, bit, sprn, cause);
>> +#endif
>> +}
>> +
>> #if !defined(CONFIG_USER_ONLY)
>>
>> void helper_store_sdr1(CPUPPCState *env, target_ulong val)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 6bb0788..bb4201c 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7297,6 +7297,45 @@ static void gen_fscr_facility_check(void *opaque, int facility_sprn, int bit,
>> tcg_temp_free_i32(t1);
>> }
>>
>> +static void gen_msr_facility_check(void *opaque, int facility_sprn, int bit,
>> + int sprn, int cause)
>> +{
>> + TCGv_i32 t1 = tcg_const_i32(bit);
>> + TCGv_i32 t2 = tcg_const_i32(sprn);
>> + TCGv_i32 t3 = tcg_const_i32(cause);
>> +
>> + gen_update_current_nip(opaque);
>> + gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
>> +
>> + tcg_temp_free_i32(t3);
>> + tcg_temp_free_i32(t2);
>> + tcg_temp_free_i32(t1);
>> +}
>> +
>> +static void spr_read_prev_upper32(void *opaque, int gprn, int sprn)
>> +{
>> + TCGv spr_up = tcg_temp_new();
>> + TCGv spr = tcg_temp_new();
>> +
>> + gen_load_spr(spr, sprn - 1);
>> + tcg_gen_shri_tl(spr_up, spr, 32);
>> + tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
>> +
>> + tcg_temp_free(spr);
>> + tcg_temp_free(spr_up);
>> +}
>> +
>> +static void spr_write_prev_upper32(void *opaque, int sprn, int gprn)
>> +{
>> + TCGv spr = tcg_temp_new();
>> +
>> + gen_load_spr(spr, sprn - 1);
>> + tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
>> + gen_store_spr(sprn - 1, spr);
>> +
>> + tcg_temp_free(spr);
>> +}
>> +
>> static int check_pow_970 (CPUPPCState *env)
>> {
>> if (env->spr[SPR_HID0] & 0x01C00000) {
>> @@ -7630,6 +7669,50 @@ static void gen_spr_power8_tce_address_control(CPUPPCState *env)
>> 0x00000000);
>> }
>>
>> +static void spr_read_tm(void *opaque, int gprn, int sprn)
>> +{
>> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
>> + spr_read_generic(opaque, gprn, sprn);
>> +}
>> +
>> +static void spr_write_tm(void *opaque, int sprn, int gprn)
>> +{
>> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
>> + spr_write_generic(opaque, sprn, gprn);
>> +}
>> +
>> +static void spr_read_tm_upper32(void *opaque, int gprn, int sprn)
>> +{
>> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
>> + spr_read_prev_upper32(opaque, gprn, sprn);
>> +}
>> +
>> +static void spr_write_tm_upper32(void *opaque, int sprn, int gprn)
>> +{
>> + gen_msr_facility_check(opaque, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
>> + spr_write_prev_upper32(opaque, sprn, gprn);
>> +}
>> +
>> +static void gen_spr_power8_tm(CPUPPCState *env)
>> +{
>> + spr_register_kvm(env, SPR_TFHAR, "TFHAR",
>> + &spr_read_tm, &spr_write_tm,
>> + &spr_read_tm, &spr_write_tm,
>> + KVM_REG_PPC_TFHAR, 0x00000000);
>> + spr_register_kvm(env, SPR_TFIAR, "TFIAR",
>> + &spr_read_tm, &spr_write_tm,
>> + &spr_read_tm, &spr_write_tm,
>> + KVM_REG_PPC_TFIAR, 0x00000000);
>> + spr_register_kvm(env, SPR_TEXASR, "TEXASR",
>> + &spr_read_tm, &spr_write_tm,
>> + &spr_read_tm, &spr_write_tm,
>> + KVM_REG_PPC_TEXASR, 0x00000000);
>> + spr_register(env, SPR_TEXASRU, "TEXASRU",
>> + &spr_read_tm_upper32, &spr_write_tm_upper32,
>> + &spr_read_tm_upper32, &spr_write_tm_upper32,
>> + 0x00000000);
>> +}
>> +
>> static void gen_spr_power8_fscr(CPUPPCState *env)
>> {
>> spr_register_kvm(env, SPR_FSCR, "FSCR",
>> @@ -7685,6 +7768,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> gen_spr_power8_fscr(env);
>> gen_spr_power8_pmu_hypv(env);
>> gen_spr_power8_pmu_user(env);
>> + gen_spr_power8_tm(env);
>> }
>> #if !defined(CONFIG_USER_ONLY)
>> switch (version) {
>> @@ -8056,6 +8140,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>> PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
>> PPC2_ISA205 | PPC2_ISA207S;
>> pcc->msr_mask = (1ull << MSR_SF) |
>> + (1ull << MSR_TM) |
>> (1ull << MSR_VR) |
>> (1ull << MSR_VSX) |
>> (1ull << MSR_EE) |
>>
>
> There are user-mode impacts here as well .... although I think we are a long way off from doing anything with TM.
>
> The typical pattern is to default MSR enable bits to 1 ... see translate_init.c/ppc_cpu_reset:
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -9459,19 +9459,19 @@ static void ppc_cpu_reset(CPUState *s)
#endif
#if defined(CONFIG_USER_ONLY)
msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
msr |= (target_ulong)1 << MSR_PR;
+ msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
#if !defined(TARGET_WORDS_BIGENDIAN)
msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
#endif
#endif
So I'll do this and if MSR_TM is not in msr_mask (CPUs older than POWER8),
the guest won't see it and we are fine. Correct?
> 9490 /* CPUClass::reset() */
> 9491 static void ppc_cpu_reset(CPUState *s)
> 9492 {
> 9493 PowerPCCPU *cpu = POWERPC_CPU(s);
> 9494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> 9495 CPUPPCState *env = &cpu->env;
> 9496 target_ulong msr;
> 9497 int i;
> 9498
> 9499 pcc->parent_reset(s);
> 9500
> 9501 msr = (target_ulong)0;
> 9502 if (0) {
> 9503 /* XXX: find a suitable condition to enable the hypervisor mode */
> 9504 msr |= (target_ulong)MSR_HVB;
> 9505 }
> 9506 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
> 9507 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
> 9508 msr |= (target_ulong)1 << MSR_EP;
> 9509 #if defined(DO_SINGLE_STEP) && 0
> 9510 /* Single step trace mode */
> 9511 msr |= (target_ulong)1 << MSR_SE;
> 9512 msr |= (target_ulong)1 << MSR_BE;
> 9513 #endif
> 9514 #if defined(CONFIG_USER_ONLY)
> 9515 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
> 9516 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
> 9517 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
> 9518 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
> 9519 msr |= (target_ulong)1 << MSR_PR;
> 9520 #if !defined(TARGET_WORDS_BIGENDIAN)
>
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs
2014-06-04 2:54 ` Alexey Kardashevskiy
@ 2014-06-04 12:30 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-04 12:30 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 9:54 PM, Alexey Kardashevskiy wrote:
> On 06/04/2014 03:58 AM, Tom Musta wrote:
>> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>>> This adds TM (Transactional Memory) SPRs.
>>>
[ ... ]
>>
>> There are user-mode impacts here as well .... although I think we are a long way off from doing anything with TM.
>>
>> The typical pattern is to default MSR enable bits to 1 ... see translate_init.c/ppc_cpu_reset:
>
>
>
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -9459,19 +9459,19 @@ static void ppc_cpu_reset(CPUState *s)
> #endif
> #if defined(CONFIG_USER_ONLY)
> msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
> msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
> msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
> msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
> msr |= (target_ulong)1 << MSR_PR;
> + msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
> #if !defined(TARGET_WORDS_BIGENDIAN)
> msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
> #endif
> #endif
>
>
> So I'll do this and if MSR_TM is not in msr_mask (CPUs older than POWER8),
> the guest won't see it and we are fine. Correct?
>
>
Correct. This is consistent with what is done with all of those other MSR bits.
>
>> 9490 /* CPUClass::reset() */
>> 9491 static void ppc_cpu_reset(CPUState *s)
>> 9492 {
>> 9493 PowerPCCPU *cpu = POWERPC_CPU(s);
>> 9494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>> 9495 CPUPPCState *env = &cpu->env;
>> 9496 target_ulong msr;
>> 9497 int i;
>> 9498
>> 9499 pcc->parent_reset(s);
>> 9500
>> 9501 msr = (target_ulong)0;
>> 9502 if (0) {
>> 9503 /* XXX: find a suitable condition to enable the hypervisor mode */
>> 9504 msr |= (target_ulong)MSR_HVB;
>> 9505 }
>> 9506 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
>> 9507 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
>> 9508 msr |= (target_ulong)1 << MSR_EP;
>> 9509 #if defined(DO_SINGLE_STEP) && 0
>> 9510 /* Single step trace mode */
>> 9511 msr |= (target_ulong)1 << MSR_SE;
>> 9512 msr |= (target_ulong)1 << MSR_BE;
>> 9513 #endif
>> 9514 #if defined(CONFIG_USER_ONLY)
>> 9515 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
>> 9516 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
>> 9517 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
>> 9518 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
>> 9519 msr |= (target_ulong)1 << MSR_PR;
>> 9520 #if !defined(TARGET_WORDS_BIGENDIAN)
>>
>
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 24/29] KVM: target-ppc: Enable TM state migration
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (22 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 23/29] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
@ 2014-06-03 9:27 ` Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
` (4 subsequent siblings)
28 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds migration support for registers saved before Transactional
Memory (TM) transaction started.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 14 ++++++++++++++
target-ppc/kvm.c | 38 ++++++++++++++++++++++++++++++++++++++
target-ppc/machine.c | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 87 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8ea471c..318b32a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1101,6 +1101,20 @@ struct CPUPPCState {
*/
uint8_t fit_period[4];
uint8_t wdt_period[4];
+
+ /* Transactional memory state */
+ target_ulong tm_gpr[32];
+ ppc_avr_t tm_vsr[64];
+ uint64_t tm_cr;
+ uint64_t tm_lr;
+ uint64_t tm_ctr;
+ uint64_t tm_fpscr;
+ uint64_t tm_amr;
+ uint64_t tm_ppr;
+ uint64_t tm_vrsave;
+ uint32_t tm_vscr;
+ uint64_t tm_dscr;
+ uint64_t tm_tar;
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index e6a1625..37efa14 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -863,6 +863,25 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
#ifdef TARGET_PPC64
+ if (msr_ts) {
+ for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
+ }
+ for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
+ }
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
+ kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
+ }
+
if (cap_papr) {
if (kvm_put_vpa(cs) < 0) {
DPRINTF("Warning: Unable to set VPA information to KVM\n");
@@ -1089,6 +1108,25 @@ int kvm_arch_get_registers(CPUState *cs)
}
#ifdef TARGET_PPC64
+ if (msr_ts) {
+ for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
+ }
+ for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
+ }
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
+ kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
+ }
+
if (cap_papr) {
if (kvm_get_vpa(cs) < 0) {
DPRINTF("Warning: Unable to get VPA information from KVM\n");
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index df7cfc5..9c0e697 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -252,6 +252,38 @@ static const VMStateDescription vmstate_vsx = {
},
};
+#ifdef TARGET_PPC64
+/* Transactional memory state */
+static bool tm_needed(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+ CPUPPCState *env = &cpu->env;
+ return msr_ts;
+}
+
+static const VMStateDescription vmstate_tm = {
+ .name = "cpu/tm",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
+ VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
+ VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
+ VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
+ VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
+ VMSTATE_END_OF_LIST()
+ },
+};
+#endif
+
static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
@@ -522,6 +554,9 @@ const VMStateDescription vmstate_ppc_cpu = {
.needed = sr_needed,
} , {
#ifdef TARGET_PPC64
+ .vmsd = &vmstate_tm,
+ .needed = tm_needed,
+ } , {
.vmsd = &vmstate_slb,
.needed = slb_needed,
} , {
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (23 preceding siblings ...)
2014-06-03 9:27 ` [Qemu-devel] [PATCH v4 24/29] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
@ 2014-06-03 9:28 ` Alexey Kardashevskiy
2014-06-03 18:01 ` Tom Musta
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 26/29] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
` (3 subsequent siblings)
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
set of SPRs access to which should generate an "Facility Unavailable"
interrupt if the facilities are not enabled in FSCR for problem state.
This adds EBB SPRs.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/cpu.h | 7 ++++++
target-ppc/translate_init.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 64 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 318b32a..e33828a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1582,11 +1582,18 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_UPERFF (0x31F)
#define SPR_RCPU_MI_RA0 (0x320)
#define SPR_MPC_MI_DBCAM (0x320)
+#define SPR_BESCRS (0x320)
#define SPR_RCPU_MI_RA1 (0x321)
#define SPR_MPC_MI_DBRAM0 (0x321)
+#define SPR_BESCRSU (0x321)
#define SPR_RCPU_MI_RA2 (0x322)
#define SPR_MPC_MI_DBRAM1 (0x322)
+#define SPR_BESCRR (0x322)
#define SPR_RCPU_MI_RA3 (0x323)
+#define SPR_BESCRRU (0x323)
+#define SPR_EBBHR (0x324)
+#define SPR_EBBRR (0x325)
+#define SPR_BESCR (0x326)
#define SPR_RCPU_L2U_RA0 (0x328)
#define SPR_MPC_MD_DBCAM (0x328)
#define SPR_RCPU_L2U_RA1 (0x329)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index bb4201c..ab40f9e 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7713,6 +7713,62 @@ static void gen_spr_power8_tm(CPUPPCState *env)
0x00000000);
}
+static void spr_read_ebb(void *opaque, int gprn, int sprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_generic(opaque, gprn, sprn);
+}
+
+static void spr_write_ebb(void *opaque, int sprn, int gprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_generic(opaque, sprn, gprn);
+}
+
+static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_read_prev_upper32(opaque, gprn, sprn);
+}
+
+static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn)
+{
+ gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
+ spr_write_prev_upper32(opaque, sprn, gprn);
+}
+
+static void gen_spr_power8_ebb(CPUPPCState *env)
+{
+ spr_register(env, SPR_BESCRS, "BESCRS",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRSU, "BESCRSU",
+ &spr_read_ebb_upper32, &spr_write_ebb_upper32,
+ &spr_read_prev_upper32, &spr_write_prev_upper32,
+ 0x00000000);
+ spr_register(env, SPR_BESCRR, "BESCRR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_BESCRRU, "BESCRRU",
+ &spr_read_ebb_upper32, &spr_write_ebb_upper32,
+ &spr_read_prev_upper32, &spr_write_prev_upper32,
+ 0x00000000);
+ spr_register_kvm(env, SPR_EBBHR, "EBBHR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_EBBHR, 0x00000000);
+ spr_register_kvm(env, SPR_EBBRR, "EBBRR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_EBBRR, 0x00000000);
+ spr_register_kvm(env, SPR_BESCR, "BESCR",
+ &spr_read_ebb, &spr_write_ebb,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_BESCR, 0x00000000);
+}
+
static void gen_spr_power8_fscr(CPUPPCState *env)
{
spr_register_kvm(env, SPR_FSCR, "FSCR",
@@ -7765,6 +7821,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
}
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_tce_address_control(env);
+ gen_spr_power8_ebb(env);
gen_spr_power8_fscr(env);
gen_spr_power8_pmu_hypv(env);
gen_spr_power8_pmu_user(env);
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
@ 2014-06-03 18:01 ` Tom Musta
0 siblings, 0 replies; 74+ messages in thread
From: Tom Musta @ 2014-06-03 18:01 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
> POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
> set of SPRs access to which should generate an "Facility Unavailable"
> interrupt if the facilities are not enabled in FSCR for problem state.
>
> This adds EBB SPRs.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/cpu.h | 7 ++++++
> target-ppc/translate_init.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 64 insertions(+)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 318b32a..e33828a 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1582,11 +1582,18 @@ static inline int cpu_mmu_index (CPUPPCState *env)
> #define SPR_UPERFF (0x31F)
> #define SPR_RCPU_MI_RA0 (0x320)
> #define SPR_MPC_MI_DBCAM (0x320)
> +#define SPR_BESCRS (0x320)
> #define SPR_RCPU_MI_RA1 (0x321)
> #define SPR_MPC_MI_DBRAM0 (0x321)
> +#define SPR_BESCRSU (0x321)
> #define SPR_RCPU_MI_RA2 (0x322)
> #define SPR_MPC_MI_DBRAM1 (0x322)
> +#define SPR_BESCRR (0x322)
> #define SPR_RCPU_MI_RA3 (0x323)
> +#define SPR_BESCRRU (0x323)
> +#define SPR_EBBHR (0x324)
> +#define SPR_EBBRR (0x325)
> +#define SPR_BESCR (0x326)
> #define SPR_RCPU_L2U_RA0 (0x328)
> #define SPR_MPC_MD_DBCAM (0x328)
> #define SPR_RCPU_L2U_RA1 (0x329)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index bb4201c..ab40f9e 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7713,6 +7713,62 @@ static void gen_spr_power8_tm(CPUPPCState *env)
> 0x00000000);
> }
>
> +static void spr_read_ebb(void *opaque, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_read_generic(opaque, gprn, sprn);
> +}
> +
> +static void spr_write_ebb(void *opaque, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_write_generic(opaque, sprn, gprn);
> +}
> +
> +static void spr_read_ebb_upper32(void *opaque, int gprn, int sprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_read_prev_upper32(opaque, gprn, sprn);
> +}
> +
> +static void spr_write_ebb_upper32(void *opaque, int sprn, int gprn)
> +{
> + gen_fscr_facility_check(opaque, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
> + spr_write_prev_upper32(opaque, sprn, gprn);
> +}
> +
> +static void gen_spr_power8_ebb(CPUPPCState *env)
> +{
> + spr_register(env, SPR_BESCRS, "BESCRS",
> + &spr_read_ebb, &spr_write_ebb,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_BESCRSU, "BESCRSU",
> + &spr_read_ebb_upper32, &spr_write_ebb_upper32,
> + &spr_read_prev_upper32, &spr_write_prev_upper32,
> + 0x00000000);
> + spr_register(env, SPR_BESCRR, "BESCRR",
> + &spr_read_ebb, &spr_write_ebb,
> + &spr_read_generic, &spr_write_generic,
> + 0x00000000);
> + spr_register(env, SPR_BESCRRU, "BESCRRU",
> + &spr_read_ebb_upper32, &spr_write_ebb_upper32,
> + &spr_read_prev_upper32, &spr_write_prev_upper32,
> + 0x00000000);
> + spr_register_kvm(env, SPR_EBBHR, "EBBHR",
> + &spr_read_ebb, &spr_write_ebb,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_EBBHR, 0x00000000);
> + spr_register_kvm(env, SPR_EBBRR, "EBBRR",
> + &spr_read_ebb, &spr_write_ebb,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_EBBRR, 0x00000000);
> + spr_register_kvm(env, SPR_BESCR, "BESCR",
> + &spr_read_ebb, &spr_write_ebb,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_BESCR, 0x00000000);
> +}
> +
> static void gen_spr_power8_fscr(CPUPPCState *env)
> {
> spr_register_kvm(env, SPR_FSCR, "FSCR",
> @@ -7765,6 +7821,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> }
> if (version >= BOOK3S_CPU_POWER8) {
> gen_spr_power8_tce_address_control(env);
> + gen_spr_power8_ebb(env);
> gen_spr_power8_fscr(env);
> gen_spr_power8_pmu_hypv(env);
> gen_spr_power8_pmu_user(env);
>
Reviewed-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 26/29] target-ppc: Enable PPR and VRSAVE SPRs migration
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (24 preceding siblings ...)
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 25/29] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
@ 2014-06-03 9:28 ` Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
` (2 subsequent siblings)
28 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This hooks SPR with theit "KVM set_one_reg" counterparts which enables
their migration.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index ab40f9e..237074d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7399,10 +7399,10 @@ static void gen_spr_book3s_altivec(CPUPPCState *env)
return;
}
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_VRSAVE, 0x00000000);
/* Can't find information on what this should be on reset. This
* value is the one used by 74xx processors. */
@@ -7625,10 +7625,10 @@ static void gen_spr_power6_dbg(CPUPPCState *env)
static void gen_spr_power5p_common(CPUPPCState *env)
{
- spr_register(env, SPR_PPR, "PPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ spr_register_kvm(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PPR, 0x00000000);
}
static void gen_spr_power6_common(CPUPPCState *env)
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (25 preceding siblings ...)
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 26/29] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
@ 2014-06-03 9:28 ` Alexey Kardashevskiy
2014-06-03 18:05 ` Tom Musta
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 28/29] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds DABRX SPR.
As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
have them (as it implements more powerful facility instead), this limits
DABR/DABRX registration by POWER7 (inclusive).
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target-ppc/translate_init.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 237074d..2c076b0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7415,6 +7415,11 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DABR, 0x00000000);
+
+ spr_register_kvm(env, SPR_DABRX, "DABRX",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ KVM_REG_PPC_DABRX, 0x00000000);
}
static void gen_spr_970_dbg(CPUPPCState *env)
@@ -7784,7 +7789,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_book3s_altivec(env);
gen_spr_book3s_pmu_hypv(env);
gen_spr_book3s_pmu_user(env);
- gen_spr_book3s_dbg(env);
gen_spr_book3s_common(env);
switch (version) {
@@ -7827,6 +7831,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
gen_spr_power8_pmu_user(env);
gen_spr_power8_tm(env);
}
+ if (version < BOOK3S_CPU_POWER8) {
+ gen_spr_book3s_dbg(env);
+ }
#if !defined(CONFIG_USER_ONLY)
switch (version) {
case BOOK3S_CPU_970:
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
@ 2014-06-03 18:05 ` Tom Musta
2014-06-04 3:12 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Tom Musta @ 2014-06-03 18:05 UTC (permalink / raw)
To: Alexey Kardashevskiy, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
> This adds DABRX SPR.
>
> As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
> have them (as it implements more powerful facility instead), this limits
> DABR/DABRX registration by POWER7 (inclusive).
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> target-ppc/translate_init.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 237074d..2c076b0 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7415,6 +7415,11 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> KVM_REG_PPC_DABR, 0x00000000);
> +
> + spr_register_kvm(env, SPR_DABRX, "DABRX",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + KVM_REG_PPC_DABRX, 0x00000000);
> }
>
Is no read nor write access in any mode what you intended? It appears to be supervisor read/write in the 970 UM.
> static void gen_spr_970_dbg(CPUPPCState *env)
> @@ -7784,7 +7789,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_book3s_altivec(env);
> gen_spr_book3s_pmu_hypv(env);
> gen_spr_book3s_pmu_user(env);
> - gen_spr_book3s_dbg(env);
> gen_spr_book3s_common(env);
>
> switch (version) {
> @@ -7827,6 +7831,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
> gen_spr_power8_pmu_user(env);
> gen_spr_power8_tm(env);
> }
> + if (version < BOOK3S_CPU_POWER8) {
> + gen_spr_book3s_dbg(env);
> + }
> #if !defined(CONFIG_USER_ONLY)
> switch (version) {
> case BOOK3S_CPU_970:
>
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7
2014-06-03 18:05 ` Tom Musta
@ 2014-06-04 3:12 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-04 3:12 UTC (permalink / raw)
To: Tom Musta, qemu-devel; +Cc: qemu-ppc, Alexander Graf
On 06/04/2014 04:05 AM, Tom Musta wrote:
> On 6/3/2014 4:28 AM, Alexey Kardashevskiy wrote:
>> This adds DABRX SPR.
>>
>> As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
>> have them (as it implements more powerful facility instead), this limits
>> DABR/DABRX registration by POWER7 (inclusive).
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> target-ppc/translate_init.c | 9 ++++++++-
>> 1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 237074d..2c076b0 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7415,6 +7415,11 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
>> SPR_NOACCESS, SPR_NOACCESS,
>> &spr_read_generic, &spr_write_generic,
>> KVM_REG_PPC_DABR, 0x00000000);
>> +
>> + spr_register_kvm(env, SPR_DABRX, "DABRX",
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + SPR_NOACCESS, SPR_NOACCESS,
>> + KVM_REG_PPC_DABRX, 0x00000000);
>> }
>>
>
> Is no read nor write access in any mode what you intended? It appears
> to be supervisor read/write in the 970 UM.
This is worse actually:
970 says it is super/write and super/read
powerisa 2.03..2.04 say it is hypv/write and super/read.
powerisa 2.05 and newer say it is hypv/write and hypv/read.
I can make it the same as DABR for now and fix this somehow when I'll be
adding H_SET_XDABR, will this be ok?
>> static void gen_spr_970_dbg(CPUPPCState *env)
>> @@ -7784,7 +7789,6 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> gen_spr_book3s_altivec(env);
>> gen_spr_book3s_pmu_hypv(env);
>> gen_spr_book3s_pmu_user(env);
>> - gen_spr_book3s_dbg(env);
>> gen_spr_book3s_common(env);
>>
>> switch (version) {
>> @@ -7827,6 +7831,9 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
>> gen_spr_power8_pmu_user(env);
>> gen_spr_power8_tm(env);
>> }
>> + if (version < BOOK3S_CPU_POWER8) {
>> + gen_spr_book3s_dbg(env);
>> + }
>> #if !defined(CONFIG_USER_ONLY)
>> switch (version) {
>> case BOOK3S_CPU_970:
>>
>
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH v4 28/29] spapr_hcall: Split h_set_mode()
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (26 preceding siblings ...)
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 27/29] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
@ 2014-06-03 9:28 ` Alexey Kardashevskiy
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
28 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This moves H_SET_MODE_RESOURCE_LE handler to a separate function
as there are other "resources" coming and this is going to become ugly.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v2:
* s/becode/become/ in commit log
---
hw/ppc/spapr_hcall.c | 67 +++++++++++++++++++++++++++-------------------------
1 file changed, 35 insertions(+), 32 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index a7460ab..cff3b0f 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -712,46 +712,49 @@ static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr,
return H_SUCCESS;
}
+static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
+ target_ulong mflags,
+ target_ulong value1,
+ target_ulong value2)
+{
+ CPUState *cs;
+
+ if (value1) {
+ return H_P3;
+ }
+ if (value2) {
+ return H_P4;
+ }
+
+ switch (mflags) {
+ case H_SET_MODE_ENDIAN_BIG:
+ CPU_FOREACH(cs) {
+ set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
+ }
+ return H_SUCCESS;
+
+ case H_SET_MODE_ENDIAN_LITTLE:
+ CPU_FOREACH(cs) {
+ set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
+ }
+ return H_SUCCESS;
+ }
+
+ return H_UNSUPPORTED_FLAG;
+}
+
static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
- CPUState *cs;
- target_ulong mflags = args[0];
target_ulong resource = args[1];
- target_ulong value1 = args[2];
- target_ulong value2 = args[3];
target_ulong ret = H_P2;
- if (resource == H_SET_MODE_RESOURCE_LE) {
- if (value1) {
- ret = H_P3;
- goto out;
- }
- if (value2) {
- ret = H_P4;
- goto out;
- }
- switch (mflags) {
- case H_SET_MODE_ENDIAN_BIG:
- CPU_FOREACH(cs) {
- set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
- }
- ret = H_SUCCESS;
- break;
-
- case H_SET_MODE_ENDIAN_LITTLE:
- CPU_FOREACH(cs) {
- set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
- }
- ret = H_SUCCESS;
- break;
-
- default:
- ret = H_UNSUPPORTED_FLAG;
- }
+ switch (resource) {
+ case H_SET_MODE_RESOURCE_LE:
+ ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
+ break;
}
-out:
return ret;
}
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* [Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-06-03 9:27 [Qemu-devel] [PATCH v4 00/29] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
` (27 preceding siblings ...)
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 28/29] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
@ 2014-06-03 9:28 ` Alexey Kardashevskiy
2014-06-03 16:51 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
28 siblings, 1 reply; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 9:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Alexey Kardashevskiy, Tom Musta, qemu-ppc, Alexander Graf
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
This defines AIL flags for LPCR special register.
This changes @excp_prefix according to the mode, takes effect in TCG.
This turns support of a new capability PPC2_ISA207S flag for TCG.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr_hcall.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 5 +++++
target-ppc/cpu.h | 4 +++-
target-ppc/excp_helper.c | 7 +++++--
4 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index cff3b0f..a2941f4 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -743,6 +743,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
return H_UNSUPPORTED_FLAG;
}
+static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
+ target_ulong mflags,
+ target_ulong value1,
+ target_ulong value2)
+{
+ CPUState *cs;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ target_ulong prefix;
+
+ if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
+ return H_P2;
+ }
+ if (value1) {
+ return H_P3;
+ }
+ if (value2) {
+ return H_P4;
+ }
+
+ switch (mflags) {
+ case H_SET_MODE_ADDR_TRANS_NONE:
+ prefix = 0;
+ break;
+ case H_SET_MODE_ADDR_TRANS_0001_8000:
+ prefix = 0x18000;
+ break;
+ case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
+ prefix = 0xC000000000004000;
+ break;
+ default:
+ return H_UNSUPPORTED_FLAG;
+ }
+
+ CPU_FOREACH(cs) {
+ CPUPPCState *env = &POWERPC_CPU(cpu)->env;
+
+ set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
+ env->excp_prefix = prefix;
+ }
+
+ return H_SUCCESS;
+}
+
static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
@@ -753,6 +796,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
case H_SET_MODE_RESOURCE_LE:
ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
break;
+ case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
+ ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0],
+ args[2], args[3]);
+ break;
}
return ret;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 4ffb903..08c301f 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -164,6 +164,11 @@ typedef struct sPAPREnvironment {
#define H_SET_MODE_ENDIAN_BIG 0
#define H_SET_MODE_ENDIAN_LITTLE 1
+/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
+#define H_SET_MODE_ADDR_TRANS_NONE 0
+#define H_SET_MODE_ADDR_TRANS_0001_8000 2
+#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
+
/* VASI States */
#define H_VASI_INVALID 0
#define H_VASI_ENABLED 1
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index e33828a..4a8e0c4 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -467,6 +467,8 @@ struct ppc_slb_t {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
#define LPCR_ILE (1 << (63-38))
+#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
+#define LPCR_AIL_SH (63-40)
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
@@ -2009,7 +2011,7 @@ enum {
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
- PPC2_ALTIVEC_207)
+ PPC2_ALTIVEC_207 | PPC2_ISA207S)
};
/*****************************************************************************/
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index fd89d99..b39bf1b 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -619,8 +619,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
if (asrr1 != -1) {
env->spr[asrr1] = env->spr[srr1];
}
- /* If we disactivated any translation, flush TLBs */
- if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
+
+ if (env->spr[SPR_LPCR] & LPCR_AIL) {
+ new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
+ } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
+ /* If we disactivated any translation, flush TLBs */
tlb_flush(cs, 1);
}
--
2.0.0
^ permalink raw reply related [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-06-03 9:28 ` [Qemu-devel] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
@ 2014-06-03 16:51 ` Greg Kurz
2014-06-03 23:44 ` Alexey Kardashevskiy
0 siblings, 1 reply; 74+ messages in thread
From: Greg Kurz @ 2014-06-03 16:51 UTC (permalink / raw)
To: Alexey Kardashevskiy; +Cc: Tom Musta, qemu-ppc, qemu-devel
On Tue, 3 Jun 2014 19:28:04 +1000
Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>
> This defines AIL flags for LPCR special register.
>
> This changes @excp_prefix according to the mode, takes effect in TCG.
>
> This turns support of a new capability PPC2_ISA207S flag for TCG.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> hw/ppc/spapr_hcall.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/spapr.h | 5 +++++
> target-ppc/cpu.h | 4 +++-
> target-ppc/excp_helper.c | 7 +++++--
> 4 files changed, 60 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index cff3b0f..a2941f4 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -743,6 +743,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
> return H_UNSUPPORTED_FLAG;
> }
>
> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
> + target_ulong mflags,
> + target_ulong value1,
> + target_ulong value2)
> +{
> + CPUState *cs;
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> + target_ulong prefix;
> +
> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
> + return H_P2;
> + }
> + if (value1) {
> + return H_P3;
> + }
> + if (value2) {
> + return H_P4;
> + }
> +
> + switch (mflags) {
> + case H_SET_MODE_ADDR_TRANS_NONE:
> + prefix = 0;
> + break;
> + case H_SET_MODE_ADDR_TRANS_0001_8000:
> + prefix = 0x18000;
> + break;
> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
> + prefix = 0xC000000000004000;
> + break;
> + default:
> + return H_UNSUPPORTED_FLAG;
> + }
> +
> + CPU_FOREACH(cs) {
> + CPUPPCState *env = &POWERPC_CPU(cpu)->env;
> +
> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
> + env->excp_prefix = prefix;
> + }
> +
> + return H_SUCCESS;
> +}
> +
> static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
> target_ulong opcode, target_ulong *args)
> {
> @@ -753,6 +796,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
> case H_SET_MODE_RESOURCE_LE:
> ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
> break;
> + case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
> + ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0],
> + args[2], args[3]);
> + break;
> }
>
> return ret;
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 4ffb903..08c301f 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -164,6 +164,11 @@ typedef struct sPAPREnvironment {
> #define H_SET_MODE_ENDIAN_BIG 0
> #define H_SET_MODE_ENDIAN_LITTLE 1
>
> +/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
> +#define H_SET_MODE_ADDR_TRANS_NONE 0
> +#define H_SET_MODE_ADDR_TRANS_0001_8000 2
> +#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
> +
> /* VASI States */
> #define H_VASI_INVALID 0
> #define H_VASI_ENABLED 1
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index e33828a..4a8e0c4 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -467,6 +467,8 @@ struct ppc_slb_t {
> #define MSR_LE 0 /* Little-endian mode 1 hflags */
>
> #define LPCR_ILE (1 << (63-38))
> +#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
> +#define LPCR_AIL_SH (63-40)
>
You seem to have missed (or disgarded) a comment on your previous post
about magic numbers. Also FWIW most of the bit shifts in this file have
the _SHIFT suffix in their name:
#define LPCR_AIL_SHIFT (63-40)
#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
> #define msr_sf ((env->msr >> MSR_SF) & 1)
> #define msr_isf ((env->msr >> MSR_ISF) & 1)
> @@ -2009,7 +2011,7 @@ enum {
> PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
> PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
> - PPC2_ALTIVEC_207)
> + PPC2_ALTIVEC_207 | PPC2_ISA207S)
> };
>
> /*****************************************************************************/
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index fd89d99..b39bf1b 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -619,8 +619,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> if (asrr1 != -1) {
> env->spr[asrr1] = env->spr[srr1];
> }
> - /* If we disactivated any translation, flush TLBs */
> - if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> +
> + if (env->spr[SPR_LPCR] & LPCR_AIL) {
> + new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
> + } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> + /* If we disactivated any translation, flush TLBs */
> tlb_flush(cs, 1);
> }
>
--
Gregory Kurz kurzgreg@fr.ibm.com
gkurz@linux.vnet.ibm.com
Software Engineer @ IBM/Meiosys http://www.ibm.com
Tel +33 (0)562 165 496
"Anarchy is about taking complete responsibility for yourself."
Alan Moore.
^ permalink raw reply [flat|nested] 74+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 29/29] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
2014-06-03 16:51 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
@ 2014-06-03 23:44 ` Alexey Kardashevskiy
0 siblings, 0 replies; 74+ messages in thread
From: Alexey Kardashevskiy @ 2014-06-03 23:44 UTC (permalink / raw)
To: Greg Kurz; +Cc: Tom Musta, qemu-ppc, qemu-devel
On 06/04/2014 02:51 AM, Greg Kurz wrote:
> On Tue, 3 Jun 2014 19:28:04 +1000
> Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
>
>> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
>> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>>
>> This defines AIL flags for LPCR special register.
>>
>> This changes @excp_prefix according to the mode, takes effect in TCG.
>>
>> This turns support of a new capability PPC2_ISA207S flag for TCG.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>> ---
>> hw/ppc/spapr_hcall.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/spapr.h | 5 +++++
>> target-ppc/cpu.h | 4 +++-
>> target-ppc/excp_helper.c | 7 +++++--
>> 4 files changed, 60 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
>> index cff3b0f..a2941f4 100644
>> --- a/hw/ppc/spapr_hcall.c
>> +++ b/hw/ppc/spapr_hcall.c
>> @@ -743,6 +743,49 @@ static target_ulong h_set_mode_resouce_le(PowerPCCPU *cpu,
>> return H_UNSUPPORTED_FLAG;
>> }
>>
>> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
>> + target_ulong mflags,
>> + target_ulong value1,
>> + target_ulong value2)
>> +{
>> + CPUState *cs;
>> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>> + target_ulong prefix;
>> +
>> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
>> + return H_P2;
>> + }
>> + if (value1) {
>> + return H_P3;
>> + }
>> + if (value2) {
>> + return H_P4;
>> + }
>> +
>> + switch (mflags) {
>> + case H_SET_MODE_ADDR_TRANS_NONE:
>> + prefix = 0;
>> + break;
>> + case H_SET_MODE_ADDR_TRANS_0001_8000:
>> + prefix = 0x18000;
>> + break;
>> + case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
>> + prefix = 0xC000000000004000;
>> + break;
>> + default:
>> + return H_UNSUPPORTED_FLAG;
>> + }
>> +
>> + CPU_FOREACH(cs) {
>> + CPUPPCState *env = &POWERPC_CPU(cpu)->env;
>> +
>> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
>> + env->excp_prefix = prefix;
>> + }
>> +
>> + return H_SUCCESS;
>> +}
>> +
>> static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
>> target_ulong opcode, target_ulong *args)
>> {
>> @@ -753,6 +796,10 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
>> case H_SET_MODE_RESOURCE_LE:
>> ret = h_set_mode_resouce_le(cpu, args[0], args[2], args[3]);
>> break;
>> + case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
>> + ret = h_set_mode_resouce_addr_trans_mode(cpu, args[0],
>> + args[2], args[3]);
>> + break;
>> }
>>
>> return ret;
>> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
>> index 4ffb903..08c301f 100644
>> --- a/include/hw/ppc/spapr.h
>> +++ b/include/hw/ppc/spapr.h
>> @@ -164,6 +164,11 @@ typedef struct sPAPREnvironment {
>> #define H_SET_MODE_ENDIAN_BIG 0
>> #define H_SET_MODE_ENDIAN_LITTLE 1
>>
>> +/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
>> +#define H_SET_MODE_ADDR_TRANS_NONE 0
>> +#define H_SET_MODE_ADDR_TRANS_0001_8000 2
>> +#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
>> +
>> /* VASI States */
>> #define H_VASI_INVALID 0
>> #define H_VASI_ENABLED 1
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index e33828a..4a8e0c4 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -467,6 +467,8 @@ struct ppc_slb_t {
>> #define MSR_LE 0 /* Little-endian mode 1 hflags */
>>
>> #define LPCR_ILE (1 << (63-38))
>> +#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
>> +#define LPCR_AIL_SH (63-40)
>>
>
> You seem to have missed (or disgarded) a comment on your previous post
> about magic numbers. Also FWIW most of the bit shifts in this file have
> the _SHIFT suffix in their name:
I simply forgot it :( Thanks for the reminder, v5 is coming.
> #define LPCR_AIL_SHIFT (63-40)
> #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
>
>> #define msr_sf ((env->msr >> MSR_SF) & 1)
>> #define msr_isf ((env->msr >> MSR_ISF) & 1)
>> @@ -2009,7 +2011,7 @@ enum {
>> PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
>> PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
>> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
>> - PPC2_ALTIVEC_207)
>> + PPC2_ALTIVEC_207 | PPC2_ISA207S)
>> };
>>
>> /*****************************************************************************/
>> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
>> index fd89d99..b39bf1b 100644
>> --- a/target-ppc/excp_helper.c
>> +++ b/target-ppc/excp_helper.c
>> @@ -619,8 +619,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>> if (asrr1 != -1) {
>> env->spr[asrr1] = env->spr[srr1];
>> }
>> - /* If we disactivated any translation, flush TLBs */
>> - if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
>> +
>> + if (env->spr[SPR_LPCR] & LPCR_AIL) {
>> + new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
>> + } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
>> + /* If we disactivated any translation, flush TLBs */
>> tlb_flush(cs, 1);
>> }
>>
>
>
>
--
Alexey
^ permalink raw reply [flat|nested] 74+ messages in thread