* [PATCH v5 01/21] xen/arm: move io.h as mmio.h to include folder
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-17 11:52 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 02/21] xen/arm: make mmio handlers domain specific vijay.kilari
` (21 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
io.h is local to arch/arm folder. move this file as mmio.h
file to include/asm-arm folder as it might be
required for inclusion in other header files in future.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
xen/arch/arm/io.c | 3 +--
xen/arch/arm/traps.c | 2 +-
xen/arch/arm/vgic.c | 2 +-
xen/arch/arm/vuart.c | 2 +-
xen/{arch/arm/io.h => include/asm-arm/mmio.h} | 8 ++++----
5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c
index a6db00b..ada1918 100644
--- a/xen/arch/arm/io.c
+++ b/xen/arch/arm/io.c
@@ -19,8 +19,7 @@
#include <xen/config.h>
#include <xen/lib.h>
#include <asm/current.h>
-
-#include "io.h"
+#include <asm/mmio.h>
static const struct mmio_handler *const mmio_handlers[] =
{
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index a4bdaaa..9348147 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -36,9 +36,9 @@
#include <asm/regs.h>
#include <asm/cpregs.h>
#include <asm/psci.h>
+#include <asm/mmio.h>
#include "decode.h"
-#include "io.h"
#include "vtimer.h"
#include <asm/gic.h>
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 4869b87..4962e70 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -27,7 +27,7 @@
#include <asm/current.h>
-#include "io.h"
+#include <asm/mmio.h>
#include <asm/gic.h>
#define REG(n) (n/4)
diff --git a/xen/arch/arm/vuart.c b/xen/arch/arm/vuart.c
index c02a8a9..953cd46 100644
--- a/xen/arch/arm/vuart.c
+++ b/xen/arch/arm/vuart.c
@@ -38,9 +38,9 @@
#include <xen/errno.h>
#include <xen/ctype.h>
#include <xen/serial.h>
+#include <asm/mmio.h>
#include "vuart.h"
-#include "io.h"
#define domain_has_vuart(d) ((d)->arch.vuart.info != NULL)
diff --git a/xen/arch/arm/io.h b/xen/include/asm-arm/mmio.h
similarity index 91%
rename from xen/arch/arm/io.h
rename to xen/include/asm-arm/mmio.h
index 8d252c0..5870985 100644
--- a/xen/arch/arm/io.h
+++ b/xen/include/asm-arm/mmio.h
@@ -1,5 +1,5 @@
/*
- * xen/arch/arm/io.h
+ * xen/include/asm-arm/mmio.h
*
* ARM I/O handlers
*
@@ -16,8 +16,8 @@
* GNU General Public License for more details.
*/
-#ifndef __ARCH_ARM_IO_H__
-#define __ARCH_ARM_IO_H__
+#ifndef __ASM_ARM_MMIO_H__
+#define __ASM_ARM_MMIO_H__
#include <xen/lib.h>
#include <asm/processor.h>
@@ -45,7 +45,7 @@ extern const struct mmio_handler vuart_mmio_handler;
extern int handle_mmio(mmio_info_t *info);
-#endif
+#endif /* __ASM_ARM_MMIO_H__ */
/*
* Local variables:
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 01/21] xen/arm: move io.h as mmio.h to include folder
2014-06-12 13:36 ` [PATCH v5 01/21] xen/arm: move io.h as mmio.h to include folder vijay.kilari
@ 2014-06-17 11:52 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 11:52 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> io.h is local to arch/arm folder. move this file as mmio.h
> file to include/asm-arm folder as it might be
> required for inclusion in other header files in future.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>
> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 02/21] xen/arm: make mmio handlers domain specific
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
2014-06-12 13:36 ` [PATCH v5 01/21] xen/arm: move io.h as mmio.h to include folder vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 16:07 ` Stefano Stabellini
` (2 more replies)
2014-06-12 13:36 ` [PATCH v5 03/21] xen/arm: make sgi handling generic vijay.kilari
` (20 subsequent siblings)
22 siblings, 3 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
register mmio handlers at runtime and make mmio handlers
domain specific and check handlers are removed.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/domain.c | 3 +++
xen/arch/arm/io.c | 56 +++++++++++++++++++++++++++++++++---------
xen/arch/arm/vgic.c | 28 +++++++++++----------
xen/arch/arm/vuart.c | 26 +++++++++-----------
xen/include/asm-arm/domain.h | 2 ++
xen/include/asm-arm/mmio.h | 22 ++++++++++++++---
6 files changed, 94 insertions(+), 43 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index e2ada12..43a2c6f 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -508,6 +508,9 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags)
share_xen_page_with_guest(
virt_to_page(d->shared_info), d, XENSHARE_writable);
+ if ( (rc = domain_io_init(d)) != 0 )
+ goto fail;
+
if ( (rc = p2m_alloc_table(d)) != 0 )
goto fail;
diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c
index ada1918..8e55d49 100644
--- a/xen/arch/arm/io.c
+++ b/xen/arch/arm/io.c
@@ -1,5 +1,5 @@
/*
- * xen/arch/arm/io.h
+ * xen/arch/arm/io.c
*
* ARM I/O handlers
*
@@ -18,29 +18,61 @@
#include <xen/config.h>
#include <xen/lib.h>
+#include <xen/spinlock.h>
+#include <xen/sched.h>
#include <asm/current.h>
#include <asm/mmio.h>
-static const struct mmio_handler *const mmio_handlers[] =
-{
- &vgic_distr_mmio_handler,
- &vuart_mmio_handler,
-};
-#define MMIO_HANDLER_NR ARRAY_SIZE(mmio_handlers)
-
int handle_mmio(mmio_info_t *info)
{
struct vcpu *v = current;
int i;
+ const struct mmio_handler *mmio_handler;
+ const struct io_handler *io_handlers = &v->domain->arch.io_handlers;
- for ( i = 0; i < MMIO_HANDLER_NR; i++ )
- if ( mmio_handlers[i]->check_handler(v, info->gpa) )
+ for ( i = 0; i < io_handlers->num_entries; i++ )
+ {
+ mmio_handler = &io_handlers->mmio_handlers[i];
+
+ if ( (info->gpa >= mmio_handler->addr) &&
+ (info->gpa < (mmio_handler->addr + mmio_handler->size)) )
+ {
return info->dabt.write ?
- mmio_handlers[i]->write_handler(v, info) :
- mmio_handlers[i]->read_handler(v, info);
+ mmio_handler->mmio_handler_ops->write_handler(v, info) :
+ mmio_handler->mmio_handler_ops->read_handler(v, info);
+ }
+ }
return 0;
}
+
+void register_mmio_handler(struct domain *d,
+ const struct mmio_handler_ops *handle,
+ paddr_t addr, paddr_t size)
+{
+ struct io_handler *handler = &d->arch.io_handlers;
+
+ BUG_ON(handler->num_entries >= MAX_IO_HANDLER);
+
+ spin_lock(&handler->lock);
+
+ handler->mmio_handlers[handler->num_entries].mmio_handler_ops = handle;
+ handler->mmio_handlers[handler->num_entries].addr = addr;
+ handler->mmio_handlers[handler->num_entries].size = size;
+ dsb(ish);
+ handler->num_entries++;
+
+ spin_unlock(&handler->lock);
+}
+
+int domain_io_init(struct domain *d)
+{
+ spin_lock_init(&d->arch.io_handlers.lock);
+ d->arch.io_handlers.num_entries = 0;
+
+ return 0;
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 4962e70..2949948 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -35,6 +35,9 @@
/* Number of ranks of interrupt registers for a domain */
#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
+static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
+static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
+
/*
* Rank containing GICD_<FOO><n> for GICD_<FOO> with
* <b>-bits-per-interrupt
@@ -73,6 +76,11 @@ static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
return NULL;
}
+const struct mmio_handler_ops vgic_distr_mmio_handler = {
+ .read_handler = vgic_distr_mmio_read,
+ .write_handler = vgic_distr_mmio_write,
+};
+
int domain_vgic_init(struct domain *d)
{
int i;
@@ -107,6 +115,13 @@ int domain_vgic_init(struct domain *d)
}
for (i=0; i<DOMAIN_NR_RANKS(d); i++)
spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
+
+ /*
+ * We rely on gicv_setup() to initialize dbase(vGIC distributor base)
+ */
+ register_mmio_handler(d, &vgic_distr_mmio_handler,
+ d->arch.vgic.dbase, PAGE_SIZE);
+
return 0;
}
@@ -676,19 +691,6 @@ write_ignore:
return 1;
}
-static int vgic_distr_mmio_check(struct vcpu *v, paddr_t addr)
-{
- struct domain *d = v->domain;
-
- return (addr >= (d->arch.vgic.dbase)) && (addr < (d->arch.vgic.dbase + PAGE_SIZE));
-}
-
-const struct mmio_handler vgic_distr_mmio_handler = {
- .check_handler = vgic_distr_mmio_check,
- .read_handler = vgic_distr_mmio_read,
- .write_handler = vgic_distr_mmio_write,
-};
-
struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq)
{
struct pending_irq *n;
diff --git a/xen/arch/arm/vuart.c b/xen/arch/arm/vuart.c
index 953cd46..a9106e6 100644
--- a/xen/arch/arm/vuart.c
+++ b/xen/arch/arm/vuart.c
@@ -44,6 +44,14 @@
#define domain_has_vuart(d) ((d)->arch.vuart.info != NULL)
+static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info);
+static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info);
+
+const struct mmio_handler_ops vuart_mmio_handler = {
+ .read_handler = vuart_mmio_read,
+ .write_handler = vuart_mmio_write,
+};
+
int domain_vuart_init(struct domain *d)
{
ASSERT( is_hardware_domain(d) );
@@ -59,6 +67,10 @@ int domain_vuart_init(struct domain *d)
if ( !d->arch.vuart.buf )
return -ENOMEM;
+ register_mmio_handler(d, &vuart_mmio_handler,
+ d->arch.vuart.info->base_addr,
+ d->arch.vuart.info->size);
+
return 0;
}
@@ -92,14 +104,6 @@ static void vuart_print_char(struct vcpu *v, char c)
spin_unlock(&uart->lock);
}
-static int vuart_mmio_check(struct vcpu *v, paddr_t addr)
-{
- const struct vuart_info *info = v->domain->arch.vuart.info;
-
- return (domain_has_vuart(v->domain) && addr >= info->base_addr &&
- addr <= (info->base_addr + info->size));
-}
-
static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info)
{
struct domain *d = v->domain;
@@ -133,12 +137,6 @@ static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info)
return 1;
}
-const struct mmio_handler vuart_mmio_handler = {
- .check_handler = vuart_mmio_check,
- .read_handler = vuart_mmio_read,
- .write_handler = vuart_mmio_write,
-};
-
/*
* Local variables:
* mode: C
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 9ef6b26..36d82e2 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -7,6 +7,7 @@
#include <asm/page.h>
#include <asm/p2m.h>
#include <asm/vfp.h>
+#include <asm/mmio.h>
#include <public/hvm/params.h>
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
@@ -119,6 +120,7 @@ struct arch_domain
struct hvm_domain hvm_domain;
xen_pfn_t *grant_table_gpfn;
+ struct io_handler io_handlers;
/* Continuable domain_relinquish_resources(). */
enum {
RELMEM_not_started,
diff --git a/xen/include/asm-arm/mmio.h b/xen/include/asm-arm/mmio.h
index 5870985..0160f09 100644
--- a/xen/include/asm-arm/mmio.h
+++ b/xen/include/asm-arm/mmio.h
@@ -23,6 +23,8 @@
#include <asm/processor.h>
#include <asm/regs.h>
+#define MAX_IO_HANDLER 16
+
typedef struct
{
struct hsr_dabt dabt;
@@ -34,16 +36,28 @@ typedef int (*mmio_read_t)(struct vcpu *v, mmio_info_t *info);
typedef int (*mmio_write_t)(struct vcpu *v, mmio_info_t *info);
typedef int (*mmio_check_t)(struct vcpu *v, paddr_t addr);
-struct mmio_handler {
- mmio_check_t check_handler;
+struct mmio_handler_ops {
mmio_read_t read_handler;
mmio_write_t write_handler;
};
-extern const struct mmio_handler vgic_distr_mmio_handler;
-extern const struct mmio_handler vuart_mmio_handler;
+struct mmio_handler {
+ paddr_t addr;
+ paddr_t size;
+ const struct mmio_handler_ops *mmio_handler_ops;
+};
+
+struct io_handler {
+ int num_entries;
+ spinlock_t lock;
+ struct mmio_handler mmio_handlers[MAX_IO_HANDLER];
+};
extern int handle_mmio(mmio_info_t *info);
+void register_mmio_handler(struct domain *d,
+ const struct mmio_handler_ops *handle,
+ paddr_t addr, paddr_t size);
+int domain_io_init(struct domain *d);
#endif /* __ASM_ARM_MMIO_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 02/21] xen/arm: make mmio handlers domain specific
2014-06-12 13:36 ` [PATCH v5 02/21] xen/arm: make mmio handlers domain specific vijay.kilari
@ 2014-06-12 16:07 ` Stefano Stabellini
2014-06-12 22:19 ` Julien Grall
2014-06-17 11:53 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 16:07 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> register mmio handlers at runtime and make mmio handlers
> domain specific and check handlers are removed.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> xen/arch/arm/domain.c | 3 +++
> xen/arch/arm/io.c | 56 +++++++++++++++++++++++++++++++++---------
> xen/arch/arm/vgic.c | 28 +++++++++++----------
> xen/arch/arm/vuart.c | 26 +++++++++-----------
> xen/include/asm-arm/domain.h | 2 ++
> xen/include/asm-arm/mmio.h | 22 ++++++++++++++---
> 6 files changed, 94 insertions(+), 43 deletions(-)
>
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index e2ada12..43a2c6f 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -508,6 +508,9 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags)
> share_xen_page_with_guest(
> virt_to_page(d->shared_info), d, XENSHARE_writable);
>
> + if ( (rc = domain_io_init(d)) != 0 )
> + goto fail;
> +
> if ( (rc = p2m_alloc_table(d)) != 0 )
> goto fail;
>
> diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c
> index ada1918..8e55d49 100644
> --- a/xen/arch/arm/io.c
> +++ b/xen/arch/arm/io.c
> @@ -1,5 +1,5 @@
> /*
> - * xen/arch/arm/io.h
> + * xen/arch/arm/io.c
> *
> * ARM I/O handlers
> *
> @@ -18,29 +18,61 @@
>
> #include <xen/config.h>
> #include <xen/lib.h>
> +#include <xen/spinlock.h>
> +#include <xen/sched.h>
> #include <asm/current.h>
> #include <asm/mmio.h>
>
> -static const struct mmio_handler *const mmio_handlers[] =
> -{
> - &vgic_distr_mmio_handler,
> - &vuart_mmio_handler,
> -};
> -#define MMIO_HANDLER_NR ARRAY_SIZE(mmio_handlers)
> -
> int handle_mmio(mmio_info_t *info)
> {
> struct vcpu *v = current;
> int i;
> + const struct mmio_handler *mmio_handler;
> + const struct io_handler *io_handlers = &v->domain->arch.io_handlers;
>
> - for ( i = 0; i < MMIO_HANDLER_NR; i++ )
> - if ( mmio_handlers[i]->check_handler(v, info->gpa) )
> + for ( i = 0; i < io_handlers->num_entries; i++ )
> + {
> + mmio_handler = &io_handlers->mmio_handlers[i];
> +
> + if ( (info->gpa >= mmio_handler->addr) &&
> + (info->gpa < (mmio_handler->addr + mmio_handler->size)) )
> + {
> return info->dabt.write ?
> - mmio_handlers[i]->write_handler(v, info) :
> - mmio_handlers[i]->read_handler(v, info);
> + mmio_handler->mmio_handler_ops->write_handler(v, info) :
> + mmio_handler->mmio_handler_ops->read_handler(v, info);
> + }
> + }
>
> return 0;
> }
> +
> +void register_mmio_handler(struct domain *d,
> + const struct mmio_handler_ops *handle,
> + paddr_t addr, paddr_t size)
> +{
> + struct io_handler *handler = &d->arch.io_handlers;
> +
> + BUG_ON(handler->num_entries >= MAX_IO_HANDLER);
> +
> + spin_lock(&handler->lock);
> +
> + handler->mmio_handlers[handler->num_entries].mmio_handler_ops = handle;
> + handler->mmio_handlers[handler->num_entries].addr = addr;
> + handler->mmio_handlers[handler->num_entries].size = size;
> + dsb(ish);
> + handler->num_entries++;
> +
> + spin_unlock(&handler->lock);
> +}
> +
> +int domain_io_init(struct domain *d)
> +{
> + spin_lock_init(&d->arch.io_handlers.lock);
> + d->arch.io_handlers.num_entries = 0;
> +
> + return 0;
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 4962e70..2949948 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -35,6 +35,9 @@
> /* Number of ranks of interrupt registers for a domain */
> #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
>
> +static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
> +static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
> +
> /*
> * Rank containing GICD_<FOO><n> for GICD_<FOO> with
> * <b>-bits-per-interrupt
> @@ -73,6 +76,11 @@ static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
> return NULL;
> }
>
> +const struct mmio_handler_ops vgic_distr_mmio_handler = {
> + .read_handler = vgic_distr_mmio_read,
> + .write_handler = vgic_distr_mmio_write,
> +};
> +
> int domain_vgic_init(struct domain *d)
> {
> int i;
> @@ -107,6 +115,13 @@ int domain_vgic_init(struct domain *d)
> }
> for (i=0; i<DOMAIN_NR_RANKS(d); i++)
> spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
> +
> + /*
> + * We rely on gicv_setup() to initialize dbase(vGIC distributor base)
> + */
> + register_mmio_handler(d, &vgic_distr_mmio_handler,
> + d->arch.vgic.dbase, PAGE_SIZE);
> +
> return 0;
> }
>
> @@ -676,19 +691,6 @@ write_ignore:
> return 1;
> }
>
> -static int vgic_distr_mmio_check(struct vcpu *v, paddr_t addr)
> -{
> - struct domain *d = v->domain;
> -
> - return (addr >= (d->arch.vgic.dbase)) && (addr < (d->arch.vgic.dbase + PAGE_SIZE));
> -}
> -
> -const struct mmio_handler vgic_distr_mmio_handler = {
> - .check_handler = vgic_distr_mmio_check,
> - .read_handler = vgic_distr_mmio_read,
> - .write_handler = vgic_distr_mmio_write,
> -};
> -
> struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq)
> {
> struct pending_irq *n;
> diff --git a/xen/arch/arm/vuart.c b/xen/arch/arm/vuart.c
> index 953cd46..a9106e6 100644
> --- a/xen/arch/arm/vuart.c
> +++ b/xen/arch/arm/vuart.c
> @@ -44,6 +44,14 @@
>
> #define domain_has_vuart(d) ((d)->arch.vuart.info != NULL)
>
> +static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info);
> +static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info);
> +
> +const struct mmio_handler_ops vuart_mmio_handler = {
> + .read_handler = vuart_mmio_read,
> + .write_handler = vuart_mmio_write,
> +};
> +
> int domain_vuart_init(struct domain *d)
> {
> ASSERT( is_hardware_domain(d) );
> @@ -59,6 +67,10 @@ int domain_vuart_init(struct domain *d)
> if ( !d->arch.vuart.buf )
> return -ENOMEM;
>
> + register_mmio_handler(d, &vuart_mmio_handler,
> + d->arch.vuart.info->base_addr,
> + d->arch.vuart.info->size);
> +
> return 0;
> }
>
> @@ -92,14 +104,6 @@ static void vuart_print_char(struct vcpu *v, char c)
> spin_unlock(&uart->lock);
> }
>
> -static int vuart_mmio_check(struct vcpu *v, paddr_t addr)
> -{
> - const struct vuart_info *info = v->domain->arch.vuart.info;
> -
> - return (domain_has_vuart(v->domain) && addr >= info->base_addr &&
> - addr <= (info->base_addr + info->size));
> -}
> -
> static int vuart_mmio_read(struct vcpu *v, mmio_info_t *info)
> {
> struct domain *d = v->domain;
> @@ -133,12 +137,6 @@ static int vuart_mmio_write(struct vcpu *v, mmio_info_t *info)
> return 1;
> }
>
> -const struct mmio_handler vuart_mmio_handler = {
> - .check_handler = vuart_mmio_check,
> - .read_handler = vuart_mmio_read,
> - .write_handler = vuart_mmio_write,
> -};
> -
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> index 9ef6b26..36d82e2 100644
> --- a/xen/include/asm-arm/domain.h
> +++ b/xen/include/asm-arm/domain.h
> @@ -7,6 +7,7 @@
> #include <asm/page.h>
> #include <asm/p2m.h>
> #include <asm/vfp.h>
> +#include <asm/mmio.h>
> #include <public/hvm/params.h>
> #include <xen/serial.h>
> #include <xen/hvm/iommu.h>
> @@ -119,6 +120,7 @@ struct arch_domain
> struct hvm_domain hvm_domain;
> xen_pfn_t *grant_table_gpfn;
>
> + struct io_handler io_handlers;
> /* Continuable domain_relinquish_resources(). */
> enum {
> RELMEM_not_started,
> diff --git a/xen/include/asm-arm/mmio.h b/xen/include/asm-arm/mmio.h
> index 5870985..0160f09 100644
> --- a/xen/include/asm-arm/mmio.h
> +++ b/xen/include/asm-arm/mmio.h
> @@ -23,6 +23,8 @@
> #include <asm/processor.h>
> #include <asm/regs.h>
>
> +#define MAX_IO_HANDLER 16
> +
> typedef struct
> {
> struct hsr_dabt dabt;
> @@ -34,16 +36,28 @@ typedef int (*mmio_read_t)(struct vcpu *v, mmio_info_t *info);
> typedef int (*mmio_write_t)(struct vcpu *v, mmio_info_t *info);
> typedef int (*mmio_check_t)(struct vcpu *v, paddr_t addr);
>
> -struct mmio_handler {
> - mmio_check_t check_handler;
> +struct mmio_handler_ops {
> mmio_read_t read_handler;
> mmio_write_t write_handler;
> };
>
> -extern const struct mmio_handler vgic_distr_mmio_handler;
> -extern const struct mmio_handler vuart_mmio_handler;
> +struct mmio_handler {
> + paddr_t addr;
> + paddr_t size;
> + const struct mmio_handler_ops *mmio_handler_ops;
> +};
> +
> +struct io_handler {
> + int num_entries;
> + spinlock_t lock;
> + struct mmio_handler mmio_handlers[MAX_IO_HANDLER];
> +};
>
> extern int handle_mmio(mmio_info_t *info);
> +void register_mmio_handler(struct domain *d,
> + const struct mmio_handler_ops *handle,
> + paddr_t addr, paddr_t size);
> +int domain_io_init(struct domain *d);
>
> #endif /* __ASM_ARM_MMIO_H__ */
>
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 02/21] xen/arm: make mmio handlers domain specific
2014-06-12 13:36 ` [PATCH v5 02/21] xen/arm: make mmio handlers domain specific vijay.kilari
2014-06-12 16:07 ` Stefano Stabellini
@ 2014-06-12 22:19 ` Julien Grall
2014-06-17 11:53 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-12 22:19 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 4962e70..2949948 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
[..]
> +const struct mmio_handler_ops vgic_distr_mmio_handler = {
NIT: This should be static const.
[..]
> diff --git a/xen/arch/arm/vuart.c b/xen/arch/arm/vuart.c
> index 953cd46..a9106e6 100644
> --- a/xen/arch/arm/vuart.c
> +++ b/xen/arch/arm/vuart.c
[..]
> +const struct mmio_handler_ops vuart_mmio_handler = {
Same here.
Assume this 2 changes:
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 02/21] xen/arm: make mmio handlers domain specific
2014-06-12 13:36 ` [PATCH v5 02/21] xen/arm: make mmio handlers domain specific vijay.kilari
2014-06-12 16:07 ` Stefano Stabellini
2014-06-12 22:19 ` Julien Grall
@ 2014-06-17 11:53 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 11:53 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> register mmio handlers at runtime and make mmio handlers
> domain specific and check handlers are removed.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
With Julien's two nits fixed:
Acked-by: Ian Campbell <ian.campbell@citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 03/21] xen/arm: make sgi handling generic
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
2014-06-12 13:36 ` [PATCH v5 01/21] xen/arm: move io.h as mmio.h to include folder vijay.kilari
2014-06-12 13:36 ` [PATCH v5 02/21] xen/arm: make mmio handlers domain specific vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-17 11:52 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 04/21] xen/arm: remove unused parameter in do_sgi call vijay.kilari
` (19 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
move all the hw specific sgi handling functionality
to one function and use it.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
xen/arch/arm/gic.c | 37 ++++++++++++++++++++++++++++---------
xen/include/asm-arm/gic.h | 8 ++++++++
2 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index efcd785..8c198ef 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -483,21 +483,40 @@ void __init gic_init(void)
spin_unlock(&gic.lock);
}
-void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
+static void send_SGI(const cpumask_t *cpu_mask, enum gic_sgi sgi,
+ enum gic_sgi_mode irqmode)
{
unsigned int mask = 0;
+
+ switch ( irqmode )
+ {
+ case SGI_TARGET_OTHERS:
+ GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS | sgi;
+ break;
+ case SGI_TARGET_SELF:
+ GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF | sgi;
+ break;
+ case SGI_TARGET_LIST:
+ mask = gic_cpu_mask(cpu_mask);
+ GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST |
+ (mask << GICD_SGI_TARGET_SHIFT) | sgi;
+ break;
+ default:
+ BUG();
+ }
+}
+
+void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
+{
cpumask_t online_mask;
ASSERT(sgi < 16); /* There are only 16 SGIs */
cpumask_and(&online_mask, cpumask, &cpu_online_map);
- mask = gic_cpu_mask(&online_mask);
dsb(sy);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST
- | (mask<<GICD_SGI_TARGET_SHIFT)
- | sgi;
+ send_SGI(&online_mask, sgi, SGI_TARGET_LIST);
}
void send_SGI_one(unsigned int cpu, enum gic_sgi sgi)
@@ -512,18 +531,18 @@ void send_SGI_self(enum gic_sgi sgi)
dsb(sy);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF
- | sgi;
+ send_SGI(cpumask_of(smp_processor_id()), sgi, SGI_TARGET_SELF);
}
void send_SGI_allbutself(enum gic_sgi sgi)
{
+ cpumask_t all_others_mask;
ASSERT(sgi < 16); /* There are only 16 SGIs */
+ cpumask_andnot(&all_others_mask, &cpu_possible_map, cpumask_of(smp_processor_id()));
dsb(sy);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS
- | sgi;
+ send_SGI(&all_others_mask, sgi, SGI_TARGET_OTHERS);
}
void smp_send_state_dump(unsigned int cpu)
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 8e37ccf..c7b7368 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -210,6 +210,14 @@ enum gic_sgi {
GIC_SGI_DUMP_STATE = 1,
GIC_SGI_CALL_FUNCTION = 2,
};
+
+/* SGI irq mode types */
+enum gic_sgi_mode {
+ SGI_TARGET_LIST,
+ SGI_TARGET_OTHERS,
+ SGI_TARGET_SELF,
+};
+
extern void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi);
extern void send_SGI_one(unsigned int cpu, enum gic_sgi sgi);
extern void send_SGI_self(enum gic_sgi sgi);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 03/21] xen/arm: make sgi handling generic
2014-06-12 13:36 ` [PATCH v5 03/21] xen/arm: make sgi handling generic vijay.kilari
@ 2014-06-17 11:52 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 11:52 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> void send_SGI_allbutself(enum gic_sgi sgi)
> {
> + cpumask_t all_others_mask;
> ASSERT(sgi < 16); /* There are only 16 SGIs */
>
> + cpumask_andnot(&all_others_mask, &cpu_possible_map, cpumask_of(smp_processor_id()));
> dsb(sy);
>
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS
> - | sgi;
> + send_SGI(&all_others_mask, sgi, SGI_TARGET_OTHERS);
What is all_others_mask for here? send_sgi doesn't reference that
argument when SGI_TARGET_OTHERS is used.
Ah, I see Stefano asked in v4 and you explained (hint: when someone has
to ask it often indicates that it is worth explaining in the commit
message next time around). You said:
In GICv2 the mask is not used in some cases. However mask value
is used in GICv3. To make it generic mask value is always
computed.
I think the right answer here is for the gicv3 implementation of
send_SGI to calculate the mask for SGI_TARGET_OTHERS and SGI_TARGET_SELF
internally.
I'd also be inclined to put the mask as the last argument, i..e
static void send_SGI(enum gic_sgi sgi,
enum gic_sgi_mode irqmode,
const cpumask_t *cpu_mask)
That seems like a more natural argument order to me. (i.e. what, where
to, more detailed target when required).
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 04/21] xen/arm: remove unused parameter in do_sgi call
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (2 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 03/21] xen/arm: make sgi handling generic vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 13:36 ` [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
` (18 subsequent siblings)
22 siblings, 0 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
othercpu parameter in do_sgi is unused
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/gic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 8c198ef..ab2777e 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -856,7 +856,7 @@ void gic_inject(void)
}
-static void do_sgi(struct cpu_user_regs *regs, int othercpu, enum gic_sgi sgi)
+static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
{
/* Lower the priority */
GICC[GICC_EOIR] = sgi;
@@ -900,8 +900,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
}
else if (unlikely(irq < 16))
{
- unsigned int cpu = (intack & GICC_IA_CPU_MASK) >> GICC_IA_CPU_SHIFT;
- do_sgi(regs, cpu, irq);
+ do_sgi(regs, irq);
}
else
{
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (3 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 04/21] xen/arm: remove unused parameter in do_sgi call vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 16:11 ` Stefano Stabellini
` (3 more replies)
2014-06-12 13:36 ` [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality vijay.kilari
` (17 subsequent siblings)
22 siblings, 4 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
gic-v2 driver uses fixmap to map the registers.
Instead use ioremap to access mmio registers.
With this patch, gic-v2 register definitions are updated
to use obsolute offset address instead of dividing the
register offset by 4.
Update vgic driver logic to compute using obsolute register
address offsets
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/gic.c | 154 +++++++++++++++++++++++++--------------------
xen/arch/arm/vgic.c | 15 +++--
xen/include/asm-arm/gic.h | 104 +++++++++++++++---------------
3 files changed, 145 insertions(+), 128 deletions(-)
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index ab2777e..8775629 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -31,20 +31,23 @@
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
-
+#include <asm/io.h>
#include <asm/gic.h>
-/* Access to the GIC Distributor registers through the fixmap */
-#define GICD ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICD))
-#define GICC ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICC1))
-#define GICH ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICH))
+#define GICD (gic.map_dbase)
+#define GICC (gic.map_cbase)
+#define GICH (gic.map_hbase)
+
static void gic_restore_pending_irqs(struct vcpu *v);
/* Global state */
static struct {
paddr_t dbase; /* Address of distributor registers */
+ void __iomem * map_dbase; /* IO mapped Address of distributor registers */
paddr_t cbase; /* Address of CPU interface registers */
+ void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
paddr_t hbase; /* Address of virtual interface registers */
+ void __iomem * map_hbase; /* IO Address of virtual interface registers */
paddr_t vbase; /* Address of virtual cpu interface registers */
unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
unsigned int maintenance_irq; /* IRQ maintenance */
@@ -101,12 +104,12 @@ void gic_save_state(struct vcpu *v)
* accessed simultaneously by another pCPU.
*/
for ( i=0; i<nr_lrs; i++)
- v->arch.gic_lr[i] = GICH[GICH_LR + i];
+ v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
v->arch.lr_mask = this_cpu(lr_mask);
- v->arch.gic_apr = GICH[GICH_APR];
- v->arch.gic_vmcr = GICH[GICH_VMCR];
+ v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
+ v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
/* Disable until next VCPU scheduled */
- GICH[GICH_HCR] = 0;
+ writel_relaxed(0, GICH + GICH_HCR);
isb();
}
@@ -120,10 +123,10 @@ void gic_restore_state(struct vcpu *v)
this_cpu(lr_mask) = v->arch.lr_mask;
for ( i=0; i<nr_lrs; i++)
- GICH[GICH_LR + i] = v->arch.gic_lr[i];
- GICH[GICH_APR] = v->arch.gic_apr;
- GICH[GICH_VMCR] = v->arch.gic_vmcr;
- GICH[GICH_HCR] = GICH_HCR_EN;
+ writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
+ writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
+ writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
+ writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
isb();
gic_restore_pending_irqs(v);
@@ -139,8 +142,7 @@ static void gic_irq_enable(struct irq_desc *desc)
spin_lock_irqsave(&gic.lock, flags);
desc->status &= ~IRQ_DISABLED;
dsb(sy);
- /* Enable routing */
- GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32));
+ writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
spin_unlock_irqrestore(&gic.lock, flags);
}
@@ -153,7 +155,7 @@ static void gic_irq_disable(struct irq_desc *desc)
spin_lock_irqsave(&gic.lock, flags);
/* Disable routing */
- GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32));
+ writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
desc->status |= IRQ_DISABLED;
spin_unlock_irqrestore(&gic.lock, flags);
}
@@ -179,16 +181,16 @@ static void gic_host_irq_end(struct irq_desc *desc)
{
int irq = desc->irq;
/* Lower the priority */
- GICC[GICC_EOIR] = irq;
+ writel_relaxed(irq, GICC + GICC_EOIR);
/* Deactivate */
- GICC[GICC_DIR] = irq;
+ writel_relaxed(irq, GICC + GICC_DIR);
}
static void gic_guest_irq_end(struct irq_desc *desc)
{
int irq = desc->irq;
/* Lower the priority of the IRQ */
- GICC[GICC_EOIR] = irq;
+ writel_relaxed(irq, GICC + GICC_EOIR);
/* Deactivation happens in maintenance interrupt / via GICV */
}
@@ -243,13 +245,13 @@ static void gic_set_irq_properties(struct irq_desc *desc,
mask = gic_cpu_mask(cpu_mask);
/* Set edge / level */
- cfg = GICD[GICD_ICFGR + irq / 16];
+ cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
edgebit = 2u << (2 * (irq % 16));
if ( type & DT_IRQ_TYPE_LEVEL_MASK )
cfg &= ~edgebit;
else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
cfg |= edgebit;
- GICD[GICD_ICFGR + irq / 16] = cfg;
+ writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
/* Set target CPU mask (RAZ/WI on uniprocessor) */
bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
@@ -303,87 +305,94 @@ static void __init gic_dist_init(void)
uint32_t cpumask;
int i;
- cpumask = GICD[GICD_ITARGETSR] & 0xff;
+ cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
/* Disable the distributor */
- GICD[GICD_CTLR] = 0;
+ writel_relaxed(0, GICD + GICD_CTLR);
- type = GICD[GICD_TYPER];
+ type = readl_relaxed(GICD + GICD_TYPER);
gic.lines = 32 * ((type & GICD_TYPE_LINES) + 1);
gic.cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
printk("GIC: %d lines, %d cpu%s%s (IID %8.8x).\n",
gic.lines, gic.cpus, (gic.cpus == 1) ? "" : "s",
(type & GICD_TYPE_SEC) ? ", secure" : "",
- GICD[GICD_IIDR]);
+ readl_relaxed(GICD + GICD_IIDR));
/* Default all global IRQs to level, active low */
for ( i = 32; i < gic.lines; i += 16 )
- GICD[GICD_ICFGR + i / 16] = 0x0;
+ writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
/* Route all global IRQs to this CPU */
for ( i = 32; i < gic.lines; i += 4 )
- GICD[GICD_ITARGETSR + i / 4] = cpumask;
+ writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
/* Default priority for global interrupts */
for ( i = 32; i < gic.lines; i += 4 )
- GICD[GICD_IPRIORITYR + i / 4] =
- GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
+ writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
/* Disable all global interrupts */
for ( i = 32; i < gic.lines; i += 32 )
- GICD[GICD_ICENABLER + i / 32] = (uint32_t)~0ul;
+ writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
/* Turn on the distributor */
- GICD[GICD_CTLR] = GICD_CTL_ENABLE;
+ writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
}
static void __cpuinit gic_cpu_init(void)
{
int i;
- this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff;
+ this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
/* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
* even though they are controlled with GICD registers, they must
* be set up here with the other per-cpu state. */
- GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */
- GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */
+ writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
+ writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
+
/* Set SGI priorities */
for (i = 0; i < 16; i += 4)
- GICD[GICD_IPRIORITYR + i / 4] =
- GIC_PRI_IPI<<24 | GIC_PRI_IPI<<16 | GIC_PRI_IPI<<8 | GIC_PRI_IPI;
+ writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
+ GIC_PRI_IPI << 8 | GIC_PRI_IPI,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
/* Set PPI priorities */
for (i = 16; i < 32; i += 4)
- GICD[GICD_IPRIORITYR + i / 4] =
- GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
+ writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
/* Local settings: interface controller */
- GICC[GICC_PMR] = 0xff; /* Don't mask by priority */
- GICC[GICC_BPR] = 0; /* Finest granularity of priority */
- GICC[GICC_CTLR] = GICC_CTL_ENABLE|GICC_CTL_EOI; /* Turn on delivery */
+ /* Don't mask by priority */
+ writel_relaxed(0xff, GICC + GICC_PMR);
+ /* Finest granularity of priority */
+ writel_relaxed(0x0, GICC + GICC_BPR);
+ /* Turn on delivery */
+ writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
}
static void gic_cpu_disable(void)
{
- GICC[GICC_CTLR] = 0;
+ writel_relaxed(0x0, GICC + GICC_CTLR);
}
static void __cpuinit gic_hyp_init(void)
{
uint32_t vtr;
- vtr = GICH[GICH_VTR];
+ vtr = readl_relaxed(GICH + GICH_VTR);
nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
- GICH[GICH_MISR] = GICH_MISR_EOI;
+ writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
this_cpu(lr_mask) = 0ULL;
}
static void __cpuinit gic_hyp_disable(void)
{
- GICH[GICH_HCR] = 0;
+ writel_relaxed(0, GICH + GICH_HCR);
}
int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
@@ -462,15 +471,21 @@ void __init gic_init(void)
(gic.hbase & ~PAGE_MASK) || (gic.vbase & ~PAGE_MASK) )
panic("GIC interfaces not page aligned");
- set_fixmap(FIXMAP_GICD, gic.dbase >> PAGE_SHIFT, DEV_SHARED);
- BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
- FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
- set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
+ gic.map_dbase = ioremap_nocache(gic.dbase, PAGE_SIZE);
+ if ( !gic.map_dbase )
+ panic("Failed to ioremap for GIC distributor\n");
+
if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
+ gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 0x10);
else
- set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
- set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
+ gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 2);
+
+ if ( !gic.map_cbase )
+ panic("Failed to ioremap for GIC CPU interface\n");
+
+ gic.map_hbase = ioremap_nocache(gic.hbase, PAGE_SIZE);
+ if ( !gic.map_hbase )
+ panic("Failed to ioremap for GIC Virtual interface\n");
/* Global settings: interrupt distributor */
spin_lock_init(&gic.lock);
@@ -491,15 +506,16 @@ static void send_SGI(const cpumask_t *cpu_mask, enum gic_sgi sgi,
switch ( irqmode )
{
case SGI_TARGET_OTHERS:
- GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS | sgi;
+ writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
break;
case SGI_TARGET_SELF:
- GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF | sgi;
+ writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
break;
case SGI_TARGET_LIST:
mask = gic_cpu_mask(cpu_mask);
- GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST |
- (mask << GICD_SGI_TARGET_SHIFT) | sgi;
+ writel_relaxed(GICD_SGI_TARGET_LIST |
+ (mask << GICD_SGI_TARGET_SHIFT) | sgi,
+ GICD + GICD_SGIR);
break;
default:
BUG();
@@ -585,7 +601,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p,
if ( p->desc != NULL )
lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT);
- GICH[GICH_LR + lr] = lr_val;
+ writel_relaxed(lr_val, GICH + GICH_LR + lr * 4);
set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status);
clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
@@ -677,7 +693,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
ASSERT(spin_is_locked(&v->arch.vgic.lock));
ASSERT(!local_irq_is_enabled());
- lr = GICH[GICH_LR + i];
+ lr = readl_relaxed(GICH + GICH_LR + i * 4);
irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
p = irq_to_pending(v, irq);
if ( lr & GICH_LR_ACTIVE )
@@ -687,7 +703,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) )
{
if ( p->desc == NULL )
- GICH[GICH_LR + i] = lr | GICH_LR_PENDING;
+ writel_relaxed(lr | GICH_LR_PENDING, GICH + GICH_LR + i * 4);
else
gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n",
irq, v->domain->domain_id, v->vcpu_id, i);
@@ -700,7 +716,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
irq, v->domain->domain_id, v->vcpu_id, i);
#endif
} else {
- GICH[GICH_LR + i] = 0;
+ writel_relaxed(0, GICH + GICH_LR + i * 4);
clear_bit(i, &this_cpu(lr_mask));
if ( p->desc != NULL )
@@ -808,7 +824,8 @@ int gic_events_need_delivery(void)
struct pending_irq *p;
unsigned long flags;
- mask_priority = (GICH[GICH_VMCR] >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
+ mask_priority = (readl_relaxed(GICH + GICH_VMCR)
+ >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
mask_priority = mask_priority << 3;
spin_lock_irqsave(&v->arch.vgic.lock, flags);
@@ -844,22 +861,23 @@ int gic_events_need_delivery(void)
void gic_inject(void)
{
+ uint32_t hcr;
ASSERT(!local_irq_is_enabled());
gic_restore_pending_irqs(current);
+ hcr = readl_relaxed(GICH + GICH_HCR);
if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() )
- GICH[GICH_HCR] |= GICH_HCR_UIE;
+ writel_relaxed(hcr | GICH_HCR_UIE, GICH + GICH_HCR);
else
- GICH[GICH_HCR] &= ~GICH_HCR_UIE;
-
+ writel_relaxed(hcr & ~GICH_HCR_UIE, GICH + GICH_HCR);
}
static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
{
/* Lower the priority */
- GICC[GICC_EOIR] = sgi;
+ writel_relaxed(sgi, GICC + GICC_EOIR);
switch (sgi)
{
@@ -878,7 +896,7 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
}
/* Deactivate */
- GICC[GICC_DIR] = sgi;
+ writel_relaxed(sgi, GICC + GICC_DIR);
}
/* Accept an interrupt from the GIC and dispatch its handler */
@@ -889,7 +907,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
do {
- intack = GICC[GICC_IAR];
+ intack = readl_relaxed(GICC + GICC_IAR);
irq = intack & GICC_IA_IRQ;
if ( likely(irq >= 16 && irq < 1021) )
@@ -976,7 +994,7 @@ void gic_dump_info(struct vcpu *v)
if ( v == current )
{
for ( i = 0; i < nr_lrs; i++ )
- printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]);
+ printk(" HW_LR[%d]=%x\n", i, readl_relaxed(GICH + GICH_LR + i * 4));
} else {
for ( i = 0; i < nr_lrs; i++ )
printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 2949948..1c37836 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -30,7 +30,7 @@
#include <asm/mmio.h>
#include <asm/gic.h>
-#define REG(n) (n/4)
+#define REG(n) (n)
/* Number of ranks of interrupt registers for a domain */
#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
@@ -58,7 +58,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
* Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
* <b>-bits-per-interrupt.
*/
-#define REG_RANK_INDEX(b, n) ((n) & ((b)-1))
+#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
/*
* Returns rank corresponding to a GICD_<FOO><n> register for
@@ -66,7 +66,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
*/
static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
{
- int rank = REG_RANK_NR(b, n);
+ int rank = REG_RANK_NR(b, (n >> 2));
if ( rank == 0 )
return &v->arch.vgic.private_irqs;
@@ -544,7 +544,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
tr = rank->ienable;
rank->ienable |= *r;
vgic_unlock_rank(v, rank);
- vgic_enable_irqs(v, (*r) & (~tr), gicd_reg - GICD_ISENABLER);
+ vgic_enable_irqs(v, (*r) & (~tr), (gicd_reg - GICD_ISENABLER) >> 2);
return 1;
case GICD_ICENABLER ... GICD_ICENABLERN:
@@ -555,7 +555,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
tr = rank->ienable;
rank->ienable &= ~*r;
vgic_unlock_rank(v, rank);
- vgic_disable_irqs(v, (*r) & tr, gicd_reg - GICD_ICENABLER);
+ vgic_disable_irqs(v, (*r) & tr, (gicd_reg - GICD_ICENABLER) >> 2);
return 1;
case GICD_ISPENDR ... GICD_ISPENDRN:
@@ -717,9 +717,8 @@ void vgic_clear_pending_irqs(struct vcpu *v)
void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
{
- int idx = irq >> 2, byte = irq & 0x3;
uint8_t priority;
- struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, idx);
+ struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, irq);
struct pending_irq *iter, *n = irq_to_pending(v, irq);
unsigned long flags;
bool_t running;
@@ -740,7 +739,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
return;
}
- priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, idx)], 0, byte);
+ priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
n->irq = irq;
set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index c7b7368..7fa3b95 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -18,37 +18,37 @@
#ifndef __ASM_ARM_GIC_H__
#define __ASM_ARM_GIC_H__
-#define GICD_CTLR (0x000/4)
-#define GICD_TYPER (0x004/4)
-#define GICD_IIDR (0x008/4)
-#define GICD_IGROUPR (0x080/4)
-#define GICD_IGROUPRN (0x0FC/4)
-#define GICD_ISENABLER (0x100/4)
-#define GICD_ISENABLERN (0x17C/4)
-#define GICD_ICENABLER (0x180/4)
-#define GICD_ICENABLERN (0x1fC/4)
-#define GICD_ISPENDR (0x200/4)
-#define GICD_ISPENDRN (0x27C/4)
-#define GICD_ICPENDR (0x280/4)
-#define GICD_ICPENDRN (0x2FC/4)
-#define GICD_ISACTIVER (0x300/4)
-#define GICD_ISACTIVERN (0x37C/4)
-#define GICD_ICACTIVER (0x380/4)
-#define GICD_ICACTIVERN (0x3FC/4)
-#define GICD_IPRIORITYR (0x400/4)
-#define GICD_IPRIORITYRN (0x7F8/4)
-#define GICD_ITARGETSR (0x800/4)
-#define GICD_ITARGETSRN (0xBF8/4)
-#define GICD_ICFGR (0xC00/4)
-#define GICD_ICFGRN (0xCFC/4)
-#define GICD_NSACR (0xE00/4)
-#define GICD_NSACRN (0xEFC/4)
-#define GICD_SGIR (0xF00/4)
-#define GICD_CPENDSGIR (0xF10/4)
-#define GICD_CPENDSGIRN (0xF1C/4)
-#define GICD_SPENDSGIR (0xF20/4)
-#define GICD_SPENDSGIRN (0xF2C/4)
-#define GICD_ICPIDR2 (0xFE8/4)
+#define GICD_CTLR (0x000)
+#define GICD_TYPER (0x004)
+#define GICD_IIDR (0x008)
+#define GICD_IGROUPR (0x080)
+#define GICD_IGROUPRN (0x0FC)
+#define GICD_ISENABLER (0x100)
+#define GICD_ISENABLERN (0x17C)
+#define GICD_ICENABLER (0x180)
+#define GICD_ICENABLERN (0x1fC)
+#define GICD_ISPENDR (0x200)
+#define GICD_ISPENDRN (0x27C)
+#define GICD_ICPENDR (0x280)
+#define GICD_ICPENDRN (0x2FC)
+#define GICD_ISACTIVER (0x300)
+#define GICD_ISACTIVERN (0x37C)
+#define GICD_ICACTIVER (0x380)
+#define GICD_ICACTIVERN (0x3FC)
+#define GICD_IPRIORITYR (0x400)
+#define GICD_IPRIORITYRN (0x7F8)
+#define GICD_ITARGETSR (0x800)
+#define GICD_ITARGETSRN (0xBF8)
+#define GICD_ICFGR (0xC00)
+#define GICD_ICFGRN (0xCFC)
+#define GICD_NSACR (0xE00)
+#define GICD_NSACRN (0xEFC)
+#define GICD_SGIR (0xF00)
+#define GICD_CPENDSGIR (0xF10)
+#define GICD_CPENDSGIRN (0xF1C)
+#define GICD_SPENDSGIR (0xF20)
+#define GICD_SPENDSGIRN (0xF2C)
+#define GICD_ICPIDR2 (0xFE8)
#define GICD_SGI_TARGET_LIST_SHIFT (24)
#define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
@@ -60,27 +60,27 @@
#define GICD_SGI_GROUP1 (1UL<<15)
#define GICD_SGI_INTID_MASK (0xFUL)
-#define GICC_CTLR (0x0000/4)
-#define GICC_PMR (0x0004/4)
-#define GICC_BPR (0x0008/4)
-#define GICC_IAR (0x000C/4)
-#define GICC_EOIR (0x0010/4)
-#define GICC_RPR (0x0014/4)
-#define GICC_HPPIR (0x0018/4)
-#define GICC_APR (0x00D0/4)
-#define GICC_NSAPR (0x00E0/4)
-#define GICC_DIR (0x1000/4)
-
-#define GICH_HCR (0x00/4)
-#define GICH_VTR (0x04/4)
-#define GICH_VMCR (0x08/4)
-#define GICH_MISR (0x10/4)
-#define GICH_EISR0 (0x20/4)
-#define GICH_EISR1 (0x24/4)
-#define GICH_ELSR0 (0x30/4)
-#define GICH_ELSR1 (0x34/4)
-#define GICH_APR (0xF0/4)
-#define GICH_LR (0x100/4)
+#define GICC_CTLR (0x0000)
+#define GICC_PMR (0x0004)
+#define GICC_BPR (0x0008)
+#define GICC_IAR (0x000C)
+#define GICC_EOIR (0x0010)
+#define GICC_RPR (0x0014)
+#define GICC_HPPIR (0x0018)
+#define GICC_APR (0x00D0)
+#define GICC_NSAPR (0x00E0)
+#define GICC_DIR (0x1000)
+
+#define GICH_HCR (0x00)
+#define GICH_VTR (0x04)
+#define GICH_VMCR (0x08)
+#define GICH_MISR (0x10)
+#define GICH_EISR0 (0x20)
+#define GICH_EISR1 (0x24)
+#define GICH_ELSR0 (0x30)
+#define GICH_ELSR1 (0x34)
+#define GICH_APR (0xF0)
+#define GICH_LR (0x100)
/* Register bits */
#define GICD_CTL_ENABLE 0x1
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers
2014-06-12 13:36 ` [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
@ 2014-06-12 16:11 ` Stefano Stabellini
2014-06-15 16:02 ` Julien Grall
` (2 subsequent siblings)
3 siblings, 0 replies; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 16:11 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic-v2 driver uses fixmap to map the registers.
> Instead use ioremap to access mmio registers.
>
> With this patch, gic-v2 register definitions are updated
> to use obsolute offset address instead of dividing the
> register offset by 4.
>
> Update vgic driver logic to compute using obsolute register
> address offsets
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> xen/arch/arm/gic.c | 154 +++++++++++++++++++++++++--------------------
> xen/arch/arm/vgic.c | 15 +++--
> xen/include/asm-arm/gic.h | 104 +++++++++++++++---------------
> 3 files changed, 145 insertions(+), 128 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index ab2777e..8775629 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -31,20 +31,23 @@
> #include <asm/p2m.h>
> #include <asm/domain.h>
> #include <asm/platform.h>
> -
> +#include <asm/io.h>
> #include <asm/gic.h>
>
> -/* Access to the GIC Distributor registers through the fixmap */
> -#define GICD ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICD))
> -#define GICC ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICC1))
> -#define GICH ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICH))
> +#define GICD (gic.map_dbase)
> +#define GICC (gic.map_cbase)
> +#define GICH (gic.map_hbase)
> +
> static void gic_restore_pending_irqs(struct vcpu *v);
>
> /* Global state */
> static struct {
> paddr_t dbase; /* Address of distributor registers */
> + void __iomem * map_dbase; /* IO mapped Address of distributor registers */
> paddr_t cbase; /* Address of CPU interface registers */
> + void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
> paddr_t hbase; /* Address of virtual interface registers */
> + void __iomem * map_hbase; /* IO Address of virtual interface registers */
> paddr_t vbase; /* Address of virtual cpu interface registers */
> unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
> unsigned int maintenance_irq; /* IRQ maintenance */
> @@ -101,12 +104,12 @@ void gic_save_state(struct vcpu *v)
> * accessed simultaneously by another pCPU.
> */
> for ( i=0; i<nr_lrs; i++)
> - v->arch.gic_lr[i] = GICH[GICH_LR + i];
> + v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
> v->arch.lr_mask = this_cpu(lr_mask);
> - v->arch.gic_apr = GICH[GICH_APR];
> - v->arch.gic_vmcr = GICH[GICH_VMCR];
> + v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
> + v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
> /* Disable until next VCPU scheduled */
> - GICH[GICH_HCR] = 0;
> + writel_relaxed(0, GICH + GICH_HCR);
> isb();
> }
>
> @@ -120,10 +123,10 @@ void gic_restore_state(struct vcpu *v)
>
> this_cpu(lr_mask) = v->arch.lr_mask;
> for ( i=0; i<nr_lrs; i++)
> - GICH[GICH_LR + i] = v->arch.gic_lr[i];
> - GICH[GICH_APR] = v->arch.gic_apr;
> - GICH[GICH_VMCR] = v->arch.gic_vmcr;
> - GICH[GICH_HCR] = GICH_HCR_EN;
> + writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
> + writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
> + writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
> + writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
> isb();
>
> gic_restore_pending_irqs(v);
> @@ -139,8 +142,7 @@ static void gic_irq_enable(struct irq_desc *desc)
> spin_lock_irqsave(&gic.lock, flags);
> desc->status &= ~IRQ_DISABLED;
> dsb(sy);
> - /* Enable routing */
> - GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32));
> + writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
> spin_unlock_irqrestore(&gic.lock, flags);
> }
>
> @@ -153,7 +155,7 @@ static void gic_irq_disable(struct irq_desc *desc)
>
> spin_lock_irqsave(&gic.lock, flags);
> /* Disable routing */
> - GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32));
> + writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
> desc->status |= IRQ_DISABLED;
> spin_unlock_irqrestore(&gic.lock, flags);
> }
> @@ -179,16 +181,16 @@ static void gic_host_irq_end(struct irq_desc *desc)
> {
> int irq = desc->irq;
> /* Lower the priority */
> - GICC[GICC_EOIR] = irq;
> + writel_relaxed(irq, GICC + GICC_EOIR);
> /* Deactivate */
> - GICC[GICC_DIR] = irq;
> + writel_relaxed(irq, GICC + GICC_DIR);
> }
>
> static void gic_guest_irq_end(struct irq_desc *desc)
> {
> int irq = desc->irq;
> /* Lower the priority of the IRQ */
> - GICC[GICC_EOIR] = irq;
> + writel_relaxed(irq, GICC + GICC_EOIR);
> /* Deactivation happens in maintenance interrupt / via GICV */
> }
>
> @@ -243,13 +245,13 @@ static void gic_set_irq_properties(struct irq_desc *desc,
> mask = gic_cpu_mask(cpu_mask);
>
> /* Set edge / level */
> - cfg = GICD[GICD_ICFGR + irq / 16];
> + cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
> edgebit = 2u << (2 * (irq % 16));
> if ( type & DT_IRQ_TYPE_LEVEL_MASK )
> cfg &= ~edgebit;
> else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
> cfg |= edgebit;
> - GICD[GICD_ICFGR + irq / 16] = cfg;
> + writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
>
> /* Set target CPU mask (RAZ/WI on uniprocessor) */
> bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
> @@ -303,87 +305,94 @@ static void __init gic_dist_init(void)
> uint32_t cpumask;
> int i;
>
> - cpumask = GICD[GICD_ITARGETSR] & 0xff;
> + cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
> cpumask |= cpumask << 8;
> cpumask |= cpumask << 16;
>
> /* Disable the distributor */
> - GICD[GICD_CTLR] = 0;
> + writel_relaxed(0, GICD + GICD_CTLR);
>
> - type = GICD[GICD_TYPER];
> + type = readl_relaxed(GICD + GICD_TYPER);
> gic.lines = 32 * ((type & GICD_TYPE_LINES) + 1);
> gic.cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
> printk("GIC: %d lines, %d cpu%s%s (IID %8.8x).\n",
> gic.lines, gic.cpus, (gic.cpus == 1) ? "" : "s",
> (type & GICD_TYPE_SEC) ? ", secure" : "",
> - GICD[GICD_IIDR]);
> + readl_relaxed(GICD + GICD_IIDR));
>
> /* Default all global IRQs to level, active low */
> for ( i = 32; i < gic.lines; i += 16 )
> - GICD[GICD_ICFGR + i / 16] = 0x0;
> + writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
>
> /* Route all global IRQs to this CPU */
> for ( i = 32; i < gic.lines; i += 4 )
> - GICD[GICD_ITARGETSR + i / 4] = cpumask;
> + writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
>
> /* Default priority for global interrupts */
> for ( i = 32; i < gic.lines; i += 4 )
> - GICD[GICD_IPRIORITYR + i / 4] =
> - GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
> + writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> + GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
> + GICD + GICD_IPRIORITYR + (i / 4) * 4);
>
> /* Disable all global interrupts */
> for ( i = 32; i < gic.lines; i += 32 )
> - GICD[GICD_ICENABLER + i / 32] = (uint32_t)~0ul;
> + writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
>
> /* Turn on the distributor */
> - GICD[GICD_CTLR] = GICD_CTL_ENABLE;
> + writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
> }
>
> static void __cpuinit gic_cpu_init(void)
> {
> int i;
>
> - this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff;
> + this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
>
> /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
> * even though they are controlled with GICD registers, they must
> * be set up here with the other per-cpu state. */
> - GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */
> - GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */
> + writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
> + writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
> +
> /* Set SGI priorities */
> for (i = 0; i < 16; i += 4)
> - GICD[GICD_IPRIORITYR + i / 4] =
> - GIC_PRI_IPI<<24 | GIC_PRI_IPI<<16 | GIC_PRI_IPI<<8 | GIC_PRI_IPI;
> + writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
> + GIC_PRI_IPI << 8 | GIC_PRI_IPI,
> + GICD + GICD_IPRIORITYR + (i / 4) * 4);
> /* Set PPI priorities */
> for (i = 16; i < 32; i += 4)
> - GICD[GICD_IPRIORITYR + i / 4] =
> - GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
> + writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> + GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
> + GICD + GICD_IPRIORITYR + (i / 4) * 4);
>
> /* Local settings: interface controller */
> - GICC[GICC_PMR] = 0xff; /* Don't mask by priority */
> - GICC[GICC_BPR] = 0; /* Finest granularity of priority */
> - GICC[GICC_CTLR] = GICC_CTL_ENABLE|GICC_CTL_EOI; /* Turn on delivery */
> + /* Don't mask by priority */
> + writel_relaxed(0xff, GICC + GICC_PMR);
> + /* Finest granularity of priority */
> + writel_relaxed(0x0, GICC + GICC_BPR);
> + /* Turn on delivery */
> + writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
> }
>
> static void gic_cpu_disable(void)
> {
> - GICC[GICC_CTLR] = 0;
> + writel_relaxed(0x0, GICC + GICC_CTLR);
> }
>
> static void __cpuinit gic_hyp_init(void)
> {
> uint32_t vtr;
>
> - vtr = GICH[GICH_VTR];
> + vtr = readl_relaxed(GICH + GICH_VTR);
> nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
>
> - GICH[GICH_MISR] = GICH_MISR_EOI;
> + writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
> this_cpu(lr_mask) = 0ULL;
> }
>
> static void __cpuinit gic_hyp_disable(void)
> {
> - GICH[GICH_HCR] = 0;
> + writel_relaxed(0, GICH + GICH_HCR);
> }
>
> int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
> @@ -462,15 +471,21 @@ void __init gic_init(void)
> (gic.hbase & ~PAGE_MASK) || (gic.vbase & ~PAGE_MASK) )
> panic("GIC interfaces not page aligned");
>
> - set_fixmap(FIXMAP_GICD, gic.dbase >> PAGE_SHIFT, DEV_SHARED);
> - BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
> - FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
> - set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
> + gic.map_dbase = ioremap_nocache(gic.dbase, PAGE_SIZE);
> + if ( !gic.map_dbase )
> + panic("Failed to ioremap for GIC distributor\n");
> +
> if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> - set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
> + gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 0x10);
> else
> - set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
> - set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
> + gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 2);
> +
> + if ( !gic.map_cbase )
> + panic("Failed to ioremap for GIC CPU interface\n");
> +
> + gic.map_hbase = ioremap_nocache(gic.hbase, PAGE_SIZE);
> + if ( !gic.map_hbase )
> + panic("Failed to ioremap for GIC Virtual interface\n");
>
> /* Global settings: interrupt distributor */
> spin_lock_init(&gic.lock);
> @@ -491,15 +506,16 @@ static void send_SGI(const cpumask_t *cpu_mask, enum gic_sgi sgi,
> switch ( irqmode )
> {
> case SGI_TARGET_OTHERS:
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS | sgi;
> + writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
> break;
> case SGI_TARGET_SELF:
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF | sgi;
> + writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
> break;
> case SGI_TARGET_LIST:
> mask = gic_cpu_mask(cpu_mask);
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST |
> - (mask << GICD_SGI_TARGET_SHIFT) | sgi;
> + writel_relaxed(GICD_SGI_TARGET_LIST |
> + (mask << GICD_SGI_TARGET_SHIFT) | sgi,
> + GICD + GICD_SGIR);
> break;
> default:
> BUG();
> @@ -585,7 +601,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p,
> if ( p->desc != NULL )
> lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT);
>
> - GICH[GICH_LR + lr] = lr_val;
> + writel_relaxed(lr_val, GICH + GICH_LR + lr * 4);
>
> set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status);
> clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
> @@ -677,7 +693,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
> ASSERT(spin_is_locked(&v->arch.vgic.lock));
> ASSERT(!local_irq_is_enabled());
>
> - lr = GICH[GICH_LR + i];
> + lr = readl_relaxed(GICH + GICH_LR + i * 4);
> irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
> p = irq_to_pending(v, irq);
> if ( lr & GICH_LR_ACTIVE )
> @@ -687,7 +703,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
> test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) )
> {
> if ( p->desc == NULL )
> - GICH[GICH_LR + i] = lr | GICH_LR_PENDING;
> + writel_relaxed(lr | GICH_LR_PENDING, GICH + GICH_LR + i * 4);
> else
> gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n",
> irq, v->domain->domain_id, v->vcpu_id, i);
> @@ -700,7 +716,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
> irq, v->domain->domain_id, v->vcpu_id, i);
> #endif
> } else {
> - GICH[GICH_LR + i] = 0;
> + writel_relaxed(0, GICH + GICH_LR + i * 4);
> clear_bit(i, &this_cpu(lr_mask));
>
> if ( p->desc != NULL )
> @@ -808,7 +824,8 @@ int gic_events_need_delivery(void)
> struct pending_irq *p;
> unsigned long flags;
>
> - mask_priority = (GICH[GICH_VMCR] >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
> + mask_priority = (readl_relaxed(GICH + GICH_VMCR)
> + >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
> mask_priority = mask_priority << 3;
>
> spin_lock_irqsave(&v->arch.vgic.lock, flags);
> @@ -844,22 +861,23 @@ int gic_events_need_delivery(void)
>
> void gic_inject(void)
> {
> + uint32_t hcr;
> ASSERT(!local_irq_is_enabled());
>
> gic_restore_pending_irqs(current);
>
> + hcr = readl_relaxed(GICH + GICH_HCR);
>
> if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() )
> - GICH[GICH_HCR] |= GICH_HCR_UIE;
> + writel_relaxed(hcr | GICH_HCR_UIE, GICH + GICH_HCR);
> else
> - GICH[GICH_HCR] &= ~GICH_HCR_UIE;
> -
> + writel_relaxed(hcr & ~GICH_HCR_UIE, GICH + GICH_HCR);
> }
>
> static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
> {
> /* Lower the priority */
> - GICC[GICC_EOIR] = sgi;
> + writel_relaxed(sgi, GICC + GICC_EOIR);
>
> switch (sgi)
> {
> @@ -878,7 +896,7 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
> }
>
> /* Deactivate */
> - GICC[GICC_DIR] = sgi;
> + writel_relaxed(sgi, GICC + GICC_DIR);
> }
>
> /* Accept an interrupt from the GIC and dispatch its handler */
> @@ -889,7 +907,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
>
>
> do {
> - intack = GICC[GICC_IAR];
> + intack = readl_relaxed(GICC + GICC_IAR);
> irq = intack & GICC_IA_IRQ;
>
> if ( likely(irq >= 16 && irq < 1021) )
> @@ -976,7 +994,7 @@ void gic_dump_info(struct vcpu *v)
> if ( v == current )
> {
> for ( i = 0; i < nr_lrs; i++ )
> - printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]);
> + printk(" HW_LR[%d]=%x\n", i, readl_relaxed(GICH + GICH_LR + i * 4));
> } else {
> for ( i = 0; i < nr_lrs; i++ )
> printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 2949948..1c37836 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -30,7 +30,7 @@
> #include <asm/mmio.h>
> #include <asm/gic.h>
>
> -#define REG(n) (n/4)
> +#define REG(n) (n)
>
> /* Number of ranks of interrupt registers for a domain */
> #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
> @@ -58,7 +58,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
> * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
> * <b>-bits-per-interrupt.
> */
> -#define REG_RANK_INDEX(b, n) ((n) & ((b)-1))
> +#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
>
> /*
> * Returns rank corresponding to a GICD_<FOO><n> register for
> @@ -66,7 +66,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
> */
> static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
> {
> - int rank = REG_RANK_NR(b, n);
> + int rank = REG_RANK_NR(b, (n >> 2));
>
> if ( rank == 0 )
> return &v->arch.vgic.private_irqs;
> @@ -544,7 +544,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> tr = rank->ienable;
> rank->ienable |= *r;
> vgic_unlock_rank(v, rank);
> - vgic_enable_irqs(v, (*r) & (~tr), gicd_reg - GICD_ISENABLER);
> + vgic_enable_irqs(v, (*r) & (~tr), (gicd_reg - GICD_ISENABLER) >> 2);
> return 1;
>
> case GICD_ICENABLER ... GICD_ICENABLERN:
> @@ -555,7 +555,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> tr = rank->ienable;
> rank->ienable &= ~*r;
> vgic_unlock_rank(v, rank);
> - vgic_disable_irqs(v, (*r) & tr, gicd_reg - GICD_ICENABLER);
> + vgic_disable_irqs(v, (*r) & tr, (gicd_reg - GICD_ICENABLER) >> 2);
> return 1;
>
> case GICD_ISPENDR ... GICD_ISPENDRN:
> @@ -717,9 +717,8 @@ void vgic_clear_pending_irqs(struct vcpu *v)
>
> void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
> {
> - int idx = irq >> 2, byte = irq & 0x3;
> uint8_t priority;
> - struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, idx);
> + struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, irq);
> struct pending_irq *iter, *n = irq_to_pending(v, irq);
> unsigned long flags;
> bool_t running;
> @@ -740,7 +739,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
> return;
> }
>
> - priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, idx)], 0, byte);
> + priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
>
> n->irq = irq;
> set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index c7b7368..7fa3b95 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -18,37 +18,37 @@
> #ifndef __ASM_ARM_GIC_H__
> #define __ASM_ARM_GIC_H__
>
> -#define GICD_CTLR (0x000/4)
> -#define GICD_TYPER (0x004/4)
> -#define GICD_IIDR (0x008/4)
> -#define GICD_IGROUPR (0x080/4)
> -#define GICD_IGROUPRN (0x0FC/4)
> -#define GICD_ISENABLER (0x100/4)
> -#define GICD_ISENABLERN (0x17C/4)
> -#define GICD_ICENABLER (0x180/4)
> -#define GICD_ICENABLERN (0x1fC/4)
> -#define GICD_ISPENDR (0x200/4)
> -#define GICD_ISPENDRN (0x27C/4)
> -#define GICD_ICPENDR (0x280/4)
> -#define GICD_ICPENDRN (0x2FC/4)
> -#define GICD_ISACTIVER (0x300/4)
> -#define GICD_ISACTIVERN (0x37C/4)
> -#define GICD_ICACTIVER (0x380/4)
> -#define GICD_ICACTIVERN (0x3FC/4)
> -#define GICD_IPRIORITYR (0x400/4)
> -#define GICD_IPRIORITYRN (0x7F8/4)
> -#define GICD_ITARGETSR (0x800/4)
> -#define GICD_ITARGETSRN (0xBF8/4)
> -#define GICD_ICFGR (0xC00/4)
> -#define GICD_ICFGRN (0xCFC/4)
> -#define GICD_NSACR (0xE00/4)
> -#define GICD_NSACRN (0xEFC/4)
> -#define GICD_SGIR (0xF00/4)
> -#define GICD_CPENDSGIR (0xF10/4)
> -#define GICD_CPENDSGIRN (0xF1C/4)
> -#define GICD_SPENDSGIR (0xF20/4)
> -#define GICD_SPENDSGIRN (0xF2C/4)
> -#define GICD_ICPIDR2 (0xFE8/4)
> +#define GICD_CTLR (0x000)
> +#define GICD_TYPER (0x004)
> +#define GICD_IIDR (0x008)
> +#define GICD_IGROUPR (0x080)
> +#define GICD_IGROUPRN (0x0FC)
> +#define GICD_ISENABLER (0x100)
> +#define GICD_ISENABLERN (0x17C)
> +#define GICD_ICENABLER (0x180)
> +#define GICD_ICENABLERN (0x1fC)
> +#define GICD_ISPENDR (0x200)
> +#define GICD_ISPENDRN (0x27C)
> +#define GICD_ICPENDR (0x280)
> +#define GICD_ICPENDRN (0x2FC)
> +#define GICD_ISACTIVER (0x300)
> +#define GICD_ISACTIVERN (0x37C)
> +#define GICD_ICACTIVER (0x380)
> +#define GICD_ICACTIVERN (0x3FC)
> +#define GICD_IPRIORITYR (0x400)
> +#define GICD_IPRIORITYRN (0x7F8)
> +#define GICD_ITARGETSR (0x800)
> +#define GICD_ITARGETSRN (0xBF8)
> +#define GICD_ICFGR (0xC00)
> +#define GICD_ICFGRN (0xCFC)
> +#define GICD_NSACR (0xE00)
> +#define GICD_NSACRN (0xEFC)
> +#define GICD_SGIR (0xF00)
> +#define GICD_CPENDSGIR (0xF10)
> +#define GICD_CPENDSGIRN (0xF1C)
> +#define GICD_SPENDSGIR (0xF20)
> +#define GICD_SPENDSGIRN (0xF2C)
> +#define GICD_ICPIDR2 (0xFE8)
>
> #define GICD_SGI_TARGET_LIST_SHIFT (24)
> #define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
> @@ -60,27 +60,27 @@
> #define GICD_SGI_GROUP1 (1UL<<15)
> #define GICD_SGI_INTID_MASK (0xFUL)
>
> -#define GICC_CTLR (0x0000/4)
> -#define GICC_PMR (0x0004/4)
> -#define GICC_BPR (0x0008/4)
> -#define GICC_IAR (0x000C/4)
> -#define GICC_EOIR (0x0010/4)
> -#define GICC_RPR (0x0014/4)
> -#define GICC_HPPIR (0x0018/4)
> -#define GICC_APR (0x00D0/4)
> -#define GICC_NSAPR (0x00E0/4)
> -#define GICC_DIR (0x1000/4)
> -
> -#define GICH_HCR (0x00/4)
> -#define GICH_VTR (0x04/4)
> -#define GICH_VMCR (0x08/4)
> -#define GICH_MISR (0x10/4)
> -#define GICH_EISR0 (0x20/4)
> -#define GICH_EISR1 (0x24/4)
> -#define GICH_ELSR0 (0x30/4)
> -#define GICH_ELSR1 (0x34/4)
> -#define GICH_APR (0xF0/4)
> -#define GICH_LR (0x100/4)
> +#define GICC_CTLR (0x0000)
> +#define GICC_PMR (0x0004)
> +#define GICC_BPR (0x0008)
> +#define GICC_IAR (0x000C)
> +#define GICC_EOIR (0x0010)
> +#define GICC_RPR (0x0014)
> +#define GICC_HPPIR (0x0018)
> +#define GICC_APR (0x00D0)
> +#define GICC_NSAPR (0x00E0)
> +#define GICC_DIR (0x1000)
> +
> +#define GICH_HCR (0x00)
> +#define GICH_VTR (0x04)
> +#define GICH_VMCR (0x08)
> +#define GICH_MISR (0x10)
> +#define GICH_EISR0 (0x20)
> +#define GICH_EISR1 (0x24)
> +#define GICH_ELSR0 (0x30)
> +#define GICH_ELSR1 (0x34)
> +#define GICH_APR (0xF0)
> +#define GICH_LR (0x100)
>
> /* Register bits */
> #define GICD_CTL_ENABLE 0x1
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers
2014-06-12 13:36 ` [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
2014-06-12 16:11 ` Stefano Stabellini
@ 2014-06-15 16:02 ` Julien Grall
2014-06-17 11:59 ` Ian Campbell
2014-06-18 21:19 ` Julien Grall
3 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:02 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic-v2 driver uses fixmap to map the registers.
> Instead use ioremap to access mmio registers.
>
> With this patch, gic-v2 register definitions are updated
> to use obsolute offset address instead of dividing the
> register offset by 4.
>
> Update vgic driver logic to compute using obsolute register
s/obsolute/absolute/ ?
Assuming this is a typo:
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers
2014-06-12 13:36 ` [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
2014-06-12 16:11 ` Stefano Stabellini
2014-06-15 16:02 ` Julien Grall
@ 2014-06-17 11:59 ` Ian Campbell
2014-06-18 21:19 ` Julien Grall
3 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 11:59 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> static void gic_restore_pending_irqs(struct vcpu *v);
>
> /* Global state */
> static struct {
> paddr_t dbase; /* Address of distributor registers */
> + void __iomem * map_dbase; /* IO mapped Address of distributor registers */
I wonder, do we still need the paddr_t ?base members after this change?
> paddr_t cbase; /* Address of CPU interface registers */
> + void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
> paddr_t hbase; /* Address of virtual interface registers */
> + void __iomem * map_hbase; /* IO Address of virtual interface registers */
> paddr_t vbase; /* Address of virtual cpu interface registers */
> unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
> unsigned int maintenance_irq; /* IRQ maintenance */
> @@ -139,8 +142,7 @@ static void gic_irq_enable(struct irq_desc *desc)
> spin_lock_irqsave(&gic.lock, flags);
> desc->status &= ~IRQ_DISABLED;
> dsb(sy);
> - /* Enable routing */
Please keep this comment.
> @@ -58,7 +58,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
> * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
> * <b>-bits-per-interrupt.
> */
> -#define REG_RANK_INDEX(b, n) ((n) & ((b)-1))
> +#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
>
> /*
> * Returns rank corresponding to a GICD_<FOO><n> register for
> @@ -66,7 +66,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
> */
> static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
> {
> - int rank = REG_RANK_NR(b, n);
> + int rank = REG_RANK_NR(b, (n >> 2));
I think there must be better ways to do this than sprinkling >> 2 around
the place (e.g. a helper macro), but OK for now.
With the missing comment reinstated and the spelling error which Julien
mentioned: Acked-by: Ian Campbell <ian.campbell@citrix.com>
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers
2014-06-12 13:36 ` [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
` (2 preceding siblings ...)
2014-06-17 11:59 ` Ian Campbell
@ 2014-06-18 21:19 ` Julien Grall
3 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-18 21:19 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
I went through this patch again today.
You forgot to modify the access of ITARGETSR by an appropriate
read/write in gic_set_irq_priorities.
Regards,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic-v2 driver uses fixmap to map the registers.
> Instead use ioremap to access mmio registers.
>
> With this patch, gic-v2 register definitions are updated
> to use obsolute offset address instead of dividing the
> register offset by 4.
>
> Update vgic driver logic to compute using obsolute register
> address offsets
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> ---
> xen/arch/arm/gic.c | 154 +++++++++++++++++++++++++--------------------
> xen/arch/arm/vgic.c | 15 +++--
> xen/include/asm-arm/gic.h | 104 +++++++++++++++---------------
> 3 files changed, 145 insertions(+), 128 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index ab2777e..8775629 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -31,20 +31,23 @@
> #include <asm/p2m.h>
> #include <asm/domain.h>
> #include <asm/platform.h>
> -
> +#include <asm/io.h>
> #include <asm/gic.h>
>
> -/* Access to the GIC Distributor registers through the fixmap */
> -#define GICD ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICD))
> -#define GICC ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICC1))
> -#define GICH ((volatile uint32_t *) FIXMAP_ADDR(FIXMAP_GICH))
> +#define GICD (gic.map_dbase)
> +#define GICC (gic.map_cbase)
> +#define GICH (gic.map_hbase)
> +
> static void gic_restore_pending_irqs(struct vcpu *v);
>
> /* Global state */
> static struct {
> paddr_t dbase; /* Address of distributor registers */
> + void __iomem * map_dbase; /* IO mapped Address of distributor registers */
> paddr_t cbase; /* Address of CPU interface registers */
> + void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
> paddr_t hbase; /* Address of virtual interface registers */
> + void __iomem * map_hbase; /* IO Address of virtual interface registers */
> paddr_t vbase; /* Address of virtual cpu interface registers */
> unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
> unsigned int maintenance_irq; /* IRQ maintenance */
> @@ -101,12 +104,12 @@ void gic_save_state(struct vcpu *v)
> * accessed simultaneously by another pCPU.
> */
> for ( i=0; i<nr_lrs; i++)
> - v->arch.gic_lr[i] = GICH[GICH_LR + i];
> + v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
> v->arch.lr_mask = this_cpu(lr_mask);
> - v->arch.gic_apr = GICH[GICH_APR];
> - v->arch.gic_vmcr = GICH[GICH_VMCR];
> + v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
> + v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
> /* Disable until next VCPU scheduled */
> - GICH[GICH_HCR] = 0;
> + writel_relaxed(0, GICH + GICH_HCR);
> isb();
> }
>
> @@ -120,10 +123,10 @@ void gic_restore_state(struct vcpu *v)
>
> this_cpu(lr_mask) = v->arch.lr_mask;
> for ( i=0; i<nr_lrs; i++)
> - GICH[GICH_LR + i] = v->arch.gic_lr[i];
> - GICH[GICH_APR] = v->arch.gic_apr;
> - GICH[GICH_VMCR] = v->arch.gic_vmcr;
> - GICH[GICH_HCR] = GICH_HCR_EN;
> + writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
> + writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
> + writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
> + writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
> isb();
>
> gic_restore_pending_irqs(v);
> @@ -139,8 +142,7 @@ static void gic_irq_enable(struct irq_desc *desc)
> spin_lock_irqsave(&gic.lock, flags);
> desc->status &= ~IRQ_DISABLED;
> dsb(sy);
> - /* Enable routing */
> - GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32));
> + writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
> spin_unlock_irqrestore(&gic.lock, flags);
> }
>
> @@ -153,7 +155,7 @@ static void gic_irq_disable(struct irq_desc *desc)
>
> spin_lock_irqsave(&gic.lock, flags);
> /* Disable routing */
> - GICD[GICD_ICENABLER + irq / 32] = (1u << (irq % 32));
> + writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
> desc->status |= IRQ_DISABLED;
> spin_unlock_irqrestore(&gic.lock, flags);
> }
> @@ -179,16 +181,16 @@ static void gic_host_irq_end(struct irq_desc *desc)
> {
> int irq = desc->irq;
> /* Lower the priority */
> - GICC[GICC_EOIR] = irq;
> + writel_relaxed(irq, GICC + GICC_EOIR);
> /* Deactivate */
> - GICC[GICC_DIR] = irq;
> + writel_relaxed(irq, GICC + GICC_DIR);
> }
>
> static void gic_guest_irq_end(struct irq_desc *desc)
> {
> int irq = desc->irq;
> /* Lower the priority of the IRQ */
> - GICC[GICC_EOIR] = irq;
> + writel_relaxed(irq, GICC + GICC_EOIR);
> /* Deactivation happens in maintenance interrupt / via GICV */
> }
>
> @@ -243,13 +245,13 @@ static void gic_set_irq_properties(struct irq_desc *desc,
> mask = gic_cpu_mask(cpu_mask);
>
> /* Set edge / level */
> - cfg = GICD[GICD_ICFGR + irq / 16];
> + cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
> edgebit = 2u << (2 * (irq % 16));
> if ( type & DT_IRQ_TYPE_LEVEL_MASK )
> cfg &= ~edgebit;
> else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
> cfg |= edgebit;
> - GICD[GICD_ICFGR + irq / 16] = cfg;
> + writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
>
> /* Set target CPU mask (RAZ/WI on uniprocessor) */
> bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
> @@ -303,87 +305,94 @@ static void __init gic_dist_init(void)
> uint32_t cpumask;
> int i;
>
> - cpumask = GICD[GICD_ITARGETSR] & 0xff;
> + cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
> cpumask |= cpumask << 8;
> cpumask |= cpumask << 16;
>
> /* Disable the distributor */
> - GICD[GICD_CTLR] = 0;
> + writel_relaxed(0, GICD + GICD_CTLR);
>
> - type = GICD[GICD_TYPER];
> + type = readl_relaxed(GICD + GICD_TYPER);
> gic.lines = 32 * ((type & GICD_TYPE_LINES) + 1);
> gic.cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
> printk("GIC: %d lines, %d cpu%s%s (IID %8.8x).\n",
> gic.lines, gic.cpus, (gic.cpus == 1) ? "" : "s",
> (type & GICD_TYPE_SEC) ? ", secure" : "",
> - GICD[GICD_IIDR]);
> + readl_relaxed(GICD + GICD_IIDR));
>
> /* Default all global IRQs to level, active low */
> for ( i = 32; i < gic.lines; i += 16 )
> - GICD[GICD_ICFGR + i / 16] = 0x0;
> + writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
>
> /* Route all global IRQs to this CPU */
> for ( i = 32; i < gic.lines; i += 4 )
> - GICD[GICD_ITARGETSR + i / 4] = cpumask;
> + writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
>
> /* Default priority for global interrupts */
> for ( i = 32; i < gic.lines; i += 4 )
> - GICD[GICD_IPRIORITYR + i / 4] =
> - GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
> + writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> + GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
> + GICD + GICD_IPRIORITYR + (i / 4) * 4);
>
> /* Disable all global interrupts */
> for ( i = 32; i < gic.lines; i += 32 )
> - GICD[GICD_ICENABLER + i / 32] = (uint32_t)~0ul;
> + writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
>
> /* Turn on the distributor */
> - GICD[GICD_CTLR] = GICD_CTL_ENABLE;
> + writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
> }
>
> static void __cpuinit gic_cpu_init(void)
> {
> int i;
>
> - this_cpu(gic_cpu_id) = GICD[GICD_ITARGETSR] & 0xff;
> + this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
>
> /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
> * even though they are controlled with GICD registers, they must
> * be set up here with the other per-cpu state. */
> - GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */
> - GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */
> + writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
> + writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
> +
> /* Set SGI priorities */
> for (i = 0; i < 16; i += 4)
> - GICD[GICD_IPRIORITYR + i / 4] =
> - GIC_PRI_IPI<<24 | GIC_PRI_IPI<<16 | GIC_PRI_IPI<<8 | GIC_PRI_IPI;
> + writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
> + GIC_PRI_IPI << 8 | GIC_PRI_IPI,
> + GICD + GICD_IPRIORITYR + (i / 4) * 4);
> /* Set PPI priorities */
> for (i = 16; i < 32; i += 4)
> - GICD[GICD_IPRIORITYR + i / 4] =
> - GIC_PRI_IRQ<<24 | GIC_PRI_IRQ<<16 | GIC_PRI_IRQ<<8 | GIC_PRI_IRQ;
> + writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> + GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
> + GICD + GICD_IPRIORITYR + (i / 4) * 4);
>
> /* Local settings: interface controller */
> - GICC[GICC_PMR] = 0xff; /* Don't mask by priority */
> - GICC[GICC_BPR] = 0; /* Finest granularity of priority */
> - GICC[GICC_CTLR] = GICC_CTL_ENABLE|GICC_CTL_EOI; /* Turn on delivery */
> + /* Don't mask by priority */
> + writel_relaxed(0xff, GICC + GICC_PMR);
> + /* Finest granularity of priority */
> + writel_relaxed(0x0, GICC + GICC_BPR);
> + /* Turn on delivery */
> + writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
> }
>
> static void gic_cpu_disable(void)
> {
> - GICC[GICC_CTLR] = 0;
> + writel_relaxed(0x0, GICC + GICC_CTLR);
> }
>
> static void __cpuinit gic_hyp_init(void)
> {
> uint32_t vtr;
>
> - vtr = GICH[GICH_VTR];
> + vtr = readl_relaxed(GICH + GICH_VTR);
> nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
>
> - GICH[GICH_MISR] = GICH_MISR_EOI;
> + writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
> this_cpu(lr_mask) = 0ULL;
> }
>
> static void __cpuinit gic_hyp_disable(void)
> {
> - GICH[GICH_HCR] = 0;
> + writel_relaxed(0, GICH + GICH_HCR);
> }
>
> int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
> @@ -462,15 +471,21 @@ void __init gic_init(void)
> (gic.hbase & ~PAGE_MASK) || (gic.vbase & ~PAGE_MASK) )
> panic("GIC interfaces not page aligned");
>
> - set_fixmap(FIXMAP_GICD, gic.dbase >> PAGE_SHIFT, DEV_SHARED);
> - BUILD_BUG_ON(FIXMAP_ADDR(FIXMAP_GICC1) !=
> - FIXMAP_ADDR(FIXMAP_GICC2)-PAGE_SIZE);
> - set_fixmap(FIXMAP_GICC1, gic.cbase >> PAGE_SHIFT, DEV_SHARED);
> + gic.map_dbase = ioremap_nocache(gic.dbase, PAGE_SIZE);
> + if ( !gic.map_dbase )
> + panic("Failed to ioremap for GIC distributor\n");
> +
> if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
> - set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x10, DEV_SHARED);
> + gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 0x10);
> else
> - set_fixmap(FIXMAP_GICC2, (gic.cbase >> PAGE_SHIFT) + 0x1, DEV_SHARED);
> - set_fixmap(FIXMAP_GICH, gic.hbase >> PAGE_SHIFT, DEV_SHARED);
> + gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 2);
> +
> + if ( !gic.map_cbase )
> + panic("Failed to ioremap for GIC CPU interface\n");
> +
> + gic.map_hbase = ioremap_nocache(gic.hbase, PAGE_SIZE);
> + if ( !gic.map_hbase )
> + panic("Failed to ioremap for GIC Virtual interface\n");
>
> /* Global settings: interrupt distributor */
> spin_lock_init(&gic.lock);
> @@ -491,15 +506,16 @@ static void send_SGI(const cpumask_t *cpu_mask, enum gic_sgi sgi,
> switch ( irqmode )
> {
> case SGI_TARGET_OTHERS:
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_OTHERS | sgi;
> + writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
> break;
> case SGI_TARGET_SELF:
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_SELF | sgi;
> + writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
> break;
> case SGI_TARGET_LIST:
> mask = gic_cpu_mask(cpu_mask);
> - GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST |
> - (mask << GICD_SGI_TARGET_SHIFT) | sgi;
> + writel_relaxed(GICD_SGI_TARGET_LIST |
> + (mask << GICD_SGI_TARGET_SHIFT) | sgi,
> + GICD + GICD_SGIR);
> break;
> default:
> BUG();
> @@ -585,7 +601,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p,
> if ( p->desc != NULL )
> lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT);
>
> - GICH[GICH_LR + lr] = lr_val;
> + writel_relaxed(lr_val, GICH + GICH_LR + lr * 4);
>
> set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status);
> clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
> @@ -677,7 +693,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
> ASSERT(spin_is_locked(&v->arch.vgic.lock));
> ASSERT(!local_irq_is_enabled());
>
> - lr = GICH[GICH_LR + i];
> + lr = readl_relaxed(GICH + GICH_LR + i * 4);
> irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
> p = irq_to_pending(v, irq);
> if ( lr & GICH_LR_ACTIVE )
> @@ -687,7 +703,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
> test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) )
> {
> if ( p->desc == NULL )
> - GICH[GICH_LR + i] = lr | GICH_LR_PENDING;
> + writel_relaxed(lr | GICH_LR_PENDING, GICH + GICH_LR + i * 4);
> else
> gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n",
> irq, v->domain->domain_id, v->vcpu_id, i);
> @@ -700,7 +716,7 @@ static void gic_update_one_lr(struct vcpu *v, int i)
> irq, v->domain->domain_id, v->vcpu_id, i);
> #endif
> } else {
> - GICH[GICH_LR + i] = 0;
> + writel_relaxed(0, GICH + GICH_LR + i * 4);
> clear_bit(i, &this_cpu(lr_mask));
>
> if ( p->desc != NULL )
> @@ -808,7 +824,8 @@ int gic_events_need_delivery(void)
> struct pending_irq *p;
> unsigned long flags;
>
> - mask_priority = (GICH[GICH_VMCR] >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
> + mask_priority = (readl_relaxed(GICH + GICH_VMCR)
> + >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
> mask_priority = mask_priority << 3;
>
> spin_lock_irqsave(&v->arch.vgic.lock, flags);
> @@ -844,22 +861,23 @@ int gic_events_need_delivery(void)
>
> void gic_inject(void)
> {
> + uint32_t hcr;
> ASSERT(!local_irq_is_enabled());
>
> gic_restore_pending_irqs(current);
>
> + hcr = readl_relaxed(GICH + GICH_HCR);
>
> if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() )
> - GICH[GICH_HCR] |= GICH_HCR_UIE;
> + writel_relaxed(hcr | GICH_HCR_UIE, GICH + GICH_HCR);
> else
> - GICH[GICH_HCR] &= ~GICH_HCR_UIE;
> -
> + writel_relaxed(hcr & ~GICH_HCR_UIE, GICH + GICH_HCR);
> }
>
> static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
> {
> /* Lower the priority */
> - GICC[GICC_EOIR] = sgi;
> + writel_relaxed(sgi, GICC + GICC_EOIR);
>
> switch (sgi)
> {
> @@ -878,7 +896,7 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
> }
>
> /* Deactivate */
> - GICC[GICC_DIR] = sgi;
> + writel_relaxed(sgi, GICC + GICC_DIR);
> }
>
> /* Accept an interrupt from the GIC and dispatch its handler */
> @@ -889,7 +907,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
>
>
> do {
> - intack = GICC[GICC_IAR];
> + intack = readl_relaxed(GICC + GICC_IAR);
> irq = intack & GICC_IA_IRQ;
>
> if ( likely(irq >= 16 && irq < 1021) )
> @@ -976,7 +994,7 @@ void gic_dump_info(struct vcpu *v)
> if ( v == current )
> {
> for ( i = 0; i < nr_lrs; i++ )
> - printk(" HW_LR[%d]=%x\n", i, GICH[GICH_LR + i]);
> + printk(" HW_LR[%d]=%x\n", i, readl_relaxed(GICH + GICH_LR + i * 4));
> } else {
> for ( i = 0; i < nr_lrs; i++ )
> printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 2949948..1c37836 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -30,7 +30,7 @@
> #include <asm/mmio.h>
> #include <asm/gic.h>
>
> -#define REG(n) (n/4)
> +#define REG(n) (n)
>
> /* Number of ranks of interrupt registers for a domain */
> #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
> @@ -58,7 +58,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
> * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
> * <b>-bits-per-interrupt.
> */
> -#define REG_RANK_INDEX(b, n) ((n) & ((b)-1))
> +#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
>
> /*
> * Returns rank corresponding to a GICD_<FOO><n> register for
> @@ -66,7 +66,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
> */
> static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
> {
> - int rank = REG_RANK_NR(b, n);
> + int rank = REG_RANK_NR(b, (n >> 2));
>
> if ( rank == 0 )
> return &v->arch.vgic.private_irqs;
> @@ -544,7 +544,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> tr = rank->ienable;
> rank->ienable |= *r;
> vgic_unlock_rank(v, rank);
> - vgic_enable_irqs(v, (*r) & (~tr), gicd_reg - GICD_ISENABLER);
> + vgic_enable_irqs(v, (*r) & (~tr), (gicd_reg - GICD_ISENABLER) >> 2);
> return 1;
>
> case GICD_ICENABLER ... GICD_ICENABLERN:
> @@ -555,7 +555,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> tr = rank->ienable;
> rank->ienable &= ~*r;
> vgic_unlock_rank(v, rank);
> - vgic_disable_irqs(v, (*r) & tr, gicd_reg - GICD_ICENABLER);
> + vgic_disable_irqs(v, (*r) & tr, (gicd_reg - GICD_ICENABLER) >> 2);
> return 1;
>
> case GICD_ISPENDR ... GICD_ISPENDRN:
> @@ -717,9 +717,8 @@ void vgic_clear_pending_irqs(struct vcpu *v)
>
> void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
> {
> - int idx = irq >> 2, byte = irq & 0x3;
> uint8_t priority;
> - struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, idx);
> + struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, irq);
> struct pending_irq *iter, *n = irq_to_pending(v, irq);
> unsigned long flags;
> bool_t running;
> @@ -740,7 +739,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
> return;
> }
>
> - priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, idx)], 0, byte);
> + priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
>
> n->irq = irq;
> set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index c7b7368..7fa3b95 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -18,37 +18,37 @@
> #ifndef __ASM_ARM_GIC_H__
> #define __ASM_ARM_GIC_H__
>
> -#define GICD_CTLR (0x000/4)
> -#define GICD_TYPER (0x004/4)
> -#define GICD_IIDR (0x008/4)
> -#define GICD_IGROUPR (0x080/4)
> -#define GICD_IGROUPRN (0x0FC/4)
> -#define GICD_ISENABLER (0x100/4)
> -#define GICD_ISENABLERN (0x17C/4)
> -#define GICD_ICENABLER (0x180/4)
> -#define GICD_ICENABLERN (0x1fC/4)
> -#define GICD_ISPENDR (0x200/4)
> -#define GICD_ISPENDRN (0x27C/4)
> -#define GICD_ICPENDR (0x280/4)
> -#define GICD_ICPENDRN (0x2FC/4)
> -#define GICD_ISACTIVER (0x300/4)
> -#define GICD_ISACTIVERN (0x37C/4)
> -#define GICD_ICACTIVER (0x380/4)
> -#define GICD_ICACTIVERN (0x3FC/4)
> -#define GICD_IPRIORITYR (0x400/4)
> -#define GICD_IPRIORITYRN (0x7F8/4)
> -#define GICD_ITARGETSR (0x800/4)
> -#define GICD_ITARGETSRN (0xBF8/4)
> -#define GICD_ICFGR (0xC00/4)
> -#define GICD_ICFGRN (0xCFC/4)
> -#define GICD_NSACR (0xE00/4)
> -#define GICD_NSACRN (0xEFC/4)
> -#define GICD_SGIR (0xF00/4)
> -#define GICD_CPENDSGIR (0xF10/4)
> -#define GICD_CPENDSGIRN (0xF1C/4)
> -#define GICD_SPENDSGIR (0xF20/4)
> -#define GICD_SPENDSGIRN (0xF2C/4)
> -#define GICD_ICPIDR2 (0xFE8/4)
> +#define GICD_CTLR (0x000)
> +#define GICD_TYPER (0x004)
> +#define GICD_IIDR (0x008)
> +#define GICD_IGROUPR (0x080)
> +#define GICD_IGROUPRN (0x0FC)
> +#define GICD_ISENABLER (0x100)
> +#define GICD_ISENABLERN (0x17C)
> +#define GICD_ICENABLER (0x180)
> +#define GICD_ICENABLERN (0x1fC)
> +#define GICD_ISPENDR (0x200)
> +#define GICD_ISPENDRN (0x27C)
> +#define GICD_ICPENDR (0x280)
> +#define GICD_ICPENDRN (0x2FC)
> +#define GICD_ISACTIVER (0x300)
> +#define GICD_ISACTIVERN (0x37C)
> +#define GICD_ICACTIVER (0x380)
> +#define GICD_ICACTIVERN (0x3FC)
> +#define GICD_IPRIORITYR (0x400)
> +#define GICD_IPRIORITYRN (0x7F8)
> +#define GICD_ITARGETSR (0x800)
> +#define GICD_ITARGETSRN (0xBF8)
> +#define GICD_ICFGR (0xC00)
> +#define GICD_ICFGRN (0xCFC)
> +#define GICD_NSACR (0xE00)
> +#define GICD_NSACRN (0xEFC)
> +#define GICD_SGIR (0xF00)
> +#define GICD_CPENDSGIR (0xF10)
> +#define GICD_CPENDSGIRN (0xF1C)
> +#define GICD_SPENDSGIR (0xF20)
> +#define GICD_SPENDSGIRN (0xF2C)
> +#define GICD_ICPIDR2 (0xFE8)
>
> #define GICD_SGI_TARGET_LIST_SHIFT (24)
> #define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
> @@ -60,27 +60,27 @@
> #define GICD_SGI_GROUP1 (1UL<<15)
> #define GICD_SGI_INTID_MASK (0xFUL)
>
> -#define GICC_CTLR (0x0000/4)
> -#define GICC_PMR (0x0004/4)
> -#define GICC_BPR (0x0008/4)
> -#define GICC_IAR (0x000C/4)
> -#define GICC_EOIR (0x0010/4)
> -#define GICC_RPR (0x0014/4)
> -#define GICC_HPPIR (0x0018/4)
> -#define GICC_APR (0x00D0/4)
> -#define GICC_NSAPR (0x00E0/4)
> -#define GICC_DIR (0x1000/4)
> -
> -#define GICH_HCR (0x00/4)
> -#define GICH_VTR (0x04/4)
> -#define GICH_VMCR (0x08/4)
> -#define GICH_MISR (0x10/4)
> -#define GICH_EISR0 (0x20/4)
> -#define GICH_EISR1 (0x24/4)
> -#define GICH_ELSR0 (0x30/4)
> -#define GICH_ELSR1 (0x34/4)
> -#define GICH_APR (0xF0/4)
> -#define GICH_LR (0x100/4)
> +#define GICC_CTLR (0x0000)
> +#define GICC_PMR (0x0004)
> +#define GICC_BPR (0x0008)
> +#define GICC_IAR (0x000C)
> +#define GICC_EOIR (0x0010)
> +#define GICC_RPR (0x0014)
> +#define GICC_HPPIR (0x0018)
> +#define GICC_APR (0x00D0)
> +#define GICC_NSAPR (0x00E0)
> +#define GICC_DIR (0x1000)
> +
> +#define GICH_HCR (0x00)
> +#define GICH_VTR (0x04)
> +#define GICH_VMCR (0x08)
> +#define GICH_MISR (0x10)
> +#define GICH_EISR0 (0x20)
> +#define GICH_EISR1 (0x24)
> +#define GICH_ELSR0 (0x30)
> +#define GICH_ELSR1 (0x34)
> +#define GICH_APR (0xF0)
> +#define GICH_LR (0x100)
>
> /* Register bits */
> #define GICD_CTL_ENABLE 0x1
>
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (4 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 05/21] xen/arm: use ioremap to map gic-v2 registers vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 16:26 ` Stefano Stabellini
` (3 more replies)
2014-06-12 13:36 ` [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver vijay.kilari
` (16 subsequent siblings)
22 siblings, 4 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
GIC driver contains both generic and hardware specific low
level functionality in gic.c file.
With this patch, low level functionality is moved to separate
file gic-v2.c and generic code is kept in gic.c file
Callbacks are registered by low level driver with generic driver
and are called whereever required.
The locking mechanism is not changed.
This helps to separate generic and hardware functionality
and implement future hardware version drivers.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/Makefile | 2 +-
xen/arch/arm/gic-v2.c | 669 +++++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/gic.c | 543 +++++-------------------------------
xen/include/asm-arm/gic.h | 106 +++++--
4 files changed, 822 insertions(+), 498 deletions(-)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 63e0460..969ee52 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -10,7 +10,7 @@ obj-y += vpsci.o
obj-y += domctl.o
obj-y += sysctl.o
obj-y += domain_build.o
-obj-y += gic.o
+obj-y += gic.o gic-v2.o
obj-y += io.o
obj-y += irq.o
obj-y += kernel.o
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
new file mode 100644
index 0000000..9cf1dc8
--- /dev/null
+++ b/xen/arch/arm/gic-v2.c
@@ -0,0 +1,669 @@
+/*
+ * xen/arch/arm/gic-v2.c
+ *
+ * ARM Generic Interrupt Controller support v2
+ *
+ * Tim Deegan <tim@xen.org>
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/mm.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+#include <xen/errno.h>
+#include <xen/softirq.h>
+#include <xen/list.h>
+#include <xen/device_tree.h>
+#include <asm/p2m.h>
+#include <asm/domain.h>
+#include <asm/platform.h>
+
+#include <asm/io.h>
+#include <asm/gic.h>
+
+/*
+ * LR register definitions are GIC v2 specific.
+ * Moved these definitions from header file to here
+ */
+#define GICH_V2_LR_VIRTUAL_MASK 0x3ff
+#define GICH_V2_LR_VIRTUAL_SHIFT 0
+#define GICH_V2_LR_PHYSICAL_MASK 0x3ff
+#define GICH_V2_LR_PHYSICAL_SHIFT 10
+#define GICH_V2_LR_STATE_MASK 0x3
+#define GICH_V2_LR_STATE_SHIFT 28
+#define GICH_V2_LR_PRIORITY_SHIFT 23
+#define GICH_V2_LR_PRIORITY_MASK 0x1f
+#define GICH_V2_LR_HW_SHIFT 31
+#define GICH_V2_LR_HW_MASK 0x1
+#define GICH_V2_LR_GRP_SHIFT 30
+#define GICH_V2_LR_GRP_MASK 0x1
+#define GICH_V2_LR_MAINTENANCE_IRQ (1<<19)
+#define GICH_V2_LR_GRP1 (1<<30)
+#define GICH_V2_LR_HW (1<<31)
+#define GICH_V2_LR_CPUID_SHIFT 9
+#define GICH_V2_VTR_NRLRGS 0x3f
+
+#define GICH_V2_VMCR_PRIORITY_MASK 0x1f
+#define GICH_V2_VMCR_PRIORITY_SHIFT 27
+
+#define GICD (gicv2.map_dbase)
+#define GICC (gicv2.map_cbase)
+#define GICH (gicv2.map_hbase)
+
+/* Global state */
+static struct {
+ paddr_t dbase; /* Address of distributor registers */
+ void __iomem * map_dbase; /* IO mapped Address of distributor registers */
+ paddr_t cbase; /* Address of CPU interface registers */
+ void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
+ paddr_t hbase; /* Address of virtual interface registers */
+ void __iomem * map_hbase; /* IO Address of virtual interface registers */
+ paddr_t vbase; /* Address of virtual cpu interface registers */
+ spinlock_t lock;
+} gicv2;
+
+static struct gic_info gicv2_info;
+
+/* The GIC mapping of CPU interfaces does not necessarily match the
+ * logical CPU numbering. Let's use mapping as returned by the GIC
+ * itself
+ */
+static DEFINE_PER_CPU(u8, gic_cpu_id);
+
+/* Maximum cpu interface per GIC */
+#define NR_GIC_CPU_IF 8
+
+static unsigned int gicv2_cpu_mask(const cpumask_t *cpumask)
+{
+ unsigned int cpu;
+ unsigned int mask = 0;
+ cpumask_t possible_mask;
+
+ cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
+ for_each_cpu( cpu, &possible_mask )
+ {
+ ASSERT(cpu < NR_GIC_CPU_IF);
+ mask |= per_cpu(gic_cpu_id, cpu);
+ }
+
+ return mask;
+}
+
+static void gicv2_save_state(struct vcpu *v)
+{
+ int i;
+
+ /* No need for spinlocks here because interrupts are disabled around
+ * this call and it only accesses struct vcpu fields that cannot be
+ * accessed simultaneously by another pCPU.
+ */
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
+
+ v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
+ v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
+ /* Disable until next VCPU scheduled */
+ writel_relaxed(0, GICH + GICH_HCR);
+}
+
+static void gicv2_restore_state(const struct vcpu *v)
+{
+ int i;
+
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
+
+ writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
+ writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
+ writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
+}
+
+static void gicv2_dump_state(const struct vcpu *v)
+{
+ int i;
+
+ if ( v == current )
+ {
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ printk(" HW_LR[%d]=%x\n", i,
+ readl_relaxed(GICH + GICH_LR + i * 4));
+ }
+ else
+ {
+ for ( i = 0; i < gicv2_info.nr_lrs; i++ )
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ }
+}
+
+static void gicv2_eoi_irq(struct irq_desc *irqd)
+{
+ int irq = irqd->irq;
+ /* Lower the priority */
+ writel_relaxed(irq, GICC + GICC_EOIR);
+}
+
+static void gicv2_dir_irq(struct irq_desc *irqd)
+{
+ /* Deactivate */
+ writel_relaxed(irqd->irq, GICC + GICC_DIR);
+}
+
+static unsigned int gicv2_read_irq(void)
+{
+ return (readl_relaxed(GICC + GICC_IAR) & GICC_IA_IRQ);
+}
+
+/*
+ * needs to be called with a valid cpu_mask, ie each cpu in the mask has
+ * already called gic_cpu_init
+ */
+static void gicv2_set_irq_properties(struct irq_desc *desc,
+ const cpumask_t *cpu_mask,
+ unsigned int priority)
+{
+ volatile unsigned char *bytereg;
+ uint32_t cfg, edgebit;
+ unsigned int mask = gicv2_cpu_mask(cpu_mask);
+ unsigned int irq = desc->irq;
+ unsigned int type = desc->arch.type;
+
+ spin_lock(&gicv2.lock);
+ /* Set edge / level */
+ cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
+ edgebit = 2u << (2 * (irq % 16));
+ if ( type & DT_IRQ_TYPE_LEVEL_MASK )
+ cfg &= ~edgebit;
+ else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
+ cfg |= edgebit;
+ writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
+
+ /* Set target CPU mask (RAZ/WI on uniprocessor) */
+ bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
+ bytereg[irq] = mask;
+
+ /* Set priority */
+ bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR);
+ bytereg[irq] = priority;
+
+ spin_unlock(&gicv2.lock);
+}
+
+static void __init gicv2_dist_init(void)
+{
+ uint32_t type;
+ uint32_t cpumask;
+ uint32_t gic_cpus;
+ int i;
+
+ cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
+ cpumask |= cpumask << 8;
+ cpumask |= cpumask << 16;
+
+ /* Disable the distributor */
+ writel_relaxed(0, GICD + GICD_CTLR);
+
+ type = readl_relaxed(GICD + GICD_TYPER);
+ gicv2_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
+ gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
+ printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n",
+ gicv2_info.nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s",
+ (type & GICD_TYPE_SEC) ? ", secure" : "",
+ readl_relaxed(GICD + GICD_IIDR));
+
+ /* Default all global IRQs to level, active low */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 16 )
+ writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
+
+ /* Route all global IRQs to this CPU */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 4 )
+ writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
+
+ /* Default priority for global interrupts */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 4 )
+ writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
+
+ /* Disable all global interrupts */
+ for ( i = 32; i < gicv2_info.nr_lines; i += 32 )
+ writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
+
+ /* Turn on the distributor */
+ writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
+}
+
+static void __cpuinit gicv2_cpu_init(void)
+{
+ int i;
+
+ this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
+
+ /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
+ * even though they are controlled with GICD registers, they must
+ * be set up here with the other per-cpu state. */
+ writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
+ writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
+
+ /* Set SGI priorities */
+ for ( i = 0; i < 16; i += 4 )
+ writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
+ GIC_PRI_IPI << 8 | GIC_PRI_IPI,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
+
+ /* Set PPI priorities */
+ for ( i = 16; i < 32; i += 4 )
+ writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
+ GICD + GICD_IPRIORITYR + (i / 4) * 4);
+
+ /* Local settings: interface controller */
+ /* Don't mask by priority */
+ writel_relaxed(0xff, GICC + GICC_PMR);
+ /* Finest granularity of priority */
+ writel_relaxed(0x0, GICC + GICC_BPR);
+ /* Turn on delivery */
+ writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
+}
+
+static void gicv2_cpu_disable(void)
+{
+ writel_relaxed(0x0, GICC + GICC_CTLR);
+}
+
+static void __cpuinit gicv2_hyp_init(void)
+{
+ uint32_t vtr;
+ uint8_t nr_lrs;
+
+ vtr = readl_relaxed(GICH + GICH_VTR);
+ nr_lrs = (vtr & GICH_V2_VTR_NRLRGS) + 1;
+ gicv2_info.nr_lrs = nr_lrs;
+
+ writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
+ update_cpu_lr_mask();
+}
+
+static void __cpuinit gicv2_hyp_disable(void)
+{
+ writel_relaxed(0, GICH + GICH_HCR);
+}
+
+static int gicv2_secondary_cpu_init(void)
+{
+ spin_lock(&gicv2.lock);
+
+ gicv2_cpu_init();
+ gicv2_hyp_init();
+
+ spin_unlock(&gicv2.lock);
+
+ return 0;
+}
+
+static void gicv2_send_SGI(const cpumask_t *cpu_mask, enum gic_sgi sgi,
+ enum gic_sgi_mode irqmode)
+{
+ unsigned int mask = 0;
+
+ switch ( irqmode )
+ {
+ case SGI_TARGET_OTHERS:
+ writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
+ break;
+ case SGI_TARGET_SELF:
+ writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
+ break;
+ case SGI_TARGET_LIST:
+ mask = gicv2_cpu_mask(cpu_mask);
+ writel_relaxed(GICD_SGI_TARGET_LIST |
+ (mask << GICD_SGI_TARGET_SHIFT) | sgi,
+ GICD + GICD_SGIR);
+ break;
+ default:
+ BUG();
+ }
+}
+
+/* Shut down the per-CPU GIC interface */
+static void gicv2_disable_interface(void)
+{
+ spin_lock(&gicv2.lock);
+ gicv2_cpu_disable();
+ gicv2_hyp_disable();
+ spin_unlock(&gicv2.lock);
+}
+
+static void gicv2_update_lr(int lr, const struct pending_irq *p,
+ unsigned int state)
+{
+ uint32_t lr_reg;
+
+ BUG_ON(lr >= gicv2_info.nr_lrs);
+ BUG_ON(lr < 0);
+
+ lr_reg = (((state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) |
+ ((GIC_PRI_TO_GUEST(p->priority) & GICH_V2_LR_PRIORITY_MASK)
+ << GICH_V2_LR_PRIORITY_SHIFT) |
+ ((p->irq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT));
+
+ if ( p->desc != NULL )
+ lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & GICH_V2_LR_PHYSICAL_MASK )
+ << GICH_V2_LR_PHYSICAL_SHIFT);
+
+ writel_relaxed(lr_reg, GICH + GICH_LR + lr * 4);
+}
+
+static void gicv2_clear_lr(int lr)
+{
+ writel_relaxed(0, GICH + GICH_LR + lr * 4);
+}
+
+static int gicv_v2_init(struct domain *d)
+{
+ int ret;
+
+ /*
+ * Domain 0 gets the hardware address.
+ * Guests get the virtual platform layout.
+ */
+ if ( d->domain_id == 0 )
+ {
+ d->arch.vgic.dbase = gicv2.dbase;
+ d->arch.vgic.cbase = gicv2.cbase;
+ }
+ else
+ {
+ d->arch.vgic.dbase = GUEST_GICD_BASE;
+ d->arch.vgic.cbase = GUEST_GICC_BASE;
+ }
+
+ d->arch.vgic.nr_lines = 0;
+
+ /*
+ * Map the gic virtual cpu interface in the gic cpu interface
+ * region of the guest.
+ *
+ * The second page is always mapped at +4K irrespective of the
+ * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
+ */
+ ret = map_mmio_regions(d, d->arch.vgic.cbase,
+ d->arch.vgic.cbase + PAGE_SIZE - 1,
+ gicv2.vbase);
+ if ( ret )
+ return ret;
+
+ if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+ ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+ d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+ gicv2.vbase + PAGE_SIZE);
+ else
+ ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
+ d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
+ gicv2.vbase + 16*PAGE_SIZE);
+
+ return ret;
+}
+
+static void gicv2_read_lr(int lr, struct gic_lr *lr_reg)
+{
+ uint32_t lrv;
+
+ lrv = readl_relaxed(GICH + GICH_LR + lr * 4);
+ lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK;
+ lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK;
+ lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK;
+ lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK;
+ lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK;
+ lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK;
+}
+
+static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg)
+{
+ uint32_t lrv = 0;
+
+ lrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) << GICH_V2_LR_PHYSICAL_SHIFT) |
+ ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) |
+ ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK)
+ << GICH_V2_LR_PRIORITY_SHIFT) |
+ ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK)
+ << GICH_V2_LR_STATE_SHIFT) |
+ ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK)
+ << GICH_V2_LR_HW_SHIFT) |
+ ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) );
+
+ writel_relaxed(lrv, GICH + GICH_LR + lr * 4);
+}
+
+static void gicv2_hcr_status(uint32_t flag, bool_t status)
+{
+ uint32_t hcr = readl_relaxed(GICH + GICH_HCR);
+
+ if ( status )
+ hcr |= flag;
+ else
+ hcr &= (~flag);
+
+ writel_relaxed(hcr, GICH + GICH_HCR);
+}
+
+static unsigned int gicv2_read_vmcr_priority(void)
+{
+ return ((readl_relaxed(GICH + GICH_VMCR) >> GICH_V2_VMCR_PRIORITY_SHIFT)
+ & GICH_V2_VMCR_PRIORITY_MASK);
+}
+
+static void gicv2_irq_enable(struct irq_desc *desc)
+{
+ unsigned long flags;
+ int irq = desc->irq;
+
+ spin_lock_irqsave(&gicv2.lock, flags);
+ desc->status &= ~IRQ_DISABLED;
+ dsb(sy);
+ /* Enable routing */
+ writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
+ spin_unlock_irqrestore(&gicv2.lock, flags);
+}
+
+static void gicv2_irq_disable(struct irq_desc *desc)
+{
+ unsigned long flags;
+ int irq = desc->irq;
+
+ spin_lock_irqsave(&gicv2.lock, flags);
+ /* Disable routing */
+ writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
+ desc->status |= IRQ_DISABLED;
+ spin_unlock_irqrestore(&gicv2.lock, flags);
+}
+
+static unsigned int gicv2_irq_startup(struct irq_desc *desc)
+{
+ gicv2_irq_enable(desc);
+
+ return 0;
+}
+
+static void gicv2_irq_shutdown(struct irq_desc *desc)
+{
+ gicv2_irq_disable(desc);
+}
+
+static void gicv2_irq_ack(struct irq_desc *desc)
+{
+ /* No ACK -- reading IAR has done this for us */
+}
+
+static void gicv2_host_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority */
+ gicv2_eoi_irq(desc);
+ /* Deactivate */
+ gicv2_dir_irq(desc);
+}
+
+static void gicv2_guest_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority of the IRQ */
+ gicv2_eoi_irq(desc);
+ /* Deactivation happens in maintenance interrupt / via GICV */
+}
+
+static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
+{
+ BUG();
+}
+
+/* XXX different for level vs edge */
+static hw_irq_controller gicv2_host_irq_type = {
+ .typename = "gic-v2",
+ .startup = gicv2_irq_startup,
+ .shutdown = gicv2_irq_shutdown,
+ .enable = gicv2_irq_enable,
+ .disable = gicv2_irq_disable,
+ .ack = gicv2_irq_ack,
+ .end = gicv2_host_irq_end,
+ .set_affinity = gicv2_irq_set_affinity,
+};
+
+static hw_irq_controller gicv2_guest_irq_type = {
+ .typename = "gic-v2",
+ .startup = gicv2_irq_startup,
+ .shutdown = gicv2_irq_shutdown,
+ .enable = gicv2_irq_enable,
+ .disable = gicv2_irq_disable,
+ .ack = gicv2_irq_ack,
+ .end = gicv2_guest_irq_end,
+ .set_affinity = gicv2_irq_set_affinity,
+};
+
+const static struct gic_hw_operations gicv2_ops = {
+ .info = &gicv2_info,
+ .secondary_init = gicv2_secondary_cpu_init,
+ .save_state = gicv2_save_state,
+ .restore_state = gicv2_restore_state,
+ .dump_state = gicv2_dump_state,
+ .gicv_setup = gicv_v2_init,
+ .gic_host_irq_type = &gicv2_host_irq_type,
+ .gic_guest_irq_type = &gicv2_guest_irq_type,
+ .eoi_irq = gicv2_eoi_irq,
+ .deactivate_irq = gicv2_dir_irq,
+ .read_irq = gicv2_read_irq,
+ .set_irq_properties = gicv2_set_irq_properties,
+ .send_SGI = gicv2_send_SGI,
+ .disable_interface = gicv2_disable_interface,
+ .update_lr = gicv2_update_lr,
+ .update_hcr_status = gicv2_hcr_status,
+ .clear_lr = gicv2_clear_lr,
+ .read_lr = gicv2_read_lr,
+ .write_lr = gicv2_write_lr,
+ .read_vmcr_priority = gicv2_read_vmcr_priority,
+};
+
+/* Set up the GIC */
+void __init gicv2_init(void)
+{
+ static const struct dt_device_match gic_ids[] __initconst =
+ {
+ DT_MATCH_GIC,
+ { /* sentinel */ },
+ };
+ struct dt_device_node *node;
+ int res;
+
+ node = dt_find_interrupt_controller(gic_ids);
+ if ( !node )
+ panic("GICv2: Unable to find compatible GIC in the device tree");
+
+ dt_device_set_used_by(node, DOMID_XEN);
+
+ res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);
+ if ( res || !gicv2.dbase || (gicv2.dbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the distributor");
+
+ res = dt_device_get_address(node, 1, &gicv2.cbase, NULL);
+ if ( res || !gicv2.cbase || (gicv2.cbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the CPU");
+
+ res = dt_device_get_address(node, 2, &gicv2.hbase, NULL);
+ if ( res || !gicv2.hbase || (gicv2.hbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the hypervisor");
+
+ res = dt_device_get_address(node, 3, &gicv2.vbase, NULL);
+ if ( res || !gicv2.vbase || (gicv2.vbase & ~PAGE_MASK) )
+ panic("GICv2: Cannot find a valid address for the virtual CPU");
+
+ res = platform_get_irq(node, 0);
+ if ( res < 0 )
+ panic("GICv2: Cannot find the maintenance IRQ");
+ gicv2_info.maintenance_irq = res;
+
+ /* Set the GIC as the primary interrupt controller */
+ dt_interrupt_controller = node;
+
+ /* TODO: Add check on distributor, cpu size */
+
+ printk("GICv2 initialization:\n"
+ " gic_dist_addr=%"PRIpaddr"\n"
+ " gic_cpu_addr=%"PRIpaddr"\n"
+ " gic_hyp_addr=%"PRIpaddr"\n"
+ " gic_vcpu_addr=%"PRIpaddr"\n"
+ " gic_maintenance_irq=%u\n",
+ gicv2.dbase, gicv2.cbase, gicv2.hbase, gicv2.vbase,
+ gicv2_info.maintenance_irq);
+
+ if ( (gicv2.dbase & ~PAGE_MASK) || (gicv2.cbase & ~PAGE_MASK) ||
+ (gicv2.hbase & ~PAGE_MASK) || (gicv2.vbase & ~PAGE_MASK) )
+ panic("GICv2 interfaces not page aligned");
+
+ gicv2.map_dbase = ioremap_nocache(gicv2.dbase, PAGE_SIZE);
+ if ( !gicv2.map_dbase )
+ panic("GICv2: Failed to ioremap for GIC distributor\n");
+
+ if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
+ gicv2.map_cbase = ioremap_nocache(gicv2.cbase, PAGE_SIZE * 0x10);
+ else
+ gicv2.map_cbase = ioremap_nocache(gicv2.cbase, PAGE_SIZE * 2);
+
+ if ( !gicv2.map_cbase )
+ panic("GICv2: Failed to ioremap for GIC CPU interface\n");
+
+ gicv2.map_hbase = ioremap_nocache(gicv2.hbase, PAGE_SIZE);
+ if ( !gicv2.map_hbase )
+ panic("GICv2: Failed to ioremap for GIC Virtual interface\n");
+
+ /* Global settings: interrupt distributor */
+ spin_lock_init(&gicv2.lock);
+ spin_lock(&gicv2.lock);
+
+ gicv2_dist_init();
+ gicv2_cpu_init();
+ gicv2_hyp_init();
+
+ spin_unlock(&gicv2.lock);
+
+ gicv2_info.hw_version = GIC_V2;
+ register_gic_ops(&gicv2_ops);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 8775629..4580d96 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -24,7 +24,6 @@
#include <xen/irq.h>
#include <xen/sched.h>
#include <xen/errno.h>
-#include <xen/serial.h>
#include <xen/softirq.h>
#include <xen/list.h>
#include <xen/device_tree.h>
@@ -34,195 +33,68 @@
#include <asm/io.h>
#include <asm/gic.h>
-#define GICD (gic.map_dbase)
-#define GICC (gic.map_cbase)
-#define GICH (gic.map_hbase)
-
static void gic_restore_pending_irqs(struct vcpu *v);
-/* Global state */
-static struct {
- paddr_t dbase; /* Address of distributor registers */
- void __iomem * map_dbase; /* IO mapped Address of distributor registers */
- paddr_t cbase; /* Address of CPU interface registers */
- void __iomem * map_cbase; /* IO mapped Address of CPU interface registers*/
- paddr_t hbase; /* Address of virtual interface registers */
- void __iomem * map_hbase; /* IO Address of virtual interface registers */
- paddr_t vbase; /* Address of virtual cpu interface registers */
- unsigned int lines; /* Number of interrupts (SPIs + PPIs + SGIs) */
- unsigned int maintenance_irq; /* IRQ maintenance */
- unsigned int cpus;
- spinlock_t lock;
-} gic;
-
static DEFINE_PER_CPU(uint64_t, lr_mask);
-static uint8_t nr_lrs;
-#define lr_all_full() (this_cpu(lr_mask) == ((1 << nr_lrs) - 1))
-
-/* The GIC mapping of CPU interfaces does not necessarily match the
- * logical CPU numbering. Let's use mapping as returned by the GIC
- * itself
- */
-static DEFINE_PER_CPU(u8, gic_cpu_id);
-
-/* Maximum cpu interface per GIC */
-#define NR_GIC_CPU_IF 8
+#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1))
#undef GIC_DEBUG
static void gic_update_one_lr(struct vcpu *v, int i);
-static unsigned int gic_cpu_mask(const cpumask_t *cpumask)
+static const struct gic_hw_operations *gic_hw_ops;
+
+void register_gic_ops(const struct gic_hw_operations *ops)
{
- unsigned int cpu;
- unsigned int mask = 0;
- cpumask_t possible_mask;
+ gic_hw_ops = ops;
+}
- cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
- for_each_cpu(cpu, &possible_mask)
- {
- ASSERT(cpu < NR_GIC_CPU_IF);
- mask |= per_cpu(gic_cpu_id, cpu);
- }
+void update_cpu_lr_mask(void)
+{
+ this_cpu(lr_mask) = 0ULL;
+}
- return mask;
+enum gic_version gic_hw_version(void)
+{
+ return gic_hw_ops->info->hw_version;
}
unsigned int gic_number_lines(void)
{
- return gic.lines;
+ return gic_hw_ops->info->nr_lines;
}
void gic_save_state(struct vcpu *v)
{
- int i;
ASSERT(!local_irq_is_enabled());
/* No need for spinlocks here because interrupts are disabled around
* this call and it only accesses struct vcpu fields that cannot be
* accessed simultaneously by another pCPU.
*/
- for ( i=0; i<nr_lrs; i++)
- v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
v->arch.lr_mask = this_cpu(lr_mask);
- v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
- v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
- /* Disable until next VCPU scheduled */
- writel_relaxed(0, GICH + GICH_HCR);
+ gic_hw_ops->save_state(v);
isb();
}
void gic_restore_state(struct vcpu *v)
{
- int i;
ASSERT(!local_irq_is_enabled());
if ( is_idle_vcpu(v) )
return;
this_cpu(lr_mask) = v->arch.lr_mask;
- for ( i=0; i<nr_lrs; i++)
- writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
- writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
- writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
- writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
+ gic_hw_ops->restore_state(v);
+
isb();
gic_restore_pending_irqs(v);
}
-static void gic_irq_enable(struct irq_desc *desc)
-{
- int irq = desc->irq;
- unsigned long flags;
-
- ASSERT(spin_is_locked(&desc->lock));
-
- spin_lock_irqsave(&gic.lock, flags);
- desc->status &= ~IRQ_DISABLED;
- dsb(sy);
- writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
- spin_unlock_irqrestore(&gic.lock, flags);
-}
-
-static void gic_irq_disable(struct irq_desc *desc)
-{
- int irq = desc->irq;
- unsigned long flags;
-
- ASSERT(spin_is_locked(&desc->lock));
-
- spin_lock_irqsave(&gic.lock, flags);
- /* Disable routing */
- writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
- desc->status |= IRQ_DISABLED;
- spin_unlock_irqrestore(&gic.lock, flags);
-}
-
-static unsigned int gic_irq_startup(struct irq_desc *desc)
-{
- gic_irq_enable(desc);
-
- return 0;
-}
-
-static void gic_irq_shutdown(struct irq_desc *desc)
-{
- gic_irq_disable(desc);
-}
-
-static void gic_irq_ack(struct irq_desc *desc)
-{
- /* No ACK -- reading IAR has done this for us */
-}
-
-static void gic_host_irq_end(struct irq_desc *desc)
-{
- int irq = desc->irq;
- /* Lower the priority */
- writel_relaxed(irq, GICC + GICC_EOIR);
- /* Deactivate */
- writel_relaxed(irq, GICC + GICC_DIR);
-}
-
-static void gic_guest_irq_end(struct irq_desc *desc)
-{
- int irq = desc->irq;
- /* Lower the priority of the IRQ */
- writel_relaxed(irq, GICC + GICC_EOIR);
- /* Deactivation happens in maintenance interrupt / via GICV */
-}
-
-static void gic_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
-{
- BUG();
-}
-
-/* XXX different for level vs edge */
-static hw_irq_controller gic_host_irq_type = {
- .typename = "gic",
- .startup = gic_irq_startup,
- .shutdown = gic_irq_shutdown,
- .enable = gic_irq_enable,
- .disable = gic_irq_disable,
- .ack = gic_irq_ack,
- .end = gic_host_irq_end,
- .set_affinity = gic_irq_set_affinity,
-};
-static hw_irq_controller gic_guest_irq_type = {
- .typename = "gic",
- .startup = gic_irq_startup,
- .shutdown = gic_irq_shutdown,
- .enable = gic_irq_enable,
- .disable = gic_irq_disable,
- .ack = gic_irq_ack,
- .end = gic_guest_irq_end,
- .set_affinity = gic_irq_set_affinity,
-};
-
/*
- * - needs to be called with a valid cpu_mask, ie each cpu in the mask has
+ * needs to be called with a valid cpu_mask, ie each cpu in the mask has
* already called gic_cpu_init
* - desc.lock must be held
* - arch.type must be valid (i.e != DT_IRQ_TYPE_INVALID)
@@ -231,37 +103,7 @@ static void gic_set_irq_properties(struct irq_desc *desc,
const cpumask_t *cpu_mask,
unsigned int priority)
{
- volatile unsigned char *bytereg;
- uint32_t cfg, edgebit;
- unsigned int mask;
- unsigned int irq = desc->irq;
- unsigned int type = desc->arch.type;
-
- ASSERT(type != DT_IRQ_TYPE_INVALID);
- ASSERT(spin_is_locked(&desc->lock));
-
- spin_lock(&gic.lock);
-
- mask = gic_cpu_mask(cpu_mask);
-
- /* Set edge / level */
- cfg = readl_relaxed(GICD + GICD_ICFGR + (irq / 16) * 4);
- edgebit = 2u << (2 * (irq % 16));
- if ( type & DT_IRQ_TYPE_LEVEL_MASK )
- cfg &= ~edgebit;
- else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
- cfg |= edgebit;
- writel_relaxed(cfg, GICD + GICD_ICFGR + (irq / 16) * 4);
-
- /* Set target CPU mask (RAZ/WI on uniprocessor) */
- bytereg = (unsigned char *) (GICD + GICD_ITARGETSR);
- bytereg[irq] = mask;
-
- /* Set priority */
- bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR);
- bytereg[irq] = priority;
-
- spin_unlock(&gic.lock);
+ gic_hw_ops->set_irq_properties(desc, cpu_mask, priority);
}
/* Program the GIC to route an interrupt to the host (i.e. Xen)
@@ -271,11 +113,11 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask,
unsigned int priority)
{
ASSERT(priority <= 0xff); /* Only 8 bits of priority */
- ASSERT(desc->irq < gic.lines);/* Can't route interrupts that don't exist */
+ ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */
ASSERT(desc->status & IRQ_DISABLED);
ASSERT(spin_is_locked(&desc->lock));
- desc->handler = &gic_host_irq_type;
+ desc->handler = gic_hw_ops->gic_host_irq_type;
gic_set_irq_properties(desc, cpu_mask, priority);
}
@@ -289,7 +131,7 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc,
struct pending_irq *p;
ASSERT(spin_is_locked(&desc->lock));
- desc->handler = &gic_guest_irq_type;
+ desc->handler = gic_hw_ops->gic_guest_irq_type;
desc->status |= IRQ_GUEST;
gic_set_irq_properties(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ);
@@ -299,102 +141,6 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc,
p->desc = desc;
}
-static void __init gic_dist_init(void)
-{
- uint32_t type;
- uint32_t cpumask;
- int i;
-
- cpumask = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
- cpumask |= cpumask << 8;
- cpumask |= cpumask << 16;
-
- /* Disable the distributor */
- writel_relaxed(0, GICD + GICD_CTLR);
-
- type = readl_relaxed(GICD + GICD_TYPER);
- gic.lines = 32 * ((type & GICD_TYPE_LINES) + 1);
- gic.cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5);
- printk("GIC: %d lines, %d cpu%s%s (IID %8.8x).\n",
- gic.lines, gic.cpus, (gic.cpus == 1) ? "" : "s",
- (type & GICD_TYPE_SEC) ? ", secure" : "",
- readl_relaxed(GICD + GICD_IIDR));
-
- /* Default all global IRQs to level, active low */
- for ( i = 32; i < gic.lines; i += 16 )
- writel_relaxed(0x0, GICD + GICD_ICFGR + (i / 16) * 4);
-
- /* Route all global IRQs to this CPU */
- for ( i = 32; i < gic.lines; i += 4 )
- writel_relaxed(cpumask, GICD + GICD_ITARGETSR + (i / 4) * 4);
-
- /* Default priority for global interrupts */
- for ( i = 32; i < gic.lines; i += 4 )
- writel_relaxed (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
- GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
- GICD + GICD_IPRIORITYR + (i / 4) * 4);
-
- /* Disable all global interrupts */
- for ( i = 32; i < gic.lines; i += 32 )
- writel_relaxed(~0x0, GICD + GICD_ICENABLER + (i / 32) * 4);
-
- /* Turn on the distributor */
- writel_relaxed(GICD_CTL_ENABLE, GICD + GICD_CTLR);
-}
-
-static void __cpuinit gic_cpu_init(void)
-{
- int i;
-
- this_cpu(gic_cpu_id) = readl_relaxed(GICD + GICD_ITARGETSR) & 0xff;
-
- /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
- * even though they are controlled with GICD registers, they must
- * be set up here with the other per-cpu state. */
- writel_relaxed(0xffff0000, GICD + GICD_ICENABLER); /* Disable all PPI */
- writel_relaxed(0x0000ffff, GICD + GICD_ISENABLER); /* Enable all SGI */
-
- /* Set SGI priorities */
- for (i = 0; i < 16; i += 4)
- writel_relaxed(GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 |
- GIC_PRI_IPI << 8 | GIC_PRI_IPI,
- GICD + GICD_IPRIORITYR + (i / 4) * 4);
- /* Set PPI priorities */
- for (i = 16; i < 32; i += 4)
- writel_relaxed(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
- GIC_PRI_IRQ << 8 | GIC_PRI_IRQ,
- GICD + GICD_IPRIORITYR + (i / 4) * 4);
-
- /* Local settings: interface controller */
- /* Don't mask by priority */
- writel_relaxed(0xff, GICC + GICC_PMR);
- /* Finest granularity of priority */
- writel_relaxed(0x0, GICC + GICC_BPR);
- /* Turn on delivery */
- writel_relaxed(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC + GICC_CTLR);
-}
-
-static void gic_cpu_disable(void)
-{
- writel_relaxed(0x0, GICC + GICC_CTLR);
-}
-
-static void __cpuinit gic_hyp_init(void)
-{
- uint32_t vtr;
-
- vtr = readl_relaxed(GICH + GICH_VTR);
- nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
-
- writel_relaxed(GICH_MISR_EOI, GICH + GICH_MISR);
- this_cpu(lr_mask) = 0ULL;
-}
-
-static void __cpuinit gic_hyp_disable(void)
-{
- writel_relaxed(0, GICH + GICH_HCR);
-}
-
int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
unsigned int *out_hwirq,
unsigned int *out_type)
@@ -418,108 +164,7 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
/* Set up the GIC */
void __init gic_init(void)
{
- static const struct dt_device_match gic_ids[] __initconst =
- {
- DT_MATCH_GIC,
- { /* sentinel */ },
- };
- struct dt_device_node *node;
- int res;
-
- node = dt_find_interrupt_controller(gic_ids);
- if ( !node )
- panic("Unable to find compatible GIC in the device tree");
-
- dt_device_set_used_by(node, DOMID_XEN);
-
- res = dt_device_get_address(node, 0, &gic.dbase, NULL);
- if ( res || !gic.dbase || (gic.dbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the distributor");
-
- res = dt_device_get_address(node, 1, &gic.cbase, NULL);
- if ( res || !gic.cbase || (gic.cbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the CPU");
-
- res = dt_device_get_address(node, 2, &gic.hbase, NULL);
- if ( res || !gic.hbase || (gic.hbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the hypervisor");
-
- res = dt_device_get_address(node, 3, &gic.vbase, NULL);
- if ( res || !gic.vbase || (gic.vbase & ~PAGE_MASK) )
- panic("GIC: Cannot find a valid address for the virtual CPU");
-
- res = platform_get_irq(node, 0);
- if ( res < 0 )
- panic("GIC: Cannot find the maintenance IRQ");
- gic.maintenance_irq = res;
-
- /* Set the GIC as the primary interrupt controller */
- dt_interrupt_controller = node;
-
- /* TODO: Add check on distributor, cpu size */
-
- printk("GIC initialization:\n"
- " gic_dist_addr=%"PRIpaddr"\n"
- " gic_cpu_addr=%"PRIpaddr"\n"
- " gic_hyp_addr=%"PRIpaddr"\n"
- " gic_vcpu_addr=%"PRIpaddr"\n"
- " gic_maintenance_irq=%u\n",
- gic.dbase, gic.cbase, gic.hbase, gic.vbase,
- gic.maintenance_irq);
-
- if ( (gic.dbase & ~PAGE_MASK) || (gic.cbase & ~PAGE_MASK) ||
- (gic.hbase & ~PAGE_MASK) || (gic.vbase & ~PAGE_MASK) )
- panic("GIC interfaces not page aligned");
-
- gic.map_dbase = ioremap_nocache(gic.dbase, PAGE_SIZE);
- if ( !gic.map_dbase )
- panic("Failed to ioremap for GIC distributor\n");
-
- if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 0x10);
- else
- gic.map_cbase = ioremap_nocache(gic.cbase, PAGE_SIZE * 2);
-
- if ( !gic.map_cbase )
- panic("Failed to ioremap for GIC CPU interface\n");
-
- gic.map_hbase = ioremap_nocache(gic.hbase, PAGE_SIZE);
- if ( !gic.map_hbase )
- panic("Failed to ioremap for GIC Virtual interface\n");
-
- /* Global settings: interrupt distributor */
- spin_lock_init(&gic.lock);
- spin_lock(&gic.lock);
-
- gic_dist_init();
- gic_cpu_init();
- gic_hyp_init();
-
- spin_unlock(&gic.lock);
-}
-
-static void send_SGI(const cpumask_t *cpu_mask, enum gic_sgi sgi,
- enum gic_sgi_mode irqmode)
-{
- unsigned int mask = 0;
-
- switch ( irqmode )
- {
- case SGI_TARGET_OTHERS:
- writel_relaxed(GICD_SGI_TARGET_OTHERS | sgi, GICD + GICD_SGIR);
- break;
- case SGI_TARGET_SELF:
- writel_relaxed(GICD_SGI_TARGET_SELF | sgi, GICD + GICD_SGIR);
- break;
- case SGI_TARGET_LIST:
- mask = gic_cpu_mask(cpu_mask);
- writel_relaxed(GICD_SGI_TARGET_LIST |
- (mask << GICD_SGI_TARGET_SHIFT) | sgi,
- GICD + GICD_SGIR);
- break;
- default:
- BUG();
- }
+ gicv2_init();
}
void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
@@ -532,12 +177,11 @@ void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
dsb(sy);
- send_SGI(&online_mask, sgi, SGI_TARGET_LIST);
+ gic_hw_ops->send_SGI(&online_mask, sgi, SGI_TARGET_LIST);
}
void send_SGI_one(unsigned int cpu, enum gic_sgi sgi)
{
- ASSERT(cpu < NR_GIC_CPU_IF); /* Targets bitmap only supports 8 CPUs */
send_SGI_mask(cpumask_of(cpu), sgi);
}
@@ -547,7 +191,7 @@ void send_SGI_self(enum gic_sgi sgi)
dsb(sy);
- send_SGI(cpumask_of(smp_processor_id()), sgi, SGI_TARGET_SELF);
+ gic_hw_ops->send_SGI(cpumask_of(smp_processor_id()), sgi, SGI_TARGET_SELF);
}
void send_SGI_allbutself(enum gic_sgi sgi)
@@ -558,7 +202,7 @@ void send_SGI_allbutself(enum gic_sgi sgi)
cpumask_andnot(&all_others_mask, &cpu_possible_map, cpumask_of(smp_processor_id()));
dsb(sy);
- send_SGI(&all_others_mask, sgi, SGI_TARGET_OTHERS);
+ gic_hw_ops->send_SGI(&all_others_mask, sgi, SGI_TARGET_OTHERS);
}
void smp_send_state_dump(unsigned int cpu)
@@ -569,10 +213,7 @@ void smp_send_state_dump(unsigned int cpu)
/* Set up the per-CPU parts of the GIC for a secondary CPU */
void __cpuinit gic_init_secondary_cpu(void)
{
- spin_lock(&gic.lock);
- gic_cpu_init();
- gic_hyp_init();
- spin_unlock(&gic.lock);
+ gic_hw_ops->secondary_init();
}
/* Shut down the per-CPU GIC interface */
@@ -580,28 +221,15 @@ void gic_disable_cpu(void)
{
ASSERT(!local_irq_is_enabled());
- spin_lock(&gic.lock);
- gic_cpu_disable();
- gic_hyp_disable();
- spin_unlock(&gic.lock);
+ gic_hw_ops->disable_interface();
}
static inline void gic_set_lr(int lr, struct pending_irq *p,
- unsigned int state)
+ unsigned int state)
{
- uint32_t lr_val;
-
ASSERT(!local_irq_is_enabled());
- BUG_ON(lr >= nr_lrs);
- BUG_ON(lr < 0);
- BUG_ON(state & ~(GICH_LR_STATE_MASK<<GICH_LR_STATE_SHIFT));
-
- lr_val = state | (GIC_PRI_TO_GUEST(p->priority) << GICH_LR_PRIORITY_SHIFT) |
- ((p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT);
- if ( p->desc != NULL )
- lr_val |= GICH_LR_HW | (p->desc->irq << GICH_LR_PHYSICAL_SHIFT);
- writel_relaxed(lr_val, GICH + GICH_LR + lr * 4);
+ gic_hw_ops->update_lr(lr, p, state);
set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status);
clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
@@ -668,6 +296,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq,
unsigned int priority)
{
int i;
+ unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
ASSERT(spin_is_locked(&v->arch.vgic.lock));
@@ -687,36 +316,43 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq,
static void gic_update_one_lr(struct vcpu *v, int i)
{
struct pending_irq *p;
- uint32_t lr;
int irq;
+ struct gic_lr lr_val;
ASSERT(spin_is_locked(&v->arch.vgic.lock));
ASSERT(!local_irq_is_enabled());
- lr = readl_relaxed(GICH + GICH_LR + i * 4);
- irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
+ gic_hw_ops->read_lr(i, &lr_val);
+ irq = lr_val.virq;
p = irq_to_pending(v, irq);
- if ( lr & GICH_LR_ACTIVE )
+ if ( lr_val.state & GICH_LR_ACTIVE )
{
set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status);
if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) &&
test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) )
{
if ( p->desc == NULL )
- writel_relaxed(lr | GICH_LR_PENDING, GICH + GICH_LR + i * 4);
+ {
+ lr_val.state |= GICH_LR_PENDING;
+ gic_hw_ops->write_lr(i, &lr_val);
+ }
else
gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n",
irq, v->domain->domain_id, v->vcpu_id, i);
}
- } else if ( lr & GICH_LR_PENDING ) {
+ }
+ else if ( lr_val.state & GICH_LR_PENDING )
+ {
int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status);
#ifdef GIC_DEBUG
if ( q )
gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n",
irq, v->domain->domain_id, v->vcpu_id, i);
#endif
- } else {
- writel_relaxed(0, GICH + GICH_LR + i * 4);
+ }
+ else
+ {
+ gic_hw_ops->clear_lr(i);
clear_bit(i, &this_cpu(lr_mask));
if ( p->desc != NULL )
@@ -736,6 +372,7 @@ void gic_clear_lrs(struct vcpu *v)
{
int i = 0;
unsigned long flags;
+ unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
if ( is_idle_vcpu(v) )
return;
@@ -753,11 +390,13 @@ void gic_clear_lrs(struct vcpu *v)
static void gic_restore_pending_irqs(struct vcpu *v)
{
- int lr = 0, lrs = nr_lrs;
+ int lr = 0, lrs;
struct pending_irq *p, *t, *p_r;
struct list_head *inflight_r;
unsigned long flags;
+ unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
+ lrs = nr_lrs;
spin_lock_irqsave(&v->arch.vgic.lock, flags);
if ( list_empty(&v->arch.vgic.lr_pending) )
@@ -818,14 +457,13 @@ void gic_clear_pending_irqs(struct vcpu *v)
int gic_events_need_delivery(void)
{
- int mask_priority, lrs = nr_lrs;
+ int mask_priority, lrs = gic_hw_ops->info->nr_lrs;
int max_priority = 0xff, active_priority = 0xff;
struct vcpu *v = current;
struct pending_irq *p;
unsigned long flags;
- mask_priority = (readl_relaxed(GICH + GICH_VMCR)
- >> GICH_VMCR_PRIORITY_SHIFT) & GICH_VMCR_PRIORITY_MASK;
+ mask_priority = gic_hw_ops->read_vmcr_priority();
mask_priority = mask_priority << 3;
spin_lock_irqsave(&v->arch.vgic.lock, flags);
@@ -861,23 +499,23 @@ int gic_events_need_delivery(void)
void gic_inject(void)
{
- uint32_t hcr;
ASSERT(!local_irq_is_enabled());
gic_restore_pending_irqs(current);
- hcr = readl_relaxed(GICH + GICH_HCR);
-
if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() )
- writel_relaxed(hcr | GICH_HCR_UIE, GICH + GICH_HCR);
+ gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 1);
else
- writel_relaxed(hcr & ~GICH_HCR_UIE, GICH + GICH_HCR);
+ gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 0);
}
static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
{
/* Lower the priority */
- writel_relaxed(sgi, GICC + GICC_EOIR);
+ struct irq_desc *desc = irq_to_desc(sgi);
+
+ /* Lower the priority */
+ gic_hw_ops->eoi_irq(desc);
switch (sgi)
{
@@ -896,19 +534,17 @@ static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi)
}
/* Deactivate */
- writel_relaxed(sgi, GICC + GICC_DIR);
+ gic_hw_ops->deactivate_irq(desc);
}
/* Accept an interrupt from the GIC and dispatch its handler */
void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
{
- uint32_t intack;
unsigned int irq;
-
do {
- intack = readl_relaxed(GICC + GICC_IAR);
- irq = intack & GICC_IA_IRQ;
+ /* Reading IRQ will ACK it */
+ irq = gic_hw_ops->read_irq();
if ( likely(irq >= 16 && irq < 1021) )
{
@@ -930,49 +566,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_fiq)
int gicv_setup(struct domain *d)
{
- int ret;
-
- /*
- * The hardware domain gets the hardware address.
- * Guests get the virtual platform layout.
- */
- if ( is_hardware_domain(d) )
- {
- d->arch.vgic.dbase = gic.dbase;
- d->arch.vgic.cbase = gic.cbase;
- }
- else
- {
- d->arch.vgic.dbase = GUEST_GICD_BASE;
- d->arch.vgic.cbase = GUEST_GICC_BASE;
- }
-
- d->arch.vgic.nr_lines = 0;
-
- /*
- * Map the gic virtual cpu interface in the gic cpu interface
- * region of the guest.
- *
- * The second page is always mapped at +4K irrespective of the
- * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
- */
- ret = map_mmio_regions(d, d->arch.vgic.cbase,
- d->arch.vgic.cbase + PAGE_SIZE - 1,
- gic.vbase);
- if (ret)
- return ret;
-
- if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
- d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
- gic.vbase + PAGE_SIZE);
- else
- ret = map_mmio_regions(d, d->arch.vgic.cbase + PAGE_SIZE,
- d->arch.vgic.cbase + (2 * PAGE_SIZE) - 1,
- gic.vbase + 16*PAGE_SIZE);
-
- return ret;
-
+ return gic_hw_ops->gicv_setup(d);
}
static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs)
@@ -987,18 +581,10 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r
void gic_dump_info(struct vcpu *v)
{
- int i;
struct pending_irq *p;
printk("GICH_LRs (vcpu %d) mask=%"PRIx64"\n", v->vcpu_id, v->arch.lr_mask);
- if ( v == current )
- {
- for ( i = 0; i < nr_lrs; i++ )
- printk(" HW_LR[%d]=%x\n", i, readl_relaxed(GICH + GICH_LR + i * 4));
- } else {
- for ( i = 0; i < nr_lrs; i++ )
- printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
- }
+ gic_hw_ops->dump_state(v);
list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight )
{
@@ -1009,12 +595,11 @@ void gic_dump_info(struct vcpu *v)
{
printk("Pending irq=%d\n", p->irq);
}
-
}
void __cpuinit init_maintenance_interrupt(void)
{
- request_irq(gic.maintenance_irq, 0, maintenance_interrupt,
+ request_irq(gic_hw_ops->info->maintenance_irq, 0, maintenance_interrupt,
"irq-maintenance", NULL);
}
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 7fa3b95..11a7c1d 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -114,24 +114,6 @@
#define GICH_MISR_VGRP1E (1 << 6)
#define GICH_MISR_VGRP1D (1 << 7)
-#define GICH_LR_VIRTUAL_MASK 0x3ff
-#define GICH_LR_VIRTUAL_SHIFT 0
-#define GICH_LR_PHYSICAL_MASK 0x3ff
-#define GICH_LR_PHYSICAL_SHIFT 10
-#define GICH_LR_STATE_MASK 0x3
-#define GICH_LR_STATE_SHIFT 28
-#define GICH_LR_PRIORITY_SHIFT 23
-#define GICH_LR_MAINTENANCE_IRQ (1<<19)
-#define GICH_LR_PENDING (1<<28)
-#define GICH_LR_ACTIVE (1<<29)
-#define GICH_LR_GRP1 (1<<30)
-#define GICH_LR_HW (1<<31)
-#define GICH_LR_CPUID_SHIFT 9
-#define GICH_VTR_NRLRGS 0x3f
-
-#define GICH_VMCR_PRIORITY_MASK 0x1f
-#define GICH_VMCR_PRIORITY_SHIFT 27
-
/*
* The minimum GICC_BPR is required to be in the range 0-3. We set
* GICC_BPR to 0 but we must expect that it might be 3. This means we
@@ -155,6 +137,8 @@
#define GIC_PRI_TO_GUEST(pri) (pri >> 3) /* GICH_LR and GICH_VMCR only support
5 bits for guest irq priority */
+#define GICH_LR_PENDING 1
+#define GICH_LR_ACTIVE 2
#ifndef __ASSEMBLY__
#include <xen/device_tree.h>
@@ -163,6 +147,28 @@
#define DT_MATCH_GIC DT_MATCH_COMPATIBLE("arm,cortex-a15-gic"), \
DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
+/*
+ * Decode LR register content.
+ * The LR register format is different for GIC HW version
+ */
+struct gic_lr {
+ /* Physical IRQ */
+ uint32_t pirq;
+ /* Virtual IRQ */
+ uint32_t virq;
+ uint8_t priority;
+ uint8_t state;
+ uint8_t hw_status;
+ uint8_t grp;
+};
+
+enum gic_version {
+ GIC_V2,
+};
+
+extern enum gic_version gic_hw_version(void);
+extern void gicv2_init(void);
+
extern int domain_vgic_init(struct domain *d);
extern void domain_vgic_free(struct domain *d);
@@ -234,6 +240,70 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
unsigned int *out_hwirq, unsigned int *out_type);
void gic_clear_lrs(struct vcpu *v);
+struct gic_info {
+ /* GIC version */
+ enum gic_version hw_version;
+ /* Number of GIC lines supported */
+ unsigned int nr_lines;
+ /* Number of LR registers */
+ uint8_t nr_lrs;
+ /* Maintenance irq number */
+ unsigned int maintenance_irq;
+};
+
+struct gic_hw_operations {
+ /* Hold GIC HW information */
+ const struct gic_info *info;
+ /* Save GIC registers */
+ void (*save_state)(struct vcpu *);
+ /* Restore GIC registers */
+ void (*restore_state)(const struct vcpu *);
+ /* Dump GIC LR register information */
+ void (*dump_state)(const struct vcpu *);
+ /* Map MMIO region of GIC */
+ int (*gicv_setup)(struct domain *);
+
+ /* hw_irq_controller to enable/disable/eoi host irq */
+ hw_irq_controller *gic_host_irq_type;
+
+ /* hw_irq_controller to enable/disable/eoi guest irq */
+ hw_irq_controller *gic_guest_irq_type;
+
+ /* End of Interrupt */
+ void (*eoi_irq)(struct irq_desc *irqd);
+ /* Deactivate/reduce priority of irq */
+ void (*deactivate_irq)(struct irq_desc *irqd);
+ /* Read IRQ id and Ack */
+ unsigned int (*read_irq)(void);
+ /* Set IRQ property */
+ void (*set_irq_properties)(struct irq_desc *desc,
+ const cpumask_t *cpu_mask,
+ unsigned int priority);
+ /* Send SGI */
+ void (*send_SGI)(const cpumask_t *online_mask,
+ enum gic_sgi sgi, enum gic_sgi_mode irqmode);
+ /* Disable CPU physical and virtual interfaces */
+ void (*disable_interface)(void);
+ /* Update LR register with state and priority */
+ void (*update_lr)(int lr, const struct pending_irq *pending_irq,
+ unsigned int state);
+ /* Update HCR status register */
+ void (*update_hcr_status)(uint32_t flag, bool_t set);
+ /* Clear LR register */
+ void (*clear_lr)(int lr);
+ /* Read LR register and populate gic_lr structure */
+ void (*read_lr)(int lr, struct gic_lr *);
+ /* Write LR register from gic_lr structure */
+ void (*write_lr)(int lr, const struct gic_lr *);
+ /* Read VMCR priority */
+ unsigned int (*read_vmcr_priority)(void);
+ /* Secondary CPU init */
+ int (*secondary_init)(void);
+};
+
+void register_gic_ops(const struct gic_hw_operations *ops);
+extern void update_cpu_lr_mask(void);
+
#endif /* __ASSEMBLY__ */
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 13:36 ` [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality vijay.kilari
@ 2014-06-12 16:26 ` Stefano Stabellini
2014-06-12 22:46 ` Julien Grall
2014-06-12 22:44 ` Julien Grall
` (2 subsequent siblings)
3 siblings, 1 reply; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 16:26 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> GIC driver contains both generic and hardware specific low
> level functionality in gic.c file.
>
> With this patch, low level functionality is moved to separate
> file gic-v2.c and generic code is kept in gic.c file
>
> Callbacks are registered by low level driver with generic driver
> and are called whereever required.
>
> The locking mechanism is not changed.
>
> This helps to separate generic and hardware functionality
> and implement future hardware version drivers.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
[...]
> +static void gicv2_irq_enable(struct irq_desc *desc)
> +{
> + unsigned long flags;
> + int irq = desc->irq;
> +
> + spin_lock_irqsave(&gicv2.lock, flags);
> + desc->status &= ~IRQ_DISABLED;
> + dsb(sy);
> + /* Enable routing */
> + writel_relaxed((1u << (irq % 32)), GICD + GICD_ISENABLER + (irq / 32) * 4);
> + spin_unlock_irqrestore(&gicv2.lock, flags);
> +}
> +
> +static void gicv2_irq_disable(struct irq_desc *desc)
> +{
> + unsigned long flags;
> + int irq = desc->irq;
> +
> + spin_lock_irqsave(&gicv2.lock, flags);
> + /* Disable routing */
> + writel_relaxed(1u << (irq % 32), GICD + GICD_ICENABLER + (irq / 32) * 4);
> + desc->status |= IRQ_DISABLED;
> + spin_unlock_irqrestore(&gicv2.lock, flags);
> +}
That's better: same locking as before.
At this point you should keep the:
ASSERT(spin_is_locked(&desc->lock));
that we currently have.
With that change:
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 16:26 ` Stefano Stabellini
@ 2014-06-12 22:46 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-12 22:46 UTC (permalink / raw)
To: Stefano Stabellini, vijay.kilari
Cc: Ian.Campbell, Prasun.Kapoor, Vijaya Kumar K, tim, xen-devel,
stefano.stabellini
On 12/06/14 17:26, Stefano Stabellini wrote:
> That's better: same locking as before.
> At this point you should keep the:
>
> ASSERT(spin_is_locked(&desc->lock));
+1 this assert is very handy in debug mode to know if the caller
correctly take the desc lock.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 13:36 ` [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality vijay.kilari
2014-06-12 16:26 ` Stefano Stabellini
@ 2014-06-12 22:44 ` Julien Grall
2014-06-13 8:30 ` Ian Campbell
2014-06-19 9:56 ` Vijay Kilari
2014-06-15 17:47 ` Julien Grall
2014-06-17 12:15 ` Ian Campbell
3 siblings, 2 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-12 22:44 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
In my answer I prefixed every comments I made on V4 but you didn't
address/answer by "From V4".
I spend lots of time to review carefully every version of series. Please
do the same by reading carefully and addressing or answering to our
comments. Thank you.
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> GIC driver contains both generic and hardware specific low
> level functionality in gic.c file.
>
> With this patch, low level functionality is moved to separate
> file gic-v2.c and generic code is kept in gic.c file
>
> Callbacks are registered by low level driver with generic driver
> and are called whereever required.
Again, whereever doesn't exist in english. What did you intend to mean?
"When it's"?
> +static int gicv_v2_init(struct domain *d)
> +{
> + int ret;
> +
> + /*
> + * Domain 0 gets the hardware address.
> + * Guests get the virtual platform layout.
> + */
> + if ( d->domain_id == 0 )
From v4:
Some of this code (here is one of the example) is modified while you are
sending new version of your patch series.
The original code (i.e in gic.c) was:
if ( is_hardware_domain(d) )
{
d->arch.vgic.dbase = gicv2.dbase;
d->arch.vgic.cbase = gicv2.cbase;
}
Now, you've moved the code and we end up to:
if ( d->domain_id == 0 )
{
d->arch.vgic.dbase = gicv2.dbase;
d->arch.vgic.cbase = gicv2.cbase;
}
[..]
> +void update_cpu_lr_mask(void)
> +{
> + this_cpu(lr_mask) = 0ULL;
> +}
From v4:
The name of this function doesn't match what it does. Hence, it seems
you only call it during CPU initialization. Why can't you directly call
in the common function gic_init_secondary_cpu?
[..]
> static void gic_restore_pending_irqs(struct vcpu *v)
> {
> - int lr = 0, lrs = nr_lrs;
> + int lr = 0, lrs;
> struct pending_irq *p, *t, *p_r;
> struct list_head *inflight_r;
> unsigned long flags;
> + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
>
> + lrs = nr_lrs;
From V4:
Hmmm ... why did you create a temporary variable nr_lrs to set lrs just
after???
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 22:44 ` Julien Grall
@ 2014-06-13 8:30 ` Ian Campbell
2014-06-19 9:56 ` Vijay Kilari
1 sibling, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-13 8:30 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 23:44 +0100, Julien Grall wrote:
> Hi Vijay,
>
> In my answer I prefixed every comments I made on V4 but you didn't
> address/answer by "From V4".
>
> I spend lots of time to review carefully every version of series. Please
> do the same by reading carefully and addressing or answering to our
> comments. Thank you.
Yes, this is important. In particular if you disagree with a review
comment then it is important to answer and explain why rather than
simply not making the change.
> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> > From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >
> > GIC driver contains both generic and hardware specific low
> > level functionality in gic.c file.
> >
> > With this patch, low level functionality is moved to separate
> > file gic-v2.c and generic code is kept in gic.c file
> >
> > Callbacks are registered by low level driver with generic driver
> > and are called whereever required.
>
> Again, whereever doesn't exist in english. What did you intend to mean?
> "When it's"?
"wherever" is probably what he meant.
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 22:44 ` Julien Grall
2014-06-13 8:30 ` Ian Campbell
@ 2014-06-19 9:56 ` Vijay Kilari
2014-06-19 10:49 ` Julien Grall
1 sibling, 1 reply; 87+ messages in thread
From: Vijay Kilari @ 2014-06-19 9:56 UTC (permalink / raw)
To: Julien Grall
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On Fri, Jun 13, 2014 at 4:14 AM, Julien Grall <julien.grall@linaro.org> wrote:
> Hi Vijay,
>
> In my answer I prefixed every comments I made on V4 but you didn't
> address/answer by "From V4".
>> static void gic_restore_pending_irqs(struct vcpu *v)
>> {
>> - int lr = 0, lrs = nr_lrs;
>> + int lr = 0, lrs;
>> struct pending_irq *p, *t, *p_r;
>> struct list_head *inflight_r;
>> unsigned long flags;
>> + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
>>
>> + lrs = nr_lrs;
>
>
> From V4:
>
> Hmmm ... why did you create a temporary variable nr_lrs to set lrs just
> after???
This function uses both global variable nr_lrs and local variable lrs.
With this patch, nr_lrs is replaced with gic_hw_ops->info->nr_lrs.
So variable nr_lrs is now made local.
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-19 9:56 ` Vijay Kilari
@ 2014-06-19 10:49 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-19 10:49 UTC (permalink / raw)
To: Vijay Kilari
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On 06/19/2014 10:56 AM, Vijay Kilari wrote:
> On Fri, Jun 13, 2014 at 4:14 AM, Julien Grall <julien.grall@linaro.org> wrote:
>> Hi Vijay,
>>
>> In my answer I prefixed every comments I made on V4 but you didn't
>> address/answer by "From V4".
>>> static void gic_restore_pending_irqs(struct vcpu *v)
>>> {
>>> - int lr = 0, lrs = nr_lrs;
>>> + int lr = 0, lrs;
>>> struct pending_irq *p, *t, *p_r;
>>> struct list_head *inflight_r;
>>> unsigned long flags;
>>> + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
>>>
>>> + lrs = nr_lrs;
>>
>>
>> From V4:
>>
>> Hmmm ... why did you create a temporary variable nr_lrs to set lrs just
>> after???
>
> This function uses both global variable nr_lrs and local variable lrs.
> With this patch, nr_lrs is replaced with gic_hw_ops->info->nr_lrs.
> So variable nr_lrs is now made local.
>
Can you just do
unsigned int nr_lrs = gic_hw_ops->info->nr_lrs;
int lrs = nr_lrs;
I found this way less confusing.
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 13:36 ` [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality vijay.kilari
2014-06-12 16:26 ` Stefano Stabellini
2014-06-12 22:44 ` Julien Grall
@ 2014-06-15 17:47 ` Julien Grall
2014-06-17 12:15 ` Ian Campbell
3 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 17:47 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> /*
> - * - needs to be called with a valid cpu_mask, ie each cpu in the mask has
> + * needs to be called with a valid cpu_mask, ie each cpu in the mask has
> * already called gic_cpu_init
> * - desc.lock must be held
> * - arch.type must be valid (i.e != DT_IRQ_TYPE_INVALID)
> @@ -231,37 +103,7 @@ static void gic_set_irq_properties(struct irq_desc *desc,
> const cpumask_t *cpu_mask,
> unsigned int priority)
> {
[..]
> - ASSERT(type != DT_IRQ_TYPE_INVALID);
> - ASSERT(spin_is_locked(&desc->lock));
Why did you drop these 2 ASSERTS? They should stay to help developer
debugging wrong code...
Hence, it validates the assertion in the comments (see above).
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality
2014-06-12 13:36 ` [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality vijay.kilari
` (2 preceding siblings ...)
2014-06-15 17:47 ` Julien Grall
@ 2014-06-17 12:15 ` Ian Campbell
3 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:15 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> GIC driver contains both generic and hardware specific low
> level functionality in gic.c file.
>
> With this patch, low level functionality is moved to separate
> file gic-v2.c and generic code is kept in gic.c file
>
> Callbacks are registered by low level driver with generic driver
> and are called whereever required.
>
> The locking mechanism is not changed.
>
> This helps to separate generic and hardware functionality
> and implement future hardware version drivers.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
I've no comments over and above what Stefano and Julien have already
said.
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (5 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 06/21] xen/arm: segregate and split GIC low level functionality vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 16:28 ` Stefano Stabellini
` (2 more replies)
2014-06-12 13:36 ` [PATCH v5 08/21] xen/arm: use device api to detect GIC version vijay.kilari
` (15 subsequent siblings)
22 siblings, 3 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
arch_domain in domain.h defines all the GIC registers
that needs to be saved/restored directly.
These GIC registers are GIC HW version specific. The number
of registers and size of registers varies with GIC version.
So move these registers to gic.h file and make a union of these
registers. This helps to define GIC HW version specific
structure to this union for later GIC versions.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/gic-v2.c | 14 +++++++-------
xen/include/asm-arm/domain.h | 5 +++--
xen/include/asm-arm/gic.h | 18 ++++++++++++++++++
3 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 9cf1dc8..8eb8f0b 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -111,10 +111,10 @@ static void gicv2_save_state(struct vcpu *v)
* accessed simultaneously by another pCPU.
*/
for ( i = 0; i < gicv2_info.nr_lrs; i++ )
- v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
+ v->arch.gic.v2.lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
- v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
- v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
+ v->arch.gic.v2.apr = readl_relaxed(GICH + GICH_APR);
+ v->arch.gic.v2.vmcr = readl_relaxed(GICH + GICH_VMCR);
/* Disable until next VCPU scheduled */
writel_relaxed(0, GICH + GICH_HCR);
}
@@ -124,10 +124,10 @@ static void gicv2_restore_state(const struct vcpu *v)
int i;
for ( i = 0; i < gicv2_info.nr_lrs; i++ )
- writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
+ writel_relaxed(v->arch.gic.v2.lr[i], GICH + GICH_LR + i * 4);
- writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
- writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
+ writel_relaxed(v->arch.gic.v2.apr, GICH + GICH_APR);
+ writel_relaxed(v->arch.gic.v2.vmcr, GICH + GICH_VMCR);
writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
}
@@ -144,7 +144,7 @@ static void gicv2_dump_state(const struct vcpu *v)
else
{
for ( i = 0; i < gicv2_info.nr_lrs; i++ )
- printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
+ printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic.v2.lr[i]);
}
}
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 36d82e2..591a825 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -8,6 +8,7 @@
#include <asm/p2m.h>
#include <asm/vfp.h>
#include <asm/mmio.h>
+#include <asm/gic.h>
#include <public/hvm/params.h>
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
@@ -263,8 +264,8 @@ struct arch_vcpu
uint32_t csselr;
register_t vmpidr;
- uint32_t gic_hcr, gic_vmcr, gic_apr;
- uint32_t gic_lr[64];
+ /* Holds gic context data */
+ union gic_state_data gic;
uint64_t lr_mask;
struct {
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 11a7c1d..978a968 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -148,6 +148,24 @@
DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
/*
+ * GICv2 register that needs to be saved/restored
+ * on VCPU context switch
+ */
+struct gic_v2 {
+ uint32_t hcr;
+ uint32_t vmcr;
+ uint32_t apr;
+ uint32_t lr[64];
+};
+
+/*
+ * Union to hold underlying hw version context information
+ */
+union gic_state_data {
+ struct gic_v2 v2;
+};
+
+/*
* Decode LR register content.
* The LR register format is different for GIC HW version
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver
2014-06-12 13:36 ` [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver vijay.kilari
@ 2014-06-12 16:28 ` Stefano Stabellini
2014-06-15 16:05 ` Julien Grall
2014-06-17 12:19 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 16:28 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> arch_domain in domain.h defines all the GIC registers
> that needs to be saved/restored directly.
>
> These GIC registers are GIC HW version specific. The number
> of registers and size of registers varies with GIC version.
> So move these registers to gic.h file and make a union of these
> registers. This helps to define GIC HW version specific
> structure to this union for later GIC versions.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> xen/arch/arm/gic-v2.c | 14 +++++++-------
> xen/include/asm-arm/domain.h | 5 +++--
> xen/include/asm-arm/gic.h | 18 ++++++++++++++++++
> 3 files changed, 28 insertions(+), 9 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> index 9cf1dc8..8eb8f0b 100644
> --- a/xen/arch/arm/gic-v2.c
> +++ b/xen/arch/arm/gic-v2.c
> @@ -111,10 +111,10 @@ static void gicv2_save_state(struct vcpu *v)
> * accessed simultaneously by another pCPU.
> */
> for ( i = 0; i < gicv2_info.nr_lrs; i++ )
> - v->arch.gic_lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
> + v->arch.gic.v2.lr[i] = readl_relaxed(GICH + GICH_LR + i * 4);
>
> - v->arch.gic_apr = readl_relaxed(GICH + GICH_APR);
> - v->arch.gic_vmcr = readl_relaxed(GICH + GICH_VMCR);
> + v->arch.gic.v2.apr = readl_relaxed(GICH + GICH_APR);
> + v->arch.gic.v2.vmcr = readl_relaxed(GICH + GICH_VMCR);
> /* Disable until next VCPU scheduled */
> writel_relaxed(0, GICH + GICH_HCR);
> }
> @@ -124,10 +124,10 @@ static void gicv2_restore_state(const struct vcpu *v)
> int i;
>
> for ( i = 0; i < gicv2_info.nr_lrs; i++ )
> - writel_relaxed(v->arch.gic_lr[i], GICH + GICH_LR + i * 4);
> + writel_relaxed(v->arch.gic.v2.lr[i], GICH + GICH_LR + i * 4);
>
> - writel_relaxed(v->arch.gic_apr, GICH + GICH_APR);
> - writel_relaxed(v->arch.gic_vmcr, GICH + GICH_VMCR);
> + writel_relaxed(v->arch.gic.v2.apr, GICH + GICH_APR);
> + writel_relaxed(v->arch.gic.v2.vmcr, GICH + GICH_VMCR);
> writel_relaxed(GICH_HCR_EN, GICH + GICH_HCR);
> }
>
> @@ -144,7 +144,7 @@ static void gicv2_dump_state(const struct vcpu *v)
> else
> {
> for ( i = 0; i < gicv2_info.nr_lrs; i++ )
> - printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic_lr[i]);
> + printk(" VCPU_LR[%d]=%x\n", i, v->arch.gic.v2.lr[i]);
> }
> }
>
> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> index 36d82e2..591a825 100644
> --- a/xen/include/asm-arm/domain.h
> +++ b/xen/include/asm-arm/domain.h
> @@ -8,6 +8,7 @@
> #include <asm/p2m.h>
> #include <asm/vfp.h>
> #include <asm/mmio.h>
> +#include <asm/gic.h>
> #include <public/hvm/params.h>
> #include <xen/serial.h>
> #include <xen/hvm/iommu.h>
> @@ -263,8 +264,8 @@ struct arch_vcpu
> uint32_t csselr;
> register_t vmpidr;
>
> - uint32_t gic_hcr, gic_vmcr, gic_apr;
> - uint32_t gic_lr[64];
> + /* Holds gic context data */
> + union gic_state_data gic;
> uint64_t lr_mask;
>
> struct {
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index 11a7c1d..978a968 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -148,6 +148,24 @@
> DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
>
> /*
> + * GICv2 register that needs to be saved/restored
> + * on VCPU context switch
> + */
> +struct gic_v2 {
> + uint32_t hcr;
> + uint32_t vmcr;
> + uint32_t apr;
> + uint32_t lr[64];
> +};
> +
> +/*
> + * Union to hold underlying hw version context information
> + */
> +union gic_state_data {
> + struct gic_v2 v2;
> +};
> +
> +/*
> * Decode LR register content.
> * The LR register format is different for GIC HW version
> */
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver
2014-06-12 13:36 ` [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver vijay.kilari
2014-06-12 16:28 ` Stefano Stabellini
@ 2014-06-15 16:05 ` Julien Grall
2014-06-17 12:19 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:05 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> arch_domain in domain.h defines all the GIC registers
> that needs to be saved/restored directly.
>
> These GIC registers are GIC HW version specific. The number
> of registers and size of registers varies with GIC version.
> So move these registers to gic.h file and make a union of these
> registers. This helps to define GIC HW version specific
> structure to this union for later GIC versions.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver
2014-06-12 13:36 ` [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver vijay.kilari
2014-06-12 16:28 ` Stefano Stabellini
2014-06-15 16:05 ` Julien Grall
@ 2014-06-17 12:19 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:19 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> arch_domain in domain.h defines all the GIC registers
> that needs to be saved/restored directly.
>
> These GIC registers are GIC HW version specific. The number
> of registers and size of registers varies with GIC version.
> So move these registers to gic.h file and make a union of these
> registers. This helps to define GIC HW version specific
> structure to this union for later GIC versions.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 08/21] xen/arm: use device api to detect GIC version
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (6 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 07/21] arm/xen: move GIC context data structure to gic driver vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-15 16:09 ` Julien Grall
2014-06-17 12:23 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 09/21] xen/arm: move vgic rank data to gic header file vijay.kilari
` (14 subsequent siblings)
22 siblings, 2 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Run through the device tree to detect
compatible GIC version and initialize GIC driver
Also change DT_MATCH_GIC to DT_MATCH_GIC_V2 to point
the GIC HW version to add later GIC versions
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/domain_build.c | 2 +-
xen/arch/arm/gic-v2.c | 27 ++++++++++++++++-----------
xen/arch/arm/gic.c | 24 +++++++++++++++++++++++-
xen/include/asm-arm/device.h | 1 +
xen/include/asm-arm/gic.h | 7 +++++--
5 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index ddbb88d..018f2f8 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -793,7 +793,7 @@ static int handle_node(struct domain *d, struct kernel_info *kinfo,
};
static const struct dt_device_match gic_matches[] __initconst =
{
- DT_MATCH_GIC,
+ DT_MATCH_GIC_V2,
{ /* sentinel */ },
};
static const struct dt_device_match timer_matches[] __initconst =
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 8eb8f0b..134815a 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -30,6 +30,7 @@
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
+#include <asm/device.h>
#include <asm/io.h>
#include <asm/gic.h>
@@ -574,20 +575,10 @@ const static struct gic_hw_operations gicv2_ops = {
};
/* Set up the GIC */
-void __init gicv2_init(void)
+static int __init gicv2_init(struct dt_device_node *node, const void *data)
{
- static const struct dt_device_match gic_ids[] __initconst =
- {
- DT_MATCH_GIC,
- { /* sentinel */ },
- };
- struct dt_device_node *node;
int res;
- node = dt_find_interrupt_controller(gic_ids);
- if ( !node )
- panic("GICv2: Unable to find compatible GIC in the device tree");
-
dt_device_set_used_by(node, DOMID_XEN);
res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);
@@ -657,8 +648,22 @@ void __init gicv2_init(void)
gicv2_info.hw_version = GIC_V2;
register_gic_ops(&gicv2_ops);
+
+ return 0;
}
+static const char * const gicv2_dt_compat[] __initconst =
+{
+ DT_MATCH_GIC_V2_STRING_1,
+ DT_MATCH_GIC_V2_STRING_2,
+ NULL
+};
+
+DT_DEVICE_START(gicv2, "GICv2:", DEVICE_GIC)
+ .compatible = gicv2_dt_compat,
+ .init = gicv2_init,
+DT_DEVICE_END
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 4580d96..bf1367b 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -30,6 +30,7 @@
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
+#include <asm/device.h>
#include <asm/io.h>
#include <asm/gic.h>
@@ -164,7 +165,28 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
/* Set up the GIC */
void __init gic_init(void)
{
- gicv2_init();
+ int rc;
+ struct dt_device_node *node;
+ bool_t num_gics = 0;
+
+ dt_for_each_device_node( dt_host, node )
+ {
+ if ( !dt_get_property(node, "interrupt-controller", NULL) )
+ continue;
+
+ if ( !dt_get_parent(node) )
+ continue;
+
+ rc = device_init(node, DEVICE_GIC, NULL);
+ if ( !rc )
+ {
+ /* NOTE: Only one GIC is supported */
+ num_gics = 1;
+ break;
+ }
+ }
+ if ( !num_gics )
+ panic("Unable to find compatible GIC in the device tree");
}
void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi)
diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h
index 60109cc..74a80c6 100644
--- a/xen/include/asm-arm/device.h
+++ b/xen/include/asm-arm/device.h
@@ -8,6 +8,7 @@ enum device_type
{
DEVICE_SERIAL,
DEVICE_IOMMU,
+ DEVICE_GIC,
/* Use for error */
DEVICE_UNKNOWN,
};
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 978a968..eb687b8 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -144,8 +144,11 @@
#include <xen/device_tree.h>
#include <xen/irq.h>
-#define DT_MATCH_GIC DT_MATCH_COMPATIBLE("arm,cortex-a15-gic"), \
- DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
+#define DT_MATCH_GIC_V2_STRING_1 "arm,cortex-a15-gic"
+#define DT_MATCH_GIC_V2_STRING_2 "arm,cortex-a7-gic"
+
+#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_1), \
+ DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_2)
/*
* GICv2 register that needs to be saved/restored
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 08/21] xen/arm: use device api to detect GIC version
2014-06-12 13:36 ` [PATCH v5 08/21] xen/arm: use device api to detect GIC version vijay.kilari
@ 2014-06-15 16:09 ` Julien Grall
2014-06-17 12:23 ` Ian Campbell
1 sibling, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:09 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Run through the device tree to detect
> compatible GIC version and initialize GIC driver
>
> Also change DT_MATCH_GIC to DT_MATCH_GIC_V2 to point
> the GIC HW version to add later GIC versions
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 08/21] xen/arm: use device api to detect GIC version
2014-06-12 13:36 ` [PATCH v5 08/21] xen/arm: use device api to detect GIC version vijay.kilari
2014-06-15 16:09 ` Julien Grall
@ 2014-06-17 12:23 ` Ian Campbell
1 sibling, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:23 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
>
> -#define DT_MATCH_GIC DT_MATCH_COMPATIBLE("arm,cortex-a15-gic"), \
> - DT_MATCH_COMPATIBLE("arm,cortex-a7-gic")
> +#define DT_MATCH_GIC_V2_STRING_1 "arm,cortex-a15-gic"
> +#define DT_MATCH_GIC_V2_STRING_2 "arm,cortex-a7-gic"
Please can you name these DT_COMPAT_GIC_CORTEX_A15 / A7.
i.e. s/MATCH/COMPAT/ (because that suits the other use which is made
better) and explicitly naming the processors rather than just string-N.
With the processor names in place I think you can safely drop the V2
from these (but not from DT_MATCH_GIC_V2 below).
With that changed: Acked-by: Ian Campbell <ian.campbell@citrix.com>
Ian.
> +
> +#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_1), \
> + DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_2)
>
> /*
> * GICv2 register that needs to be saved/restored
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 09/21] xen/arm: move vgic rank data to gic header file
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (7 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 08/21] xen/arm: use device api to detect GIC version vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-17 12:25 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 10/21] xen/arm: move vgic defines to vgic " vijay.kilari
` (13 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
vgic_irq_rank structure contains gic specific data elements.
Move this out of domain.h to new vgic header file vgic.h
Allocate memory dynamically in vgic driver.
This patch reduces the size of domain struct and helps to
keep domain struct within PAGE_SIZE when future GIC hw versions
are added
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
xen/arch/arm/domain.c | 2 ++
xen/arch/arm/vgic.c | 18 ++++++++++++++----
xen/include/asm-arm/domain.h | 11 +----------
xen/include/asm-arm/vgic.h | 40 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 43a2c6f..8881da8 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -31,6 +31,7 @@
#include <asm/procinfo.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/platform.h>
#include "vtimer.h"
#include "vuart.h"
@@ -481,6 +482,7 @@ int vcpu_initialise(struct vcpu *v)
void vcpu_destroy(struct vcpu *v)
{
vcpu_timer_destroy(v);
+ vcpu_vgic_free(v);
free_xenheap_pages(v->arch.stack, STACK_ORDER);
}
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 1c37836..76d7400 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -29,6 +29,7 @@
#include <asm/mmio.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#define REG(n) (n)
@@ -69,7 +70,7 @@ static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
int rank = REG_RANK_NR(b, (n >> 2));
if ( rank == 0 )
- return &v->arch.vgic.private_irqs;
+ return v->arch.vgic.private_irqs;
else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
return &v->domain->arch.vgic.shared_irqs[rank - 1];
else
@@ -134,9 +135,12 @@ void domain_vgic_free(struct domain *d)
int vcpu_vgic_init(struct vcpu *v)
{
int i;
- memset(&v->arch.vgic.private_irqs, 0, sizeof(v->arch.vgic.private_irqs));
- spin_lock_init(&v->arch.vgic.private_irqs.lock);
+ v->arch.vgic.private_irqs = xzalloc(struct vgic_irq_rank);
+ if ( v->arch.vgic.private_irqs == NULL )
+ return -ENOMEM;
+
+ spin_lock_init(&v->arch.vgic.private_irqs->lock);
memset(&v->arch.vgic.pending_irqs, 0, sizeof(v->arch.vgic.pending_irqs));
for (i = 0; i < 32; i++)
@@ -147,7 +151,7 @@ int vcpu_vgic_init(struct vcpu *v)
/* For SGI and PPI the target is always this CPU */
for ( i = 0 ; i < 8 ; i++ )
- v->arch.vgic.private_irqs.itargets[i] =
+ v->arch.vgic.private_irqs->itargets[i] =
(1<<(v->vcpu_id+0))
| (1<<(v->vcpu_id+8))
| (1<<(v->vcpu_id+16))
@@ -159,6 +163,12 @@ int vcpu_vgic_init(struct vcpu *v)
return 0;
}
+int vcpu_vgic_free(struct vcpu *v)
+{
+ xfree(v->arch.vgic.private_irqs);
+ return 0;
+}
+
#define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock)
#define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 591a825..3de33a9 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -13,15 +13,6 @@
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
-/* Represents state corresponding to a block of 32 interrupts */
-struct vgic_irq_rank {
- spinlock_t lock; /* Covers access to all other members of this struct */
- uint32_t ienable, iactive, ipend, pendsgi;
- uint32_t icfg[2];
- uint32_t ipriority[8];
- uint32_t itargets[8];
-};
-
struct pending_irq
{
/*
@@ -274,7 +265,7 @@ struct arch_vcpu
* struct arch_domain.
*/
struct pending_irq pending_irqs[32];
- struct vgic_irq_rank private_irqs;
+ struct vgic_irq_rank *private_irqs;
/* This list is ordered by IRQ priority and it is used to keep
* track of the IRQs that the VGIC injected into the guest.
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
new file mode 100644
index 0000000..0fd5b41
--- /dev/null
+++ b/xen/include/asm-arm/vgic.h
@@ -0,0 +1,40 @@
+/*
+ * ARM Virtual Generic Interrupt Controller support
+ *
+ * Ian Campbell <ian.campbell@citrix.com>
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_VGIC_H__
+#define __ASM_ARM_VGIC_H__
+
+/* Represents state corresponding to a block of 32 interrupts */
+struct vgic_irq_rank {
+ spinlock_t lock; /* Covers access to all other members of this struct */
+ uint32_t ienable, iactive, ipend, pendsgi;
+ uint32_t icfg[2];
+ uint32_t ipriority[8];
+ uint32_t itargets[8];
+};
+
+extern int vcpu_vgic_free(struct vcpu *v);
+#endif /* __ASM_ARM_VGIC_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 09/21] xen/arm: move vgic rank data to gic header file
2014-06-12 13:36 ` [PATCH v5 09/21] xen/arm: move vgic rank data to gic header file vijay.kilari
@ 2014-06-17 12:25 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:25 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> vgic_irq_rank structure contains gic specific data elements.
> Move this out of domain.h to new vgic header file vgic.h
> Allocate memory dynamically in vgic driver.
>
> This patch reduces the size of domain struct and helps to
> keep domain struct within PAGE_SIZE when future GIC hw versions
> are added
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Julien Grall <julien.grall@linaro.org>
> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>, although I think the
headline (i.e. $subject) should have been the switch to dynamic
allocation rather than the header movement.
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 10/21] xen/arm: move vgic defines to vgic header file
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (8 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 09/21] xen/arm: move vgic rank data to gic header file vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-17 12:27 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
` (12 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
gic.h contains defines of vgic. Move these to vgic
header file. Also move inline functions and defines/macros
in vgic.c to vgic.h. These vgic functions and macros
can be used by other GIC HW specific VGIC drivers,
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
---
xen/arch/arm/irq.c | 1 +
xen/arch/arm/time.c | 1 +
xen/arch/arm/vgic.c | 53 --------------------------------------
xen/arch/arm/vpsci.c | 1 +
xen/arch/arm/vtimer.c | 1 +
xen/include/asm-arm/gic.h | 9 -------
xen/include/asm-arm/vgic.h | 61 ++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 65 insertions(+), 62 deletions(-)
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 9c141bc..3a8acbf 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -26,6 +26,7 @@
#include <xen/sched.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
static unsigned int local_irqs_type[NR_LOCAL_IRQS];
static DEFINE_SPINLOCK(local_irqs_type_lock);
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index 06cc709..4c3e1a6 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -32,6 +32,7 @@
#include <asm/system.h>
#include <asm/time.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/cpufeature.h>
#include <asm/platform.h>
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 76d7400..ab39d44 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -33,35 +33,10 @@
#define REG(n) (n)
-/* Number of ranks of interrupt registers for a domain */
-#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
-
static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
/*
- * Rank containing GICD_<FOO><n> for GICD_<FOO> with
- * <b>-bits-per-interrupt
- */
-static inline int REG_RANK_NR(int b, uint32_t n)
-{
- switch ( b )
- {
- case 8: return n >> 3;
- case 4: return n >> 2;
- case 2: return n >> 1;
- case 1: return n;
- default: BUG();
- }
-}
-
-/*
- * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
- * <b>-bits-per-interrupt.
- */
-#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
-
-/*
* Returns rank corresponding to a GICD_<FOO><n> register for
* GICD_<FOO> with <b>-bits-per-interrupt.
*/
@@ -169,34 +144,6 @@ int vcpu_vgic_free(struct vcpu *v)
return 0;
}
-#define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock)
-#define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
-
-#define vgic_lock_rank(v, r) spin_lock(&(r)->lock)
-#define vgic_unlock_rank(v, r) spin_unlock(&(r)->lock)
-
-static uint32_t byte_read(uint32_t val, int sign, int offset)
-{
- int byte = offset & 0x3;
-
- val = val >> (8*byte);
- if ( sign && (val & 0x80) )
- val |= 0xffffff00;
- else
- val &= 0x000000ff;
- return val;
-}
-
-static void byte_write(uint32_t *reg, uint32_t var, int offset)
-{
- int byte = offset & 0x3;
-
- var &= (0xff << (8*byte));
-
- *reg &= ~(0xff << (8*byte));
- *reg |= var;
-}
-
static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
{
struct hsr_dabt dabt = info->dabt;
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 1ceb8cb..80678f6 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -16,6 +16,7 @@
#include <asm/current.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/psci.h>
int do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c
index b751692..7016989 100644
--- a/xen/arch/arm/vtimer.c
+++ b/xen/arch/arm/vtimer.c
@@ -24,6 +24,7 @@
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/gic.h>
+#include <asm/vgic.h>
#include <asm/regs.h>
extern s_time_t ticks_to_ns(uint64_t ticks);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index eb687b8..a8740fe 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -188,15 +188,6 @@ enum gic_version {
};
extern enum gic_version gic_hw_version(void);
-extern void gicv2_init(void);
-
-extern int domain_vgic_init(struct domain *d);
-extern void domain_vgic_free(struct domain *d);
-
-extern int vcpu_vgic_init(struct vcpu *v);
-
-extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
-extern void vgic_clear_pending_irqs(struct vcpu *v);
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
/* Program the GIC to route an interrupt */
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 0fd5b41..c9851d1 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -18,6 +18,8 @@
#ifndef __ASM_ARM_VGIC_H__
#define __ASM_ARM_VGIC_H__
+#include <xen/bitops.h>
+
/* Represents state corresponding to a block of 32 interrupts */
struct vgic_irq_rank {
spinlock_t lock; /* Covers access to all other members of this struct */
@@ -27,6 +29,65 @@ struct vgic_irq_rank {
uint32_t itargets[8];
};
+/* Number of ranks of interrupt registers for a domain */
+#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
+
+#define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock)
+#define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
+
+#define vgic_lock_rank(v, r) spin_lock(&(r)->lock)
+#define vgic_unlock_rank(v, r) spin_unlock(&(r)->lock)
+
+/*
+ * Rank containing GICD_<FOO><n> for GICD_<FOO> with
+ * <b>-bits-per-interrupt
+ */
+static inline int REG_RANK_NR(int b, uint32_t n)
+{
+ switch ( b )
+ {
+ case 8: return n >> 3;
+ case 4: return n >> 2;
+ case 2: return n >> 1;
+ case 1: return n;
+ default: BUG();
+ }
+}
+
+static inline uint32_t byte_read(uint32_t val, int sign, int offset)
+{
+ int byte = offset & 0x3;
+
+ val = val >> (8*byte);
+ if ( sign && (val & 0x80) )
+ val |= 0xffffff00;
+ else
+ val &= 0x000000ff;
+ return val;
+}
+
+static inline void byte_write(uint32_t *reg, uint32_t var, int offset)
+{
+ int byte = offset & 0x3;
+
+ var &= (0xff << (8*byte));
+
+ *reg &= ~(0xff << (8*byte));
+ *reg |= var;
+}
+
+/*
+ * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
+ * <b>-bits-per-interrupt.
+ */
+#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
+
+extern int domain_vgic_init(struct domain *d);
+extern void domain_vgic_free(struct domain *d);
+extern int vcpu_vgic_init(struct vcpu *v);
+extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
+extern void vgic_clear_pending_irqs(struct vcpu *v);
+
extern int vcpu_vgic_free(struct vcpu *v);
#endif /* __ASM_ARM_VGIC_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 10/21] xen/arm: move vgic defines to vgic header file
2014-06-12 13:36 ` [PATCH v5 10/21] xen/arm: move vgic defines to vgic " vijay.kilari
@ 2014-06-17 12:27 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:27 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic.h contains defines of vgic. Move these to vgic
> header file. Also move inline functions and defines/macros
> in vgic.c to vgic.h. These vgic functions and macros
> can be used by other GIC HW specific VGIC drivers,
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (9 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 10/21] xen/arm: move vgic defines to vgic " vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-15 16:23 ` Julien Grall
2014-06-15 16:34 ` Julien Grall
2014-06-12 13:36 ` [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h vijay.kilari
` (11 subsequent siblings)
22 siblings, 2 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
prefix byte_read and byte_write vgic functions with vgic_
to make these function vgic specific.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/vgic.c | 18 +++++++++---------
xen/include/asm-arm/vgic.h | 4 ++--
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index ab39d44..e5b698e 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -209,7 +209,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -218,7 +218,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -248,7 +248,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
vgic_lock_rank(v, rank);
*r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)];
if ( dabt.size == 0 )
- *r = byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -260,7 +260,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
vgic_lock_rank(v, rank);
*r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)];
if ( dabt.size == 0 )
- *r = byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -288,7 +288,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -297,7 +297,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -557,7 +557,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
if ( dabt.size == 2 )
rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r;
else
- byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
+ vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
*r, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -570,7 +570,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
if ( dabt.size == 2 )
rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)] = *r;
else
- byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
+ vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
*r, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -696,7 +696,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
return;
}
- priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
+ priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
n->irq = irq;
set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index c9851d1..92f1e86 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -54,7 +54,7 @@ static inline int REG_RANK_NR(int b, uint32_t n)
}
}
-static inline uint32_t byte_read(uint32_t val, int sign, int offset)
+static inline uint32_t vgic_byte_read(uint32_t val, int sign, int offset)
{
int byte = offset & 0x3;
@@ -66,7 +66,7 @@ static inline uint32_t byte_read(uint32_t val, int sign, int offset)
return val;
}
-static inline void byte_write(uint32_t *reg, uint32_t var, int offset)
+static inline void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
{
int byte = offset & 0x3;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic
2014-06-12 13:36 ` [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
@ 2014-06-15 16:23 ` Julien Grall
2014-06-15 16:34 ` Julien Grall
1 sibling, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:23 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> prefix byte_read and byte_write vgic functions with vgic_
> to make these function vgic specific.
For one patch you are exposing byte_read and byte_write globally. I
think, you should rename the function in first and then move them to the
headers.
So I would move this patch before #10.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic
2014-06-12 13:36 ` [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
2014-06-15 16:23 ` Julien Grall
@ 2014-06-15 16:34 ` Julien Grall
2014-06-17 12:28 ` Ian Campbell
1 sibling, 1 reply; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:34 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> @@ -557,7 +557,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> if ( dabt.size == 2 )
> rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r;
> else
> - byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
> + vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
> *r, offset);
Please correctly realign the second line.
> vgic_unlock_rank(v, rank);
> return 1;
> @@ -570,7 +570,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> if ( dabt.size == 2 )
> rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)] = *r;
> else
> - byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
> + vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
> *r, offset);
Same here.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic
2014-06-15 16:34 ` Julien Grall
@ 2014-06-17 12:28 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:28 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Sun, 2014-06-15 at 17:34 +0100, Julien Grall wrote:
> Hi Vijay,
>
> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> > @@ -557,7 +557,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> > if ( dabt.size == 2 )
> > rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r;
> > else
> > - byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
> > + vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
> > *r, offset);
>
> Please correctly realign the second line.
Yes, please. Other than that (and the other one):
Acked-by: Ian Campbell <ian.campbell@citrix.com>
>
> > vgic_unlock_rank(v, rank);
> > return 1;
> > @@ -570,7 +570,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> > if ( dabt.size == 2 )
> > rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)] = *r;
> > else
> > - byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
> > + vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
> > *r, offset);
>
> Same here.
>
> Regards,
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (10 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 11/21] xen/arm: prefix byte_read and byte_write functions with vgic vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-15 16:26 ` Julien Grall
2014-06-12 13:36 ` [PATCH v5 13/21] xen/arm: move pending_irq structure to vgic header file vijay.kilari
` (10 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
is_vcpu_running function in vgic driver is generic. So move
this to sched.h
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/vgic.c | 16 ----------------
xen/include/xen/sched.h | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index e5b698e..10faceb 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -397,22 +397,6 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
}
}
-static inline int is_vcpu_running(struct domain *d, int vcpuid)
-{
- struct vcpu *v;
-
- if ( vcpuid >= d->max_vcpus )
- return 0;
-
- v = d->vcpu[vcpuid];
- if ( v == NULL )
- return 0;
- if (test_bit(_VPF_down, &v->pause_flags) )
- return 0;
-
- return 1;
-}
-
static int vgic_to_sgi(struct vcpu *v, register_t sgir)
{
struct domain *d = v->domain;
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index 44851ae..03416b5 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -826,6 +826,22 @@ void watchdog_domain_destroy(struct domain *d);
#define need_iommu(d) (0)
#endif
+static inline int is_vcpu_running(struct domain *d, int vcpuid)
+{
+ struct vcpu *v;
+
+ if ( vcpuid >= d->max_vcpus )
+ return 0;
+
+ v = d->vcpu[vcpuid];
+ if ( v == NULL )
+ return 0;
+ if (test_bit(_VPF_down, &v->pause_flags) )
+ return 0;
+
+ return 1;
+}
+
void set_vcpu_migration_delay(unsigned int delay);
unsigned int get_vcpu_migration_delay(void);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h
2014-06-12 13:36 ` [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h vijay.kilari
@ 2014-06-15 16:26 ` Julien Grall
2014-06-16 8:34 ` Jan Beulich
2014-06-19 11:11 ` Vijay Kilari
0 siblings, 2 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:26 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, Stefano Stabellini,
stefano.stabellini, tim, xen-devel
Cc: Keir Fraser, Prasun Kapoor, Vijaya Kumar K, xen.org,
george.dunlap, Jan Beulich
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> is_vcpu_running function in vgic driver is generic. So move
> this to sched.h
As said on v4 please add the relevant maintainers. You can use
scripts/get_maintainers.pl for this purpose. I've again cced them.
Also, I've asked to justify why this function should go to the common
code. Can you explain it?
Regards,
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> ---
> xen/arch/arm/vgic.c | 16 ----------------
> xen/include/xen/sched.h | 16 ++++++++++++++++
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index e5b698e..10faceb 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -397,22 +397,6 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
> }
> }
>
> -static inline int is_vcpu_running(struct domain *d, int vcpuid)
> -{
> - struct vcpu *v;
> -
> - if ( vcpuid >= d->max_vcpus )
> - return 0;
> -
> - v = d->vcpu[vcpuid];
> - if ( v == NULL )
> - return 0;
> - if (test_bit(_VPF_down, &v->pause_flags) )
> - return 0;
> -
> - return 1;
> -}
> -
> static int vgic_to_sgi(struct vcpu *v, register_t sgir)
> {
> struct domain *d = v->domain;
> diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
> index 44851ae..03416b5 100644
> --- a/xen/include/xen/sched.h
> +++ b/xen/include/xen/sched.h
> @@ -826,6 +826,22 @@ void watchdog_domain_destroy(struct domain *d);
> #define need_iommu(d) (0)
> #endif
>
> +static inline int is_vcpu_running(struct domain *d, int vcpuid)
> +{
> + struct vcpu *v;
> +
> + if ( vcpuid >= d->max_vcpus )
> + return 0;
> +
> + v = d->vcpu[vcpuid];
> + if ( v == NULL )
> + return 0;
> + if (test_bit(_VPF_down, &v->pause_flags) )
> + return 0;
> +
> + return 1;
> +}
> +
> void set_vcpu_migration_delay(unsigned int delay);
> unsigned int get_vcpu_migration_delay(void);
>
>
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h
2014-06-15 16:26 ` Julien Grall
@ 2014-06-16 8:34 ` Jan Beulich
2014-06-19 10:58 ` Vijay Kilari
2014-06-19 11:11 ` Vijay Kilari
1 sibling, 1 reply; 87+ messages in thread
From: Jan Beulich @ 2014-06-16 8:34 UTC (permalink / raw)
To: vijay.kilari
Cc: Keir Fraser, Ian.Campbell, Stefano Stabellini, Prasun Kapoor,
tim, Vijaya Kumar K, Julien Grall, xen.org, george.dunlap,
xen-devel, stefano.stabellini
>>> On 15.06.14 at 18:26, <julien.grall@linaro.org> wrote:
>> --- a/xen/include/xen/sched.h
>> +++ b/xen/include/xen/sched.h
>> @@ -826,6 +826,22 @@ void watchdog_domain_destroy(struct domain *d);
>> #define need_iommu(d) (0)
>> #endif
>>
>> +static inline int is_vcpu_running(struct domain *d, int vcpuid)
>> +{
>> + struct vcpu *v;
>> +
>> + if ( vcpuid >= d->max_vcpus )
>> + return 0;
>> +
>> + v = d->vcpu[vcpuid];
>> + if ( v == NULL )
>> + return 0;
>> + if (test_bit(_VPF_down, &v->pause_flags) )
>> + return 0;
>> +
>> + return 1;
>> +}
If this function was to become common code, you'd have to not only
justify it (as requested by Julien), but also
- name it according to its function (VPF_down not set doesn't mean
"running", it merely means "up")
- make it properly check d->vcpu != NULL alongside the other checks
- returning a boolean value it should have return type bool_t
- "d" and "v" only ever used for read accesses both pointers should
get const-qualified
- fix the one coding style violation in the last if().
Jan
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h
2014-06-16 8:34 ` Jan Beulich
@ 2014-06-19 10:58 ` Vijay Kilari
2014-06-19 11:03 ` Julien Grall
0 siblings, 1 reply; 87+ messages in thread
From: Vijay Kilari @ 2014-06-19 10:58 UTC (permalink / raw)
To: Jan Beulich
Cc: Keir Fraser, Ian Campbell, Stefano Stabellini, Prasun Kapoor,
Tim Deegan, Vijaya Kumar K, Julien Grall, xen.org, george.dunlap,
xen-devel, Stefano Stabellini
Hi Julien, Stefano, Jan,
On Mon, Jun 16, 2014 at 2:04 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 15.06.14 at 18:26, <julien.grall@linaro.org> wrote:
>>> --- a/xen/include/xen/sched.h
>>> +++ b/xen/include/xen/sched.h
>>> @@ -826,6 +826,22 @@ void watchdog_domain_destroy(struct domain *d);
>>> #define need_iommu(d) (0)
>>> #endif
>>>
>>> +static inline int is_vcpu_running(struct domain *d, int vcpuid)
>>> +{
>>> + struct vcpu *v;
>>> +
>>> + if ( vcpuid >= d->max_vcpus )
>>> + return 0;
>>> +
>>> + v = d->vcpu[vcpuid];
>>> + if ( v == NULL )
>>> + return 0;
>>> + if (test_bit(_VPF_down, &v->pause_flags) )
>>> + return 0;
>>> +
>>> + return 1;
>>> +}
>
> If this function was to become common code, you'd have to not only
> justify it (as requested by Julien), but also
> - name it according to its function (VPF_down not set doesn't mean
> "running", it merely means "up")
IMO, is_vcpu_running() usage in vgic.c is just to check if vcpu is runnable
and not down. So checking apart from VPF_down is enough.
If so, we should change the name of this function
> - make it properly check d->vcpu != NULL alongside the other checks
> - returning a boolean value it should have return type bool_t
> - "d" and "v" only ever used for read accesses both pointers should
> get const-qualified
> - fix the one coding style violation in the last if().
>
> Jan
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h
2014-06-19 10:58 ` Vijay Kilari
@ 2014-06-19 11:03 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-19 11:03 UTC (permalink / raw)
To: Vijay Kilari, Jan Beulich
Cc: Keir Fraser, Ian Campbell, Stefano Stabellini, Prasun Kapoor,
Tim Deegan, Vijaya Kumar K, xen.org, george.dunlap, xen-devel,
Stefano Stabellini
On 06/19/2014 11:58 AM, Vijay Kilari wrote:
> Hi Julien, Stefano, Jan,
>
> On Mon, Jun 16, 2014 at 2:04 PM, Jan Beulich <JBeulich@suse.com> wrote:
>>>>> On 15.06.14 at 18:26, <julien.grall@linaro.org> wrote:
>>>> --- a/xen/include/xen/sched.h
>>>> +++ b/xen/include/xen/sched.h
>>>> @@ -826,6 +826,22 @@ void watchdog_domain_destroy(struct domain *d);
>>>> #define need_iommu(d) (0)
>>>> #endif
>>>>
>>>> +static inline int is_vcpu_running(struct domain *d, int vcpuid)
>>>> +{
>>>> + struct vcpu *v;
>>>> +
>>>> + if ( vcpuid >= d->max_vcpus )
>>>> + return 0;
>>>> +
>>>> + v = d->vcpu[vcpuid];
>>>> + if ( v == NULL )
>>>> + return 0;
>>>> + if (test_bit(_VPF_down, &v->pause_flags) )
>>>> + return 0;
>>>> +
>>>> + return 1;
>>>> +}
>>
>> If this function was to become common code, you'd have to not only
>> justify it (as requested by Julien), but also
>> - name it according to its function (VPF_down not set doesn't mean
>> "running", it merely means "up")
>
> IMO, is_vcpu_running() usage in vgic.c is just to check if vcpu is runnable
> and not down. So checking apart from VPF_down is enough.
> If so, we should change the name of this function
You are wrong, the usage in vgic.c is to check that the VCPU is online.
So we don't inject an IRQ to this VCPU.
We don't care if the VCPU is block/runnable or whatever.
What Jan was asking is to rename the function in is_vcpu_up (or smth
similar).
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h
2014-06-15 16:26 ` Julien Grall
2014-06-16 8:34 ` Jan Beulich
@ 2014-06-19 11:11 ` Vijay Kilari
1 sibling, 0 replies; 87+ messages in thread
From: Vijay Kilari @ 2014-06-19 11:11 UTC (permalink / raw)
To: Julien Grall
Cc: Keir Fraser, Ian Campbell, Stefano Stabellini, Prasun Kapoor,
xen.org, Vijaya Kumar K, Tim Deegan, george.dunlap, xen-devel,
Stefano Stabellini, Jan Beulich
On Sun, Jun 15, 2014 at 9:56 PM, Julien Grall <julien.grall@linaro.org> wrote:
> Hi Vijay,
>
>
> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
>>
>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>
>> is_vcpu_running function in vgic driver is generic. So move
>> this to sched.h
>
>
> As said on v4 please add the relevant maintainers. You can use
> scripts/get_maintainers.pl for this purpose. I've again cced them.
Though I used this script, It does not show Jan as maintainer :-(.
For all GICv3 patches it pops Ian, Stefano, Tim and your name
xen$ ./scripts/get_maintainer.pl
0012-xen-arm-move-is_vcpu_running-function-to-sched.h.patch
Ian Campbell <ian.campbell@citrix.com>
Stefano Stabellini <stefano.stabellini@citrix.com>
Tim Deegan <tim@xen.org>
xen-devel@lists.xen.org
Regards
Vijay
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 13/21] xen/arm: move pending_irq structure to vgic header file
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (11 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 12/21] xen/arm: move is_vcpu_running function to sched.h vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-17 12:33 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 14/21] xen/arm: calculate vgic irq rank based on register size vijay.kilari
` (9 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
gic.h requires definition of pending_irq structure defined
in domain.h and domain.h requires gic_state structure defined
in gic.h and hence there is inter-dependency between domain.h
and gic.h files.
So move pending_irq to vgic.h which is relevant place for this
structure and break domain.h and gic.h interdependency
By this move irq_to_pending function declaration from gic.h
to vgic.h
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/include/asm-arm/domain.h | 57 -----------------------------------------
xen/include/asm-arm/gic.h | 2 +-
xen/include/asm-arm/vgic.h | 58 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 59 insertions(+), 58 deletions(-)
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 3de33a9..4321b7c 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -13,63 +13,6 @@
#include <xen/serial.h>
#include <xen/hvm/iommu.h>
-struct pending_irq
-{
- /*
- * The following two states track the lifecycle of the guest irq.
- * However because we are not sure and we don't want to track
- * whether an irq added to an LR register is PENDING or ACTIVE, the
- * following states are just an approximation.
- *
- * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for
- * injection into the guest's LRs.
- *
- * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register,
- * therefore the guest is aware of it. From the guest point of view
- * the irq can be pending (if the guest has not acked the irq yet)
- * or active (after acking the irq).
- *
- * In order for the state machine to be fully accurate, for level
- * interrupts, we should keep the interrupt's pending state until
- * the guest deactivates the irq. However because we are not sure
- * when that happens, we instead track whether there is an interrupt
- * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to
- * an LR register. We set it when we receive another interrupt
- * notification. Therefore it is possible to set
- * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We
- * could also change the state of the guest irq in the LR register
- * from active to active and pending, but for simplicity we simply
- * inject a second irq after the guest EOIs the first one.
- *
- *
- * An additional state is used to keep track of whether the guest
- * irq is enabled at the vgicd level:
- *
- * GIC_IRQ_GUEST_ENABLED: the guest IRQ is enabled at the VGICD
- * level (GICD_ICENABLER/GICD_ISENABLER).
- *
- */
-#define GIC_IRQ_GUEST_QUEUED 0
-#define GIC_IRQ_GUEST_ACTIVE 1
-#define GIC_IRQ_GUEST_VISIBLE 2
-#define GIC_IRQ_GUEST_ENABLED 3
- unsigned long status;
- struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */
- int irq;
-#define GIC_INVALID_LR ~(uint8_t)0
- uint8_t lr;
- uint8_t priority;
- /* inflight is used to append instances of pending_irq to
- * vgic.inflight_irqs */
- struct list_head inflight;
- /* lr_queue is used to append instances of pending_irq to
- * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue
- * accesses are protected with the vgic lock.
- * TODO: when implementing irq migration, taking only the current
- * vgic lock is not going to be enough. */
- struct list_head lr_queue;
-};
-
struct hvm_domain
{
uint64_t params[HVM_NR_PARAMS];
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index a8740fe..a3ca9a0 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -143,6 +143,7 @@
#ifndef __ASSEMBLY__
#include <xen/device_tree.h>
#include <xen/irq.h>
+#include <asm-arm/vgic.h>
#define DT_MATCH_GIC_V2_STRING_1 "arm,cortex-a15-gic"
#define DT_MATCH_GIC_V2_STRING_2 "arm,cortex-a7-gic"
@@ -188,7 +189,6 @@ enum gic_version {
};
extern enum gic_version gic_hw_version(void);
-extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
/* Program the GIC to route an interrupt */
extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask,
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 92f1e86..003c3e9 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -20,6 +20,63 @@
#include <xen/bitops.h>
+struct pending_irq
+{
+ /*
+ * The following two states track the lifecycle of the guest irq.
+ * However because we are not sure and we don't want to track
+ * whether an irq added to an LR register is PENDING or ACTIVE, the
+ * following states are just an approximation.
+ *
+ * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for
+ * injection into the guest's LRs.
+ *
+ * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register,
+ * therefore the guest is aware of it. From the guest point of view
+ * the irq can be pending (if the guest has not acked the irq yet)
+ * or active (after acking the irq).
+ *
+ * In order for the state machine to be fully accurate, for level
+ * interrupts, we should keep the interrupt's pending state until
+ * the guest deactivates the irq. However because we are not sure
+ * when that happens, we instead track whether there is an interrupt
+ * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to
+ * an LR register. We set it when we receive another interrupt
+ * notification. Therefore it is possible to set
+ * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We
+ * could also change the state of the guest irq in the LR register
+ * from active to active and pending, but for simplicity we simply
+ * inject a second irq after the guest EOIs the first one.
+ *
+ *
+ * An additional state is used to keep track of whether the guest
+ * irq is enabled at the vgicd level:
+ *
+ * GIC_IRQ_GUEST_ENABLED: the guest IRQ is enabled at the VGICD
+ * level (GICD_ICENABLER/GICD_ISENABLER).
+ *
+ */
+#define GIC_IRQ_GUEST_QUEUED 0
+#define GIC_IRQ_GUEST_ACTIVE 1
+#define GIC_IRQ_GUEST_VISIBLE 2
+#define GIC_IRQ_GUEST_ENABLED 3
+ unsigned long status;
+ struct irq_desc *desc; /* only set it the irq corresponds to a physical irq */
+ int irq;
+#define GIC_INVALID_LR ~(uint8_t)0
+ uint8_t lr;
+ uint8_t priority;
+ /* inflight is used to append instances of pending_irq to
+ * vgic.inflight_irqs */
+ struct list_head inflight;
+ /* lr_queue is used to append instances of pending_irq to
+ * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue
+ * accesses are protected with the vgic lock.
+ * TODO: when implementing irq migration, taking only the current
+ * vgic lock is not going to be enough. */
+ struct list_head lr_queue;
+};
+
/* Represents state corresponding to a block of 32 interrupts */
struct vgic_irq_rank {
spinlock_t lock; /* Covers access to all other members of this struct */
@@ -87,6 +144,7 @@ extern void domain_vgic_free(struct domain *d);
extern int vcpu_vgic_init(struct vcpu *v);
extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
extern void vgic_clear_pending_irqs(struct vcpu *v);
+extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
extern int vcpu_vgic_free(struct vcpu *v);
#endif /* __ASM_ARM_VGIC_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 13/21] xen/arm: move pending_irq structure to vgic header file
2014-06-12 13:36 ` [PATCH v5 13/21] xen/arm: move pending_irq structure to vgic header file vijay.kilari
@ 2014-06-17 12:33 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:33 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> gic.h requires definition of pending_irq structure defined
> in domain.h and domain.h requires gic_state structure defined
> in gic.h and hence there is inter-dependency between domain.h
> and gic.h files.
>
> So move pending_irq to vgic.h which is relevant place for this
> structure and break domain.h and gic.h interdependency
>
> By this move irq_to_pending function declaration from gic.h
> to vgic.h
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 14/21] xen/arm: calculate vgic irq rank based on register size
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (12 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 13/21] xen/arm: move pending_irq structure to vgic header file vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-17 12:36 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver vijay.kilari
` (8 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
vGIC irq rank was computed assuming the register offset is byte
size.Use the HSR abort address size in calculating register size.
So, with this patch following are acheived
(1) In the code 'dabt.size != number' this number is always
BYTE/HALF_WORD/WORD/DOUBLE defined by hsr registers.
Instead of checking for hard coded values use HSR abort
address size values.
(2) The vgic_irq_rank also depends on the same HSR defined
values to calculate irq rank.
This make vgic_irq_rank generic as it takes register
size as parameter to calculate irq rank instead of hard coding to
value 2 in previous patches
Also, output of REG_RANK_INDEX macro is module by 32 to make
sure register index is always within irq rank
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/vgic.c | 143 ++++++++++++++++++++-------------------
xen/include/asm-arm/processor.h | 8 +++
xen/include/asm-arm/vgic.h | 4 +-
3 files changed, 85 insertions(+), 70 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 10faceb..7be2b8f 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -40,9 +40,10 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
* Returns rank corresponding to a GICD_<FOO><n> register for
* GICD_<FOO> with <b>-bits-per-interrupt.
*/
-static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n)
+static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b,
+ int n, int s)
{
- int rank = REG_RANK_NR(b, (n >> 2));
+ int rank = REG_RANK_NR(b, (n >> s));
if ( rank == 0 )
return v->arch.vgic.private_irqs;
@@ -156,13 +157,13 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
switch ( gicd_reg )
{
case GICD_CTLR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
vgic_lock(v);
*r = v->domain->arch.vgic.ctlr;
vgic_unlock(v);
return 1;
case GICD_TYPER:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/* No secure world support for guests. */
vgic_lock(v);
*r = ( (v->domain->max_vcpus<<5) & GICD_TYPE_CPUS )
@@ -170,7 +171,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
vgic_unlock(v);
return 1;
case GICD_IIDR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/*
* XXX Do we need a JEP106 manufacturer ID?
* Just use the physical h/w value for now
@@ -187,8 +188,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
goto read_as_zero;
case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->ienable;
@@ -196,8 +197,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->ienable;
@@ -205,8 +206,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->ipend, dabt.sign, offset);
@@ -214,8 +215,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->ipend, dabt.sign, offset);
@@ -223,8 +224,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->iactive;
@@ -232,8 +233,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = rank->iactive;
@@ -241,35 +242,37 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ITARGETSR ... GICD_ITARGETSRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)];
- if ( dabt.size == 0 )
+ *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
*r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR);
+ if ( dabt.size != 0 && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)];
- if ( dabt.size == 0 )
+ *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
*r = vgic_byte_read(*r, dabt.sign, offset);
vgic_unlock_rank(v, rank);
return 1;
case GICD_ICFGR ... GICD_ICFGRN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR)];
+ *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)];
vgic_unlock_rank(v, rank);
return 1;
@@ -278,14 +281,14 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
goto read_as_zero;
case GICD_SGIR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/* Write only -- read unknown */
*r = 0xdeadbeef;
return 1;
case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
@@ -293,8 +296,8 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
*r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
@@ -306,7 +309,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
goto read_as_zero;
case GICD_ICPIDR2:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled read from ICPIDR2\n");
return 0;
@@ -336,7 +339,7 @@ bad_width:
return 0;
read_as_zero:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
*r = 0;
return 1;
}
@@ -459,7 +462,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
switch ( gicd_reg )
{
case GICD_CTLR:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
/* Ignore all but the enable bit */
v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
return 1;
@@ -478,42 +481,44 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
tr = rank->ienable;
rank->ienable |= *r;
vgic_unlock_rank(v, rank);
- vgic_enable_irqs(v, (*r) & (~tr), (gicd_reg - GICD_ISENABLER) >> 2);
+ vgic_enable_irqs(v, (*r) & (~tr),
+ (gicd_reg - GICD_ISENABLER) >> DABT_WORD);
return 1;
case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
tr = rank->ienable;
rank->ienable &= ~*r;
vgic_unlock_rank(v, rank);
- vgic_disable_irqs(v, (*r) & tr, (gicd_reg - GICD_ICENABLER) >> 2);
+ vgic_disable_irqs(v, (*r) & tr,
+ (gicd_reg - GICD_ICENABLER) >> DABT_WORD);
return 1;
case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ISPENDR);
return 0;
case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ICPENDR);
return 0;
case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
rank->iactive &= ~*r;
@@ -521,8 +526,8 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
return 1;
case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
rank->iactive &= ~*r;
@@ -534,28 +539,30 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
- if ( dabt.size == 2 )
- rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)] = *r;
+ if ( dabt.size == DABT_WORD )
+ rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)] = *r;
else
- vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)],
- *r, offset);
+ vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
+ gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, offset);
vgic_unlock_rank(v, rank);
return 1;
case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR);
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
- if ( dabt.size == 2 )
- rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)] = *r;
+ if ( dabt.size == DABT_WORD )
+ rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)] = *r;
else
- vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR)],
- *r, offset);
+ vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
+ gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, offset);
vgic_unlock_rank(v, rank);
return 1;
@@ -565,11 +572,11 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
/* It is implementation defined if these are writeable. We chose not */
goto write_ignore;
case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
- if ( dabt.size != 2 ) goto bad_width;
- rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR);
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
- rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR)] = *r;
+ rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
vgic_unlock_rank(v, rank);
return 1;
@@ -583,13 +590,13 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
return vgic_to_sgi(v, *r);
case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDSGIR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_CPENDSGIR);
return 0;
case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != 0 && dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDSGIR%d\n",
dabt.size ? "word" : "byte", *r, gicd_reg - GICD_SPENDSGIR);
return 0;
@@ -628,7 +635,7 @@ bad_width:
return 0;
write_ignore:
- if ( dabt.size != 2 ) goto bad_width;
+ if ( dabt.size != DABT_WORD ) goto bad_width;
return 1;
}
@@ -659,7 +666,7 @@ void vgic_clear_pending_irqs(struct vcpu *v)
void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
{
uint8_t priority;
- struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, irq);
+ struct vgic_irq_rank *rank = vgic_irq_rank(v, 8, irq, DABT_WORD);
struct pending_irq *iter, *n = irq_to_pending(v, irq);
unsigned long flags;
bool_t running;
@@ -680,7 +687,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq)
return;
}
- priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq)], 0, irq & 0x3);
+ priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq, DABT_WORD)], 0, irq & 0x3);
n->irq = irq;
set_bit(GIC_IRQ_GUEST_QUEUED, &n->status);
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 9267c1b..3662749 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -251,6 +251,14 @@ extern struct cpuinfo_arm cpu_data[];
extern u32 __cpu_logical_map[];
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
+/* HSR data abort size definition */
+enum dabt_size {
+ DABT_BYTE = 0,
+ DABT_HALF_WORD = 1,
+ DABT_WORD = 2,
+ DABT_DOUBLE_WORD = 3,
+};
+
union hsr {
uint32_t bits;
struct {
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 003c3e9..81e2740 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -134,10 +134,10 @@ static inline void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
}
/*
- * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
+ * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> size s with
* <b>-bits-per-interrupt.
*/
-#define REG_RANK_INDEX(b, n) (((n) >> 2) & ((b)-1))
+#define REG_RANK_INDEX(b, n, s) ((((n) >> s) & ((b)-1)) % 32)
extern int domain_vgic_init(struct domain *d);
extern void domain_vgic_free(struct domain *d);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 14/21] xen/arm: calculate vgic irq rank based on register size
2014-06-12 13:36 ` [PATCH v5 14/21] xen/arm: calculate vgic irq rank based on register size vijay.kilari
@ 2014-06-17 12:36 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:36 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> vGIC irq rank was computed assuming the register offset is byte
> size.Use the HSR abort address size in calculating register size.
>
> So, with this patch following are acheived
> (1) In the code 'dabt.size != number' this number is always
> BYTE/HALF_WORD/WORD/DOUBLE defined by hsr registers.
> Instead of checking for hard coded values use HSR abort
> address size values.
> (2) The vgic_irq_rank also depends on the same HSR defined
> values to calculate irq rank.
>
> This make vgic_irq_rank generic as it takes register
> size as parameter to calculate irq rank instead of hard coding to
> value 2 in previous patches
>
> Also, output of REG_RANK_INDEX macro is module by 32 to make
ITYM "modulo 32".
> diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
> index 003c3e9..81e2740 100644
> --- a/xen/include/asm-arm/vgic.h
> +++ b/xen/include/asm-arm/vgic.h
> @@ -134,10 +134,10 @@ static inline void vgic_byte_write(uint32_t *reg, uint32_t var, int offset)
> }
>
> /*
> - * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> with
> + * Offset of GICD_<FOO><n> with its rank, for GICD_<FOO> size s with
Can you write <s> for consistency please.
With those two minor things fixed: Acked-by: Ian Campbell
<ian.campbell@citrix.com>
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (13 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 14/21] xen/arm: calculate vgic irq rank based on register size vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 16:42 ` Stefano Stabellini
` (2 more replies)
2014-06-12 13:36 ` [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
` (7 subsequent siblings)
22 siblings, 3 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
REG macro does not compute any value and offset
variable is no more required. Hence removed
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/vgic.c | 68 ++++++++++++++++++++++++---------------------------
1 file changed, 32 insertions(+), 36 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 7be2b8f..a6b1894 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -31,8 +31,6 @@
#include <asm/gic.h>
#include <asm/vgic.h>
-#define REG(n) (n)
-
static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
@@ -151,8 +149,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
struct cpu_user_regs *regs = guest_cpu_user_regs();
register_t *r = select_user_reg(regs, dabt.reg);
struct vgic_irq_rank *rank;
- int offset = (int)(info->gpa - v->domain->arch.vgic.dbase);
- int gicd_reg = REG(offset);
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
switch ( gicd_reg )
{
@@ -180,7 +177,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 1;
/* Implementation defined -- read as zero */
- case REG(0x020) ... REG(0x03c):
+ case 0x020 ... 0x03c:
goto read_as_zero;
case GICD_IGROUPR ... GICD_IGROUPRN:
@@ -210,7 +207,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -219,7 +216,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -250,7 +247,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
*r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
DABT_WORD)];
if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -263,7 +260,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
*r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
DABT_WORD)];
if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, offset);
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -291,7 +288,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -300,12 +297,12 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
/* Implementation defined -- read as zero */
- case REG(0xfd0) ... REG(0xfe4):
+ case 0xfd0 ... 0xfe4:
goto read_as_zero;
case GICD_ICPIDR2:
@@ -314,27 +311,27 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
return 0;
/* Implementation defined -- read as zero */
- case REG(0xfec) ... REG(0xffc):
+ case 0xfec ... 0xffc:
goto read_as_zero;
/* Reserved -- read as zero */
- case REG(0x00c) ... REG(0x01c):
- case REG(0x040) ... REG(0x07c):
- case REG(0x7fc):
- case REG(0xbfc):
- case REG(0xf04) ... REG(0xf0c):
- case REG(0xf30) ... REG(0xfcc):
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
goto read_as_zero;
default:
printk("vGICD: unhandled read r%d offset %#08x\n",
- dabt.reg, offset);
+ dabt.reg, gicd_reg);
return 0;
}
bad_width:
printk("vGICD: bad read width %d r%d offset %#08x\n",
- dabt.size, dabt.reg, offset);
+ dabt.size, dabt.reg, gicd_reg);
domain_crash_synchronous();
return 0;
@@ -455,8 +452,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
struct cpu_user_regs *regs = guest_cpu_user_regs();
register_t *r = select_user_reg(regs, dabt.reg);
struct vgic_irq_rank *rank;
- int offset = (int)(info->gpa - v->domain->arch.vgic.dbase);
- int gicd_reg = REG(offset);
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
uint32_t tr;
switch ( gicd_reg )
@@ -473,7 +469,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
/* Implementation defined -- write ignored */
- case REG(0x020) ... REG(0x03c):
+ case 0x020 ... 0x03c:
goto write_ignore;
case GICD_IGROUPR ... GICD_IGROUPRN:
@@ -548,7 +544,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
DABT_WORD)] = *r;
else
vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
- gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, offset);
+ gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -562,7 +558,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
DABT_WORD)] = *r;
else
vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
- gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, offset);
+ gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -602,7 +598,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
return 0;
/* Implementation defined -- write ignored */
- case REG(0xfd0) ... REG(0xfe4):
+ case 0xfd0 ... 0xfe4:
goto write_ignore;
/* R/O -- write ignore */
@@ -610,27 +606,27 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
goto write_ignore;
/* Implementation defined -- write ignored */
- case REG(0xfec) ... REG(0xffc):
+ case 0xfec ... 0xffc:
goto write_ignore;
/* Reserved -- write ignored */
- case REG(0x00c) ... REG(0x01c):
- case REG(0x040) ... REG(0x07c):
- case REG(0x7fc):
- case REG(0xbfc):
- case REG(0xf04) ... REG(0xf0c):
- case REG(0xf30) ... REG(0xfcc):
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
goto write_ignore;
default:
printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
- dabt.reg, *r, offset);
+ dabt.reg, *r, gicd_reg);
return 0;
}
bad_width:
printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
- dabt.size, dabt.reg, *r, offset);
+ dabt.size, dabt.reg, *r, gicd_reg);
domain_crash_synchronous();
return 0;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver
2014-06-12 13:36 ` [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver vijay.kilari
@ 2014-06-12 16:42 ` Stefano Stabellini
2014-06-15 16:37 ` Julien Grall
2014-06-17 12:37 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 16:42 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> REG macro does not compute any value and offset
> variable is no more required. Hence removed
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> xen/arch/arm/vgic.c | 68 ++++++++++++++++++++++++---------------------------
> 1 file changed, 32 insertions(+), 36 deletions(-)
>
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 7be2b8f..a6b1894 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -31,8 +31,6 @@
> #include <asm/gic.h>
> #include <asm/vgic.h>
>
> -#define REG(n) (n)
> -
> static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
> static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
>
> @@ -151,8 +149,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> struct cpu_user_regs *regs = guest_cpu_user_regs();
> register_t *r = select_user_reg(regs, dabt.reg);
> struct vgic_irq_rank *rank;
> - int offset = (int)(info->gpa - v->domain->arch.vgic.dbase);
> - int gicd_reg = REG(offset);
> + int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
>
> switch ( gicd_reg )
> {
> @@ -180,7 +177,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> return 1;
>
> /* Implementation defined -- read as zero */
> - case REG(0x020) ... REG(0x03c):
> + case 0x020 ... 0x03c:
> goto read_as_zero;
>
> case GICD_IGROUPR ... GICD_IGROUPRN:
> @@ -210,7 +207,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
> if ( rank == NULL) goto read_as_zero;
> vgic_lock_rank(v, rank);
> - *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
> + *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -219,7 +216,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
> if ( rank == NULL) goto read_as_zero;
> vgic_lock_rank(v, rank);
> - *r = vgic_byte_read(rank->ipend, dabt.sign, offset);
> + *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -250,7 +247,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
> DABT_WORD)];
> if ( dabt.size == DABT_BYTE )
> - *r = vgic_byte_read(*r, dabt.sign, offset);
> + *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -263,7 +260,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
> DABT_WORD)];
> if ( dabt.size == DABT_BYTE )
> - *r = vgic_byte_read(*r, dabt.sign, offset);
> + *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -291,7 +288,7 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
> if ( rank == NULL) goto read_as_zero;
> vgic_lock_rank(v, rank);
> - *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
> + *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -300,12 +297,12 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
> if ( rank == NULL) goto read_as_zero;
> vgic_lock_rank(v, rank);
> - *r = vgic_byte_read(rank->pendsgi, dabt.sign, offset);
> + *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> /* Implementation defined -- read as zero */
> - case REG(0xfd0) ... REG(0xfe4):
> + case 0xfd0 ... 0xfe4:
> goto read_as_zero;
>
> case GICD_ICPIDR2:
> @@ -314,27 +311,27 @@ static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
> return 0;
>
> /* Implementation defined -- read as zero */
> - case REG(0xfec) ... REG(0xffc):
> + case 0xfec ... 0xffc:
> goto read_as_zero;
>
> /* Reserved -- read as zero */
> - case REG(0x00c) ... REG(0x01c):
> - case REG(0x040) ... REG(0x07c):
> - case REG(0x7fc):
> - case REG(0xbfc):
> - case REG(0xf04) ... REG(0xf0c):
> - case REG(0xf30) ... REG(0xfcc):
> + case 0x00c ... 0x01c:
> + case 0x040 ... 0x07c:
> + case 0x7fc:
> + case 0xbfc:
> + case 0xf04 ... 0xf0c:
> + case 0xf30 ... 0xfcc:
> goto read_as_zero;
>
> default:
> printk("vGICD: unhandled read r%d offset %#08x\n",
> - dabt.reg, offset);
> + dabt.reg, gicd_reg);
> return 0;
> }
>
> bad_width:
> printk("vGICD: bad read width %d r%d offset %#08x\n",
> - dabt.size, dabt.reg, offset);
> + dabt.size, dabt.reg, gicd_reg);
> domain_crash_synchronous();
> return 0;
>
> @@ -455,8 +452,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> struct cpu_user_regs *regs = guest_cpu_user_regs();
> register_t *r = select_user_reg(regs, dabt.reg);
> struct vgic_irq_rank *rank;
> - int offset = (int)(info->gpa - v->domain->arch.vgic.dbase);
> - int gicd_reg = REG(offset);
> + int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
> uint32_t tr;
>
> switch ( gicd_reg )
> @@ -473,7 +469,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> goto write_ignore;
>
> /* Implementation defined -- write ignored */
> - case REG(0x020) ... REG(0x03c):
> + case 0x020 ... 0x03c:
> goto write_ignore;
>
> case GICD_IGROUPR ... GICD_IGROUPRN:
> @@ -548,7 +544,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> DABT_WORD)] = *r;
> else
> vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
> - gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, offset);
> + gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -562,7 +558,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> DABT_WORD)] = *r;
> else
> vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
> - gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, offset);
> + gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, gicd_reg);
> vgic_unlock_rank(v, rank);
> return 1;
>
> @@ -602,7 +598,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> return 0;
>
> /* Implementation defined -- write ignored */
> - case REG(0xfd0) ... REG(0xfe4):
> + case 0xfd0 ... 0xfe4:
> goto write_ignore;
>
> /* R/O -- write ignore */
> @@ -610,27 +606,27 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
> goto write_ignore;
>
> /* Implementation defined -- write ignored */
> - case REG(0xfec) ... REG(0xffc):
> + case 0xfec ... 0xffc:
> goto write_ignore;
>
> /* Reserved -- write ignored */
> - case REG(0x00c) ... REG(0x01c):
> - case REG(0x040) ... REG(0x07c):
> - case REG(0x7fc):
> - case REG(0xbfc):
> - case REG(0xf04) ... REG(0xf0c):
> - case REG(0xf30) ... REG(0xfcc):
> + case 0x00c ... 0x01c:
> + case 0x040 ... 0x07c:
> + case 0x7fc:
> + case 0xbfc:
> + case 0xf04 ... 0xf0c:
> + case 0xf30 ... 0xfcc:
> goto write_ignore;
>
> default:
> printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
> - dabt.reg, *r, offset);
> + dabt.reg, *r, gicd_reg);
> return 0;
> }
>
> bad_width:
> printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
> - dabt.size, dabt.reg, *r, offset);
> + dabt.size, dabt.reg, *r, gicd_reg);
> domain_crash_synchronous();
> return 0;
>
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver
2014-06-12 13:36 ` [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver vijay.kilari
2014-06-12 16:42 ` Stefano Stabellini
@ 2014-06-15 16:37 ` Julien Grall
2014-06-17 12:37 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 16:37 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> REG macro does not compute any value and offset
> variable is no more required. Hence removed
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver
2014-06-12 13:36 ` [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver vijay.kilari
2014-06-12 16:42 ` Stefano Stabellini
2014-06-15 16:37 ` Julien Grall
@ 2014-06-17 12:37 ` Ian Campbell
2 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 12:37 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> REG macro does not compute any value and offset
> variable is no more required. Hence removed
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (14 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 15/21] xen/arm: Remove REG macro in vgic driver vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-15 17:04 ` Julien Grall
2014-06-17 13:21 ` Ian Campbell
2014-06-12 13:36 ` [PATCH v5 17/21] xen/arm: Add support for GIC v3 vijay.kilari
` (6 subsequent siblings)
22 siblings, 2 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Existing vGIC driver has both generic code and hw specific
code. Segregate vGIC low level driver into vgic-v2.c and
keep generic code in existing vgic.c file
some static generic functions in vgic.c is made as non-static
so that these generic functions can be used in vGIC v2 driver.
vGIC v2 driver registers required callbacks to generic vGIC
driver. This helps to plug in next version of vGIC drivers
like vGIC v3. These callbacks are registered per domain
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/Makefile | 2 +-
xen/arch/arm/vgic-v2.c | 510 ++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic.c | 484 ++++-----------------------------------
xen/include/asm-arm/domain.h | 2 +
xen/include/asm-arm/gic.h | 3 +
xen/include/asm-arm/vgic.h | 12 +
6 files changed, 573 insertions(+), 440 deletions(-)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 969ee52..20f59f4 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -26,7 +26,7 @@ obj-y += smpboot.o
obj-y += smp.o
obj-y += shutdown.o
obj-y += traps.o
-obj-y += vgic.o
+obj-y += vgic.o vgic-v2.o
obj-y += vtimer.o
obj-y += vuart.o
obj-y += hvm.o
diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
new file mode 100644
index 0000000..68956e5
--- /dev/null
+++ b/xen/arch/arm/vgic-v2.c
@@ -0,0 +1,510 @@
+/*
+ * xen/arch/arm/vgic-v2.c
+ *
+ * ARM Virtual Generic Interrupt Controller support v2
+ *
+ * Ian Campbell <ian.campbell@citrix.com>
+ * Copyright (c) 2011 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/bitops.h>
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/softirq.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+
+#include <asm/current.h>
+#include <asm/device.h>
+
+#include <asm/mmio.h>
+#include <asm/gic.h>
+#include <asm/vgic.h>
+
+extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
+ enum gic_sgi_mode irqmode, int virq,
+ unsigned long vcpu_mask);
+
+static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vgic_lock(v);
+ *r = v->domain->arch.vgic.ctlr;
+ vgic_unlock(v);
+ return 1;
+ case GICD_TYPER:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* No secure world support for guests. */
+ vgic_lock(v);
+ *r = ( (v->domain->max_vcpus << 5) & GICD_TYPE_CPUS )
+ |( ((v->domain->arch.vgic.nr_lines / 32)) & GICD_TYPE_LINES );
+ vgic_unlock(v);
+ return 1;
+ case GICD_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /*
+ * XXX Do we need a JEP106 manufacturer ID?
+ * Just use the physical h/w value for now
+ */
+ *r = 0x0000043b;
+ return 1;
+
+ /* Implementation defined -- read as zero */
+ case 0x020 ... 0x03c:
+ goto read_as_zero;
+
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ITARGETSR ... GICD_ITARGETSRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+
+ vgic_lock_rank(v, rank);
+ *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+
+ vgic_lock_rank(v, rank);
+ *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICFGR ... GICD_ICFGRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)];
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+
+ case GICD_SGIR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* Write only -- read unknown */
+ *r = 0xdeadbeef;
+ return 1;
+
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ /* Implementation defined -- read as zero */
+ case 0xfd0 ... 0xfe4:
+ goto read_as_zero;
+
+ case GICD_ICPIDR2:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled read from ICPIDR2\n");
+ return 0;
+
+ /* Implementation defined -- read as zero */
+ case 0xfec ... 0xffc:
+ goto read_as_zero;
+
+ /* Reserved -- read as zero */
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
+ goto read_as_zero;
+
+ default:
+ printk("vGICD: unhandled read r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ printk("vGICD: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int vgic_v2_to_sgi(struct vcpu *v, register_t sgir)
+{
+
+ int virq;
+ int irqmode;
+ enum gic_sgi_mode sgi_mode;
+ unsigned long vcpu_mask = 0;
+
+ irqmode = (sgir & GICD_SGI_TARGET_LIST_MASK) >> GICD_SGI_TARGET_LIST_SHIFT;
+ virq = (sgir & GICD_SGI_INTID_MASK);
+ vcpu_mask = (sgir & GICD_SGI_TARGET_MASK) >> GICD_SGI_TARGET_SHIFT;
+
+ /* Map GIC sgi value to enum value */
+ switch ( irqmode )
+ {
+ case GICD_SGI_TARGET_LIST_VAL:
+ sgi_mode = SGI_TARGET_LIST;
+ break;
+ case GICD_SGI_TARGET_OTHERS_VAL:
+ sgi_mode = SGI_TARGET_OTHERS;
+ break;
+ case GICD_SGI_TARGET_SELF_VAL:
+ sgi_mode = SGI_TARGET_SELF;
+ break;
+ default:
+ BUG();
+ }
+
+ return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
+}
+
+static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+ uint32_t tr;
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* Ignore all but the enable bit */
+ v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
+ return 1;
+
+ /* R/O -- write ignored */
+ case GICD_TYPER:
+ case GICD_IIDR:
+ goto write_ignore;
+
+ /* Implementation defined -- write ignored */
+ case 0x020 ... 0x03c:
+ goto write_ignore;
+
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable |= *r;
+ vgic_unlock_rank(v, rank);
+ /* The virtual irq is derived from register offset.
+ * The register difference is word difference. So divide by 2(DABT_WORD)
+ * to get Virtual irq number */
+ vgic_enable_irqs(v, (*r) & (~tr),
+ (gicd_reg - GICD_ISENABLER) >> DABT_WORD);
+ return 1;
+
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable &= ~*r;
+ vgic_unlock_rank(v, rank);
+ /* The virtual irq is derived from register offset.
+ * The register difference is word difference. So divide by 2(DABT_WORD)
+ * to get Virtual irq number */
+ vgic_disable_irqs(v, (*r) & tr,
+ (gicd_reg - GICD_ICENABLER) >> DABT_WORD);
+ return 1;
+
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ISPENDR);
+ return 0;
+
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ICPENDR);
+ return 0;
+
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ITARGETSR ... GICD_ITARGETSR + 7:
+ /* SGI/PPI target is read only */
+ goto write_ignore;
+
+ case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ if ( dabt.size == DABT_WORD )
+ rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ DABT_WORD)] = *r;
+ else
+ vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
+ gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ if ( dabt.size == DABT_WORD )
+ rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
+ DABT_WORD)] = *r;
+ else
+ vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
+ gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_ICFGR: /* SGIs */
+ goto write_ignore;
+ case GICD_ICFGR + 1: /* PPIs */
+ /* It is implementation defined if these are writeable. We chose not */
+ goto write_ignore;
+ case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
+ vgic_lock_rank(v, rank);
+ if ( rank == NULL) goto write_ignore;
+ rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+
+ case GICD_SGIR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return vgic_v2_to_sgi(v, *r);
+
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDSGIR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_CPENDSGIR);
+ return 0;
+
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDSGIR%d\n",
+ dabt.size ? "word" : "byte", *r, gicd_reg - GICD_SPENDSGIR);
+ return 0;
+
+ /* Implementation defined -- write ignored */
+ case 0xfd0 ... 0xfe4:
+ goto write_ignore;
+
+ /* R/O -- write ignore */
+ case GICD_ICPIDR2:
+ goto write_ignore;
+
+ /* Implementation defined -- write ignored */
+ case 0xfec ... 0xffc:
+ goto write_ignore;
+
+ /* Reserved -- write ignored */
+ case 0x00c ... 0x01c:
+ case 0x040 ... 0x07c:
+ case 0x7fc:
+ case 0xbfc:
+ case 0xf04 ... 0xf0c:
+ case 0xf30 ... 0xfcc:
+ goto write_ignore;
+
+ default:
+ printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
+ dabt.reg, *r, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
+ dabt.size, dabt.reg, *r, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+const struct mmio_handler_ops vgic_v2_distr_mmio_handler = {
+ .read_handler = vgic_v2_distr_mmio_read,
+ .write_handler = vgic_v2_distr_mmio_write,
+};
+
+static int vgic_v2_vcpu_init(struct vcpu *v)
+{
+ int i;
+
+ /* For SGI and PPI the target is always this CPU */
+ for ( i = 0 ; i < 8 ; i++ )
+ v->arch.vgic.private_irqs->itargets[i] =
+ (1<<(v->vcpu_id+0))
+ | (1<<(v->vcpu_id+8))
+ | (1<<(v->vcpu_id+16))
+ | (1<<(v->vcpu_id+24));
+
+ return 0;
+}
+
+static int vgic_v2_domain_init(struct domain *d)
+{
+ /* We rely on gicv_setup() to initialize dbase(vGIC distributor base) */
+ register_mmio_handler(d, &vgic_v2_distr_mmio_handler, d->arch.vgic.dbase,
+ PAGE_SIZE);
+
+ return 0;
+}
+
+const static struct vgic_ops vgic_v2_ops = {
+ .vcpu_init = vgic_v2_vcpu_init,
+ .domain_init = vgic_v2_domain_init,
+};
+
+int vgic_v2_init(struct domain *d)
+{
+ register_vgic_ops(d, &vgic_v2_ops);
+
+ return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index a6b1894..61c225f 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -31,15 +31,11 @@
#include <asm/gic.h>
#include <asm/vgic.h>
-static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info);
-static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info);
-
/*
* Returns rank corresponding to a GICD_<FOO><n> register for
* GICD_<FOO> with <b>-bits-per-interrupt.
*/
-static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b,
- int n, int s)
+struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n, int s)
{
int rank = REG_RANK_NR(b, (n >> s));
@@ -51,11 +47,6 @@ static struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b,
return NULL;
}
-const struct mmio_handler_ops vgic_distr_mmio_handler = {
- .read_handler = vgic_distr_mmio_read,
- .write_handler = vgic_distr_mmio_write,
-};
-
int domain_vgic_init(struct domain *d)
{
int i;
@@ -70,11 +61,23 @@ int domain_vgic_init(struct domain *d)
else
d->arch.vgic.nr_lines = 0; /* We don't need SPIs for the guest */
+ switch ( gic_hw_version() )
+ {
+ case GIC_V2:
+ vgic_v2_init(d);
+ break;
+ default:
+ return -ENODEV;
+ }
+
d->arch.vgic.shared_irqs =
xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_RANKS(d));
if ( d->arch.vgic.shared_irqs == NULL )
return -ENOMEM;
+ for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ )
+ spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
+
d->arch.vgic.pending_irqs =
xzalloc_array(struct pending_irq, d->arch.vgic.nr_lines);
if ( d->arch.vgic.pending_irqs == NULL )
@@ -88,18 +91,17 @@ int domain_vgic_init(struct domain *d)
INIT_LIST_HEAD(&d->arch.vgic.pending_irqs[i].inflight);
INIT_LIST_HEAD(&d->arch.vgic.pending_irqs[i].lr_queue);
}
- for (i=0; i<DOMAIN_NR_RANKS(d); i++)
- spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
- /*
- * We rely on gicv_setup() to initialize dbase(vGIC distributor base)
- */
- register_mmio_handler(d, &vgic_distr_mmio_handler,
- d->arch.vgic.dbase, PAGE_SIZE);
+ d->arch.vgic.handler->domain_init(d);
return 0;
}
+void register_vgic_ops(struct domain *d, const struct vgic_ops *ops)
+{
+ d->arch.vgic.handler = ops;
+}
+
void domain_vgic_free(struct domain *d)
{
xfree(d->arch.vgic.shared_irqs);
@@ -116,6 +118,8 @@ int vcpu_vgic_init(struct vcpu *v)
spin_lock_init(&v->arch.vgic.private_irqs->lock);
+ v->domain->arch.vgic.handler->vcpu_init(v);
+
memset(&v->arch.vgic.pending_irqs, 0, sizeof(v->arch.vgic.pending_irqs));
for (i = 0; i < 32; i++)
{
@@ -123,13 +127,6 @@ int vcpu_vgic_init(struct vcpu *v)
INIT_LIST_HEAD(&v->arch.vgic.pending_irqs[i].lr_queue);
}
- /* For SGI and PPI the target is always this CPU */
- for ( i = 0 ; i < 8 ; i++ )
- v->arch.vgic.private_irqs->itargets[i] =
- (1<<(v->vcpu_id+0))
- | (1<<(v->vcpu_id+8))
- | (1<<(v->vcpu_id+16))
- | (1<<(v->vcpu_id+24));
INIT_LIST_HEAD(&v->arch.vgic.inflight_irqs);
INIT_LIST_HEAD(&v->arch.vgic.lr_pending);
spin_lock_init(&v->arch.vgic.lock);
@@ -143,205 +140,7 @@ int vcpu_vgic_free(struct vcpu *v)
return 0;
}
-static int vgic_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
-{
- struct hsr_dabt dabt = info->dabt;
- struct cpu_user_regs *regs = guest_cpu_user_regs();
- register_t *r = select_user_reg(regs, dabt.reg);
- struct vgic_irq_rank *rank;
- int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
-
- switch ( gicd_reg )
- {
- case GICD_CTLR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- vgic_lock(v);
- *r = v->domain->arch.vgic.ctlr;
- vgic_unlock(v);
- return 1;
- case GICD_TYPER:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /* No secure world support for guests. */
- vgic_lock(v);
- *r = ( (v->domain->max_vcpus<<5) & GICD_TYPE_CPUS )
- |( ((v->domain->arch.vgic.nr_lines/32)) & GICD_TYPE_LINES );
- vgic_unlock(v);
- return 1;
- case GICD_IIDR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /*
- * XXX Do we need a JEP106 manufacturer ID?
- * Just use the physical h/w value for now
- */
- *r = 0x0000043b;
- return 1;
-
- /* Implementation defined -- read as zero */
- case 0x020 ... 0x03c:
- goto read_as_zero;
-
- case GICD_IGROUPR ... GICD_IGROUPRN:
- /* We do not implement security extensions for guests, read zero */
- goto read_as_zero;
-
- case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->ienable;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->ienable;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISPENDR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICPENDR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->ipend, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->iactive;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->iactive;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ITARGETSR ... GICD_ITARGETSRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
-
- vgic_lock_rank(v, rank);
- *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
- DABT_WORD)];
- if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != 0 && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
-
- vgic_lock_rank(v, rank);
- *r = rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
- DABT_WORD)];
- if ( dabt.size == DABT_BYTE )
- *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICFGR ... GICD_ICFGRN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)];
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_NSACR ... GICD_NSACRN:
- /* We do not implement security extensions for guests, read zero */
- goto read_as_zero;
-
- case GICD_SGIR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /* Write only -- read unknown */
- *r = 0xdeadbeef;
- return 1;
-
- case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_CPENDSGIR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_SPENDSGIR, DABT_WORD);
- if ( rank == NULL) goto read_as_zero;
- vgic_lock_rank(v, rank);
- *r = vgic_byte_read(rank->pendsgi, dabt.sign, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- /* Implementation defined -- read as zero */
- case 0xfd0 ... 0xfe4:
- goto read_as_zero;
-
- case GICD_ICPIDR2:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled read from ICPIDR2\n");
- return 0;
-
- /* Implementation defined -- read as zero */
- case 0xfec ... 0xffc:
- goto read_as_zero;
-
- /* Reserved -- read as zero */
- case 0x00c ... 0x01c:
- case 0x040 ... 0x07c:
- case 0x7fc:
- case 0xbfc:
- case 0xf04 ... 0xf0c:
- case 0xf30 ... 0xfcc:
- goto read_as_zero;
-
- default:
- printk("vGICD: unhandled read r%d offset %#08x\n",
- dabt.reg, gicd_reg);
- return 0;
- }
-
-bad_width:
- printk("vGICD: bad read width %d r%d offset %#08x\n",
- dabt.size, dabt.reg, gicd_reg);
- domain_crash_synchronous();
- return 0;
-
-read_as_zero:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- *r = 0;
- return 1;
-}
-
-static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
+void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
{
const unsigned long mask = r;
struct pending_irq *p;
@@ -364,7 +163,7 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n)
}
}
-static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
+void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
{
const unsigned long mask = r;
struct pending_irq *p;
@@ -397,241 +196,48 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n)
}
}
-static int vgic_to_sgi(struct vcpu *v, register_t sgir)
+int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq,
+ unsigned long vcpu_mask)
{
struct domain *d = v->domain;
- int virtual_irq;
- int filter;
int vcpuid;
int i;
- unsigned long vcpu_mask = 0;
ASSERT(d->max_vcpus < 8*sizeof(vcpu_mask));
- filter = (sgir & GICD_SGI_TARGET_LIST_MASK);
- virtual_irq = (sgir & GICD_SGI_INTID_MASK);
- ASSERT( virtual_irq < 16 );
+ ASSERT( virq < 16 );
- switch ( filter )
+ switch ( irqmode )
{
- case GICD_SGI_TARGET_LIST:
- vcpu_mask = (sgir & GICD_SGI_TARGET_MASK) >> GICD_SGI_TARGET_SHIFT;
- break;
- case GICD_SGI_TARGET_OTHERS:
- for ( i = 0; i < d->max_vcpus; i++ )
- {
- if ( i != current->vcpu_id && is_vcpu_running(d, i) )
- set_bit(i, &vcpu_mask);
- }
- break;
- case GICD_SGI_TARGET_SELF:
- set_bit(current->vcpu_id, &vcpu_mask);
- break;
- default:
- gdprintk(XENLOG_WARNING, "vGICD: unhandled GICD_SGIR write %"PRIregister" with wrong TargetListFilter field\n",
- sgir);
- return 0;
+ case SGI_TARGET_LIST:
+ break;
+ case SGI_TARGET_OTHERS:
+ for ( i = 0; i < d->max_vcpus; i++ )
+ {
+ if ( i != current->vcpu_id && is_vcpu_running(d, i) )
+ set_bit(i, &vcpu_mask);
+ }
+ break;
+ case SGI_TARGET_SELF:
+ set_bit(current->vcpu_id, &vcpu_mask);
+ break;
+ default:
+ gdprintk(XENLOG_WARNING, "vGICD: unhandled GICD_SGIR write %"PRIregister" with wrong mode\n",
+ sgir);
+ return 0;
}
for_each_set_bit( vcpuid, &vcpu_mask, d->max_vcpus )
{
if ( !is_vcpu_running(d, vcpuid) )
{
- gdprintk(XENLOG_WARNING, "vGICD: GICD_SGIR write r=%"PRIregister" vcpu_mask=%lx, wrong CPUTargetList\n",
+ gdprintk(XENLOG_WARNING, " write r=%"PRIregister" vcpu_mask=%lx, wrong CPUTargetList\n",
sgir, vcpu_mask);
continue;
}
- vgic_vcpu_inject_irq(d->vcpu[vcpuid], virtual_irq);
+ vgic_vcpu_inject_irq(d->vcpu[vcpuid], virq);
}
- return 1;
-}
-
-static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
-{
- struct hsr_dabt dabt = info->dabt;
- struct cpu_user_regs *regs = guest_cpu_user_regs();
- register_t *r = select_user_reg(regs, dabt.reg);
- struct vgic_irq_rank *rank;
- int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
- uint32_t tr;
-
- switch ( gicd_reg )
- {
- case GICD_CTLR:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- /* Ignore all but the enable bit */
- v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
- return 1;
-
- /* R/O -- write ignored */
- case GICD_TYPER:
- case GICD_IIDR:
- goto write_ignore;
-
- /* Implementation defined -- write ignored */
- case 0x020 ... 0x03c:
- goto write_ignore;
-
- case GICD_IGROUPR ... GICD_IGROUPRN:
- /* We do not implement security extensions for guests, write ignore */
- goto write_ignore;
-
- case GICD_ISENABLER ... GICD_ISENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISENABLER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- tr = rank->ienable;
- rank->ienable |= *r;
- vgic_unlock_rank(v, rank);
- vgic_enable_irqs(v, (*r) & (~tr),
- (gicd_reg - GICD_ISENABLER) >> DABT_WORD);
- return 1;
-
- case GICD_ICENABLER ... GICD_ICENABLERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICENABLER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- tr = rank->ienable;
- rank->ienable &= ~*r;
- vgic_unlock_rank(v, rank);
- vgic_disable_irqs(v, (*r) & tr,
- (gicd_reg - GICD_ICENABLER) >> DABT_WORD);
- return 1;
-
- case GICD_ISPENDR ... GICD_ISPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ISPENDR);
- return 0;
-
- case GICD_ICPENDR ... GICD_ICPENDRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_ICPENDR);
- return 0;
-
- case GICD_ISACTIVER ... GICD_ISACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ISACTIVER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- rank->iactive &= ~*r;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICACTIVER ... GICD_ICACTIVERN:
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 1, gicd_reg - GICD_ICACTIVER, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- rank->iactive &= ~*r;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ITARGETSR ... GICD_ITARGETSR + 7:
- /* SGI/PPI target is read only */
- goto write_ignore;
-
- case GICD_ITARGETSR + 8 ... GICD_ITARGETSRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_ITARGETSR, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- if ( dabt.size == DABT_WORD )
- rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
- DABT_WORD)] = *r;
- else
- vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
- gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 8, gicd_reg - GICD_IPRIORITYR, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- if ( dabt.size == DABT_WORD )
- rank->ipriority[REG_RANK_INDEX(8, gicd_reg - GICD_IPRIORITYR,
- DABT_WORD)] = *r;
- else
- vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
- gicd_reg - GICD_IPRIORITYR, DABT_WORD)], *r, gicd_reg);
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_ICFGR: /* SGIs */
- goto write_ignore;
- case GICD_ICFGR + 1: /* PPIs */
- /* It is implementation defined if these are writeable. We chose not */
- goto write_ignore;
- case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
- if ( dabt.size != DABT_WORD ) goto bad_width;
- rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
- if ( rank == NULL) goto write_ignore;
- vgic_lock_rank(v, rank);
- rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
- vgic_unlock_rank(v, rank);
- return 1;
-
- case GICD_NSACR ... GICD_NSACRN:
- /* We do not implement security extensions for guests, write ignore */
- goto write_ignore;
-
- case GICD_SGIR:
- if ( dabt.size != 2 )
- goto bad_width;
- return vgic_to_sgi(v, *r);
-
- case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ICPENDSGIR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_CPENDSGIR);
- return 0;
-
- case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
- if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
- printk("vGICD: unhandled %s write %#"PRIregister" to ISPENDSGIR%d\n",
- dabt.size ? "word" : "byte", *r, gicd_reg - GICD_SPENDSGIR);
- return 0;
-
- /* Implementation defined -- write ignored */
- case 0xfd0 ... 0xfe4:
- goto write_ignore;
-
- /* R/O -- write ignore */
- case GICD_ICPIDR2:
- goto write_ignore;
-
- /* Implementation defined -- write ignored */
- case 0xfec ... 0xffc:
- goto write_ignore;
-
- /* Reserved -- write ignored */
- case 0x00c ... 0x01c:
- case 0x040 ... 0x07c:
- case 0x7fc:
- case 0xbfc:
- case 0xf04 ... 0xf0c:
- case 0xf30 ... 0xfcc:
- goto write_ignore;
-
- default:
- printk("vGICD: unhandled write r%d=%"PRIregister" offset %#08x\n",
- dabt.reg, *r, gicd_reg);
- return 0;
- }
-
-bad_width:
- printk("vGICD: bad write width %d r%d=%"PRIregister" offset %#08x\n",
- dabt.size, dabt.reg, *r, gicd_reg);
- domain_crash_synchronous();
- return 0;
-write_ignore:
- if ( dabt.size != DABT_WORD ) goto bad_width;
return 1;
}
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 4321b7c..c95ee96 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -76,6 +76,8 @@ struct arch_domain
} virt_timer_base;
struct {
+ /* GIC HW version specific vGIC driver handler */
+ const struct vgic_ops *handler;
/*
* Covers access to other members of this struct _except_ for
* shared_irqs where each member contains its own locking.
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index a3ca9a0..d5b9bf9 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -53,8 +53,11 @@
#define GICD_SGI_TARGET_LIST_SHIFT (24)
#define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT)
#define GICD_SGI_TARGET_LIST (0UL<<GICD_SGI_TARGET_LIST_SHIFT)
+#define GICD_SGI_TARGET_LIST_VAL (0)
#define GICD_SGI_TARGET_OTHERS (1UL<<GICD_SGI_TARGET_LIST_SHIFT)
+#define GICD_SGI_TARGET_OTHERS_VAL (1)
#define GICD_SGI_TARGET_SELF (2UL<<GICD_SGI_TARGET_LIST_SHIFT)
+#define GICD_SGI_TARGET_SELF_VAL (2)
#define GICD_SGI_TARGET_SHIFT (16)
#define GICD_SGI_TARGET_MASK (0xFFUL<<GICD_SGI_TARGET_SHIFT)
#define GICD_SGI_GROUP1 (1UL<<15)
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 81e2740..399a241 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -86,6 +86,13 @@ struct vgic_irq_rank {
uint32_t itargets[8];
};
+struct vgic_ops {
+ /* Initialize vGIC */
+ int (*vcpu_init)(struct vcpu *v);
+ /* Domain specific initialization of vGIC */
+ int (*domain_init)(struct domain *d);
+};
+
/* Number of ranks of interrupt registers for a domain */
#define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_lines+31)/32)
@@ -145,6 +152,11 @@ extern int vcpu_vgic_init(struct vcpu *v);
extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
extern void vgic_clear_pending_irqs(struct vcpu *v);
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
+extern struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n, int s);
+extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
+extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
+extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
+int vgic_v2_init(struct domain *d);
extern int vcpu_vgic_free(struct vcpu *v);
#endif /* __ASM_ARM_VGIC_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-12 13:36 ` [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
@ 2014-06-15 17:04 ` Julien Grall
2014-06-17 13:19 ` Ian Campbell
2014-06-19 12:35 ` Vijay Kilari
2014-06-17 13:21 ` Ian Campbell
1 sibling, 2 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 17:04 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
You didn't address the comments I made on V4 for this patch.
See a copy of them inline...
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> +static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
I didn't review closer this function. I guess it's a simple copy from
vgic_distr_mmio_read?
[..]
> +static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
Same question here?
[..]
> + case GICD_ICFGR + 2 ... GICD_ICFGRN: /* SPIs */
> + if ( dabt.size != DABT_WORD ) goto bad_width;
> + rank = vgic_irq_rank(v, 2, gicd_reg - GICD_ICFGR, DABT_WORD);
> + vgic_lock_rank(v, rank);
> + if ( rank == NULL) goto write_ignore;
> + rank->icfg[REG_RANK_INDEX(2, gicd_reg - GICD_ICFGR, DABT_WORD)] = *r;
> + vgic_unlock_rank(v, rank);
> + return 1;
You've reintroduced the XSA-94 here (see bf70db7 vgic: Check rank in
GICD_ICFGR* emulation before locking). When you send a new version of a
serie, please *check* there is no update on this code which may fix error.
I saw you shared a part of the emulation between the distributor and the
redistributor in GICv3. I think you can also share with GICv2, this
could avoid fix in 2 places the same bug (or worst only fixing in 1 place).
[..]
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index a6b1894..61c225f 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
[..]
> int domain_vgic_init(struct domain *d)
> {
[..]
> + for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ )
> + spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
> +
Why did you move this 2 lines earlier? There were fine below...
> d->arch.vgic.pending_irqs =
> xzalloc_array(struct pending_irq, d->arch.vgic.nr_lines);
> if ( d->arch.vgic.pending_irqs == NULL )
> @@ -88,18 +91,17 @@ int domain_vgic_init(struct domain *d)
> INIT_LIST_HEAD(&d->arch.vgic.pending_irqs[i].inflight);
> INIT_LIST_HEAD(&d->arch.vgic.pending_irqs[i].lr_queue);
> }
> - for (i=0; i<DOMAIN_NR_RANKS(d); i++)
> - spin_lock_init(&d->arch.vgic.shared_irqs[i].lock);
Just here.
> -static int vgic_to_sgi(struct vcpu *v, register_t sgir)
> +int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq,
> + unsigned long vcpu_mask)
You can't assume that all the VCPU bits will fit in an unsigned long. We
will have to use cpumask_t at some point.
I'm fine if you don't handle it for now, but you need to *write down*
somewhere the limitation of this function.
[..]
> + case SGI_TARGET_OTHERS:
[..]
> + case SGI_TARGET_SELF:
For this 2 case, you can't assume that vcpu_mask will be equal to 0...
It comes from the GICD_SGIR...
> + default:
> + gdprintk(XENLOG_WARNING, "vGICD: unhandled GICD_SGIR write %"PRIregister" with wrong mode\n",
> + sgir);
> + return 0;
> }
>
> for_each_set_bit( vcpuid, &vcpu_mask, d->max_vcpus )
> {
> if ( !is_vcpu_running(d, vcpuid) )
> {
> - gdprintk(XENLOG_WARNING, "vGICD: GICD_SGIR write r=%"PRIregister" vcpu_mask=%lx, wrong CPUTargetList\n",
> + gdprintk(XENLOG_WARNING, " write r=%"PRIregister" vcpu_mask=%lx, wrong CPUTargetList\n",
For clarity, I would keep at least vGIC in the warning message.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-15 17:04 ` Julien Grall
@ 2014-06-17 13:19 ` Ian Campbell
2014-06-17 13:40 ` Julien Grall
2014-06-19 12:35 ` Vijay Kilari
1 sibling, 1 reply; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 13:19 UTC (permalink / raw)
To: Julien Grall
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On Sun, 2014-06-15 at 18:04 +0100, Julien Grall wrote:
> You've reintroduced the XSA-94 here (see bf70db7 vgic: Check rank in
> GICD_ICFGR* emulation before locking). When you send a new version of a
> serie, please *check* there is no update on this code which may fix error.
One technique I use here is, given the patch in file "x":
grep ^- x | cut -c2- > A
grep ^\+ x | cut -c2- > B
diff -u A B
It's far from perfect and relies on the code order not changing too
drastically over the movement, but it would have caught this.
> I saw you shared a part of the emulation between the distributor and the
> redistributor in GICv3. I think you can also share with GICv2, this
> could avoid fix in 2 places the same bug (or worst only fixing in 1 place).
I'm not convinced that sharing vgic-2 and vgic-3 code wouldn't end up
being more confusing in the long run.
> > -static int vgic_to_sgi(struct vcpu *v, register_t sgir)
> > +int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq,
> > + unsigned long vcpu_mask)
>
>
> You can't assume that all the VCPU bits will fit in an unsigned long. We
> will have to use cpumask_t at some point.
>
> I'm fine if you don't handle it for now, but you need to *write down*
> somewhere the limitation of this function.
To be fair, this is a preexisting restriction and this is far from the
only place which will need fixing.
> [..]
>
> > + case SGI_TARGET_OTHERS:
>
> [..]
>
> > + case SGI_TARGET_SELF:
>
> For this 2 case, you can't assume that vcpu_mask will be equal to 0...
> It comes from the GICD_SGIR...
This is passed from the caller, isn't it?
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-17 13:19 ` Ian Campbell
@ 2014-06-17 13:40 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-17 13:40 UTC (permalink / raw)
To: Ian Campbell
Cc: vijay.kilari, stefano.stabellini, Prasun.Kapoor, vijaya.kumar,
tim, xen-devel, stefano.stabellini
On 06/17/2014 02:19 PM, Ian Campbell wrote:
> On Sun, 2014-06-15 at 18:04 +0100, Julien Grall wrote:
>> You've reintroduced the XSA-94 here (see bf70db7 vgic: Check rank in
>> GICD_ICFGR* emulation before locking). When you send a new version of a
>> serie, please *check* there is no update on this code which may fix error.
>
> One technique I use here is, given the patch in file "x":
> grep ^- x | cut -c2- > A
> grep ^\+ x | cut -c2- > B
> diff -u A B
>
> It's far from perfect and relies on the code order not changing too
> drastically over the movement, but it would have caught this.
>
>> I saw you shared a part of the emulation between the distributor and the
>> redistributor in GICv3. I think you can also share with GICv2, this
>> could avoid fix in 2 places the same bug (or worst only fixing in 1 place).
>
> I'm not convinced that sharing vgic-2 and vgic-3 code wouldn't end up
> being more confusing in the long run.
There is about 200 lines common between v2 and v3 (I{C,S}ENABLER,
I{C,S}ACTIVER, IPRIORITYR, ICFGR...). Some of theses registers
implementation contains non-obvious code (when we will implement
correctly I*ACTIVER). Duplicating them will be very hard to maintain.
While it's not so important for this series. I think we should merge
them sooner or later.
>>> -static int vgic_to_sgi(struct vcpu *v, register_t sgir)
>>> +int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq,
>>> + unsigned long vcpu_mask)
>>
>>
>> You can't assume that all the VCPU bits will fit in an unsigned long. We
>> will have to use cpumask_t at some point.
>>
>> I'm fine if you don't handle it for now, but you need to *write down*
>> somewhere the limitation of this function.
>
> To be fair, this is a preexisting restriction and this is far from the
> only place which will need fixing.
It might be a preexisting condition, but the previous version was taking
care of the vcpu_mask internally. Now we are using it as an argument.
AFAIK, this is the only place where we use unsigned long to describe a
list of vcpu. Every other place in Xen use correctly cpumask.
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-15 17:04 ` Julien Grall
2014-06-17 13:19 ` Ian Campbell
@ 2014-06-19 12:35 ` Vijay Kilari
1 sibling, 0 replies; 87+ messages in thread
From: Vijay Kilari @ 2014-06-19 12:35 UTC (permalink / raw)
To: Julien Grall
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On Sun, Jun 15, 2014 at 10:34 PM, Julien Grall <julien.grall@linaro.org> wrote:
> Hi Vijay,
>
> You didn't address the comments I made on V4 for this patch.
> See a copy of them inline...
>
>
> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
>>
>> +static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
>
>
> I didn't review closer this function. I guess it's a simple copy from
> vgic_distr_mmio_read?
Yes, it is just code movement
>
> [..]
>
>
>> +static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
>
>
> Same question here?
Yes, it is just code movement
>> -static int vgic_to_sgi(struct vcpu *v, register_t sgir)
>> +int vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode
>> irqmode, int virq,
>> + unsigned long vcpu_mask)
>
>
>
> You can't assume that all the VCPU bits will fit in an unsigned long. We
> will have to use cpumask_t at some point.
>
> I'm fine if you don't handle it for now, but you need to *write down*
> somewhere the limitation of this function.
I have just put TODO here. IMO vcpu_mask cannot be more than
8 bits (8 cpus) in GICv2 and 16 bits (16 cpus) in GICv3.
>
>
> [..]
>
>> + case SGI_TARGET_OTHERS:
>
>
> [..]
>
>> + case SGI_TARGET_SELF:
>
>
> For this 2 case, you can't assume that vcpu_mask will be equal to 0...
> It comes from the GICD_SGIR...
Yes, it comes from GICD_SGIR emulation write. Only way to check is to
put an assert
Regards
Vijay
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-12 13:36 ` [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
2014-06-15 17:04 ` Julien Grall
@ 2014-06-17 13:21 ` Ian Campbell
2014-06-18 3:33 ` Vijay Kilari
1 sibling, 1 reply; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 13:21 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, vijaya.kumar, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> +extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
> + enum gic_sgi_mode irqmode, int virq,
> + unsigned long vcpu_mask);
No externs in C files please. Put them in the appropriate header.
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-17 13:21 ` Ian Campbell
@ 2014-06-18 3:33 ` Vijay Kilari
2014-06-18 9:17 ` Julien Grall
0 siblings, 1 reply; 87+ messages in thread
From: Vijay Kilari @ 2014-06-18 3:33 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel, Stefano Stabellini
On Tue, Jun 17, 2014 at 6:51 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
>> +extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
>> + enum gic_sgi_mode irqmode, int virq,
>> + unsigned long vcpu_mask);
>
> No externs in C files please. Put them in the appropriate header.
OK. I remember why I placed this here.
The enum gic_sig_mode is defined in gic.h and used by both gic and vgic
C files. So this function declaration in vgic.h requires gic.h and
gic.h requires vgic.h.
So there is cross dependency between vgic.h and gic.h file
Solution is to move enum gic_sgi_mode to vgic.h which I will take care
>
> Ian.
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver
2014-06-18 3:33 ` Vijay Kilari
@ 2014-06-18 9:17 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-18 9:17 UTC (permalink / raw)
To: Vijay Kilari, Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Tim Deegan,
xen-devel, Stefano Stabellini
On 18/06/14 04:33, Vijay Kilari wrote:
> On Tue, Jun 17, 2014 at 6:51 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
>> On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
>>> +extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
>>> + enum gic_sgi_mode irqmode, int virq,
>>> + unsigned long vcpu_mask);
>>
>> No externs in C files please. Put them in the appropriate header.
>
> OK. I remember why I placed this here.
> The enum gic_sig_mode is defined in gic.h and used by both gic and vgic
> C files. So this function declaration in vgic.h requires gic.h and
> gic.h requires vgic.h.
> So there is cross dependency between vgic.h and gic.h file
>
> Solution is to move enum gic_sgi_mode to vgic.h which I will take care
enum gic_sgi_mode belongs to gic.h not vgic.h. Please use a forward
declaration in vgic.h.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 17/21] xen/arm: Add support for GIC v3
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (15 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 16/21] xen/arm: split vgic driver into generic and vgic-v2 driver vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 17:03 ` Stefano Stabellini
2014-06-15 18:10 ` Julien Grall
2014-06-12 13:36 ` [PATCH v5 18/21] xen/arm: Add virtual GICv3 support vijay.kilari
` (5 subsequent siblings)
22 siblings, 2 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Add support for GIC v3 specification System register access(SRE)
is enabled to access cpu and virtual interface regiseters based
on kernel GICv3 driver.
This patch adds only basic v3 support.
Does not support Interrupt Translation support (ITS)
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/gic-v3.c | 1152 +++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/domain.h | 8 +
xen/include/asm-arm/gic.h | 20 +
xen/include/asm-arm/gic_v3_defs.h | 157 +++++
xen/include/asm-arm/processor.h | 14 +
xen/include/xen/lib.h | 2 +
7 files changed, 1354 insertions(+)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 20f59f4..1684c09 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -11,6 +11,7 @@ obj-y += domctl.o
obj-y += sysctl.o
obj-y += domain_build.o
obj-y += gic.o gic-v2.o
+obj-$(CONFIG_ARM_64) += gic-v3.o
obj-y += io.o
obj-y += irq.o
obj-y += kernel.o
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
new file mode 100644
index 0000000..29cfd93
--- /dev/null
+++ b/xen/arch/arm/gic-v3.c
@@ -0,0 +1,1152 @@
+/*
+ * xen/arch/arm/gic-v3.c
+ *
+ * ARM Generic Interrupt Controller support v3 version
+ * based on xen/arch/arm/gic-v2.c and kernel GICv3 driver
+ *
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>, Cavium Inc
+ * ported to Xen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/cpu.h>
+#include <xen/mm.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+#include <xen/errno.h>
+#include <xen/delay.h>
+#include <xen/device_tree.h>
+#include <asm/p2m.h>
+#include <asm/domain.h>
+#include <asm/io.h>
+#include <asm/device.h>
+#include <asm/gic.h>
+#include <asm/gic_v3_defs.h>
+
+struct rdist_region {
+ paddr_t base;
+ paddr_t size;
+ void __iomem *map_base;
+};
+
+/* Global state */
+static struct {
+ paddr_t dbase; /* Address of distributor registers */
+ paddr_t dbase_size;
+ void __iomem *map_dbase; /* Mapped address of distributor registers */
+ struct rdist_region *rdist_regions;
+ uint32_t rdist_stride;
+ unsigned int rdist_count; /* Number of rdist regions count */
+ unsigned int nr_priorities;
+ spinlock_t lock;
+} gicv3;
+
+static struct gic_info gicv3_info;
+
+/* per-cpu re-distributor base */
+static DEFINE_PER_CPU(void __iomem*, rbase);
+
+#define GICD (gicv3.map_dbase)
+#define GICD_RDIST_BASE (this_cpu(rbase))
+#define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K)
+
+/*
+ * Saves all 16(Max) LR registers. Though number of LRs implemented
+ * is implementation specific.
+ */
+static inline void gicv3_save_lrs(int nr_lrs, struct vcpu *v)
+{
+ /* Fall through for all the cases */
+ switch ( nr_lrs )
+ {
+ case 16:
+ v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2);
+ case 15:
+ v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2);
+ case 14:
+ v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2);
+ case 13:
+ v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2);
+ case 12:
+ v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2);
+ case 11:
+ v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2);
+ case 10:
+ v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2);
+ case 9:
+ v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2);
+ case 8:
+ v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2);
+ case 7:
+ v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2);
+ case 6:
+ v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2);
+ case 5:
+ v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2);
+ case 4:
+ v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2);
+ case 3:
+ v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2);
+ case 2:
+ v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2);
+ case 1:
+ v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+/*
+ * Restores all 16(Max) LR registers. Though number of LRs implemented
+ * is implementation specific.
+ */
+static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
+{
+ /* Fall through for all the cases */
+ switch ( nr_lrs )
+ {
+ case 16:
+ WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2);
+ case 15:
+ WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2);
+ case 14:
+ WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2);
+ case 13:
+ WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2);
+ case 12:
+ WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2);
+ case 11:
+ WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2);
+ case 10:
+ WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2);
+ case 9:
+ WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2);
+ case 8:
+ WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2);
+ case 7:
+ WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2);
+ case 6:
+ WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2);
+ case 5:
+ WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2);
+ case 4:
+ WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2);
+ case 3:
+ WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2);
+ case 2:
+ WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2);
+ case 1:
+ WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static uint64_t gicv3_ich_read_lr(int lr)
+{
+ switch ( lr )
+ {
+ case 0: return READ_SYSREG(ICH_LR0_EL2);
+ case 1: return READ_SYSREG(ICH_LR1_EL2);
+ case 2: return READ_SYSREG(ICH_LR2_EL2);
+ case 3: return READ_SYSREG(ICH_LR3_EL2);
+ case 4: return READ_SYSREG(ICH_LR4_EL2);
+ case 5: return READ_SYSREG(ICH_LR5_EL2);
+ case 6: return READ_SYSREG(ICH_LR6_EL2);
+ case 7: return READ_SYSREG(ICH_LR7_EL2);
+ case 8: return READ_SYSREG(ICH_LR8_EL2);
+ case 9: return READ_SYSREG(ICH_LR9_EL2);
+ case 10: return READ_SYSREG(ICH_LR10_EL2);
+ case 11: return READ_SYSREG(ICH_LR11_EL2);
+ case 12: return READ_SYSREG(ICH_LR12_EL2);
+ case 13: return READ_SYSREG(ICH_LR13_EL2);
+ case 14: return READ_SYSREG(ICH_LR14_EL2);
+ case 15: return READ_SYSREG(ICH_LR15_EL2);
+ default:
+ BUG();
+ }
+}
+
+static void gicv3_ich_write_lr(int lr, uint64_t val)
+{
+ switch ( lr )
+ {
+ case 0:
+ WRITE_SYSREG(val, ICH_LR0_EL2);
+ break;
+ case 1:
+ WRITE_SYSREG(val, ICH_LR1_EL2);
+ break;
+ case 2:
+ WRITE_SYSREG(val, ICH_LR2_EL2);
+ break;
+ case 3:
+ WRITE_SYSREG(val, ICH_LR3_EL2);
+ break;
+ case 4:
+ WRITE_SYSREG(val, ICH_LR4_EL2);
+ break;
+ case 5:
+ WRITE_SYSREG(val, ICH_LR5_EL2);
+ break;
+ case 6:
+ WRITE_SYSREG(val, ICH_LR6_EL2);
+ break;
+ case 7:
+ WRITE_SYSREG(val, ICH_LR7_EL2);
+ break;
+ case 8:
+ WRITE_SYSREG(val, ICH_LR8_EL2);
+ break;
+ case 9:
+ WRITE_SYSREG(val, ICH_LR9_EL2);
+ break;
+ case 10:
+ WRITE_SYSREG(val, ICH_LR10_EL2);
+ break;
+ case 11:
+ WRITE_SYSREG(val, ICH_LR11_EL2);
+ break;
+ case 12:
+ WRITE_SYSREG(val, ICH_LR12_EL2);
+ break;
+ case 13:
+ WRITE_SYSREG(val, ICH_LR13_EL2);
+ break;
+ case 14:
+ WRITE_SYSREG(val, ICH_LR14_EL2);
+ break;
+ case 15:
+ WRITE_SYSREG(val, ICH_LR15_EL2);
+ break;
+ default:
+ return;
+ }
+ isb();
+}
+
+/*
+ * System Register Enable (SRE). Enable to access CPU & Virtual
+ * interface registers as system registers in EL2
+ */
+static void gicv3_enable_sre(void)
+{
+ uint32_t val;
+
+ val = READ_SYSREG32(ICC_SRE_EL2);
+ val |= GICC_SRE_EL2_SRE | GICC_SRE_EL2_ENEL1;
+
+ WRITE_SYSREG32(val, ICC_SRE_EL2);
+ isb();
+}
+
+/* Wait for completion of a distributor change */
+static void gicv3_do_wait_for_rwp(void __iomem *base)
+{
+ uint32_t val;
+ bool_t timeout = 0;
+ s_time_t deadline = NOW() + MILLISECS(1000);
+
+ do {
+ val = readl_relaxed(base + GICD_CTLR);
+ if ( !(val & GICD_CTLR_RWP) )
+ break;
+ if ( NOW() > deadline )
+ {
+ timeout = 1;
+ break;
+ }
+ cpu_relax();
+ udelay(1);
+ } while ( 1 );
+
+ if ( timeout )
+ dprintk(XENLOG_ERR, "RWP timeout\n");
+}
+
+static void gicv3_dist_wait_for_rwp(void)
+{
+ gicv3_do_wait_for_rwp(GICD);
+}
+
+static void gicv3_redist_wait_for_rwp(void)
+{
+ gicv3_do_wait_for_rwp(GICD_RDIST_BASE);
+}
+
+static void gicv3_wait_for_rwp(int irq)
+{
+ if ( irq < NR_LOCAL_IRQS )
+ gicv3_redist_wait_for_rwp();
+ else
+ gicv3_dist_wait_for_rwp();
+}
+
+static unsigned int gicv3_get_cpu_from_mask(const cpumask_t *cpumask)
+{
+ unsigned int cpu;
+ cpumask_t possible_mask;
+
+ cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
+ cpu = cpumask_any(&possible_mask);
+
+ return cpu;
+}
+
+static void restore_aprn_regs(const union gic_state_data *d)
+{
+ /* Write APRn register based on number of priorities
+ platform has implemented */
+ switch ( gicv3.nr_priorities )
+ {
+ case 7:
+ WRITE_SYSREG32(d->v3.apr0[2], ICH_AP0R2_EL2);
+ WRITE_SYSREG32(d->v3.apr1[2], ICH_AP1R2_EL2);
+ /* Fall through */
+ case 6:
+ WRITE_SYSREG32(d->v3.apr0[1], ICH_AP0R1_EL2);
+ WRITE_SYSREG32(d->v3.apr1[1], ICH_AP1R1_EL2);
+ /* Fall through */
+ case 5:
+ WRITE_SYSREG32(d->v3.apr0[0], ICH_AP0R0_EL2);
+ WRITE_SYSREG32(d->v3.apr1[0], ICH_AP1R0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void save_aprn_regs(union gic_state_data *d)
+{
+ /* Read APRn register based on number of priorities
+ platform has implemented */
+ switch ( gicv3.nr_priorities )
+ {
+ case 7:
+ d->v3.apr0[2] = READ_SYSREG32(ICH_AP0R2_EL2);
+ d->v3.apr1[2] = READ_SYSREG32(ICH_AP1R2_EL2);
+ /* Fall through */
+ case 6:
+ d->v3.apr0[1] = READ_SYSREG32(ICH_AP0R1_EL2);
+ d->v3.apr1[1] = READ_SYSREG32(ICH_AP1R1_EL2);
+ /* Fall through */
+ case 5:
+ d->v3.apr0[0] = READ_SYSREG32(ICH_AP0R0_EL2);
+ d->v3.apr1[0] = READ_SYSREG32(ICH_AP1R0_EL2);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void gicv3_save_state(struct vcpu *v)
+{
+
+ /* No need for spinlocks here because interrupts are disabled around
+ * this call and it only accesses struct vcpu fields that cannot be
+ * accessed simultaneously by another pCPU.
+ *
+ * Make sure all stores to the GIC via the memory mapped interface
+ * are now visible to the system register interface
+ */
+ dsb(sy);
+ v->arch.gic.v3.vmcr = READ_SYSREG32(ICH_VMCR_EL2);
+ gicv3_save_lrs(gicv3_info.nr_lrs, v);
+ save_aprn_regs(&v->arch.gic);
+}
+
+static void gicv3_restore_state(const struct vcpu *v)
+{
+ WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2);
+ restore_aprn_regs(&v->arch.gic);
+ gicv3_restore_lrs(gicv3_info.nr_lrs, v);
+
+ /*
+ * Make sure all stores are visible the GIC
+ */
+ dsb(sy);
+}
+
+static void gicv3_dump_state(const struct vcpu *v)
+{
+ int i;
+
+ if ( v == current )
+ {
+ for ( i = 0; i < gicv3_info.nr_lrs; i++ )
+ printk(" HW_LR[%d]=%lx\n", i, gicv3_ich_read_lr(i));
+ }
+ else
+ {
+ for ( i = 0; i < gicv3_info.nr_lrs; i++ )
+ printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]);
+ }
+}
+
+static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset)
+{
+ u32 mask = 1 << (irqd->irq % 32);
+ void __iomem *base;
+
+ if ( irqd->irq < NR_GIC_LOCAL_IRQS )
+ base = GICD_RDIST_SGI_BASE;
+ else
+ base = GICD;
+
+ writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
+ gicv3_wait_for_rwp(irqd->irq);
+}
+
+static void gicv3_unmask_irq(struct irq_desc *irqd)
+{
+ gicv3_poke_irq(irqd, GICD_ISENABLER);
+}
+
+static void gicv3_mask_irq(struct irq_desc *irqd)
+{
+ gicv3_poke_irq(irqd, GICD_ICENABLER);
+}
+
+static void gicv3_eoi_irq(struct irq_desc *irqd)
+{
+ /* Lower the priority */
+ WRITE_SYSREG32(irqd->irq, ICC_EOIR1_EL1);
+ isb();
+}
+
+static void gicv3_dir_irq(struct irq_desc *irqd)
+{
+ /* Deactivate */
+ WRITE_SYSREG32(irqd->irq, ICC_DIR_EL1);
+ isb();
+}
+
+static unsigned int gicv3_read_irq(void)
+{
+ return (READ_SYSREG32(ICC_IAR1_EL1) & GICC_IA_IRQ);
+}
+
+static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
+{
+ uint64_t mpidr = cpu_logical_map(cpu);
+ return (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+}
+
+static void gicv3_set_irq_properties(struct irq_desc *desc,
+ const cpumask_t *cpu_mask,
+ unsigned int priority)
+{
+ uint32_t cfg, edgebit;
+ uint64_t affinity;
+ void __iomem *base;
+ unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask);
+ unsigned int irq = desc->irq;
+ unsigned int type = desc->arch.type;
+
+ /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
+ ASSERT(irq >= NR_GIC_SGI);
+
+ spin_lock(&gicv3.lock);
+
+ if ( irq < NR_GIC_LOCAL_IRQS)
+ base = GICD + GICD_ICFGR + (irq / 16) * 4;
+ else
+ base = GICD_RDIST_SGI_BASE + GICR_ICFGR1;
+
+ cfg = readl_relaxed(base);
+
+ edgebit = 2u << (2 * (irq % 16));
+ if ( type & DT_IRQ_TYPE_LEVEL_MASK )
+ cfg &= ~edgebit;
+ else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
+ cfg |= edgebit;
+
+ writel_relaxed(cfg, base);
+
+ affinity = gicv3_mpidr_to_affinity(cpu);
+ /* Make sure we don't broadcast the interrupt */
+ affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
+
+ if ( irq >= NR_GIC_LOCAL_IRQS )
+ writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8));
+
+ /* Set priority */
+ if ( irq < NR_GIC_LOCAL_IRQS )
+ writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq);
+ else
+ writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
+
+ spin_unlock(&gicv3.lock);
+}
+
+static void __init gicv3_dist_init(void)
+{
+ uint32_t type;
+ uint32_t priority;
+ uint64_t affinity;
+ int i;
+
+ /* Disable the distributor */
+ writel_relaxed(0, GICD + GICD_CTLR);
+
+ type = readl_relaxed(GICD + GICD_TYPER);
+ gicv3_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
+
+ printk("GICv3: %d lines, (IID %8.8x).\n",
+ gicv3_info.nr_lines, readl_relaxed(GICD + GICD_IIDR));
+
+ /* Default all global IRQs to level, active low */
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 16 )
+ writel_relaxed(0, GICD + GICD_ICFGR + (i / 16) * 4);
+
+ /* Default priority for global interrupts */
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 4 )
+ {
+ priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
+ GIC_PRI_IRQ << 8 | GIC_PRI_IRQ);
+ writel_relaxed(priority, GICD + GICD_IPRIORITYR + (i / 4) * 4);
+ }
+
+ /* Disable all global interrupts */
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 32 )
+ writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4);
+
+ gicv3_dist_wait_for_rwp();
+
+ /* Turn on the distributor */
+ writel_relaxed(GICD_CTL_ENABLE | GICD_CTLR_ARE_NS |
+ GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
+
+ /* Route all global IRQs to this CPU */
+ affinity = gicv3_mpidr_to_affinity(smp_processor_id());
+ /* Make sure we don't broadcast the interrupt */
+ affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
+
+ for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i++ )
+ writeq_relaxed(affinity, GICD + GICD_IROUTER + i * 8);
+}
+
+static int gicv3_enable_redist(void)
+{
+ uint32_t val;
+ bool_t timeout = 0;
+ s_time_t deadline = NOW() + MILLISECS(1000);
+
+ /* Wake up this CPU redistributor */
+ val = readl_relaxed(GICD_RDIST_BASE + GICR_WAKER);
+ val &= ~GICR_WAKER_ProcessorSleep;
+ writel_relaxed(val, GICD_RDIST_BASE + GICR_WAKER);
+
+ do {
+ val = readl_relaxed(GICD_RDIST_BASE + GICR_WAKER);
+ if ( !(val & GICR_WAKER_ChildrenAsleep) )
+ break;
+ if ( NOW() > deadline )
+ {
+ timeout = 1;
+ break;
+ }
+ cpu_relax();
+ udelay(1);
+ } while ( timeout );
+
+ if ( timeout )
+ {
+ dprintk(XENLOG_ERR, "GICv3: Redist enable RWP timeout\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static int __init gicv3_populate_rdist(void)
+{
+ int i;
+ uint32_t aff;
+ uint32_t reg;
+ uint64_t typer;
+ uint64_t mpidr = cpu_logical_map(smp_processor_id());
+
+ /*
+ * Convert affinity to a 32bit value that can be matched to GICR_TYPER
+ * bits [63:32]
+ */
+ aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
+ MPIDR_AFFINITY_LEVEL(mpidr, 0));
+
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ void __iomem *ptr = gicv3.rdist_regions[i].map_base;
+
+ reg = readl_relaxed(ptr + GICR_PIDR2) & GICR_PIDR2_ARCH_MASK;
+ if ( reg != (GICV3_GICR_PIDR2 & GICR_PIDR2_ARCH_MASK) )
+ {
+ dprintk(XENLOG_ERR,
+ "GICv3: No redistributor present @%"PRIpaddr"\n",
+ gicv3.rdist_regions[i].base);
+ break;
+ }
+
+ do {
+ typer = readq_relaxed(ptr + GICR_TYPER);
+
+ if ( (typer >> 32) == aff )
+ {
+ this_cpu(rbase) = ptr;
+ printk("GICv3: CPU%d: Found redistributor in region %d @%p\n",
+ smp_processor_id(), i, ptr);
+ return 0;
+ }
+ if ( gicv3.rdist_stride )
+ ptr += gicv3.rdist_stride;
+ else
+ {
+ ptr += SZ_64K * 2;
+ if ( typer & GICR_TYPER_VLPIS )
+ ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
+ }
+
+ } while ( !(typer & GICR_TYPER_LAST) );
+ }
+
+ dprintk(XENLOG_ERR, "GICv3: CPU%d: mpidr 0x%x has no re-distributor!\n",
+ smp_processor_id(), cpu_logical_map(smp_processor_id()));
+ return -ENODEV;
+}
+
+static int __cpuinit gicv3_cpu_init(void)
+{
+ int i;
+ uint32_t priority;
+
+ /* Register ourselves with the rest of the world */
+ if ( gicv3_populate_rdist() )
+ return -ENODEV;
+
+ if ( gicv3_enable_redist() )
+ return -ENODEV;
+
+ /* Set priority on PPI and SGI interrupts */
+ priority = (GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 | GIC_PRI_IPI << 8 |
+ GIC_PRI_IPI);
+ for (i = 0; i < NR_GIC_SGI; i += 4)
+ writel_relaxed(priority,
+ GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + (i / 4) * 4);
+
+ priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | GIC_PRI_IRQ << 8 |
+ GIC_PRI_IRQ);
+ for (i = NR_GIC_SGI; i < NR_GIC_LOCAL_IRQS; i += 4)
+ writel_relaxed(priority,
+ GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + (i / 4) * 4);
+
+ /*
+ * Disable all PPI interrupts, ensure all SGI interrupts are
+ * enabled.
+ */
+ writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
+ writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
+
+ gicv3_redist_wait_for_rwp();
+
+ /* Enable system registers */
+ gicv3_enable_sre();
+
+ /* No priority grouping */
+ WRITE_SYSREG32(0, ICC_BPR1_EL1);
+
+ /* Set priority mask register */
+ WRITE_SYSREG32(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
+
+ /* EOI drops priority too (mode 0) */
+ WRITE_SYSREG32(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1);
+ isb();
+
+ /* Enable Group1 interrupts */
+ WRITE_SYSREG32(1, ICC_IGRPEN1_EL1);
+ isb();
+
+ return 0;
+}
+
+static void gicv3_cpu_disable(void)
+{
+ WRITE_SYSREG32(0, ICC_CTLR_EL1);
+ isb();
+}
+
+static void __cpuinit gicv3_hyp_init(void)
+{
+ uint32_t vtr;
+
+ vtr = READ_SYSREG32(ICH_VTR_EL2);
+ gicv3_info.nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
+ gicv3.nr_priorities = ((vtr >> GICH_VTR_PRIBITS_SHIFT) &
+ GICH_VTR_PRIBITS_MASK) + 1;
+
+ ASSERT((gicv3.nr_priorities > 4 && gicv3.nr_priorities < 8));
+
+ WRITE_SYSREG32(GICH_VMCR_EOI | GICH_VMCR_VENG1, ICH_VMCR_EL2);
+ WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2);
+
+ update_cpu_lr_mask();
+}
+
+/* Set up the per-CPU parts of the GIC for a secondary CPU */
+static int gicv3_secondary_cpu_init(void)
+{
+ int res;
+
+ spin_lock(&gicv3.lock);
+
+ res = gicv3_cpu_init();
+ gicv3_hyp_init();
+
+ spin_unlock(&gicv3.lock);
+
+ return res;
+}
+
+static void __cpuinit gicv3_hyp_disable(void)
+{
+ uint32_t vtr;
+
+ vtr = READ_SYSREG32(ICH_HCR_EL2);
+ vtr &= ~0x1;
+ WRITE_SYSREG32(vtr, ICH_HCR_EL2);
+ isb();
+}
+
+static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
+ uint64_t cluster_id)
+{
+ int cpu = *base_cpu;
+ uint64_t mpidr = cpu_logical_map(cpu);
+ u16 tlist = 0;
+
+ while ( cpu < nr_cpu_ids )
+ {
+ /*
+ * If we ever get a cluster of more than 16 CPUs, just
+ * scream and skip that CPU.
+ */
+ if ( (mpidr & 0xff) >= 16 )
+ {
+ dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
+ goto out;
+ }
+ tlist |= 1 << (mpidr & 0xf);
+
+ cpu = cpumask_next(cpu, mask);
+ if ( cpu == nr_cpu_ids )
+ {
+ cpu--;
+ goto out;
+ }
+
+ mpidr = cpu_logical_map(cpu);
+ if ( cluster_id != (mpidr & ~0xffUL) ) {
+ cpu--;
+ goto out;
+ }
+ }
+out:
+ *base_cpu = cpu;
+
+ return tlist;
+}
+
+static void gicv3_send_sgi(const cpumask_t *cpumask, enum gic_sgi sgi,
+ enum gic_sgi_mode mode)
+{
+ int cpu = 0;
+ uint64_t val;
+
+ dsb(sy);
+
+ for_each_cpu(cpu, cpumask)
+ {
+ uint64_t cluster_id = cpu_logical_map(cpu) & ~0xffUL;
+ u16 tlist;
+
+ /* Get targetlist for the cluster to send SGI */
+ tlist = gicv3_compute_target_list(&cpu, cpumask, cluster_id);
+
+ /*
+ * Prepare affinity path of the cluster for which SGI is generated
+ * along with SGI number
+ */
+ val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 |
+ MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 |
+ sgi << 24 |
+ MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 |
+ tlist);
+
+ WRITE_SYSREG(val, ICC_SGI1R_EL1);
+ }
+ /* Force above writes to ICC_SGI1R_EL1 */
+ isb();
+}
+
+/* Shut down the per-CPU GIC interface */
+static void gicv3_disable_interface(void)
+{
+ spin_lock(&gicv3.lock);
+
+ gicv3_cpu_disable();
+ gicv3_hyp_disable();
+
+ spin_unlock(&gicv3.lock);
+}
+
+static void gicv3_update_lr(int lr, const struct pending_irq *p,
+ unsigned int state)
+{
+ uint64_t grp = GICH_LR_GRP1;
+ uint64_t val = 0;
+
+ BUG_ON(lr >= gicv3_info.nr_lrs);
+ BUG_ON(lr < 0);
+
+ val = (((uint64_t)state & 0x3) << GICH_LR_STATE_SHIFT) | grp;
+ val |= ((uint64_t)p->priority & 0xff) << GICH_LR_PRIORITY_SHIFT;
+ val |= ((uint64_t)p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT;
+
+ if ( p->desc != NULL )
+ val |= GICH_LR_HW | (((uint64_t)p->desc->irq & GICH_LR_PHYSICAL_MASK)
+ << GICH_LR_PHYSICAL_SHIFT);
+
+ gicv3_ich_write_lr(lr, val);
+}
+
+static void gicv3_clear_lr(int lr)
+{
+ gicv3_ich_write_lr(lr, 0);
+}
+
+static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
+{
+ uint64_t lrv;
+
+ lrv = gicv3_ich_read_lr(lr);
+
+ lr_reg->pirq = (lrv >> GICH_LR_PHYSICAL_SHIFT) & GICH_LR_PHYSICAL_MASK;
+ lr_reg->virq = (lrv >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
+
+ lr_reg->priority = (lrv >> GICH_LR_PRIORITY_SHIFT) & GICH_LR_PRIORITY_MASK;
+ lr_reg->state = (lrv >> GICH_LR_STATE_SHIFT) & GICH_LR_STATE_MASK;
+ lr_reg->hw_status = (lrv >> GICH_LR_HW_SHIFT) & GICH_LR_HW_MASK;
+ lr_reg->grp = (lrv >> GICH_LR_GRP_SHIFT) & GICH_LR_GRP_MASK;
+}
+
+static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
+{
+ uint64_t lrv = 0;
+
+ lrv = ( ((u64)(lr->pirq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT)|
+ ((u64)(lr->virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT) |
+ ((u64)(lr->priority & GICH_LR_PRIORITY_MASK) << GICH_LR_PRIORITY_SHIFT)|
+ ((u64)(lr->state & GICH_LR_STATE_MASK) << GICH_LR_STATE_SHIFT) |
+ ((u64)(lr->hw_status & GICH_LR_HW_MASK) << GICH_LR_HW_SHIFT) |
+ ((u64)(lr->grp & GICH_LR_GRP_MASK) << GICH_LR_GRP_SHIFT) );
+
+ gicv3_ich_write_lr(lr_reg, lrv);
+}
+
+static int gicv_v3_init(struct domain *d)
+{
+ int i;
+
+ /*
+ * Domain 0 gets the hardware address.
+ * Guests get the virtual platform layout.
+ */
+ if ( is_hardware_domain(d) )
+ {
+ d->arch.vgic.dbase = gicv3.dbase;
+ d->arch.vgic.dbase_size = gicv3.dbase_size;
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ d->arch.vgic.rbase[i] = gicv3.rdist_regions[i].base;
+ d->arch.vgic.rbase_size[i] = gicv3.rdist_regions[i].size;
+ }
+ d->arch.vgic.rdist_stride = gicv3.rdist_stride;
+ d->arch.vgic.rdist_count = gicv3.rdist_count;
+ }
+ else
+ d->arch.vgic.dbase = GUEST_GICD_BASE;
+
+ d->arch.vgic.nr_lines = 0;
+
+ return 0;
+}
+
+static void gicv3_hcr_status(uint32_t flag, bool_t status)
+{
+ uint32_t hcr;
+
+ hcr = READ_SYSREG32(ICH_HCR_EL2);
+ if ( status )
+ WRITE_SYSREG32(hcr | flag, ICH_HCR_EL2);
+ else
+ WRITE_SYSREG32(hcr & (~flag), ICH_HCR_EL2);
+ isb();
+}
+
+static unsigned int gicv3_read_vmcr_priority(void)
+{
+ return ((READ_SYSREG32(ICH_VMCR_EL2) >> GICH_VMCR_PRIORITY_SHIFT) &
+ GICH_VMCR_PRIORITY_MASK);
+}
+
+static void gicv3_irq_enable(struct irq_desc *desc)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&gicv3.lock, flags);
+ desc->status &= ~IRQ_DISABLED;
+ dsb(sy);
+ /* Enable routing */
+ gicv3_unmask_irq(desc);
+ spin_unlock_irqrestore(&gicv3.lock, flags);
+}
+
+static void gicv3_irq_disable(struct irq_desc *desc)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&gicv3.lock, flags);
+ /* Disable routing */
+ gicv3_mask_irq(desc);
+ desc->status |= IRQ_DISABLED;
+ spin_unlock_irqrestore(&gicv3.lock, flags);
+}
+
+static unsigned int gicv3_irq_startup(struct irq_desc *desc)
+{
+ gicv3_irq_enable(desc);
+
+ return 0;
+}
+
+static void gicv3_irq_shutdown(struct irq_desc *desc)
+{
+ gicv3_irq_disable(desc);
+}
+
+static void gicv3_irq_ack(struct irq_desc *desc)
+{
+ /* No ACK -- reading IAR has done this for us */
+}
+
+static void gicv3_host_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority */
+ gicv3_eoi_irq(desc);
+ /* Deactivate */
+ gicv3_dir_irq(desc);
+}
+
+static void gicv3_guest_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority of the IRQ */
+ gicv3_eoi_irq(desc);
+ /* Deactivation happens in maintenance interrupt / via GICV */
+}
+
+static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
+{
+ BUG();
+}
+
+static const hw_irq_controller gicv3_host_irq_type = {
+ .typename = "gic-v3",
+ .startup = gicv3_irq_startup,
+ .shutdown = gicv3_irq_shutdown,
+ .enable = gicv3_irq_enable,
+ .disable = gicv3_irq_disable,
+ .ack = gicv3_irq_ack,
+ .end = gicv3_host_irq_end,
+ .set_affinity = gicv3_irq_set_affinity,
+};
+
+static const hw_irq_controller gicv3_guest_irq_type = {
+ .typename = "gic-v3",
+ .startup = gicv3_irq_startup,
+ .shutdown = gicv3_irq_shutdown,
+ .enable = gicv3_irq_enable,
+ .disable = gicv3_irq_disable,
+ .ack = gicv3_irq_ack,
+ .end = gicv3_guest_irq_end,
+ .set_affinity = gicv3_irq_set_affinity,
+};
+
+static const struct gic_hw_operations gicv3_ops = {
+ .info = &gicv3_info,
+ .save_state = gicv3_save_state,
+ .restore_state = gicv3_restore_state,
+ .dump_state = gicv3_dump_state,
+ .gicv_setup = gicv_v3_init,
+ .gic_host_irq_type = &gicv3_host_irq_type,
+ .gic_guest_irq_type = &gicv3_guest_irq_type,
+ .eoi_irq = gicv3_eoi_irq,
+ .deactivate_irq = gicv3_dir_irq,
+ .read_irq = gicv3_read_irq,
+ .set_irq_properties = gicv3_set_irq_properties,
+ .send_SGI = gicv3_send_sgi,
+ .disable_interface = gicv3_disable_interface,
+ .update_lr = gicv3_update_lr,
+ .update_hcr_status = gicv3_hcr_status,
+ .clear_lr = gicv3_clear_lr,
+ .read_lr = gicv3_read_lr,
+ .write_lr = gicv3_write_lr,
+ .read_vmcr_priority = gicv3_read_vmcr_priority,
+ .secondary_init = gicv3_secondary_cpu_init,
+};
+
+/* Set up the GIC */
+static int __init gicv3_init(struct dt_device_node *node, const void *data)
+{
+ struct rdist_region *rdist_regs;
+ int res, i;
+ uint32_t reg;
+
+ dt_device_set_used_by(node, DOMID_XEN);
+
+ res = dt_device_get_address(node, 0, &gicv3.dbase, &gicv3.dbase_size);
+ if ( res || !gicv3.dbase )
+ panic("GICv3: Cannot find a valid distributor address");
+
+ if ( (gicv3.dbase & ~PAGE_MASK) || (gicv3.dbase_size & ~PAGE_MASK) )
+ panic("GICv3: Found unaligned distributor address %"PRIpaddr"",
+ gicv3.dbase);
+
+ gicv3.map_dbase = ioremap_nocache(gicv3.dbase, gicv3.dbase_size);
+ if ( !gicv3.map_dbase )
+ panic("GICv3: Failed to ioremap for GIC distributor\n");
+
+ reg = readl_relaxed(GICD + GICD_PIDR2) & GICD_PIDR2_ARCH_MASK;
+ if ( reg != (GICV3_GICD_PIDR2 & GICD_PIDR2_ARCH_MASK) )
+ panic("GICv3: no distributor detected\n");
+
+ if ( !dt_property_read_u32(node, "#redistributor-regions",
+ &gicv3.rdist_count) )
+ gicv3.rdist_count = 1;
+
+ if ( gicv3.rdist_count > MAX_RDIST_COUNT )
+ panic("GICv3: Number of redistributor regions is more than"
+ "%d (Increase MAX_RDIST_COUNT!!)\n", MAX_RDIST_COUNT);
+
+ rdist_regs = xzalloc_array(struct rdist_region, gicv3.rdist_count);
+ if ( !rdist_regs )
+ panic("GICv3: Failed to allocate memory for rdist regions\n");
+
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ uint64_t rdist_base, rdist_size;
+
+ res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size);
+ if ( res || !rdist_base )
+ panic("GICv3: No rdist base found for region %d\n", i);
+
+ rdist_regs[i].base = rdist_base;
+ rdist_regs[i].size = rdist_size;
+ }
+
+ /* If stride is not set in dt. Set default to 2 * SZ_64K */
+ if ( !dt_property_read_u32(node, "redistributor-stride", &gicv3.rdist_stride) )
+ gicv3.rdist_stride = 0;
+
+ gicv3.rdist_regions= rdist_regs;
+
+ res = platform_get_irq(node, 0);
+ if ( res < 0 )
+ panic("GICv3: Cannot find the maintenance IRQ");
+ gicv3_info.maintenance_irq = res;
+
+ /* Set the GIC as the primary interrupt controller */
+ dt_interrupt_controller = node;
+
+ for ( i = 0; i < gicv3.rdist_count; i++ )
+ {
+ /* map dbase & rdist regions */
+ gicv3.rdist_regions[i].map_base =
+ ioremap_nocache(gicv3.rdist_regions[i].base,
+ gicv3.rdist_regions[i].size);
+
+ if ( !gicv3.rdist_regions[i].map_base )
+ panic("GICv3: Failed to ioremap rdist region for region %d\n", i);
+ }
+
+ printk("GICv3 initialization:\n"
+ " gic_dist_addr=%"PRIpaddr"\n"
+ " gic_dist_size=%"PRIpaddr"\n"
+ " gic_dist_mapaddr=%p\n"
+ " gic_rdist_regions=%d\n"
+ " gic_rdist_stride=%x\n"
+ " gic_rdist_base=%"PRIpaddr"\n"
+ " gic_rdist_base_size=%"PRIpaddr"\n"
+ " gic_rdist_base_mapaddr=%p\n"
+ " gic_maintenance_irq=%u\n",
+ gicv3.dbase, gicv3.dbase_size, gicv3.map_dbase, gicv3.rdist_count,
+ gicv3.rdist_stride, gicv3.rdist_regions[0].base,
+ gicv3.rdist_regions[0].size, gicv3.rdist_regions[0].map_base,
+ gicv3_info.maintenance_irq);
+
+ spin_lock_init(&gicv3.lock);
+
+ spin_lock(&gicv3.lock);
+
+ gicv3_dist_init();
+ res = gicv3_cpu_init();
+ gicv3_hyp_init();
+
+ gicv3_info.hw_version = GIC_V3;
+ /* Register hw ops*/
+ register_gic_ops(&gicv3_ops);
+
+ spin_unlock(&gicv3.lock);
+
+ return res;
+}
+
+static const char * const gicv3_dt_compat[] __initconst =
+{
+ DT_MATCH_GIC_V3_STRING1,
+ NULL
+};
+
+DT_DEVICE_START(gicv3, "GICv3", DEVICE_GIC)
+ .compatible = gicv3_dt_compat,
+ .init = gicv3_init,
+DT_DEVICE_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index c95ee96..0f0e8af 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -99,6 +99,14 @@ struct arch_domain
/* Base address for guest GIC */
paddr_t dbase; /* Distributor base address */
paddr_t cbase; /* CPU base address */
+#ifdef CONFIG_ARM_64
+ /* GIC V3 addressing */
+ paddr_t dbase_size; /* Distributor base size */
+ paddr_t rbase[MAX_RDIST_COUNT]; /* Re-Distributor base address */
+ paddr_t rbase_size[MAX_RDIST_COUNT]; /* Re-Distributor size */
+ uint32_t rdist_stride; /* Re-Distributor stride */
+ int rdist_count; /* No. of Re-Distributors */
+#endif
} vgic;
struct vuart {
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index d5b9bf9..61a4933 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -18,6 +18,10 @@
#ifndef __ASM_ARM_GIC_H__
#define __ASM_ARM_GIC_H__
+#define NR_GIC_LOCAL_IRQS NR_LOCAL_IRQS
+#define NR_GIC_SGI 16
+#define MAX_RDIST_COUNT 4
+
#define GICD_CTLR (0x000)
#define GICD_TYPER (0x004)
#define GICD_IIDR (0x008)
@@ -154,6 +158,20 @@
#define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_1), \
DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_2)
+#define DT_MATCH_GIC_V3_STRING1 "arm,gic-v3"
+
+#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1);
+
+/*
+ * GICv3 registers that needs to be saved/restored
+ */
+struct gic_v3 {
+ uint32_t hcr, vmcr;
+ uint32_t apr0[4];
+ uint32_t apr1[4];
+ uint64_t lr[16];
+};
+
/*
* GICv2 register that needs to be saved/restored
* on VCPU context switch
@@ -170,6 +188,7 @@ struct gic_v2 {
*/
union gic_state_data {
struct gic_v2 v2;
+ struct gic_v3 v3;
};
/*
@@ -189,6 +208,7 @@ struct gic_lr {
enum gic_version {
GIC_V2,
+ GIC_V3,
};
extern enum gic_version gic_hw_version(void);
diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
new file mode 100644
index 0000000..b8d2e77
--- /dev/null
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -0,0 +1,157 @@
+/*
+ * ARM Generic Interrupt Controller v3 definitions
+ *
+ * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>
+ * Copyright (c) 2014 Cavium Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_GIC_V3_DEFS_H__
+#define __ASM_ARM_GIC_V3_DEFS_H__
+
+/*
+ * Additional registers defined in GIC v3.
+ * Common GICD registers are defined in gic.h
+ */
+
+#define GICD_STATUSR (0x010)
+#define GICD_SETSPI_NSR (0x040)
+#define GICD_CLRSPI_NSR (0x048)
+#define GICD_SETSPI_SR (0x050)
+#define GICD_CLRSPI_SR (0x058)
+#define GICD_IROUTER (0x6000)
+#define GICD_IROUTER31 (0x60F8)
+#define GICD_IROUTER32 (0x6100)
+#define GICD_IROUTERN (0x7FF8)
+#define GICD_PIDR0 (0xFFE0)
+#define GICD_PIDR1 (0xFFE4)
+#define GICD_PIDR2 (0xFFE8)
+#define GICD_PIDR3 (0xFFEC)
+#define GICD_PIDR4 (0xFFD0)
+#define GICD_PIDR5 (0xFFD4)
+#define GICD_PIDR7 (0xFFDC)
+
+#define GICC_SRE_EL2_SRE (1UL << 0)
+#define GICC_SRE_EL2_DFB (1UL << 1)
+#define GICC_SRE_EL2_DIB (1UL << 2)
+#define GICC_SRE_EL2_ENEL1 (1UL << 3)
+
+#define GICD_CTLR_RWP (1UL << 31)
+#define GICD_CTLR_ARE_NS (1U << 4)
+#define GICD_CTLR_ENABLE_G1A (1U << 1)
+#define GICD_CTLR_ENABLE_G1 (1U << 0)
+#define GICD_IROUTER_SPI_MODE_ANY (1UL << 31)
+
+#define GICC_CTLR_EL1_EOImode_drop (1U << 1)
+
+#define GICR_WAKER_ProcessorSleep (1U << 1)
+#define GICR_WAKER_ChildrenAsleep (1U << 2)
+
+#define GICV3_GICD_PIDR0 (0x92)
+#define GICV3_GICD_PIDR1 (0xb4)
+#define GICV3_GICD_PIDR2 (0x3b)
+#define GICV3_GICD_PIDR4 (0x04)
+#define GICD_PIDR2_ARCH_MASK (0xf0)
+
+#define GICV3_GICR_PIDR0 (0x93)
+#define GICV3_GICR_PIDR1 GICV3_GICD_PIDR1
+#define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2
+#define GICV3_GICR_PIDR4 GICV3_GICD_PIDR4
+#define GICR_PIDR2_ARCH_MASK GICD_PIDR2_ARCH_MASK
+#define GICR_SYNCR_NOT_BUSY 1
+/*
+ * Implementation defined value JEP106?
+ * use physical hw value for now
+ */
+#define GICV3_GICD_IIDR_VAL 0x34c
+#define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL
+
+#define GICR_CTLR (0x0000)
+#define GICR_IIDR (0x0004)
+#define GICR_TYPER (0x0008)
+#define GICR_STATUSR (0x0010)
+#define GICR_WAKER (0x0014)
+#define GICR_SETLPIR (0x0040)
+#define GICR_CLRLPIR (0x0048)
+#define GICR_PROPBASER (0x0070)
+#define GICR_PENDBASER (0x0078)
+#define GICR_INVLPIR (0x00A0)
+#define GICR_INVALLR (0x00B0)
+#define GICR_SYNCR (0x00C0)
+#define GICR_MOVLPIR (0x100)
+#define GICR_MOVALLR (0x0110)
+#define GICR_PIDR0 GICD_PIDR0
+#define GICR_PIDR1 GICD_PIDR1
+#define GICR_PIDR2 GICD_PIDR2
+#define GICR_PIDR3 GICD_PIDR3
+#define GICR_PIDR4 GICD_PIDR4
+#define GICR_PIDR5 GICD_PIDR5
+#define GICR_PIDR7 GICD_PIDR7
+
+/* GICR for SGI's & PPI's */
+
+#define GICR_IGROUPR0 (0x0080)
+#define GICR_IGRPMODR0 (0x0F80)
+#define GICR_ISENABLER0 (0x0100)
+#define GICR_ICENABLER0 (0x0180)
+#define GICR_ISPENDR0 (0x0200)
+#define GICR_ICPENDR0 (0x0280)
+#define GICR_ISACTIVER0 (0x0300)
+#define GICR_ICACTIVER0 (0x0380)
+#define GICR_IPRIORITYR0 (0x0400)
+#define GICR_IPRIORITYR7 (0x041C)
+#define GICR_ICFGR0 (0x0C00)
+#define GICR_ICFGR1 (0x0C04)
+#define GICR_NSACR (0x0E00)
+
+#define GICR_TYPER_PLPIS (1U << 0)
+#define GICR_TYPER_VLPIS (1U << 1)
+#define GICR_TYPER_LAST (1U << 4)
+
+#define DEFAULT_PMR_VALUE 0xff
+
+#define GICH_VMCR_EOI (1 << 9)
+#define GICH_VMCR_VENG1 (1 << 1)
+
+#define GICH_LR_VIRTUAL_MASK 0xffff
+#define GICH_LR_VIRTUAL_SHIFT 0
+#define GICH_LR_PHYSICAL_MASK 0x3ff
+#define GICH_LR_PHYSICAL_SHIFT 32
+#define GICH_LR_STATE_MASK 0x3
+#define GICH_LR_STATE_SHIFT 62
+#define GICH_LR_PRIORITY_MASK 0xff
+#define GICH_LR_PRIORITY_SHIFT 48
+#define GICH_LR_HW_MASK 0x1
+#define GICH_LR_HW_SHIFT 61
+#define GICH_LR_GRP_MASK 0x1
+#define GICH_LR_GRP_SHIFT 60
+#define GICH_LR_MAINTENANCE_IRQ (1UL<<41)
+#define GICH_LR_GRP1 (1UL<<60)
+#define GICH_LR_HW (1UL<<61)
+
+#define GICH_VTR_NRLRGS 0x3f
+#define GICH_VTR_PRIBITS_MASK 0x7
+#define GICH_VTR_PRIBITS_SHIFT 29
+
+#define GICH_VMCR_PRIORITY_MASK 0xff
+#define GICH_VMCR_PRIORITY_SHIFT 24
+
+#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 3662749..5978b8a 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -17,6 +17,20 @@
#define MPIDR_HWID_MASK _AC(0xffffff,U)
#define MPIDR_INVALID (~MPIDR_HWID_MASK)
+/*
+ * Macros to extract affinity level. picked from kernel
+ */
+
+#define MPIDR_LEVEL_BITS_SHIFT 3
+#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
+#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
+
+#define MPIDR_LEVEL_SHIFT(level) \
+ (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
+
+#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
+ ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
+
/* TTBCR Translation Table Base Control Register */
#define TTBCR_EAE _AC(0x80000000,U)
#define TTBCR_N_MASK _AC(0x07,U)
diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
index e81b80e..7aef378 100644
--- a/xen/include/xen/lib.h
+++ b/xen/include/xen/lib.h
@@ -67,6 +67,8 @@ do { \
#define reserve_bootmem(_p,_l) ((void)0)
+#define SZ_64K 0x00010000
+
struct domain;
void cmdline_parse(const char *cmdline);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 17/21] xen/arm: Add support for GIC v3
2014-06-12 13:36 ` [PATCH v5 17/21] xen/arm: Add support for GIC v3 vijay.kilari
@ 2014-06-12 17:03 ` Stefano Stabellini
2014-06-12 22:58 ` Julien Grall
2014-06-15 18:10 ` Julien Grall
1 sibling, 1 reply; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 17:03 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Add support for GIC v3 specification System register access(SRE)
> is enabled to access cpu and virtual interface regiseters based
> on kernel GICv3 driver.
>
> This patch adds only basic v3 support.
> Does not support Interrupt Translation support (ITS)
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
I see that a lot of things changed in this version of the patch. It
would be nice if you kept a log of the incremental changes.
In particular in this version of the patch we basically added isb()
everywhere. I would like to see a written comment about it.
When Julien commented "isb?", I think he was just asking whether they
are needed, not requesting you to add them. The only one I was sure
about was the one at the end of gicv3_eoi_irq.
But it is good to see that you addressed all my comments.
> xen/arch/arm/Makefile | 1 +
> xen/arch/arm/gic-v3.c | 1152 +++++++++++++++++++++++++++++++++++++
> xen/include/asm-arm/domain.h | 8 +
> xen/include/asm-arm/gic.h | 20 +
> xen/include/asm-arm/gic_v3_defs.h | 157 +++++
> xen/include/asm-arm/processor.h | 14 +
> xen/include/xen/lib.h | 2 +
> 7 files changed, 1354 insertions(+)
>
> diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
> index 20f59f4..1684c09 100644
> --- a/xen/arch/arm/Makefile
> +++ b/xen/arch/arm/Makefile
> @@ -11,6 +11,7 @@ obj-y += domctl.o
> obj-y += sysctl.o
> obj-y += domain_build.o
> obj-y += gic.o gic-v2.o
> +obj-$(CONFIG_ARM_64) += gic-v3.o
> obj-y += io.o
> obj-y += irq.o
> obj-y += kernel.o
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> new file mode 100644
> index 0000000..29cfd93
> --- /dev/null
> +++ b/xen/arch/arm/gic-v3.c
> @@ -0,0 +1,1152 @@
> +/*
> + * xen/arch/arm/gic-v3.c
> + *
> + * ARM Generic Interrupt Controller support v3 version
> + * based on xen/arch/arm/gic-v2.c and kernel GICv3 driver
> + *
> + * Copyright (C) 2012,2013 - ARM Ltd
> + * Marc Zyngier <marc.zyngier@arm.com>
> + *
> + * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>, Cavium Inc
> + * ported to Xen
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <xen/config.h>
> +#include <xen/lib.h>
> +#include <xen/init.h>
> +#include <xen/cpu.h>
> +#include <xen/mm.h>
> +#include <xen/irq.h>
> +#include <xen/sched.h>
> +#include <xen/errno.h>
> +#include <xen/delay.h>
> +#include <xen/device_tree.h>
> +#include <asm/p2m.h>
> +#include <asm/domain.h>
> +#include <asm/io.h>
> +#include <asm/device.h>
> +#include <asm/gic.h>
> +#include <asm/gic_v3_defs.h>
> +
> +struct rdist_region {
> + paddr_t base;
> + paddr_t size;
> + void __iomem *map_base;
> +};
> +
> +/* Global state */
> +static struct {
> + paddr_t dbase; /* Address of distributor registers */
> + paddr_t dbase_size;
> + void __iomem *map_dbase; /* Mapped address of distributor registers */
> + struct rdist_region *rdist_regions;
> + uint32_t rdist_stride;
> + unsigned int rdist_count; /* Number of rdist regions count */
> + unsigned int nr_priorities;
> + spinlock_t lock;
> +} gicv3;
> +
> +static struct gic_info gicv3_info;
> +
> +/* per-cpu re-distributor base */
> +static DEFINE_PER_CPU(void __iomem*, rbase);
> +
> +#define GICD (gicv3.map_dbase)
> +#define GICD_RDIST_BASE (this_cpu(rbase))
> +#define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K)
> +
> +/*
> + * Saves all 16(Max) LR registers. Though number of LRs implemented
> + * is implementation specific.
> + */
> +static inline void gicv3_save_lrs(int nr_lrs, struct vcpu *v)
> +{
> + /* Fall through for all the cases */
> + switch ( nr_lrs )
> + {
> + case 16:
> + v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2);
> + case 15:
> + v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2);
> + case 14:
> + v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2);
> + case 13:
> + v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2);
> + case 12:
> + v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2);
> + case 11:
> + v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2);
> + case 10:
> + v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2);
> + case 9:
> + v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2);
> + case 8:
> + v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2);
> + case 7:
> + v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2);
> + case 6:
> + v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2);
> + case 5:
> + v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2);
> + case 4:
> + v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2);
> + case 3:
> + v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2);
> + case 2:
> + v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2);
> + case 1:
> + v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2);
> + break;
> + default:
> + BUG();
> + }
> +}
> +
> +/*
> + * Restores all 16(Max) LR registers. Though number of LRs implemented
> + * is implementation specific.
> + */
> +static inline void gicv3_restore_lrs(int nr_lrs, const struct vcpu *v)
> +{
> + /* Fall through for all the cases */
> + switch ( nr_lrs )
> + {
> + case 16:
> + WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2);
> + case 15:
> + WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2);
> + case 14:
> + WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2);
> + case 13:
> + WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2);
> + case 12:
> + WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2);
> + case 11:
> + WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2);
> + case 10:
> + WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2);
> + case 9:
> + WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2);
> + case 8:
> + WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2);
> + case 7:
> + WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2);
> + case 6:
> + WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2);
> + case 5:
> + WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2);
> + case 4:
> + WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2);
> + case 3:
> + WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2);
> + case 2:
> + WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2);
> + case 1:
> + WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2);
> + break;
> + default:
> + BUG();
> + }
> +}
> +
> +static uint64_t gicv3_ich_read_lr(int lr)
> +{
> + switch ( lr )
> + {
> + case 0: return READ_SYSREG(ICH_LR0_EL2);
> + case 1: return READ_SYSREG(ICH_LR1_EL2);
> + case 2: return READ_SYSREG(ICH_LR2_EL2);
> + case 3: return READ_SYSREG(ICH_LR3_EL2);
> + case 4: return READ_SYSREG(ICH_LR4_EL2);
> + case 5: return READ_SYSREG(ICH_LR5_EL2);
> + case 6: return READ_SYSREG(ICH_LR6_EL2);
> + case 7: return READ_SYSREG(ICH_LR7_EL2);
> + case 8: return READ_SYSREG(ICH_LR8_EL2);
> + case 9: return READ_SYSREG(ICH_LR9_EL2);
> + case 10: return READ_SYSREG(ICH_LR10_EL2);
> + case 11: return READ_SYSREG(ICH_LR11_EL2);
> + case 12: return READ_SYSREG(ICH_LR12_EL2);
> + case 13: return READ_SYSREG(ICH_LR13_EL2);
> + case 14: return READ_SYSREG(ICH_LR14_EL2);
> + case 15: return READ_SYSREG(ICH_LR15_EL2);
> + default:
> + BUG();
> + }
> +}
> +
> +static void gicv3_ich_write_lr(int lr, uint64_t val)
> +{
> + switch ( lr )
> + {
> + case 0:
> + WRITE_SYSREG(val, ICH_LR0_EL2);
> + break;
> + case 1:
> + WRITE_SYSREG(val, ICH_LR1_EL2);
> + break;
> + case 2:
> + WRITE_SYSREG(val, ICH_LR2_EL2);
> + break;
> + case 3:
> + WRITE_SYSREG(val, ICH_LR3_EL2);
> + break;
> + case 4:
> + WRITE_SYSREG(val, ICH_LR4_EL2);
> + break;
> + case 5:
> + WRITE_SYSREG(val, ICH_LR5_EL2);
> + break;
> + case 6:
> + WRITE_SYSREG(val, ICH_LR6_EL2);
> + break;
> + case 7:
> + WRITE_SYSREG(val, ICH_LR7_EL2);
> + break;
> + case 8:
> + WRITE_SYSREG(val, ICH_LR8_EL2);
> + break;
> + case 9:
> + WRITE_SYSREG(val, ICH_LR9_EL2);
> + break;
> + case 10:
> + WRITE_SYSREG(val, ICH_LR10_EL2);
> + break;
> + case 11:
> + WRITE_SYSREG(val, ICH_LR11_EL2);
> + break;
> + case 12:
> + WRITE_SYSREG(val, ICH_LR12_EL2);
> + break;
> + case 13:
> + WRITE_SYSREG(val, ICH_LR13_EL2);
> + break;
> + case 14:
> + WRITE_SYSREG(val, ICH_LR14_EL2);
> + break;
> + case 15:
> + WRITE_SYSREG(val, ICH_LR15_EL2);
> + break;
> + default:
> + return;
> + }
> + isb();
> +}
> +
> +/*
> + * System Register Enable (SRE). Enable to access CPU & Virtual
> + * interface registers as system registers in EL2
> + */
> +static void gicv3_enable_sre(void)
> +{
> + uint32_t val;
> +
> + val = READ_SYSREG32(ICC_SRE_EL2);
> + val |= GICC_SRE_EL2_SRE | GICC_SRE_EL2_ENEL1;
> +
> + WRITE_SYSREG32(val, ICC_SRE_EL2);
> + isb();
> +}
> +
> +/* Wait for completion of a distributor change */
> +static void gicv3_do_wait_for_rwp(void __iomem *base)
> +{
> + uint32_t val;
> + bool_t timeout = 0;
> + s_time_t deadline = NOW() + MILLISECS(1000);
> +
> + do {
> + val = readl_relaxed(base + GICD_CTLR);
> + if ( !(val & GICD_CTLR_RWP) )
> + break;
> + if ( NOW() > deadline )
> + {
> + timeout = 1;
> + break;
> + }
> + cpu_relax();
> + udelay(1);
> + } while ( 1 );
> +
> + if ( timeout )
> + dprintk(XENLOG_ERR, "RWP timeout\n");
> +}
> +
> +static void gicv3_dist_wait_for_rwp(void)
> +{
> + gicv3_do_wait_for_rwp(GICD);
> +}
> +
> +static void gicv3_redist_wait_for_rwp(void)
> +{
> + gicv3_do_wait_for_rwp(GICD_RDIST_BASE);
> +}
> +
> +static void gicv3_wait_for_rwp(int irq)
> +{
> + if ( irq < NR_LOCAL_IRQS )
> + gicv3_redist_wait_for_rwp();
> + else
> + gicv3_dist_wait_for_rwp();
> +}
> +
> +static unsigned int gicv3_get_cpu_from_mask(const cpumask_t *cpumask)
> +{
> + unsigned int cpu;
> + cpumask_t possible_mask;
> +
> + cpumask_and(&possible_mask, cpumask, &cpu_possible_map);
> + cpu = cpumask_any(&possible_mask);
> +
> + return cpu;
> +}
> +
> +static void restore_aprn_regs(const union gic_state_data *d)
> +{
> + /* Write APRn register based on number of priorities
> + platform has implemented */
> + switch ( gicv3.nr_priorities )
> + {
> + case 7:
> + WRITE_SYSREG32(d->v3.apr0[2], ICH_AP0R2_EL2);
> + WRITE_SYSREG32(d->v3.apr1[2], ICH_AP1R2_EL2);
> + /* Fall through */
> + case 6:
> + WRITE_SYSREG32(d->v3.apr0[1], ICH_AP0R1_EL2);
> + WRITE_SYSREG32(d->v3.apr1[1], ICH_AP1R1_EL2);
> + /* Fall through */
> + case 5:
> + WRITE_SYSREG32(d->v3.apr0[0], ICH_AP0R0_EL2);
> + WRITE_SYSREG32(d->v3.apr1[0], ICH_AP1R0_EL2);
> + break;
> + default:
> + BUG();
> + }
> +}
> +
> +static void save_aprn_regs(union gic_state_data *d)
> +{
> + /* Read APRn register based on number of priorities
> + platform has implemented */
> + switch ( gicv3.nr_priorities )
> + {
> + case 7:
> + d->v3.apr0[2] = READ_SYSREG32(ICH_AP0R2_EL2);
> + d->v3.apr1[2] = READ_SYSREG32(ICH_AP1R2_EL2);
> + /* Fall through */
> + case 6:
> + d->v3.apr0[1] = READ_SYSREG32(ICH_AP0R1_EL2);
> + d->v3.apr1[1] = READ_SYSREG32(ICH_AP1R1_EL2);
> + /* Fall through */
> + case 5:
> + d->v3.apr0[0] = READ_SYSREG32(ICH_AP0R0_EL2);
> + d->v3.apr1[0] = READ_SYSREG32(ICH_AP1R0_EL2);
> + break;
> + default:
> + BUG();
> + }
> +}
> +
> +static void gicv3_save_state(struct vcpu *v)
> +{
> +
> + /* No need for spinlocks here because interrupts are disabled around
> + * this call and it only accesses struct vcpu fields that cannot be
> + * accessed simultaneously by another pCPU.
> + *
> + * Make sure all stores to the GIC via the memory mapped interface
> + * are now visible to the system register interface
> + */
> + dsb(sy);
> + v->arch.gic.v3.vmcr = READ_SYSREG32(ICH_VMCR_EL2);
> + gicv3_save_lrs(gicv3_info.nr_lrs, v);
> + save_aprn_regs(&v->arch.gic);
> +}
> +
> +static void gicv3_restore_state(const struct vcpu *v)
> +{
> + WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2);
> + restore_aprn_regs(&v->arch.gic);
> + gicv3_restore_lrs(gicv3_info.nr_lrs, v);
> +
> + /*
> + * Make sure all stores are visible the GIC
> + */
> + dsb(sy);
> +}
> +
> +static void gicv3_dump_state(const struct vcpu *v)
> +{
> + int i;
> +
> + if ( v == current )
> + {
> + for ( i = 0; i < gicv3_info.nr_lrs; i++ )
> + printk(" HW_LR[%d]=%lx\n", i, gicv3_ich_read_lr(i));
> + }
> + else
> + {
> + for ( i = 0; i < gicv3_info.nr_lrs; i++ )
> + printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]);
> + }
> +}
> +
> +static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset)
> +{
> + u32 mask = 1 << (irqd->irq % 32);
> + void __iomem *base;
> +
> + if ( irqd->irq < NR_GIC_LOCAL_IRQS )
> + base = GICD_RDIST_SGI_BASE;
> + else
> + base = GICD;
> +
> + writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
> + gicv3_wait_for_rwp(irqd->irq);
> +}
> +
> +static void gicv3_unmask_irq(struct irq_desc *irqd)
> +{
> + gicv3_poke_irq(irqd, GICD_ISENABLER);
> +}
> +
> +static void gicv3_mask_irq(struct irq_desc *irqd)
> +{
> + gicv3_poke_irq(irqd, GICD_ICENABLER);
> +}
> +
> +static void gicv3_eoi_irq(struct irq_desc *irqd)
> +{
> + /* Lower the priority */
> + WRITE_SYSREG32(irqd->irq, ICC_EOIR1_EL1);
> + isb();
> +}
> +
> +static void gicv3_dir_irq(struct irq_desc *irqd)
> +{
> + /* Deactivate */
> + WRITE_SYSREG32(irqd->irq, ICC_DIR_EL1);
> + isb();
> +}
> +
> +static unsigned int gicv3_read_irq(void)
> +{
> + return (READ_SYSREG32(ICC_IAR1_EL1) & GICC_IA_IRQ);
> +}
> +
> +static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
> +{
> + uint64_t mpidr = cpu_logical_map(cpu);
> + return (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
> + MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
> + MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
> + MPIDR_AFFINITY_LEVEL(mpidr, 0));
> +}
> +
> +static void gicv3_set_irq_properties(struct irq_desc *desc,
> + const cpumask_t *cpu_mask,
> + unsigned int priority)
> +{
> + uint32_t cfg, edgebit;
> + uint64_t affinity;
> + void __iomem *base;
> + unsigned int cpu = gicv3_get_cpu_from_mask(cpu_mask);
> + unsigned int irq = desc->irq;
> + unsigned int type = desc->arch.type;
> +
> + /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
> + ASSERT(irq >= NR_GIC_SGI);
> +
> + spin_lock(&gicv3.lock);
> +
> + if ( irq < NR_GIC_LOCAL_IRQS)
> + base = GICD + GICD_ICFGR + (irq / 16) * 4;
> + else
> + base = GICD_RDIST_SGI_BASE + GICR_ICFGR1;
> +
> + cfg = readl_relaxed(base);
> +
> + edgebit = 2u << (2 * (irq % 16));
> + if ( type & DT_IRQ_TYPE_LEVEL_MASK )
> + cfg &= ~edgebit;
> + else if ( type & DT_IRQ_TYPE_EDGE_BOTH )
> + cfg |= edgebit;
> +
> + writel_relaxed(cfg, base);
> +
> + affinity = gicv3_mpidr_to_affinity(cpu);
> + /* Make sure we don't broadcast the interrupt */
> + affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
> +
> + if ( irq >= NR_GIC_LOCAL_IRQS )
> + writeq_relaxed(affinity, (GICD + GICD_IROUTER + irq * 8));
> +
> + /* Set priority */
> + if ( irq < NR_GIC_LOCAL_IRQS )
> + writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq);
> + else
> + writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
> +
> + spin_unlock(&gicv3.lock);
> +}
> +
> +static void __init gicv3_dist_init(void)
> +{
> + uint32_t type;
> + uint32_t priority;
> + uint64_t affinity;
> + int i;
> +
> + /* Disable the distributor */
> + writel_relaxed(0, GICD + GICD_CTLR);
> +
> + type = readl_relaxed(GICD + GICD_TYPER);
> + gicv3_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1);
> +
> + printk("GICv3: %d lines, (IID %8.8x).\n",
> + gicv3_info.nr_lines, readl_relaxed(GICD + GICD_IIDR));
> +
> + /* Default all global IRQs to level, active low */
> + for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 16 )
> + writel_relaxed(0, GICD + GICD_ICFGR + (i / 16) * 4);
> +
> + /* Default priority for global interrupts */
> + for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 4 )
> + {
> + priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 |
> + GIC_PRI_IRQ << 8 | GIC_PRI_IRQ);
> + writel_relaxed(priority, GICD + GICD_IPRIORITYR + (i / 4) * 4);
> + }
> +
> + /* Disable all global interrupts */
> + for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 32 )
> + writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4);
> +
> + gicv3_dist_wait_for_rwp();
> +
> + /* Turn on the distributor */
> + writel_relaxed(GICD_CTL_ENABLE | GICD_CTLR_ARE_NS |
> + GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, GICD + GICD_CTLR);
> +
> + /* Route all global IRQs to this CPU */
> + affinity = gicv3_mpidr_to_affinity(smp_processor_id());
> + /* Make sure we don't broadcast the interrupt */
> + affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
> +
> + for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i++ )
> + writeq_relaxed(affinity, GICD + GICD_IROUTER + i * 8);
> +}
> +
> +static int gicv3_enable_redist(void)
> +{
> + uint32_t val;
> + bool_t timeout = 0;
> + s_time_t deadline = NOW() + MILLISECS(1000);
> +
> + /* Wake up this CPU redistributor */
> + val = readl_relaxed(GICD_RDIST_BASE + GICR_WAKER);
> + val &= ~GICR_WAKER_ProcessorSleep;
> + writel_relaxed(val, GICD_RDIST_BASE + GICR_WAKER);
> +
> + do {
> + val = readl_relaxed(GICD_RDIST_BASE + GICR_WAKER);
> + if ( !(val & GICR_WAKER_ChildrenAsleep) )
> + break;
> + if ( NOW() > deadline )
> + {
> + timeout = 1;
> + break;
> + }
> + cpu_relax();
> + udelay(1);
> + } while ( timeout );
> +
> + if ( timeout )
> + {
> + dprintk(XENLOG_ERR, "GICv3: Redist enable RWP timeout\n");
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> +static int __init gicv3_populate_rdist(void)
> +{
> + int i;
> + uint32_t aff;
> + uint32_t reg;
> + uint64_t typer;
> + uint64_t mpidr = cpu_logical_map(smp_processor_id());
> +
> + /*
> + * Convert affinity to a 32bit value that can be matched to GICR_TYPER
> + * bits [63:32]
> + */
> + aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
> + MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
> + MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
> + MPIDR_AFFINITY_LEVEL(mpidr, 0));
> +
> + for ( i = 0; i < gicv3.rdist_count; i++ )
> + {
> + void __iomem *ptr = gicv3.rdist_regions[i].map_base;
> +
> + reg = readl_relaxed(ptr + GICR_PIDR2) & GICR_PIDR2_ARCH_MASK;
> + if ( reg != (GICV3_GICR_PIDR2 & GICR_PIDR2_ARCH_MASK) )
> + {
> + dprintk(XENLOG_ERR,
> + "GICv3: No redistributor present @%"PRIpaddr"\n",
> + gicv3.rdist_regions[i].base);
> + break;
> + }
> +
> + do {
> + typer = readq_relaxed(ptr + GICR_TYPER);
> +
> + if ( (typer >> 32) == aff )
> + {
> + this_cpu(rbase) = ptr;
> + printk("GICv3: CPU%d: Found redistributor in region %d @%p\n",
> + smp_processor_id(), i, ptr);
> + return 0;
> + }
> + if ( gicv3.rdist_stride )
> + ptr += gicv3.rdist_stride;
> + else
> + {
> + ptr += SZ_64K * 2;
> + if ( typer & GICR_TYPER_VLPIS )
> + ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
> + }
> +
> + } while ( !(typer & GICR_TYPER_LAST) );
> + }
> +
> + dprintk(XENLOG_ERR, "GICv3: CPU%d: mpidr 0x%x has no re-distributor!\n",
> + smp_processor_id(), cpu_logical_map(smp_processor_id()));
> + return -ENODEV;
> +}
> +
> +static int __cpuinit gicv3_cpu_init(void)
> +{
> + int i;
> + uint32_t priority;
> +
> + /* Register ourselves with the rest of the world */
> + if ( gicv3_populate_rdist() )
> + return -ENODEV;
> +
> + if ( gicv3_enable_redist() )
> + return -ENODEV;
> +
> + /* Set priority on PPI and SGI interrupts */
> + priority = (GIC_PRI_IPI << 24 | GIC_PRI_IPI << 16 | GIC_PRI_IPI << 8 |
> + GIC_PRI_IPI);
> + for (i = 0; i < NR_GIC_SGI; i += 4)
> + writel_relaxed(priority,
> + GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + (i / 4) * 4);
> +
> + priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | GIC_PRI_IRQ << 8 |
> + GIC_PRI_IRQ);
> + for (i = NR_GIC_SGI; i < NR_GIC_LOCAL_IRQS; i += 4)
> + writel_relaxed(priority,
> + GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + (i / 4) * 4);
> +
> + /*
> + * Disable all PPI interrupts, ensure all SGI interrupts are
> + * enabled.
> + */
> + writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
> + writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
> +
> + gicv3_redist_wait_for_rwp();
> +
> + /* Enable system registers */
> + gicv3_enable_sre();
> +
> + /* No priority grouping */
> + WRITE_SYSREG32(0, ICC_BPR1_EL1);
> +
> + /* Set priority mask register */
> + WRITE_SYSREG32(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
> +
> + /* EOI drops priority too (mode 0) */
> + WRITE_SYSREG32(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1);
> + isb();
> +
> + /* Enable Group1 interrupts */
> + WRITE_SYSREG32(1, ICC_IGRPEN1_EL1);
> + isb();
> +
> + return 0;
> +}
> +
> +static void gicv3_cpu_disable(void)
> +{
> + WRITE_SYSREG32(0, ICC_CTLR_EL1);
> + isb();
> +}
> +
> +static void __cpuinit gicv3_hyp_init(void)
> +{
> + uint32_t vtr;
> +
> + vtr = READ_SYSREG32(ICH_VTR_EL2);
> + gicv3_info.nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
> + gicv3.nr_priorities = ((vtr >> GICH_VTR_PRIBITS_SHIFT) &
> + GICH_VTR_PRIBITS_MASK) + 1;
> +
> + ASSERT((gicv3.nr_priorities > 4 && gicv3.nr_priorities < 8));
> +
> + WRITE_SYSREG32(GICH_VMCR_EOI | GICH_VMCR_VENG1, ICH_VMCR_EL2);
> + WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2);
> +
> + update_cpu_lr_mask();
> +}
> +
> +/* Set up the per-CPU parts of the GIC for a secondary CPU */
> +static int gicv3_secondary_cpu_init(void)
> +{
> + int res;
> +
> + spin_lock(&gicv3.lock);
> +
> + res = gicv3_cpu_init();
> + gicv3_hyp_init();
> +
> + spin_unlock(&gicv3.lock);
> +
> + return res;
> +}
> +
> +static void __cpuinit gicv3_hyp_disable(void)
> +{
> + uint32_t vtr;
> +
> + vtr = READ_SYSREG32(ICH_HCR_EL2);
> + vtr &= ~0x1;
> + WRITE_SYSREG32(vtr, ICH_HCR_EL2);
> + isb();
> +}
> +
> +static u16 gicv3_compute_target_list(int *base_cpu, const struct cpumask *mask,
> + uint64_t cluster_id)
> +{
> + int cpu = *base_cpu;
> + uint64_t mpidr = cpu_logical_map(cpu);
> + u16 tlist = 0;
> +
> + while ( cpu < nr_cpu_ids )
> + {
> + /*
> + * If we ever get a cluster of more than 16 CPUs, just
> + * scream and skip that CPU.
> + */
> + if ( (mpidr & 0xff) >= 16 )
> + {
> + dprintk(XENLOG_WARNING, "GICv3:Cluster with more than 16's cpus\n");
> + goto out;
> + }
> + tlist |= 1 << (mpidr & 0xf);
> +
> + cpu = cpumask_next(cpu, mask);
> + if ( cpu == nr_cpu_ids )
> + {
> + cpu--;
> + goto out;
> + }
> +
> + mpidr = cpu_logical_map(cpu);
> + if ( cluster_id != (mpidr & ~0xffUL) ) {
> + cpu--;
> + goto out;
> + }
> + }
> +out:
> + *base_cpu = cpu;
> +
> + return tlist;
> +}
> +
> +static void gicv3_send_sgi(const cpumask_t *cpumask, enum gic_sgi sgi,
> + enum gic_sgi_mode mode)
> +{
> + int cpu = 0;
> + uint64_t val;
> +
> + dsb(sy);
> +
> + for_each_cpu(cpu, cpumask)
> + {
> + uint64_t cluster_id = cpu_logical_map(cpu) & ~0xffUL;
> + u16 tlist;
> +
> + /* Get targetlist for the cluster to send SGI */
> + tlist = gicv3_compute_target_list(&cpu, cpumask, cluster_id);
> +
> + /*
> + * Prepare affinity path of the cluster for which SGI is generated
> + * along with SGI number
> + */
> + val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 |
> + MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 |
> + sgi << 24 |
> + MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 |
> + tlist);
> +
> + WRITE_SYSREG(val, ICC_SGI1R_EL1);
> + }
> + /* Force above writes to ICC_SGI1R_EL1 */
> + isb();
> +}
> +
> +/* Shut down the per-CPU GIC interface */
> +static void gicv3_disable_interface(void)
> +{
> + spin_lock(&gicv3.lock);
> +
> + gicv3_cpu_disable();
> + gicv3_hyp_disable();
> +
> + spin_unlock(&gicv3.lock);
> +}
> +
> +static void gicv3_update_lr(int lr, const struct pending_irq *p,
> + unsigned int state)
> +{
> + uint64_t grp = GICH_LR_GRP1;
> + uint64_t val = 0;
> +
> + BUG_ON(lr >= gicv3_info.nr_lrs);
> + BUG_ON(lr < 0);
> +
> + val = (((uint64_t)state & 0x3) << GICH_LR_STATE_SHIFT) | grp;
> + val |= ((uint64_t)p->priority & 0xff) << GICH_LR_PRIORITY_SHIFT;
> + val |= ((uint64_t)p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT;
> +
> + if ( p->desc != NULL )
> + val |= GICH_LR_HW | (((uint64_t)p->desc->irq & GICH_LR_PHYSICAL_MASK)
> + << GICH_LR_PHYSICAL_SHIFT);
> +
> + gicv3_ich_write_lr(lr, val);
> +}
> +
> +static void gicv3_clear_lr(int lr)
> +{
> + gicv3_ich_write_lr(lr, 0);
> +}
> +
> +static void gicv3_read_lr(int lr, struct gic_lr *lr_reg)
> +{
> + uint64_t lrv;
> +
> + lrv = gicv3_ich_read_lr(lr);
> +
> + lr_reg->pirq = (lrv >> GICH_LR_PHYSICAL_SHIFT) & GICH_LR_PHYSICAL_MASK;
> + lr_reg->virq = (lrv >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK;
> +
> + lr_reg->priority = (lrv >> GICH_LR_PRIORITY_SHIFT) & GICH_LR_PRIORITY_MASK;
> + lr_reg->state = (lrv >> GICH_LR_STATE_SHIFT) & GICH_LR_STATE_MASK;
> + lr_reg->hw_status = (lrv >> GICH_LR_HW_SHIFT) & GICH_LR_HW_MASK;
> + lr_reg->grp = (lrv >> GICH_LR_GRP_SHIFT) & GICH_LR_GRP_MASK;
> +}
> +
> +static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr)
> +{
> + uint64_t lrv = 0;
> +
> + lrv = ( ((u64)(lr->pirq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT)|
> + ((u64)(lr->virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT) |
> + ((u64)(lr->priority & GICH_LR_PRIORITY_MASK) << GICH_LR_PRIORITY_SHIFT)|
> + ((u64)(lr->state & GICH_LR_STATE_MASK) << GICH_LR_STATE_SHIFT) |
> + ((u64)(lr->hw_status & GICH_LR_HW_MASK) << GICH_LR_HW_SHIFT) |
> + ((u64)(lr->grp & GICH_LR_GRP_MASK) << GICH_LR_GRP_SHIFT) );
> +
> + gicv3_ich_write_lr(lr_reg, lrv);
> +}
> +
> +static int gicv_v3_init(struct domain *d)
> +{
> + int i;
> +
> + /*
> + * Domain 0 gets the hardware address.
> + * Guests get the virtual platform layout.
> + */
> + if ( is_hardware_domain(d) )
> + {
> + d->arch.vgic.dbase = gicv3.dbase;
> + d->arch.vgic.dbase_size = gicv3.dbase_size;
> + for ( i = 0; i < gicv3.rdist_count; i++ )
> + {
> + d->arch.vgic.rbase[i] = gicv3.rdist_regions[i].base;
> + d->arch.vgic.rbase_size[i] = gicv3.rdist_regions[i].size;
> + }
> + d->arch.vgic.rdist_stride = gicv3.rdist_stride;
> + d->arch.vgic.rdist_count = gicv3.rdist_count;
> + }
> + else
> + d->arch.vgic.dbase = GUEST_GICD_BASE;
> +
> + d->arch.vgic.nr_lines = 0;
> +
> + return 0;
> +}
> +
> +static void gicv3_hcr_status(uint32_t flag, bool_t status)
> +{
> + uint32_t hcr;
> +
> + hcr = READ_SYSREG32(ICH_HCR_EL2);
> + if ( status )
> + WRITE_SYSREG32(hcr | flag, ICH_HCR_EL2);
> + else
> + WRITE_SYSREG32(hcr & (~flag), ICH_HCR_EL2);
> + isb();
> +}
> +
> +static unsigned int gicv3_read_vmcr_priority(void)
> +{
> + return ((READ_SYSREG32(ICH_VMCR_EL2) >> GICH_VMCR_PRIORITY_SHIFT) &
> + GICH_VMCR_PRIORITY_MASK);
> +}
> +
> +static void gicv3_irq_enable(struct irq_desc *desc)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&gicv3.lock, flags);
> + desc->status &= ~IRQ_DISABLED;
> + dsb(sy);
> + /* Enable routing */
> + gicv3_unmask_irq(desc);
> + spin_unlock_irqrestore(&gicv3.lock, flags);
> +}
> +
> +static void gicv3_irq_disable(struct irq_desc *desc)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&gicv3.lock, flags);
> + /* Disable routing */
> + gicv3_mask_irq(desc);
> + desc->status |= IRQ_DISABLED;
> + spin_unlock_irqrestore(&gicv3.lock, flags);
> +}
> +
> +static unsigned int gicv3_irq_startup(struct irq_desc *desc)
> +{
> + gicv3_irq_enable(desc);
> +
> + return 0;
> +}
> +
> +static void gicv3_irq_shutdown(struct irq_desc *desc)
> +{
> + gicv3_irq_disable(desc);
> +}
> +
> +static void gicv3_irq_ack(struct irq_desc *desc)
> +{
> + /* No ACK -- reading IAR has done this for us */
> +}
> +
> +static void gicv3_host_irq_end(struct irq_desc *desc)
> +{
> + /* Lower the priority */
> + gicv3_eoi_irq(desc);
> + /* Deactivate */
> + gicv3_dir_irq(desc);
> +}
> +
> +static void gicv3_guest_irq_end(struct irq_desc *desc)
> +{
> + /* Lower the priority of the IRQ */
> + gicv3_eoi_irq(desc);
> + /* Deactivation happens in maintenance interrupt / via GICV */
> +}
> +
> +static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
> +{
> + BUG();
> +}
> +
> +static const hw_irq_controller gicv3_host_irq_type = {
> + .typename = "gic-v3",
> + .startup = gicv3_irq_startup,
> + .shutdown = gicv3_irq_shutdown,
> + .enable = gicv3_irq_enable,
> + .disable = gicv3_irq_disable,
> + .ack = gicv3_irq_ack,
> + .end = gicv3_host_irq_end,
> + .set_affinity = gicv3_irq_set_affinity,
> +};
> +
> +static const hw_irq_controller gicv3_guest_irq_type = {
> + .typename = "gic-v3",
> + .startup = gicv3_irq_startup,
> + .shutdown = gicv3_irq_shutdown,
> + .enable = gicv3_irq_enable,
> + .disable = gicv3_irq_disable,
> + .ack = gicv3_irq_ack,
> + .end = gicv3_guest_irq_end,
> + .set_affinity = gicv3_irq_set_affinity,
> +};
> +
> +static const struct gic_hw_operations gicv3_ops = {
> + .info = &gicv3_info,
> + .save_state = gicv3_save_state,
> + .restore_state = gicv3_restore_state,
> + .dump_state = gicv3_dump_state,
> + .gicv_setup = gicv_v3_init,
> + .gic_host_irq_type = &gicv3_host_irq_type,
> + .gic_guest_irq_type = &gicv3_guest_irq_type,
> + .eoi_irq = gicv3_eoi_irq,
> + .deactivate_irq = gicv3_dir_irq,
> + .read_irq = gicv3_read_irq,
> + .set_irq_properties = gicv3_set_irq_properties,
> + .send_SGI = gicv3_send_sgi,
> + .disable_interface = gicv3_disable_interface,
> + .update_lr = gicv3_update_lr,
> + .update_hcr_status = gicv3_hcr_status,
> + .clear_lr = gicv3_clear_lr,
> + .read_lr = gicv3_read_lr,
> + .write_lr = gicv3_write_lr,
> + .read_vmcr_priority = gicv3_read_vmcr_priority,
> + .secondary_init = gicv3_secondary_cpu_init,
> +};
> +
> +/* Set up the GIC */
> +static int __init gicv3_init(struct dt_device_node *node, const void *data)
> +{
> + struct rdist_region *rdist_regs;
> + int res, i;
> + uint32_t reg;
> +
> + dt_device_set_used_by(node, DOMID_XEN);
> +
> + res = dt_device_get_address(node, 0, &gicv3.dbase, &gicv3.dbase_size);
> + if ( res || !gicv3.dbase )
> + panic("GICv3: Cannot find a valid distributor address");
> +
> + if ( (gicv3.dbase & ~PAGE_MASK) || (gicv3.dbase_size & ~PAGE_MASK) )
> + panic("GICv3: Found unaligned distributor address %"PRIpaddr"",
> + gicv3.dbase);
> +
> + gicv3.map_dbase = ioremap_nocache(gicv3.dbase, gicv3.dbase_size);
> + if ( !gicv3.map_dbase )
> + panic("GICv3: Failed to ioremap for GIC distributor\n");
> +
> + reg = readl_relaxed(GICD + GICD_PIDR2) & GICD_PIDR2_ARCH_MASK;
> + if ( reg != (GICV3_GICD_PIDR2 & GICD_PIDR2_ARCH_MASK) )
> + panic("GICv3: no distributor detected\n");
> +
> + if ( !dt_property_read_u32(node, "#redistributor-regions",
> + &gicv3.rdist_count) )
> + gicv3.rdist_count = 1;
> +
> + if ( gicv3.rdist_count > MAX_RDIST_COUNT )
> + panic("GICv3: Number of redistributor regions is more than"
> + "%d (Increase MAX_RDIST_COUNT!!)\n", MAX_RDIST_COUNT);
> +
> + rdist_regs = xzalloc_array(struct rdist_region, gicv3.rdist_count);
> + if ( !rdist_regs )
> + panic("GICv3: Failed to allocate memory for rdist regions\n");
> +
> + for ( i = 0; i < gicv3.rdist_count; i++ )
> + {
> + uint64_t rdist_base, rdist_size;
> +
> + res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size);
> + if ( res || !rdist_base )
> + panic("GICv3: No rdist base found for region %d\n", i);
> +
> + rdist_regs[i].base = rdist_base;
> + rdist_regs[i].size = rdist_size;
> + }
> +
> + /* If stride is not set in dt. Set default to 2 * SZ_64K */
> + if ( !dt_property_read_u32(node, "redistributor-stride", &gicv3.rdist_stride) )
> + gicv3.rdist_stride = 0;
> +
> + gicv3.rdist_regions= rdist_regs;
> +
> + res = platform_get_irq(node, 0);
> + if ( res < 0 )
> + panic("GICv3: Cannot find the maintenance IRQ");
> + gicv3_info.maintenance_irq = res;
> +
> + /* Set the GIC as the primary interrupt controller */
> + dt_interrupt_controller = node;
> +
> + for ( i = 0; i < gicv3.rdist_count; i++ )
> + {
> + /* map dbase & rdist regions */
> + gicv3.rdist_regions[i].map_base =
> + ioremap_nocache(gicv3.rdist_regions[i].base,
> + gicv3.rdist_regions[i].size);
> +
> + if ( !gicv3.rdist_regions[i].map_base )
> + panic("GICv3: Failed to ioremap rdist region for region %d\n", i);
> + }
> +
> + printk("GICv3 initialization:\n"
> + " gic_dist_addr=%"PRIpaddr"\n"
> + " gic_dist_size=%"PRIpaddr"\n"
> + " gic_dist_mapaddr=%p\n"
> + " gic_rdist_regions=%d\n"
> + " gic_rdist_stride=%x\n"
> + " gic_rdist_base=%"PRIpaddr"\n"
> + " gic_rdist_base_size=%"PRIpaddr"\n"
> + " gic_rdist_base_mapaddr=%p\n"
> + " gic_maintenance_irq=%u\n",
> + gicv3.dbase, gicv3.dbase_size, gicv3.map_dbase, gicv3.rdist_count,
> + gicv3.rdist_stride, gicv3.rdist_regions[0].base,
> + gicv3.rdist_regions[0].size, gicv3.rdist_regions[0].map_base,
> + gicv3_info.maintenance_irq);
> +
> + spin_lock_init(&gicv3.lock);
> +
> + spin_lock(&gicv3.lock);
> +
> + gicv3_dist_init();
> + res = gicv3_cpu_init();
> + gicv3_hyp_init();
> +
> + gicv3_info.hw_version = GIC_V3;
> + /* Register hw ops*/
> + register_gic_ops(&gicv3_ops);
> +
> + spin_unlock(&gicv3.lock);
> +
> + return res;
> +}
> +
> +static const char * const gicv3_dt_compat[] __initconst =
> +{
> + DT_MATCH_GIC_V3_STRING1,
> + NULL
> +};
> +
> +DT_DEVICE_START(gicv3, "GICv3", DEVICE_GIC)
> + .compatible = gicv3_dt_compat,
> + .init = gicv3_init,
> +DT_DEVICE_END
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
> index c95ee96..0f0e8af 100644
> --- a/xen/include/asm-arm/domain.h
> +++ b/xen/include/asm-arm/domain.h
> @@ -99,6 +99,14 @@ struct arch_domain
> /* Base address for guest GIC */
> paddr_t dbase; /* Distributor base address */
> paddr_t cbase; /* CPU base address */
> +#ifdef CONFIG_ARM_64
> + /* GIC V3 addressing */
> + paddr_t dbase_size; /* Distributor base size */
> + paddr_t rbase[MAX_RDIST_COUNT]; /* Re-Distributor base address */
> + paddr_t rbase_size[MAX_RDIST_COUNT]; /* Re-Distributor size */
> + uint32_t rdist_stride; /* Re-Distributor stride */
> + int rdist_count; /* No. of Re-Distributors */
> +#endif
> } vgic;
>
> struct vuart {
> diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
> index d5b9bf9..61a4933 100644
> --- a/xen/include/asm-arm/gic.h
> +++ b/xen/include/asm-arm/gic.h
> @@ -18,6 +18,10 @@
> #ifndef __ASM_ARM_GIC_H__
> #define __ASM_ARM_GIC_H__
>
> +#define NR_GIC_LOCAL_IRQS NR_LOCAL_IRQS
> +#define NR_GIC_SGI 16
> +#define MAX_RDIST_COUNT 4
> +
> #define GICD_CTLR (0x000)
> #define GICD_TYPER (0x004)
> #define GICD_IIDR (0x008)
> @@ -154,6 +158,20 @@
> #define DT_MATCH_GIC_V2 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_1), \
> DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V2_STRING_2)
>
> +#define DT_MATCH_GIC_V3_STRING1 "arm,gic-v3"
> +
> +#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1);
> +
> +/*
> + * GICv3 registers that needs to be saved/restored
> + */
> +struct gic_v3 {
> + uint32_t hcr, vmcr;
> + uint32_t apr0[4];
> + uint32_t apr1[4];
> + uint64_t lr[16];
> +};
> +
> /*
> * GICv2 register that needs to be saved/restored
> * on VCPU context switch
> @@ -170,6 +188,7 @@ struct gic_v2 {
> */
> union gic_state_data {
> struct gic_v2 v2;
> + struct gic_v3 v3;
> };
>
> /*
> @@ -189,6 +208,7 @@ struct gic_lr {
>
> enum gic_version {
> GIC_V2,
> + GIC_V3,
> };
>
> extern enum gic_version gic_hw_version(void);
> diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
> new file mode 100644
> index 0000000..b8d2e77
> --- /dev/null
> +++ b/xen/include/asm-arm/gic_v3_defs.h
> @@ -0,0 +1,157 @@
> +/*
> + * ARM Generic Interrupt Controller v3 definitions
> + *
> + * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>
> + * Copyright (c) 2014 Cavium Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef __ASM_ARM_GIC_V3_DEFS_H__
> +#define __ASM_ARM_GIC_V3_DEFS_H__
> +
> +/*
> + * Additional registers defined in GIC v3.
> + * Common GICD registers are defined in gic.h
> + */
> +
> +#define GICD_STATUSR (0x010)
> +#define GICD_SETSPI_NSR (0x040)
> +#define GICD_CLRSPI_NSR (0x048)
> +#define GICD_SETSPI_SR (0x050)
> +#define GICD_CLRSPI_SR (0x058)
> +#define GICD_IROUTER (0x6000)
> +#define GICD_IROUTER31 (0x60F8)
> +#define GICD_IROUTER32 (0x6100)
> +#define GICD_IROUTERN (0x7FF8)
> +#define GICD_PIDR0 (0xFFE0)
> +#define GICD_PIDR1 (0xFFE4)
> +#define GICD_PIDR2 (0xFFE8)
> +#define GICD_PIDR3 (0xFFEC)
> +#define GICD_PIDR4 (0xFFD0)
> +#define GICD_PIDR5 (0xFFD4)
> +#define GICD_PIDR7 (0xFFDC)
> +
> +#define GICC_SRE_EL2_SRE (1UL << 0)
> +#define GICC_SRE_EL2_DFB (1UL << 1)
> +#define GICC_SRE_EL2_DIB (1UL << 2)
> +#define GICC_SRE_EL2_ENEL1 (1UL << 3)
> +
> +#define GICD_CTLR_RWP (1UL << 31)
> +#define GICD_CTLR_ARE_NS (1U << 4)
> +#define GICD_CTLR_ENABLE_G1A (1U << 1)
> +#define GICD_CTLR_ENABLE_G1 (1U << 0)
> +#define GICD_IROUTER_SPI_MODE_ANY (1UL << 31)
> +
> +#define GICC_CTLR_EL1_EOImode_drop (1U << 1)
> +
> +#define GICR_WAKER_ProcessorSleep (1U << 1)
> +#define GICR_WAKER_ChildrenAsleep (1U << 2)
> +
> +#define GICV3_GICD_PIDR0 (0x92)
> +#define GICV3_GICD_PIDR1 (0xb4)
> +#define GICV3_GICD_PIDR2 (0x3b)
> +#define GICV3_GICD_PIDR4 (0x04)
> +#define GICD_PIDR2_ARCH_MASK (0xf0)
> +
> +#define GICV3_GICR_PIDR0 (0x93)
> +#define GICV3_GICR_PIDR1 GICV3_GICD_PIDR1
> +#define GICV3_GICR_PIDR2 GICV3_GICD_PIDR2
> +#define GICV3_GICR_PIDR4 GICV3_GICD_PIDR4
> +#define GICR_PIDR2_ARCH_MASK GICD_PIDR2_ARCH_MASK
> +#define GICR_SYNCR_NOT_BUSY 1
> +/*
> + * Implementation defined value JEP106?
> + * use physical hw value for now
> + */
> +#define GICV3_GICD_IIDR_VAL 0x34c
> +#define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL
> +
> +#define GICR_CTLR (0x0000)
> +#define GICR_IIDR (0x0004)
> +#define GICR_TYPER (0x0008)
> +#define GICR_STATUSR (0x0010)
> +#define GICR_WAKER (0x0014)
> +#define GICR_SETLPIR (0x0040)
> +#define GICR_CLRLPIR (0x0048)
> +#define GICR_PROPBASER (0x0070)
> +#define GICR_PENDBASER (0x0078)
> +#define GICR_INVLPIR (0x00A0)
> +#define GICR_INVALLR (0x00B0)
> +#define GICR_SYNCR (0x00C0)
> +#define GICR_MOVLPIR (0x100)
> +#define GICR_MOVALLR (0x0110)
> +#define GICR_PIDR0 GICD_PIDR0
> +#define GICR_PIDR1 GICD_PIDR1
> +#define GICR_PIDR2 GICD_PIDR2
> +#define GICR_PIDR3 GICD_PIDR3
> +#define GICR_PIDR4 GICD_PIDR4
> +#define GICR_PIDR5 GICD_PIDR5
> +#define GICR_PIDR7 GICD_PIDR7
> +
> +/* GICR for SGI's & PPI's */
> +
> +#define GICR_IGROUPR0 (0x0080)
> +#define GICR_IGRPMODR0 (0x0F80)
> +#define GICR_ISENABLER0 (0x0100)
> +#define GICR_ICENABLER0 (0x0180)
> +#define GICR_ISPENDR0 (0x0200)
> +#define GICR_ICPENDR0 (0x0280)
> +#define GICR_ISACTIVER0 (0x0300)
> +#define GICR_ICACTIVER0 (0x0380)
> +#define GICR_IPRIORITYR0 (0x0400)
> +#define GICR_IPRIORITYR7 (0x041C)
> +#define GICR_ICFGR0 (0x0C00)
> +#define GICR_ICFGR1 (0x0C04)
> +#define GICR_NSACR (0x0E00)
> +
> +#define GICR_TYPER_PLPIS (1U << 0)
> +#define GICR_TYPER_VLPIS (1U << 1)
> +#define GICR_TYPER_LAST (1U << 4)
> +
> +#define DEFAULT_PMR_VALUE 0xff
> +
> +#define GICH_VMCR_EOI (1 << 9)
> +#define GICH_VMCR_VENG1 (1 << 1)
> +
> +#define GICH_LR_VIRTUAL_MASK 0xffff
> +#define GICH_LR_VIRTUAL_SHIFT 0
> +#define GICH_LR_PHYSICAL_MASK 0x3ff
> +#define GICH_LR_PHYSICAL_SHIFT 32
> +#define GICH_LR_STATE_MASK 0x3
> +#define GICH_LR_STATE_SHIFT 62
> +#define GICH_LR_PRIORITY_MASK 0xff
> +#define GICH_LR_PRIORITY_SHIFT 48
> +#define GICH_LR_HW_MASK 0x1
> +#define GICH_LR_HW_SHIFT 61
> +#define GICH_LR_GRP_MASK 0x1
> +#define GICH_LR_GRP_SHIFT 60
> +#define GICH_LR_MAINTENANCE_IRQ (1UL<<41)
> +#define GICH_LR_GRP1 (1UL<<60)
> +#define GICH_LR_HW (1UL<<61)
> +
> +#define GICH_VTR_NRLRGS 0x3f
> +#define GICH_VTR_PRIBITS_MASK 0x7
> +#define GICH_VTR_PRIBITS_SHIFT 29
> +
> +#define GICH_VMCR_PRIORITY_MASK 0xff
> +#define GICH_VMCR_PRIORITY_SHIFT 24
> +
> +#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 3662749..5978b8a 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -17,6 +17,20 @@
> #define MPIDR_HWID_MASK _AC(0xffffff,U)
> #define MPIDR_INVALID (~MPIDR_HWID_MASK)
>
> +/*
> + * Macros to extract affinity level. picked from kernel
> + */
> +
> +#define MPIDR_LEVEL_BITS_SHIFT 3
> +#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
> +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
> +
> +#define MPIDR_LEVEL_SHIFT(level) \
> + (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
> +
> +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
> + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
> +
> /* TTBCR Translation Table Base Control Register */
> #define TTBCR_EAE _AC(0x80000000,U)
> #define TTBCR_N_MASK _AC(0x07,U)
> diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
> index e81b80e..7aef378 100644
> --- a/xen/include/xen/lib.h
> +++ b/xen/include/xen/lib.h
> @@ -67,6 +67,8 @@ do { \
>
> #define reserve_bootmem(_p,_l) ((void)0)
>
> +#define SZ_64K 0x00010000
> +
> struct domain;
>
> void cmdline_parse(const char *cmdline);
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 17/21] xen/arm: Add support for GIC v3
2014-06-12 17:03 ` Stefano Stabellini
@ 2014-06-12 22:58 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-12 22:58 UTC (permalink / raw)
To: Stefano Stabellini, vijay.kilari
Cc: Ian.Campbell, Prasun.Kapoor, Vijaya Kumar K, tim, xen-devel,
stefano.stabellini
On 12/06/14 18:03, Stefano Stabellini wrote:
> On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>
>> Add support for GIC v3 specification System register access(SRE)
>> is enabled to access cpu and virtual interface regiseters based
>> on kernel GICv3 driver.
>>
>> This patch adds only basic v3 support.
>> Does not support Interrupt Translation support (ITS)
>>
>> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> I see that a lot of things changed in this version of the patch. It
> would be nice if you kept a log of the incremental changes.
+1 for the other patches.
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 17/21] xen/arm: Add support for GIC v3
2014-06-12 13:36 ` [PATCH v5 17/21] xen/arm: Add support for GIC v3 vijay.kilari
2014-06-12 17:03 ` Stefano Stabellini
@ 2014-06-15 18:10 ` Julien Grall
1 sibling, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 18:10 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Add support for GIC v3 specification System register access(SRE)
> is enabled to access cpu and virtual interface regiseters based
s/regiseters/registers/
[..]
> + for ( i = 0; i < gicv3.rdist_count; i++ )
> + {
> + void __iomem *ptr = gicv3.rdist_regions[i].map_base;
> +
> + reg = readl_relaxed(ptr + GICR_PIDR2) & GICR_PIDR2_ARCH_MASK;
> + if ( reg != (GICV3_GICR_PIDR2 & GICR_PIDR2_ARCH_MASK) )
GICV3_GICR_PIDR2 is used for the emulation. You can't use this value to
test hardware stuff. Please use 0x30 (GICv3) which is clearer.
[..]
> +static void __cpuinit gicv3_hyp_init(void)
> +{
> + uint32_t vtr;
> +
> + vtr = READ_SYSREG32(ICH_VTR_EL2);
> + gicv3_info.nr_lrs = (vtr & GICH_VTR_NRLRGS) + 1;
> + gicv3.nr_priorities = ((vtr >> GICH_VTR_PRIBITS_SHIFT) &
> + GICH_VTR_PRIBITS_MASK) + 1;
> +
> + ASSERT((gicv3.nr_priorities > 4 && gicv3.nr_priorities < 8));
For hardware "feature" checking, it's *better* to print a correct error
message than ASSERT (which is not enabled on non-debug build).
[..]
> +static void gicv3_send_sgi(const cpumask_t *cpumask, enum gic_sgi sgi,
> + enum gic_sgi_mode mode)
> +{
> + int cpu = 0;
> + uint64_t val;
> +
> + dsb(sy);
Why a dsb here? I don't think it's useful there.
> + for_each_cpu(cpu, cpumask)
> + {
> + uint64_t cluster_id = cpu_logical_map(cpu) & ~0xffUL;
~0xff???? Can't we use a define here?
Or at least a comment explain why this value.
[..]
> +static void gicv3_irq_enable(struct irq_desc *desc)
> +{
> + unsigned long flags;
> +
We require to call this function with the desc->lock locked. Please add
an ASSERT here:
ASSERT(spin_is_locked(&desc->lock));
[..]
> +static void gicv3_irq_disable(struct irq_desc *desc)
> +{
> + unsigned long flags;
ASSERT(spin_is_locked(&desc->lock));
[..]
> diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
> index e81b80e..7aef378 100644
> --- a/xen/include/xen/lib.h
> +++ b/xen/include/xen/lib.h
> @@ -67,6 +67,8 @@ do { \
>
> #define reserve_bootmem(_p,_l) ((void)0)
>
> +#define SZ_64K 0x00010000
> +
As said on V4, you have to cc the relevant maintainers for every file
you've modified... (I didn't cced them this time)
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (16 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 17/21] xen/arm: Add support for GIC v3 vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 17:09 ` Stefano Stabellini
2014-06-15 18:32 ` Julien Grall
2014-06-12 13:36 ` [PATCH v5 19/21] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
` (4 subsequent siblings)
22 siblings, 2 replies; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Add virtual GICv3 driver support.
Also, with this patch vgic_irq_rank structure is modified to
hold GICv2 GICD_TARGET and GICv3 GICD_ROUTER registers under
union.
This patch adds only basic GICv3 support.
Does not support Interrupt Translation support (ITS)
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/Makefile | 1 +
xen/arch/arm/vgic-v2.c | 8 +-
xen/arch/arm/vgic-v3.c | 904 ++++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic.c | 5 +
xen/include/asm-arm/vgic.h | 13 +-
5 files changed, 926 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index 1684c09..ba61e58 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -28,6 +28,7 @@ obj-y += smp.o
obj-y += shutdown.o
obj-y += traps.o
obj-y += vgic.o vgic-v2.o
+obj-$(CONFIG_ARM_64) += vgic-v3.o
obj-y += vtimer.o
obj-y += vuart.o
obj-y += hvm.o
diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
index 68956e5..78fa9ba 100644
--- a/xen/arch/arm/vgic-v2.c
+++ b/xen/arch/arm/vgic-v2.c
@@ -137,7 +137,7 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
if ( rank == NULL) goto read_as_zero;
vgic_lock_rank(v, rank);
- *r = rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ *r = rank->v2.itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
DABT_WORD)];
if ( dabt.size == DABT_BYTE )
*r = vgic_byte_read(*r, dabt.sign, gicd_reg);
@@ -365,10 +365,10 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
if ( rank == NULL) goto write_ignore;
vgic_lock_rank(v, rank);
if ( dabt.size == DABT_WORD )
- rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
+ rank->v2.itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR,
DABT_WORD)] = *r;
else
- vgic_byte_write(&rank->itargets[REG_RANK_INDEX(8,
+ vgic_byte_write(&rank->v2.itargets[REG_RANK_INDEX(8,
gicd_reg - GICD_ITARGETSR, DABT_WORD)], *r, gicd_reg);
vgic_unlock_rank(v, rank);
return 1;
@@ -470,7 +470,7 @@ static int vgic_v2_vcpu_init(struct vcpu *v)
/* For SGI and PPI the target is always this CPU */
for ( i = 0 ; i < 8 ; i++ )
- v->arch.vgic.private_irqs->itargets[i] =
+ v->arch.vgic.private_irqs->v2.itargets[i] =
(1<<(v->vcpu_id+0))
| (1<<(v->vcpu_id+8))
| (1<<(v->vcpu_id+16))
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
new file mode 100644
index 0000000..b116d27
--- /dev/null
+++ b/xen/arch/arm/vgic-v3.c
@@ -0,0 +1,904 @@
+/*
+ * xen/arch/arm/vgic-v3.c
+ *
+ * ARM Virtual Generic Interrupt Controller v3 support
+ * based on xen/arch/arm/vgic.c
+ *
+ * Vijaya Kumar K <vijaya.kumar@caviumnetworks.com>
+ * Copyright (c) 2014 Cavium Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/bitops.h>
+#include <xen/config.h>
+#include <xen/lib.h>
+#include <xen/init.h>
+#include <xen/softirq.h>
+#include <xen/irq.h>
+#include <xen/sched.h>
+
+#include <asm/current.h>
+#include <asm/device.h>
+
+#include <asm/mmio.h>
+#include <asm/gic_v3_defs.h>
+#include <asm/gic.h>
+#include <asm/vgic.h>
+
+static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ uint64_t aff;
+
+ switch ( gicr_reg )
+ {
+ case GICR_CTLR:
+ /* We have not implemented LPI's, read zero */
+ goto read_as_zero;
+ case GICR_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_IIDR_VAL;
+ return 1;
+ case GICR_TYPER:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ /* TBD: Update processor id in [23:8] when ITS support is added */
+ aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32);
+ *r = aff;
+ return 1;
+ case GICR_STATUSR:
+ /* Not implemented */
+ goto read_as_zero;
+ case GICR_WAKER:
+ /* Power management is not implemented */
+ goto read_as_zero;
+ case GICR_SETLPIR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ case GICR_CLRLPIR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ case GICR_PROPBASER:
+ /* LPI's not implemented */
+ goto read_as_zero_64;
+ case GICR_PENDBASER:
+ /* LPI's not implemented */
+ goto read_as_zero_64;
+ case GICR_INVLPIR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ case GICR_INVALLR:
+ /* WO. Read as zero */
+ goto read_as_zero_64;
+ return 0;
+ case GICR_SYNCR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* RO . But when read it always returns busy bito bit[0] */
+ *r = GICR_SYNCR_NOT_BUSY;
+ return 1;
+ case GICR_MOVLPIR:
+ /* WO Read as zero */
+ goto read_as_zero_64;
+ case GICR_MOVALLR:
+ /* WO Read as zero */
+ goto read_as_zero_64;
+ case GICR_PIDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR0;
+ return 1;
+ case GICR_PIDR1:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR1;
+ return 1;
+ case GICR_PIDR2:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR2;
+ return 1;
+ case GICR_PIDR3:
+ /* Manufacture/customer defined */
+ goto read_as_zero;
+ case GICR_PIDR4:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICR_PIDR4;
+ return 1;
+ case GICR_PIDR5 ... GICR_PIDR7:
+ /* Reserved0 */
+ goto read_as_zero;
+ default:
+ printk("vGICv3: vGICR: read r%d offset %#08x\n not found",
+ dabt.reg, gicr_reg);
+ return 0;
+ }
+bad_width:
+ printk("vGICv3: vGICR: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int __vgic_v3_rdistr_rd_mmio_write(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+
+ switch ( gicr_reg )
+ {
+ case GICR_CTLR:
+ /* LPI's not implemented */
+ goto write_ignore;
+ case GICR_IIDR:
+ /* RO */
+ goto write_ignore;
+ case GICR_TYPER:
+ /* RO */
+ goto write_ignore_64;
+ case GICR_STATUSR:
+ /* Not implemented */
+ goto write_ignore;
+ case GICR_WAKER:
+ /* Power mgmt not implemented */
+ goto write_ignore;
+ case GICR_SETLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_CLRLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_PROPBASER:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_PENDBASER:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_INVLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_INVALLR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_SYNCR:
+ /* RO */
+ goto write_ignore;
+ case GICR_MOVLPIR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_MOVALLR:
+ /* LPI is not implemented */
+ goto write_ignore_64;
+ case GICR_PIDR7... GICR_PIDR0:
+ /* RO */
+ goto write_ignore;
+ default:
+ printk("vGICR: write r%d offset %#08x\n not found", dabt.reg, gicr_reg);
+ return 0;
+ }
+bad_width:
+ printk("vGICR: bad write width %d r%d=%"PRIregister" offset %#08x\n",
+ dabt.size, dabt.reg, *r, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ return 1;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+static int __vgic_v3_distr_common_mmio_read(struct vcpu *v, mmio_info_t *info,
+ uint32_t reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+
+ switch ( reg )
+ {
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->ienable;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ISPENDR, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ICPENDR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = vgic_byte_read(rank->ipend, dabt.sign, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->iactive;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+
+ vgic_lock_rank(v, rank);
+ *r = rank->ipriority[REG_RANK_INDEX(8, reg - GICD_IPRIORITYR,
+ DABT_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICFGR ... GICD_ICFGRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 2, reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)];
+ vgic_unlock_rank(v, rank);
+ return 1;
+ default:
+ printk("GICv3: vGICD/vGICR: unhandled read r%d offset %#08x\n",
+ dabt.reg, reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "vGICv3: vGICD/vGICR: bad read width %d r%d \
+ offset %#08x\n", dabt.size, dabt.reg, reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int __vgic_v3_distr_common_mmio_write(struct vcpu *v, mmio_info_t *info,
+ uint32_t reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ uint32_t tr;
+
+ switch ( reg )
+ {
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ISENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable |= *r;
+ vgic_unlock_rank(v, rank);
+ /* The irq number is extracted from offset. so shift by register size */
+ vgic_enable_irqs(v, (*r) & (~tr), (reg - GICD_ISENABLER) >> DABT_WORD);
+ return 1;
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ICENABLER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ tr = rank->ienable;
+ rank->ienable &= ~*r;
+ vgic_unlock_rank(v, rank);
+ /* The irq number is extracted from offset. so shift by register size */
+ vgic_disable_irqs(v, (*r) & tr, (reg - GICD_ICENABLER) >> DABT_WORD);
+ return 1;
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ISPENDR, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->ipend = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ICPENDR, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->ipend &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ISACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, reg - GICD_ICACTIVER, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->iactive &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ if ( dabt.size == DABT_WORD )
+ rank->ipriority[REG_RANK_INDEX(8, reg - GICD_IPRIORITYR,
+ DABT_WORD)] = *r;
+ else
+ vgic_byte_write(&rank->ipriority[REG_RANK_INDEX(8,
+ reg - GICD_IPRIORITYR, DABT_WORD)], *r, reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_ICFGR: /* Restricted to configure SGIs */
+ goto write_ignore;
+ case GICD_ICFGR + 4 ... GICD_ICFGRN: /* PPI + SPIs */
+ /* ICFGR1 for PPI's, which is implementation defined
+ if ICFGR1 is programmable or not. We chose to program */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 2, reg - GICD_ICFGR, DABT_WORD);
+ if ( rank == NULL) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)] = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ default:
+ printk("vGICv3: vGICD/vGICR: unhandled write r%d \
+ =%"PRIregister" offset %#08x\n", dabt.reg, *r, reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "vGICv3: vGICD/vGICR: bad write width %d \
+ r%d=%"PRIregister" offset %#08x\n", dabt.size, dabt.reg, *r, reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+static int vgic_v3_rdistr_sgi_mmio_read(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+
+ switch ( gicr_reg )
+ {
+ case GICR_IGRPMODR0:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+ case GICR_IGROUPR0:
+ case GICR_ISENABLER0:
+ case GICR_ICENABLER0:
+ case GICR_ISACTIVER0:
+ case GICR_ICACTIVER0:
+ case GICR_IPRIORITYR0...GICR_IPRIORITYR7:
+ case GICR_ICFGR0... GICR_ICFGR1:
+ /*
+ * Above registers offset are common with GICD.
+ * So handle in common with GICD handling
+ */
+ return __vgic_v3_distr_common_mmio_read(v, info, gicr_reg);
+ case GICR_ISPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicr_reg - GICR_ISPENDR0, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->pendsgi;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_ICPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicr_reg - GICR_ICPENDR0, DABT_WORD);
+ if ( rank == NULL ) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ *r = rank->pendsgi;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_NSACR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+ default:
+ printk("vGICv3: vGICR: read r%d offset %#08x\n not found",
+ dabt.reg, gicr_reg);
+ return 0;
+ }
+bad_width:
+ printk("vGICv3: vGICR: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int vgic_v3_rdistr_sgi_mmio_write(struct vcpu *v, mmio_info_t *info,
+ uint32_t gicr_reg)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+
+ switch ( gicr_reg )
+ {
+ case GICR_IGRPMODR0:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ case GICR_IGROUPR0:
+ case GICR_ISENABLER0:
+ case GICR_ICENABLER0:
+ case GICR_ISACTIVER0:
+ case GICR_ICACTIVER0:
+ case GICR_ICFGR1:
+ case GICR_IPRIORITYR0...GICR_IPRIORITYR7:
+ /*
+ * Above registers offset are common with GICD.
+ * So handle common with GICD handling
+ */
+ return __vgic_v3_distr_common_mmio_write(v, info, gicr_reg);
+ case GICR_ISPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicr_reg - GICR_ISACTIVER0, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ /* TODO: we just store the SGI pending status. Handle it properly */
+ rank->pendsgi |= *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_ICPENDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 1, gicr_reg - GICR_ISACTIVER0, DABT_WORD);
+ if ( rank == NULL ) goto write_ignore;
+ vgic_lock_rank(v, rank);
+ /* TODO: we just store the SGI pending status. Handle it properly */
+ rank->pendsgi &= ~*r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICR_NSACR:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ default:
+ printk("vGICv3: vGICR SGI: write r%d offset %#08x\n not found",
+ dabt.reg, gicr_reg);
+ return 0;
+ }
+
+bad_width:
+ printk("vGICR SGI: bad write width %d r%d=%"PRIregister" offset %#08x\n",
+ dabt.size, dabt.reg, *r, gicr_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+}
+
+static int vgic_v3_rdistr_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ uint32_t offset;
+
+ offset = info->gpa & (v->domain->arch.vgic.rdist_stride - 1);
+
+ if ( offset < SZ_64K )
+ return __vgic_v3_rdistr_rd_mmio_read(v, info, offset);
+ else if ( (offset >= SZ_64K) && (offset < 2 * SZ_64K) )
+ return vgic_v3_rdistr_sgi_mmio_read(v, info, (offset - SZ_64K));
+ else
+ gdprintk(XENLOG_WARNING, "vGICv3: vGICR: unknown gpa read address \
+ %"PRIpaddr"\n", info->gpa);
+
+ return 0;
+}
+
+static int vgic_v3_rdistr_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ uint32_t offset;
+
+ offset = info->gpa & (v->domain->arch.vgic.rdist_stride - 1);
+ if ( offset < SZ_64K )
+ return __vgic_v3_rdistr_rd_mmio_write(v, info, offset);
+ else if ( (offset >= SZ_64K) && (offset < 2 * SZ_64K) )
+ return vgic_v3_rdistr_sgi_mmio_write(v, info, (offset - SZ_64K));
+ else
+ gdprintk(XENLOG_WARNING, "vGICV3: vGICR: unknown gpa write address \
+ %"PRIpaddr"\n", info->gpa);
+
+ return 0;
+}
+
+static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vgic_lock(v);
+ *r = v->domain->arch.vgic.ctlr;
+ vgic_unlock(v);
+ return 1;
+ case GICD_TYPER:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* No secure world support for guests. */
+ *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
+ ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
+ return 1;
+ case GICD_STATUSR:
+ /*
+ * Optional, Not implemented for now.
+ * Update to support guest debugging.
+ */
+ goto read_as_zero;
+ case GICD_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_IIDR_VAL;
+ return 1;
+ case 0x020 ... 0x03c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- read as zero */
+ goto read_as_zero;
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ case GICD_ICFGR ... GICD_ICFGRN:
+ /*
+ * Above all register are common with GICR and GICD
+ * Manage in common
+ */
+ return __vgic_v3_distr_common_mmio_read(v, info, gicd_reg);
+ case GICD_IROUTER ... GICD_IROUTER31:
+ /* SGI/PPI is RES0 */
+ goto read_as_zero_64;
+ case GICD_IROUTER32 ... GICD_IROUTERN:
+ if ( dabt.size != DABT_BYTE && dabt.size != DABT_DOUBLE_WORD )
+ goto bad_width;
+ rank = vgic_irq_rank(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD);
+ if ( rank == NULL) goto read_as_zero;
+ vgic_lock_rank(v, rank);
+ /* IROUTER is 64 bit so, to make it byte size right shift by 3.
+ Here once. macro REG_RANK_INDEX will do it twice */
+ *r = rank->v3.irouter[REG_RANK_INDEX(64,
+ (gicd_reg - GICD_IROUTER), DABT_DOUBLE_WORD)];
+ if ( dabt.size == DABT_BYTE )
+ *r = vgic_byte_read(*r, dabt.sign, gicd_reg);
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, read zero */
+ goto read_as_zero;
+ case GICD_SGIR:
+ /* Read as ICH_SGIR system register with SRE set. So ignore */
+ goto read_as_zero;
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ /* Replaced with GICR_ICPENDR0. So ignore write */
+ goto read_as_zero;
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ /* Replaced with GICR_ISPENDR0. So ignore write */
+ goto read_as_zero;
+ case GICD_PIDR0:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR0;
+ return 1;
+ case GICD_PIDR1:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR1;
+ return 1;
+ case GICD_PIDR2:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR2;
+ return 1;
+ case GICD_PIDR3:
+ /* GICv3 identification value. Manufacturer/Customer defined */
+ goto read_as_zero;
+ case GICD_PIDR4:
+ /* GICv3 identification value */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = GICV3_GICD_PIDR4;
+ return 1;
+ case GICD_PIDR5 ... GICD_PIDR7:
+ /* Reserved0 */
+ goto read_as_zero;
+ case 0x00c:
+ case 0x044:
+ case 0x04c:
+ case 0x05c ... 0x07c:
+ case 0xf30 ... 0x5fcc:
+ case 0x8000 ... 0xbfcc:
+ /* These are reserved register addresses */
+ printk("vGICv3: vGICD: read unknown 0x00c .. 0xfcc r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ goto read_as_zero;
+ default:
+ printk("vGICv3: vGICD: unhandled read r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "vGICv3: vGICD: bad read width %d r%d offset %#08x\n",
+ dabt.size, dabt.reg, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+
+read_as_zero:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = 0;
+ return 1;
+}
+
+static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ struct vgic_irq_rank *rank;
+ int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase);
+
+ switch ( gicd_reg )
+ {
+ case GICD_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ /* Ignore all but the enable bit */
+ v->domain->arch.vgic.ctlr = (*r) & GICD_CTL_ENABLE;
+ return 1;
+ case GICD_TYPER:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GICD_IIDR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GICD_STATUSR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GICD_SETSPI_NSR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case GICD_CLRSPI_NSR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case GICD_SETSPI_SR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case GICD_CLRSPI_SR:
+ /* Message based SPI is not implemented */
+ goto write_ignore;
+ case 0x020 ... 0x03c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- write ignored */
+ printk("vGICD: write unknown 0x020 - 0x03c r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ goto write_ignore;
+ case GICD_IGROUPR ... GICD_IGROUPRN:
+ case GICD_ISENABLER ... GICD_ISENABLERN:
+ case GICD_ICENABLER ... GICD_ICENABLERN:
+ case GICD_ISPENDR ... GICD_ISPENDRN:
+ case GICD_ICPENDR ... GICD_ICPENDRN:
+ case GICD_ISACTIVER ... GICD_ISACTIVERN:
+ case GICD_ICACTIVER ... GICD_ICACTIVERN:
+ case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
+ case GICD_ICFGR ... GICD_ICFGRN:
+ /* Above registers are common with GICR and GICD
+ * Manage in common */
+ return __vgic_v3_distr_common_mmio_write(v, info, gicd_reg);
+ case GICD_IROUTER ... GICD_IROUTER31:
+ /* SGI/PPI is RES0 */
+ goto write_ignore_64;
+ case GICD_IROUTER32 ... GICD_IROUTERN:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ rank = vgic_irq_rank(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD);
+ if ( rank == NULL) goto write_ignore_64;
+ if ( *r )
+ {
+ /* TODO: Ignored. We don't support irq delivery for vcpu != 0 */
+ gdprintk(XENLOG_DEBUG,
+ "SPI delivery to secondary cpus not supported\n");
+ goto write_ignore_64;
+ }
+ vgic_lock_rank(v, rank);
+ rank->v3.irouter[REG_RANK_INDEX(64,
+ (gicd_reg - GICD_IROUTER), DABT_DOUBLE_WORD)] = *r;
+ vgic_unlock_rank(v, rank);
+ return 1;
+ case GICD_NSACR ... GICD_NSACRN:
+ /* We do not implement security extensions for guests, write ignore */
+ goto write_ignore;
+ case GICD_SGIR:
+ /* it is accessed as system register in GICv3 */
+ goto write_ignore;
+ case GICD_CPENDSGIR ... GICD_CPENDSGIRN:
+ /* Replaced with GICR_ICPENDR0. So ignore write */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 0;
+ case GICD_SPENDSGIR ... GICD_SPENDSGIRN:
+ /* Replaced with GICR_ISPENDR0. So ignore write */
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 0;
+ case GICD_PIDR7... GICD_PIDR0:
+ /* RO -- write ignore */
+ goto write_ignore;
+ case 0x00c:
+ case 0x044:
+ case 0x04c:
+ case 0x05c ... 0x07c:
+ case 0xf30 ... 0x5fcc:
+ case 0x8000 ... 0xbfcc:
+ /* Reserved register addresses */
+ printk("vGICv3: vGICD: write unknown 0x00c 0xfcc r%d offset %#08x\n",
+ dabt.reg, gicd_reg);
+ goto write_ignore;
+ default:
+ printk("vGICv3: vGICD: unhandled write r%d=%"PRIregister" \
+ offset %#08x\n", dabt.reg, *r, gicd_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_ERR, "VGICv3: vGICD: bad write width %d r%d=%"PRIregister" \
+ offset %#08x\n", dabt.size, dabt.reg, *r, gicd_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+
+write_ignore_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ return 1;
+}
+
+static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
+ .read_handler = vgic_v3_rdistr_mmio_read,
+ .write_handler = vgic_v3_rdistr_mmio_write,
+};
+
+static const struct mmio_handler_ops vgic_distr_mmio_handler = {
+ .read_handler = vgic_v3_distr_mmio_read,
+ .write_handler = vgic_v3_distr_mmio_write,
+};
+
+static int vgicv3_vcpu_init(struct vcpu *v)
+{
+ int i;
+ uint64_t affinity;
+
+ /* For SGI and PPI the target is always this CPU */
+ affinity = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 32 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 16 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 8 |
+ MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0));
+
+ for ( i = 0 ; i < 32 ; i++ )
+ v->arch.vgic.private_irqs->v3.irouter[i] = affinity;
+
+ return 0;
+}
+
+static int vgicv3_domain_init(struct domain *d)
+{
+ int i;
+
+ register_mmio_handler(d, &vgic_distr_mmio_handler, d->arch.vgic.dbase,
+ d->arch.vgic.dbase_size);
+
+ /*
+ * Register mmio handler per redistributor region but not for
+ * every sgi rdist region which is per core.
+ * The redistributor region encompasses per core sgi region.
+ */
+ for ( i = 0; i < d->arch.vgic.rdist_count; i++ )
+ register_mmio_handler(d, &vgic_rdistr_mmio_handler,
+ d->arch.vgic.rbase[i], d->arch.vgic.rbase_size[i]);
+
+ return 0;
+}
+
+static const struct vgic_ops v3_ops = {
+ .vcpu_init = vgicv3_vcpu_init,
+ .domain_init = vgicv3_domain_init,
+};
+
+int vgic_v3_init(struct domain *d)
+{
+ register_vgic_ops(d, &v3_ops);
+ return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 61c225f..b94bfc7 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -63,6 +63,11 @@ int domain_vgic_init(struct domain *d)
switch ( gic_hw_version() )
{
+#ifdef CONFIG_ARM_64
+ case GIC_V3:
+ vgic_v3_init(d);
+ break;
+#endif
case GIC_V2:
vgic_v2_init(d);
break;
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 399a241..a237f4d 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -83,7 +83,14 @@ struct vgic_irq_rank {
uint32_t ienable, iactive, ipend, pendsgi;
uint32_t icfg[2];
uint32_t ipriority[8];
- uint32_t itargets[8];
+ union {
+ struct {
+ uint32_t itargets[8];
+ }v2;
+ struct {
+ uint64_t irouter[32];
+ }v3;
+ };
};
struct vgic_ops {
@@ -110,6 +117,9 @@ static inline int REG_RANK_NR(int b, uint32_t n)
{
switch ( b )
{
+ case 64: return n >> 6;
+ case 32: return n >> 5;
+ case 16: return n >> 4;
case 8: return n >> 3;
case 4: return n >> 2;
case 2: return n >> 1;
@@ -157,6 +167,7 @@ extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
int vgic_v2_init(struct domain *d);
+int vgic_v3_init(struct domain *d);
extern int vcpu_vgic_free(struct vcpu *v);
#endif /* __ASM_ARM_VGIC_H__ */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-12 13:36 ` [PATCH v5 18/21] xen/arm: Add virtual GICv3 support vijay.kilari
@ 2014-06-12 17:09 ` Stefano Stabellini
2014-06-15 17:07 ` Julien Grall
2014-06-15 18:32 ` Julien Grall
1 sibling, 1 reply; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 17:09 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> + switch ( gicd_reg )
> + {
> + case GICD_CTLR:
> + if ( dabt.size != DABT_WORD ) goto bad_width;
> + vgic_lock(v);
> + *r = v->domain->arch.vgic.ctlr;
> + vgic_unlock(v);
> + return 1;
> + case GICD_TYPER:
> + if ( dabt.size != DABT_WORD ) goto bad_width;
> + /* No secure world support for guests. */
> + *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
> + ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
> + return 1;
There used to be a vgic_lock(v) and vgic_unlock(v) here. Why did you
remove them?
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-12 17:09 ` Stefano Stabellini
@ 2014-06-15 17:07 ` Julien Grall
2014-06-16 10:59 ` Stefano Stabellini
0 siblings, 1 reply; 87+ messages in thread
From: Julien Grall @ 2014-06-15 17:07 UTC (permalink / raw)
To: Stefano Stabellini, vijay.kilari
Cc: Ian.Campbell, Prasun.Kapoor, Vijaya Kumar K, tim, xen-devel,
stefano.stabellini
Hi Stefano,
On 12/06/14 18:09, Stefano Stabellini wrote:
> On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
>> + switch ( gicd_reg )
>> + {
>> + case GICD_CTLR:
>> + if ( dabt.size != DABT_WORD ) goto bad_width;
>> + vgic_lock(v);
>> + *r = v->domain->arch.vgic.ctlr;
>> + vgic_unlock(v);
>> + return 1;
>> + case GICD_TYPER:
>> + if ( dabt.size != DABT_WORD ) goto bad_width;
>> + /* No secure world support for guests. */
>> + *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
>> + ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
>> + return 1;
>
> There used to be a vgic_lock(v) and vgic_unlock(v) here. Why did you
> remove them?
I don't think it's important to take the vgic lock here. Xen only access
read-only data, max_vcpus and nr_lines doesn't change.
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-15 17:07 ` Julien Grall
@ 2014-06-16 10:59 ` Stefano Stabellini
2014-06-16 11:08 ` Stefano Stabellini
0 siblings, 1 reply; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-16 10:59 UTC (permalink / raw)
To: Julien Grall
Cc: Ian.Campbell, vijay.kilari, Stefano Stabellini, Prasun.Kapoor,
Vijaya Kumar K, tim, xen-devel, stefano.stabellini
On Sun, 15 Jun 2014, Julien Grall wrote:
> Hi Stefano,
>
> On 12/06/14 18:09, Stefano Stabellini wrote:
> > On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> > > + switch ( gicd_reg )
> > > + {
> > > + case GICD_CTLR:
> > > + if ( dabt.size != DABT_WORD ) goto bad_width;
> > > + vgic_lock(v);
> > > + *r = v->domain->arch.vgic.ctlr;
> > > + vgic_unlock(v);
> > > + return 1;
> > > + case GICD_TYPER:
> > > + if ( dabt.size != DABT_WORD ) goto bad_width;
> > > + /* No secure world support for guests. */
> > > + *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
> > > + ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
> > > + return 1;
> >
> > There used to be a vgic_lock(v) and vgic_unlock(v) here. Why did you
> > remove them?
>
> I don't think it's important to take the vgic lock here. Xen only access
> read-only data, max_vcpus and nr_lines doesn't change.
OK. It should be written in the commit message.
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-16 10:59 ` Stefano Stabellini
@ 2014-06-16 11:08 ` Stefano Stabellini
0 siblings, 0 replies; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-16 11:08 UTC (permalink / raw)
To: Stefano Stabellini
Cc: Ian.Campbell, vijay.kilari, Prasun.Kapoor, Vijaya Kumar K,
Julien Grall, tim, xen-devel, stefano.stabellini
On Mon, 16 Jun 2014, Stefano Stabellini wrote:
> On Sun, 15 Jun 2014, Julien Grall wrote:
> > Hi Stefano,
> >
> > On 12/06/14 18:09, Stefano Stabellini wrote:
> > > On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> > > > + switch ( gicd_reg )
> > > > + {
> > > > + case GICD_CTLR:
> > > > + if ( dabt.size != DABT_WORD ) goto bad_width;
> > > > + vgic_lock(v);
> > > > + *r = v->domain->arch.vgic.ctlr;
> > > > + vgic_unlock(v);
> > > > + return 1;
> > > > + case GICD_TYPER:
> > > > + if ( dabt.size != DABT_WORD ) goto bad_width;
> > > > + /* No secure world support for guests. */
> > > > + *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
> > > > + ((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
> > > > + return 1;
> > >
> > > There used to be a vgic_lock(v) and vgic_unlock(v) here. Why did you
> > > remove them?
> >
> > I don't think it's important to take the vgic lock here. Xen only access
> > read-only data, max_vcpus and nr_lines doesn't change.
>
> OK. It should be written in the commit message.
You could write something like:
The GICD emulation for GICv3 is taken from the original GICD emulation
for GICv2. One difference is that we don't take the vgic lock to read
GICD_TYPER.
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-12 13:36 ` [PATCH v5 18/21] xen/arm: Add virtual GICv3 support vijay.kilari
2014-06-12 17:09 ` Stefano Stabellini
@ 2014-06-15 18:32 ` Julien Grall
2014-06-20 6:31 ` Vijay Kilari
1 sibling, 1 reply; 87+ messages in thread
From: Julien Grall @ 2014-06-15 18:32 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
I didn't look very closely to each part of this patch. But it looks good
to me. I've only one question, see below.
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> +static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
[..]
> + case GICD_IROUTER32 ... GICD_IROUTERN:
> + if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
> + rank = vgic_irq_rank(v, 64, gicd_reg - GICD_IROUTER, DABT_DOUBLE_WORD);
You've handled word read-access a bit above. Why don't you handle word
write-access?
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 18/21] xen/arm: Add virtual GICv3 support
2014-06-15 18:32 ` Julien Grall
@ 2014-06-20 6:31 ` Vijay Kilari
0 siblings, 0 replies; 87+ messages in thread
From: Vijay Kilari @ 2014-06-20 6:31 UTC (permalink / raw)
To: Julien Grall
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On Mon, Jun 16, 2014 at 12:02 AM, Julien Grall <julien.grall@linaro.org> wrote:
> Hi Vijay,
>
> I didn't look very closely to each part of this patch. But it looks good to
> me. I've only one question, see below.
>
>
> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
>>
>> +static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info)
>
>
> [..]
>
>
>> + case GICD_IROUTER32 ... GICD_IROUTERN:
>> + if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
>> + rank = vgic_irq_rank(v, 64, gicd_reg - GICD_IROUTER,
>> DABT_DOUBLE_WORD);
>
>
> You've handled word read-access a bit above. Why don't you handle word
> write-access?
OK. I will remove byte read-access. 64-bit IROUTER<n> is per irq.
So byte access has no meaning.
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 19/21] xen/arm: Update Dom0 GIC dt node with GICv3 information
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (17 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 18/21] xen/arm: Add virtual GICv3 support vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-15 18:36 ` Julien Grall
2014-06-12 13:36 ` [PATCH v5 20/21] xen/arm: add SGI handling for GICv3 vijay.kilari
` (3 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Update GIC device tree node for DOM0 with GICv3
information. GIC hw specfic device tree information
is moved to respective GIC driver.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/domain_build.c | 47 ++------------------------
xen/arch/arm/gic-v2.c | 51 ++++++++++++++++++++++++++++
xen/arch/arm/gic-v3.c | 78 +++++++++++++++++++++++++++++++++++++++++++
xen/arch/arm/gic.c | 6 ++++
xen/include/asm-arm/gic.h | 7 +++-
5 files changed, 143 insertions(+), 46 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 018f2f8..87754c3 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -525,9 +525,6 @@ static int make_gic_node(const struct domain *d, void *fdt,
const struct dt_device_node *node)
{
const struct dt_device_node *gic = dt_interrupt_controller;
- const void *compatible = NULL;
- u32 len;
- __be32 *new_cells, *tmp;
int res = 0;
/*
@@ -542,48 +539,7 @@ static int make_gic_node(const struct domain *d, void *fdt,
DPRINT("Create gic node\n");
- compatible = dt_get_property(gic, "compatible", &len);
- if ( !compatible )
- {
- dprintk(XENLOG_ERR, "Can't find compatible property for the gic node\n");
- return -FDT_ERR_XEN(ENOENT);
- }
-
- res = fdt_begin_node(fdt, "interrupt-controller");
- if ( res )
- return res;
-
- res = fdt_property(fdt, "compatible", compatible, len);
- if ( res )
- return res;
-
- res = fdt_property_cell(fdt, "#interrupt-cells", 3);
- if ( res )
- return res;
-
- res = fdt_property(fdt, "interrupt-controller", NULL, 0);
-
- if ( res )
- return res;
-
- len = dt_cells_to_size(dt_n_addr_cells(node) + dt_n_size_cells(node));
- len *= 2; /* GIC has two memory regions: Distributor + CPU interface */
- new_cells = xzalloc_bytes(len);
- if ( new_cells == NULL )
- return -FDT_ERR_XEN(ENOMEM);
-
- tmp = new_cells;
- DPRINT(" Set Distributor Base 0x%"PRIpaddr"-0x%"PRIpaddr"\n",
- d->arch.vgic.dbase, d->arch.vgic.dbase + PAGE_SIZE - 1);
- dt_set_range(&tmp, node, d->arch.vgic.dbase, PAGE_SIZE);
-
- DPRINT(" Set Cpu Base 0x%"PRIpaddr"-0x%"PRIpaddr"\n",
- d->arch.vgic.cbase, d->arch.vgic.cbase + (PAGE_SIZE * 2) - 1);
- dt_set_range(&tmp, node, d->arch.vgic.cbase, PAGE_SIZE * 2);
-
- res = fdt_property(fdt, "reg", new_cells, len);
- xfree(new_cells);
-
+ res = gic_make_node(d, node, fdt);
if ( res )
return res;
@@ -794,6 +750,7 @@ static int handle_node(struct domain *d, struct kernel_info *kinfo,
static const struct dt_device_match gic_matches[] __initconst =
{
DT_MATCH_GIC_V2,
+ DT_MATCH_GIC_V3,
{ /* sentinel */ },
};
static const struct dt_device_match timer_matches[] __initconst =
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 134815a..0d4cda0 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -27,6 +27,7 @@
#include <xen/softirq.h>
#include <xen/list.h>
#include <xen/device_tree.h>
+#include <xen/libfdt/libfdt.h>
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/platform.h>
@@ -528,6 +529,55 @@ static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
BUG();
}
+static int gicv2_make_dt_node(const struct domain *d,
+ const struct dt_device_node *node, void *fdt)
+{
+ const struct dt_device_node *gic = dt_interrupt_controller;
+ const void *compatible = NULL;
+ u32 len;
+ __be32 *new_cells, *tmp;
+ int res = 0;
+
+ compatible = dt_get_property(gic, "compatible", &len);
+ if ( !compatible )
+ {
+ dprintk(XENLOG_ERR, "Can't find compatible property for the gic node\n");
+ return -FDT_ERR_XEN(ENOENT);
+ }
+
+ res = fdt_begin_node(fdt, "interrupt-controller");
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "compatible", compatible, len);
+ if ( res )
+ return res;
+
+ res = fdt_property_cell(fdt, "#interrupt-cells", 3);
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "interrupt-controller", NULL, 0);
+
+ if ( res )
+ return res;
+
+ len = dt_cells_to_size(dt_n_addr_cells(node) + dt_n_size_cells(node));
+ len *= 2; /* GIC has two memory regions: Distributor + CPU interface */
+ new_cells = xzalloc_bytes(len);
+ if ( new_cells == NULL )
+ return -FDT_ERR_XEN(ENOMEM);
+
+ tmp = new_cells;
+ dt_set_range(&tmp, node, d->arch.vgic.dbase, PAGE_SIZE);
+ dt_set_range(&tmp, node, d->arch.vgic.cbase, PAGE_SIZE * 2);
+
+ res = fdt_property(fdt, "reg", new_cells, len);
+ xfree(new_cells);
+
+ return res;
+}
+
/* XXX different for level vs edge */
static hw_irq_controller gicv2_host_irq_type = {
.typename = "gic-v2",
@@ -572,6 +622,7 @@ const static struct gic_hw_operations gicv2_ops = {
.read_lr = gicv2_read_lr,
.write_lr = gicv2_write_lr,
.read_vmcr_priority = gicv2_read_vmcr_priority,
+ .make_dt_node = gicv2_make_dt_node,
};
/* Set up the GIC */
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 29cfd93..d7d53ce 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -31,6 +31,7 @@
#include <xen/errno.h>
#include <xen/delay.h>
#include <xen/device_tree.h>
+#include <xen/libfdt/libfdt.h>
#include <asm/p2m.h>
#include <asm/domain.h>
#include <asm/io.h>
@@ -980,6 +981,82 @@ static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
BUG();
}
+static int gicv3_make_dt_node(const struct domain *d,
+ const struct dt_device_node *node, void *fdt)
+{
+ const struct dt_device_node *gic = dt_interrupt_controller;
+ const void *compatible = NULL;
+ uint32_t len;
+ __be32 *new_cells, *tmp;
+ uint32_t rd_stride = 0;
+ uint32_t rd_count = 0;
+
+ int i, res = 0;
+
+ compatible = dt_get_property(gic, "compatible", &len);
+ if ( !compatible )
+ {
+ dprintk(XENLOG_ERR, "Can't find compatible property for the gic node\n");
+ return -FDT_ERR_XEN(ENOENT);
+ }
+
+ res = fdt_begin_node(fdt, "interrupt-controller");
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "compatible", compatible, len);
+ if ( res )
+ return res;
+
+ res = fdt_property_cell(fdt, "#interrupt-cells", 3);
+ if ( res )
+ return res;
+
+ res = fdt_property(fdt, "interrupt-controller", NULL, 0);
+ if ( res )
+ return res;
+
+ res = dt_property_read_u32(gic, "redistributor-stride", &rd_stride);
+ if ( !res )
+ rd_stride = 0;
+
+ res = dt_property_read_u32(gic, "#redistributor-regions", &rd_count);
+ if ( !res )
+ rd_count = 1;
+
+ res = fdt_property_cell(fdt, "redistributor-stride", rd_stride);
+ if ( res )
+ return res;
+
+ res = fdt_property_cell(fdt, "#redistributor-regions", rd_count);
+ if ( res )
+ return res;
+
+ len = dt_cells_to_size(dt_n_addr_cells(node) + dt_n_size_cells(node));
+ /*
+ * GIC has two memory regions: Distributor + rdist regions
+ * CPU interface and virtual cpu interfaces accessesed as System registers
+ * So cells are created only for Distributor and rdist regions
+ */
+ len = len * (d->arch.vgic.rdist_count + 1);
+ new_cells = xzalloc_bytes(len);
+ if ( new_cells == NULL )
+ return -FDT_ERR_XEN(ENOMEM);
+
+ tmp = new_cells;
+
+ dt_set_range(&tmp, node, d->arch.vgic.dbase, d->arch.vgic.dbase_size);
+
+ for ( i = 0; i < d->arch.vgic.rdist_count; i++ )
+ dt_set_range(&tmp, node, d->arch.vgic.rbase[i],
+ d->arch.vgic.rbase_size[i]);
+
+ res = fdt_property(fdt, "reg", new_cells, len);
+ xfree(new_cells);
+
+ return res;
+}
+
static const hw_irq_controller gicv3_host_irq_type = {
.typename = "gic-v3",
.startup = gicv3_irq_startup,
@@ -1023,6 +1100,7 @@ static const struct gic_hw_operations gicv3_ops = {
.write_lr = gicv3_write_lr,
.read_vmcr_priority = gicv3_read_vmcr_priority,
.secondary_init = gicv3_secondary_cpu_init,
+ .make_dt_node = gicv3_make_dt_node,
};
/* Set up the GIC */
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index bf1367b..876ca25 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -625,6 +625,12 @@ void __cpuinit init_maintenance_interrupt(void)
"irq-maintenance", NULL);
}
+int gic_make_node(const struct domain *d,const struct dt_device_node *node,
+ void *fdt)
+{
+ return gic_hw_ops->make_dt_node(d, node, fdt);
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index 61a4933..1142b27 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -160,7 +160,7 @@
#define DT_MATCH_GIC_V3_STRING1 "arm,gic-v3"
-#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1);
+#define DT_MATCH_GIC_V3 DT_MATCH_COMPATIBLE(DT_MATCH_GIC_V3_STRING1)
/*
* GICv3 registers that needs to be saved/restored
@@ -334,10 +334,15 @@ struct gic_hw_operations {
unsigned int (*read_vmcr_priority)(void);
/* Secondary CPU init */
int (*secondary_init)(void);
+ int (*make_dt_node)(const struct domain *d,
+ const struct dt_device_node *node, void *fdt);
};
void register_gic_ops(const struct gic_hw_operations *ops);
extern void update_cpu_lr_mask(void);
+int gic_make_node(const struct domain *d,const struct dt_device_node *node,
+ void *fdt);
+
#endif /* __ASSEMBLY__ */
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 19/21] xen/arm: Update Dom0 GIC dt node with GICv3 information
2014-06-12 13:36 ` [PATCH v5 19/21] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
@ 2014-06-15 18:36 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-15 18:36 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Update GIC device tree node for DOM0 with GICv3
> information. GIC hw specfic device tree information
> is moved to respective GIC driver.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 20/21] xen/arm: add SGI handling for GICv3
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (18 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 19/21] xen/arm: Update Dom0 GIC dt node with GICv3 information vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 17:15 ` Stefano Stabellini
2014-06-12 13:36 ` [PATCH v5 21/21] xen/arm: check for GICv3 platform support vijay.kilari
` (2 subsequent siblings)
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
In ARMv8, write to ICC_SGI1R_EL1 register raises trap to EL2.
Handle the trap and inject SGI to vcpu.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/traps.c | 30 ++++++++++++++++++++
xen/arch/arm/vgic-v3.c | 55 +++++++++++++++++++++++++++++++++++++
xen/include/asm-arm/gic_v3_defs.h | 7 +++++
xen/include/asm-arm/sysregs.h | 3 ++
xen/include/asm-arm/vgic.h | 1 +
5 files changed, 96 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 9348147..1ac01ee 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -41,6 +41,7 @@
#include "decode.h"
#include "vtimer.h"
#include <asm/gic.h>
+#include <asm/vgic.h>
/* The base of the stack must always be double-word aligned, which means
* that both the kernel half of struct cpu_user_regs (which is pushed in
@@ -496,6 +497,18 @@ static void inject_dabt_exception(struct cpu_user_regs *regs,
#endif
}
+static void inject_undef_exception(struct cpu_user_regs *regs,
+ register_t addr,
+ int instr_len)
+{
+ if ( is_32bit_domain(current->domain) )
+ inject_undef32_exception(regs);
+#ifdef CONFIG_ARM_64
+ else
+ inject_undef64_exception(regs, instr_len);
+#endif
+}
+
struct reg_ctxt {
/* Guest-side state */
uint32_t sctlr_el1;
@@ -1467,6 +1480,7 @@ static void do_sysreg(struct cpu_user_regs *regs,
union hsr hsr)
{
register_t *x = select_user_reg(regs, hsr.sysreg.reg);
+ register_t addr;
switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
{
@@ -1515,6 +1529,22 @@ static void do_sysreg(struct cpu_user_regs *regs,
domain_crash_synchronous();
}
break;
+ case HSR_SYSREG_ICC_SGI1R_EL1:
+ if ( !vgic_emulate(regs, hsr) )
+ {
+ addr = READ_SYSREG64(FAR_EL2);
+ dprintk(XENLOG_WARNING,
+ "failed emulation of sysreg ICC_SGI1R_EL1 access\n");
+ inject_undef_exception(regs, addr, hsr.len);
+ }
+ break;
+ case HSR_SYSREG_ICC_SGI0R_EL1:
+ case HSR_SYSREG_ICC_ASGI1R_EL1:
+ /* TBD: Implement to support secure grp0/1 SGI forwarding */
+ dprintk(XENLOG_WARNING,
+ "Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not supported\n");
+ addr = READ_SYSREG64(FAR_EL2);
+ inject_undef_exception(regs, addr, hsr.len);
default:
bad_sysreg:
{
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index b116d27..45bb090 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -34,6 +34,10 @@
#include <asm/gic.h>
#include <asm/vgic.h>
+extern int vgic_to_sgi(struct vcpu *v, register_t sgir,
+ enum gic_sgi_mode irqmode, int virq,
+ unsigned long vcpu_mask);
+
static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
uint32_t gicr_reg)
{
@@ -837,6 +841,57 @@ write_ignore_64:
return 1;
}
+static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
+{
+ int virq;
+ int irqmode;
+ enum gic_sgi_mode sgi_mode;
+ unsigned long vcpu_mask = 0;
+
+ irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
+ virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
+ vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
+
+ /* Map GIC sgi value to enum value */
+ switch ( irqmode )
+ {
+ case ICH_SGI_TARGET_LIST:
+ sgi_mode = SGI_TARGET_LIST;
+ break;
+ case ICH_SGI_TARGET_OTHERS:
+ sgi_mode = SGI_TARGET_OTHERS;
+ break;
+ default:
+ BUG();
+ }
+
+ return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
+}
+
+int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
+{
+ struct vcpu *v = current;
+ struct hsr_sysreg sysreg = hsr.sysreg;
+ register_t *r = select_user_reg(regs, sysreg.reg);
+
+ ASSERT (hsr.ec == HSR_EC_SYSREG);
+
+ switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
+ {
+ case HSR_SYSREG_ICC_SGI1R_EL1:
+ /* WO */
+ if ( !sysreg.read )
+ return vgicv3_to_sgi(v, *r);
+ else
+ {
+ gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
+ return 0;
+ }
+ default:
+ return 0;
+ }
+}
+
static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
.read_handler = vgic_v3_rdistr_mmio_read,
.write_handler = vgic_v3_rdistr_mmio_write,
diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h
index b8d2e77..ce7e6b3 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -145,6 +145,13 @@
#define GICH_VMCR_PRIORITY_MASK 0xff
#define GICH_VMCR_PRIORITY_SHIFT 24
+#define ICH_SGI_IRQMODE_SHIFT 40
+#define ICH_SGI_IRQMODE_MASK 0x1
+#define ICH_SGI_TARGET_OTHERS 1
+#define ICH_SGI_TARGET_LIST 0
+#define ICH_SGI_IRQ_SHIFT 24
+#define ICH_SGI_IRQ_MASK 0xf
+#define ICH_SGI_TARGETLIST_MASK 0xffff
#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
/*
diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h
index 4a4de34..5029851 100644
--- a/xen/include/asm-arm/sysregs.h
+++ b/xen/include/asm-arm/sysregs.h
@@ -77,6 +77,9 @@
#define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
#define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0)
#define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0)
+#define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5)
+#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
+#define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7)
#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
#define HSR_SYSREG_PMCR_EL0 HSR_SYSREG(3,3,c9,c12,0)
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index a237f4d..0fa4d86 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -163,6 +163,7 @@ extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq);
extern void vgic_clear_pending_irqs(struct vcpu *v);
extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq);
extern struct vgic_irq_rank *vgic_irq_rank(struct vcpu *v, int b, int n, int s);
+extern int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr);
extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n);
extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n);
extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 20/21] xen/arm: add SGI handling for GICv3
2014-06-12 13:36 ` [PATCH v5 20/21] xen/arm: add SGI handling for GICv3 vijay.kilari
@ 2014-06-12 17:15 ` Stefano Stabellini
2014-06-12 17:23 ` Stefano Stabellini
0 siblings, 1 reply; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 17:15 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
> +{
> + int virq;
> + int irqmode;
> + enum gic_sgi_mode sgi_mode;
> + unsigned long vcpu_mask = 0;
> +
> + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
> + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
> + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
> +
> + /* Map GIC sgi value to enum value */
> + switch ( irqmode )
> + {
> + case ICH_SGI_TARGET_LIST:
> + sgi_mode = SGI_TARGET_LIST;
> + break;
> + case ICH_SGI_TARGET_OTHERS:
> + sgi_mode = SGI_TARGET_OTHERS;
> + break;
> + default:
> + BUG();
If this field can be written by the guest than a BUG is a mistake (a
guest could crash the hypervisor).
> + }
> +
> + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
> +}
> +
> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> +{
> + struct vcpu *v = current;
> + struct hsr_sysreg sysreg = hsr.sysreg;
> + register_t *r = select_user_reg(regs, sysreg.reg);
> +
> + ASSERT (hsr.ec == HSR_EC_SYSREG);
> +
> + switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
> + {
> + case HSR_SYSREG_ICC_SGI1R_EL1:
> + /* WO */
> + if ( !sysreg.read )
> + return vgicv3_to_sgi(v, *r);
> + else
> + {
> + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
> + return 0;
> + }
> + default:
> + return 0;
> + }
> +}
> +
> static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
> .read_handler = vgic_v3_rdistr_mmio_read,
> .write_handler = vgic_v3_rdistr_mmio_write,
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 20/21] xen/arm: add SGI handling for GICv3
2014-06-12 17:15 ` Stefano Stabellini
@ 2014-06-12 17:23 ` Stefano Stabellini
0 siblings, 0 replies; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-12 17:23 UTC (permalink / raw)
To: Stefano Stabellini
Cc: Ian.Campbell, vijay.kilari, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, Stefano Stabellini wrote:
> On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> > +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
> > +{
> > + int virq;
> > + int irqmode;
> > + enum gic_sgi_mode sgi_mode;
> > + unsigned long vcpu_mask = 0;
> > +
> > + irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
> > + virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
> > + vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
> > +
> > + /* Map GIC sgi value to enum value */
> > + switch ( irqmode )
> > + {
> > + case ICH_SGI_TARGET_LIST:
> > + sgi_mode = SGI_TARGET_LIST;
> > + break;
> > + case ICH_SGI_TARGET_OTHERS:
> > + sgi_mode = SGI_TARGET_OTHERS;
> > + break;
> > + default:
> > + BUG();
>
> If this field can be written by the guest than a BUG is a mistake (a
> guest could crash the hypervisor).
>
It would be nice to add a comment to the code like:
/* XXX: ignoring affinity 1, 2, 3 */
> > + }
> > +
> > + return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
> > +}
> > +
> > +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> > +{
> > + struct vcpu *v = current;
> > + struct hsr_sysreg sysreg = hsr.sysreg;
> > + register_t *r = select_user_reg(regs, sysreg.reg);
> > +
> > + ASSERT (hsr.ec == HSR_EC_SYSREG);
> > +
> > + switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
> > + {
> > + case HSR_SYSREG_ICC_SGI1R_EL1:
> > + /* WO */
> > + if ( !sysreg.read )
> > + return vgicv3_to_sgi(v, *r);
> > + else
> > + {
> > + gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
> > + return 0;
> > + }
> > + default:
> > + return 0;
> > + }
> > +}
> > +
> > static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
> > .read_handler = vgic_v3_rdistr_mmio_read,
> > .write_handler = vgic_v3_rdistr_mmio_write,
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* [PATCH v5 21/21] xen/arm: check for GICv3 platform support
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (19 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 20/21] xen/arm: add SGI handling for GICv3 vijay.kilari
@ 2014-06-12 13:36 ` vijay.kilari
2014-06-12 22:51 ` Julien Grall
2014-06-13 15:59 ` [PATCH v5 00/21] xen/arm: Add GICv3 support Stefano Stabellini
2014-06-17 15:39 ` Ian Campbell
22 siblings, 1 reply; 87+ messages in thread
From: vijay.kilari @ 2014-06-12 13:36 UTC (permalink / raw)
To: Ian.Campbell, julien.grall, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, Vijaya Kumar K, vijay.kilari
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
ID_AA64PFR0_EL1 register provides information about GIC support.
Check for this register in GICv3 driver.
Also print GICv3 support information in boot log
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
xen/arch/arm/gic-v3.c | 4 ++++
xen/arch/arm/setup.c | 5 +++--
xen/include/asm-arm/cpufeature.h | 1 +
xen/include/asm-arm/processor.h | 5 ++---
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index d7d53ce..de3f03a 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -38,6 +38,7 @@
#include <asm/device.h>
#include <asm/gic.h>
#include <asm/gic_v3_defs.h>
+#include <asm/cpufeature.h>
struct rdist_region {
paddr_t base;
@@ -1110,6 +1111,9 @@ static int __init gicv3_init(struct dt_device_node *node, const void *data)
int res, i;
uint32_t reg;
+ if ( !cpu_has_gicv3 )
+ panic("Platform does not support GICv3\n");
+
dt_device_set_used_by(node, DOMID_XEN);
res = dt_device_get_address(node, 0, &gicv3.dbase, &gicv3.dbase_size);
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index b9ce7a9..54351aa 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -100,9 +100,10 @@ static void __init processor_id(void)
cpu_has_el2_32 ? "64+32" : cpu_has_el2_64 ? "64" : "No",
cpu_has_el1_32 ? "64+32" : cpu_has_el1_64 ? "64" : "No",
cpu_has_el0_32 ? "64+32" : cpu_has_el0_64 ? "64" : "No");
- printk(" Extensions:%s%s\n",
+ printk(" Extensions:%s%s%s\n",
cpu_has_fp ? " FloatingPoint" : "",
- cpu_has_simd ? " AdvancedSIMD" : "");
+ cpu_has_simd ? " AdvancedSIMD" : "",
+ cpu_has_gicv3 ? " GICv3" : "");
printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h
index 1d2c9c7..bd84c57 100644
--- a/xen/include/asm-arm/cpufeature.h
+++ b/xen/include/asm-arm/cpufeature.h
@@ -15,6 +15,7 @@
#define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1)
#define cpu_has_fp (boot_cpu_feature64(fp) == 0)
#define cpu_has_simd (boot_cpu_feature64(simd) == 0)
+#define cpu_has_gicv3 (boot_cpu_feature64(gicv3) == 1)
#endif
#define cpu_feature32(c, feat) ((c)->pfr32.feat)
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 5978b8a..2bad30e 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -188,9 +188,8 @@ struct cpuinfo_arm {
unsigned long el3:4;
unsigned long fp:4; /* Floating Point */
unsigned long simd:4; /* Advanced SIMD */
- unsigned long __res0:8;
-
- unsigned long __res1;
+ unsigned long gicv3:4; /* GIC support */
+ unsigned long __res0:36;
};
} pfr64;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 87+ messages in thread* Re: [PATCH v5 21/21] xen/arm: check for GICv3 platform support
2014-06-12 13:36 ` [PATCH v5 21/21] xen/arm: check for GICv3 platform support vijay.kilari
@ 2014-06-12 22:51 ` Julien Grall
2014-06-16 15:28 ` Vijay Kilari
0 siblings, 1 reply; 87+ messages in thread
From: Julien Grall @ 2014-06-12 22:51 UTC (permalink / raw)
To: vijay.kilari, Ian.Campbell, stefano.stabellini,
stefano.stabellini, tim, xen-devel
Cc: Prasun.Kapoor, vijaya.kumar
Hi Vijay,
On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> ID_AA64PFR0_EL1 register provides information about GIC support.
> Check for this register in GICv3 driver.
>
> Also print GICv3 support information in boot log
We already have a GICv3 node in the device tree. Why do we need to check
that GICv3 is effectively support by board?
We rely on the user provide us a correct device tree, so I don't think
this patch is helpful...
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 21/21] xen/arm: check for GICv3 platform support
2014-06-12 22:51 ` Julien Grall
@ 2014-06-16 15:28 ` Vijay Kilari
2014-06-16 15:37 ` Julien Grall
0 siblings, 1 reply; 87+ messages in thread
From: Vijay Kilari @ 2014-06-16 15:28 UTC (permalink / raw)
To: Julien Grall
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On Fri, Jun 13, 2014 at 4:21 AM, Julien Grall <julien.grall@linaro.org> wrote:
> Hi Vijay,
>
>
> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
>>
>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>
>> ID_AA64PFR0_EL1 register provides information about GIC support.
>> Check for this register in GICv3 driver.
>>
>> Also print GICv3 support information in boot log
>
>
> We already have a GICv3 node in the device tree. Why do we need to check
> that GICv3 is effectively support by board?
>
> We rely on the user provide us a correct device tree, so I don't think this
> patch is helpful...
GICv3 driver is compiled for arm64 alone. Assume that platform does not support
GICv3 and DT is passed with GICv3 info. In such scenario this patch helps.
However, still first part of patch where in printing the platform
support for GICv3 still valid.
>
> Regards,
>
> --
> Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 21/21] xen/arm: check for GICv3 platform support
2014-06-16 15:28 ` Vijay Kilari
@ 2014-06-16 15:37 ` Julien Grall
2014-06-16 15:43 ` Ian Campbell
0 siblings, 1 reply; 87+ messages in thread
From: Julien Grall @ 2014-06-16 15:37 UTC (permalink / raw)
To: Vijay Kilari
Cc: Ian Campbell, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On 06/16/2014 04:28 PM, Vijay Kilari wrote:
> On Fri, Jun 13, 2014 at 4:21 AM, Julien Grall <julien.grall@linaro.org> wrote:
>> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
>>>
>>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>>
>>> ID_AA64PFR0_EL1 register provides information about GIC support.
>>> Check for this register in GICv3 driver.
>>>
>>> Also print GICv3 support information in boot log
>>
>>
>> We already have a GICv3 node in the device tree. Why do we need to check
>> that GICv3 is effectively support by board?
>>
>> We rely on the user provide us a correct device tree, so I don't think this
>> patch is helpful...
>
> GICv3 driver is compiled for arm64 alone. Assume that platform does not support
> GICv3 and DT is passed with GICv3 info. In such scenario this patch helps.
I think this is pointless, lots of things (worst than trying to poke a
GICv3 on a GICv2 platform) can happen on Xen and Linux if the user fails
to give a valid device tree.
IHMO, it's safe to assume that the user will provide a device tree with
valid devices...
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 21/21] xen/arm: check for GICv3 platform support
2014-06-16 15:37 ` Julien Grall
@ 2014-06-16 15:43 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-16 15:43 UTC (permalink / raw)
To: Julien Grall
Cc: Vijay Kilari, Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K,
Tim Deegan, xen-devel, Stefano Stabellini
On Mon, 2014-06-16 at 16:37 +0100, Julien Grall wrote:
> On 06/16/2014 04:28 PM, Vijay Kilari wrote:
> > On Fri, Jun 13, 2014 at 4:21 AM, Julien Grall <julien.grall@linaro.org> wrote:
> >> On 12/06/14 14:36, vijay.kilari@gmail.com wrote:
> >>>
> >>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >>>
> >>> ID_AA64PFR0_EL1 register provides information about GIC support.
> >>> Check for this register in GICv3 driver.
> >>>
> >>> Also print GICv3 support information in boot log
> >>
> >>
> >> We already have a GICv3 node in the device tree. Why do we need to check
> >> that GICv3 is effectively support by board?
> >>
> >> We rely on the user provide us a correct device tree, so I don't think this
> >> patch is helpful...
> >
> > GICv3 driver is compiled for arm64 alone. Assume that platform does not support
> > GICv3 and DT is passed with GICv3 info. In such scenario this patch helps.
>
> I think this is pointless, lots of things (worst than trying to poke a
> GICv3 on a GICv2 platform) can happen on Xen and Linux if the user fails
> to give a valid device tree.
>
> IHMO, it's safe to assume that the user will provide a device tree with
> valid devices...
Given that Vijay has already written the code and that it's pretty
unintrusive it seems like there is no downside to having a meaningful
error message if gicv3 isn't present.
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 00/21] xen/arm: Add GICv3 support
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (20 preceding siblings ...)
2014-06-12 13:36 ` [PATCH v5 21/21] xen/arm: check for GICv3 platform support vijay.kilari
@ 2014-06-13 15:59 ` Stefano Stabellini
2014-06-13 16:15 ` Julien Grall
2014-06-17 15:39 ` Ian Campbell
22 siblings, 1 reply; 87+ messages in thread
From: Stefano Stabellini @ 2014-06-13 15:59 UTC (permalink / raw)
To: vijay.kilari
Cc: Ian.Campbell, stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K,
julien.grall, tim, xen-devel, stefano.stabellini
On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Made changes to existing gic and vgic drivers
> to make it generic and added support for GIC v3
> hw version
>
> Tested with ARM64 simulator with multicore core
> and booted Dom0 kernel.
FYI I tested this series on Midway and it doesn't introduce any
regressions.
> Major changes in v5:
> - Introduced new patch for checking platform capability for gicv3
> - Introduced more patches for vgic clean up and code movement
> - Added synchronization barriers and clean up in GICv3 driver
> - Rebase on top of master branch +
> remotes/origin/no_maintenance_interrupts-v8 patch set
> - Code base available in github
> git clone https://github.com/vijaykilari/Xen-GICv3.git
> - Fixed comments and coding style
>
> Major changes in v4:
> - Changed io handlers to take mmio address and size as
> parameters
> - ioremap is used instead of fixmap to map GICv2 address
> space. Removed /4 in GICv2 register definitions
> - vGIC driver now uses register size to calculate IRQ rank
> - GICv2 LR register definitions are declared locally in GICv2 driver
> - GICR & GICD common register handling in vgic-v3 driver are segregated
> in one common function
> - irq_hw_controller definition is managed in GICv2 and GICv3 drivers
> - Made irq_ops const
> - GIC DT node is updated in respective drivers
> - Comments and coding style fixes
> - Rebased on remotes/origin/no_maintenance_interrupts-v8 + Julien's
> patch set
>
> Major changes in v3:
> - Moved io.h from xen/arch/arm to xen/include/asm-arm
> and renamed as mmio.h
> - Made all the io handlers as domain specific and removed
> check handlers. Instead address and size are passed
> - Cleaned up sgi handling functions in V2 gic driver and
> made generic
> - Removed unused parameters in do_sgi call
> - VGIC driver is chosen based on GIC driver initialized
> - Implemented SGI handling for GICv3 to boot multicore
> - Missing coding style fixes
> - Rebased to remotes/origin/no_maintenance_interrupts-v6
> branch of Stephano's unstable tree
>
> Major Changes in v2:
> - Added per domain io handler
> - Use device api to initialize gic driver
> - Avoid use of void pointer to access common data
> - Moved vgic address information data from domain.h
> - Coding style
>
> Vijaya Kumar K (21):
> xen/arm: move io.h as mmio.h to include folder
> xen/arm: make mmio handlers domain specific
> xen/arm: make sgi handling generic
> xen/arm: remove unused parameter in do_sgi call
> xen/arm: use ioremap to map gic-v2 registers
> xen/arm: segregate and split GIC low level functionality
> arm/xen: move GIC context data structure to gic driver
> xen/arm: use device api to detect GIC version
> xen/arm: move vgic rank data to gic header file
> xen/arm: move vgic defines to vgic header file
> xen/arm: prefix byte_read and byte_write functions with vgic
> xen/arm: move is_vcpu_running function to sched.h
> xen/arm: move pending_irq structure to vgic header file
> xen/arm: calculate vgic irq rank based on register size
> xen/arm: Remove REG macro in vgic driver
> xen/arm: split vgic driver into generic and vgic-v2 driver
> xen/arm: Add support for GIC v3
> xen/arm: Add virtual GICv3 support
> xen/arm: Update Dom0 GIC dt node with GICv3 information
> xen/arm: add SGI handling for GICv3
> xen/arm: check for GICv3 platform support
>
> xen/arch/arm/Makefile | 6 +-
> xen/arch/arm/domain.c | 5 +
> xen/arch/arm/domain_build.c | 49 +-
> xen/arch/arm/gic-v2.c | 725 +++++++++++++++
> xen/arch/arm/gic-v3.c | 1234 +++++++++++++++++++++++++
> xen/arch/arm/gic.c | 537 ++---------
> xen/arch/arm/io.c | 59 +-
> xen/arch/arm/irq.c | 1 +
> xen/arch/arm/setup.c | 5 +-
> xen/arch/arm/time.c | 1 +
> xen/arch/arm/traps.c | 32 +-
> xen/arch/arm/vgic-v2.c | 510 ++++++++++
> xen/arch/arm/vgic-v3.c | 959 +++++++++++++++++++
> xen/arch/arm/vgic.c | 574 ++----------
> xen/arch/arm/vpsci.c | 1 +
> xen/arch/arm/vtimer.c | 1 +
> xen/arch/arm/vuart.c | 28 +-
> xen/include/asm-arm/cpufeature.h | 1 +
> xen/include/asm-arm/device.h | 1 +
> xen/include/asm-arm/domain.h | 85 +-
> xen/include/asm-arm/gic.h | 274 ++++--
> xen/include/asm-arm/gic_v3_defs.h | 164 ++++
> xen/{arch/arm/io.h => include/asm-arm/mmio.h} | 30 +-
> xen/include/asm-arm/processor.h | 27 +-
> xen/include/asm-arm/sysregs.h | 3 +
> xen/include/asm-arm/vgic.h | 183 ++++
> xen/include/xen/lib.h | 2 +
> xen/include/xen/sched.h | 16 +
> 28 files changed, 4322 insertions(+), 1191 deletions(-)
> create mode 100644 xen/arch/arm/gic-v2.c
> create mode 100644 xen/arch/arm/gic-v3.c
> create mode 100644 xen/arch/arm/vgic-v2.c
> create mode 100644 xen/arch/arm/vgic-v3.c
> create mode 100644 xen/include/asm-arm/gic_v3_defs.h
> rename xen/{arch/arm/io.h => include/asm-arm/mmio.h} (66%)
> create mode 100644 xen/include/asm-arm/vgic.h
>
> --
> 1.7.9.5
>
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 00/21] xen/arm: Add GICv3 support
2014-06-13 15:59 ` [PATCH v5 00/21] xen/arm: Add GICv3 support Stefano Stabellini
@ 2014-06-13 16:15 ` Julien Grall
0 siblings, 0 replies; 87+ messages in thread
From: Julien Grall @ 2014-06-13 16:15 UTC (permalink / raw)
To: Stefano Stabellini, vijay.kilari
Cc: Ian.Campbell, Prasun.Kapoor, Vijaya Kumar K, tim, xen-devel,
stefano.stabellini
On 13/06/14 16:59, Stefano Stabellini wrote:
> On Thu, 12 Jun 2014, vijay.kilari@gmail.com wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>
>> Made changes to existing gic and vgic drivers
>> to make it generic and added support for GIC v3
>> hw version
>>
>> Tested with ARM64 simulator with multicore core
>> and booted Dom0 kernel.
>
> FYI I tested this series on Midway and it doesn't introduce any
> regressions.
Thanks for testing this series on GICv2! I was planning to do it later,
I won't need to do now :).
Regards,
--
Julien Grall
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 00/21] xen/arm: Add GICv3 support
2014-06-12 13:36 [PATCH v5 00/21] xen/arm: Add GICv3 support vijay.kilari
` (21 preceding siblings ...)
2014-06-13 15:59 ` [PATCH v5 00/21] xen/arm: Add GICv3 support Stefano Stabellini
@ 2014-06-17 15:39 ` Ian Campbell
2014-06-18 3:43 ` Vijay Kilari
22 siblings, 1 reply; 87+ messages in thread
From: Ian Campbell @ 2014-06-17 15:39 UTC (permalink / raw)
To: vijay.kilari
Cc: stefano.stabellini, Prasun.Kapoor, Vijaya Kumar K, julien.grall,
tim, xen-devel, stefano.stabellini
On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>
> Made changes to existing gic and vgic drivers
> to make it generic and added support for GIC v3
> hw version
I've just been through patches 1..15 and with the exception of #12 it
seems to me that they are all either acked or have mostly minor
comments. From 16 onwards it seems like we are getting more into the
meat of v3 support and there are still some substantive comments
(although I've not looked closely to see how substantive).
With that in mind perhaps you'd like to address the comments on 1..15
and repost "v6a" with just those precursor/cleanup/refactoring patches? That
way we can get them in and reduce the size of your outstanding work
pretty substantially, which I hope would make stuff easier for you going
forward, since I bet all that code motion is a real pain to rebase...
OTOH I'm out of the office Thursday-Monday inclusive so unless you think
you will have this stuff ready before tomorrow early afternoon (BST, to
give me time to commit) then there is no rush. Or if on Tuesday you've
got the stuff up to #15 ready to repost you might as well go ahead with
it.
Cheers,
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread* Re: [PATCH v5 00/21] xen/arm: Add GICv3 support
2014-06-17 15:39 ` Ian Campbell
@ 2014-06-18 3:43 ` Vijay Kilari
2014-06-18 10:37 ` Ian Campbell
0 siblings, 1 reply; 87+ messages in thread
From: Vijay Kilari @ 2014-06-18 3:43 UTC (permalink / raw)
To: Ian Campbell
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel, Stefano Stabellini
On Tue, Jun 17, 2014 at 9:09 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
>
> On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
>>
>> Made changes to existing gic and vgic drivers
>> to make it generic and added support for GIC v3
>> hw version
>
> I've just been through patches 1..15 and with the exception of #12 it
> seems to me that they are all either acked or have mostly minor
> comments. From 16 onwards it seems like we are getting more into the
> meat of v3 support and there are still some substantive comments
> (although I've not looked closely to see how substantive).
>
> With that in mind perhaps you'd like to address the comments on 1..15
> and repost "v6a" with just those precursor/cleanup/refactoring patches? That
> way we can get them in and reduce the size of your outstanding work
> pretty substantially, which I hope would make stuff easier for you going
> forward, since I bet all that code motion is a real pain to rebase...
>
My patch series is based on Stefano's 'no_maintenance_interrupts' v8.
So before you take my patches, Stefano's patches should be merged
> OTOH I'm out of the office Thursday-Monday inclusive so unless you think
> you will have this stuff ready before tomorrow early afternoon (BST, to
> give me time to commit) then there is no rush. Or if on Tuesday you've
> got the stuff up to #15 ready to repost you might as well go ahead with
> it.
I think it may not be possible for me to do it by tomorrow. I have to
rebase and commit my changes on top of Stefano's v9 version.
>
> Cheers,
> Ian.
>
>
>
^ permalink raw reply [flat|nested] 87+ messages in thread
* Re: [PATCH v5 00/21] xen/arm: Add GICv3 support
2014-06-18 3:43 ` Vijay Kilari
@ 2014-06-18 10:37 ` Ian Campbell
0 siblings, 0 replies; 87+ messages in thread
From: Ian Campbell @ 2014-06-18 10:37 UTC (permalink / raw)
To: Vijay Kilari
Cc: Stefano Stabellini, Prasun Kapoor, Vijaya Kumar K, Julien Grall,
Tim Deegan, xen-devel, Stefano Stabellini
On Wed, 2014-06-18 at 09:13 +0530, Vijay Kilari wrote:
> On Tue, Jun 17, 2014 at 9:09 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:
> >
> > On Thu, 2014-06-12 at 19:06 +0530, vijay.kilari@gmail.com wrote:
> >> From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
> >>
> >> Made changes to existing gic and vgic drivers
> >> to make it generic and added support for GIC v3
> >> hw version
> >
> > I've just been through patches 1..15 and with the exception of #12 it
> > seems to me that they are all either acked or have mostly minor
> > comments. From 16 onwards it seems like we are getting more into the
> > meat of v3 support and there are still some substantive comments
> > (although I've not looked closely to see how substantive).
> >
> > With that in mind perhaps you'd like to address the comments on 1..15
> > and repost "v6a" with just those precursor/cleanup/refactoring patches? That
> > way we can get them in and reduce the size of your outstanding work
> > pretty substantially, which I hope would make stuff easier for you going
> > forward, since I bet all that code motion is a real pain to rebase...
> >
>
> My patch series is based on Stefano's 'no_maintenance_interrupts' v8.
> So before you take my patches, Stefano's patches should be merged
Ah, OK, I'd forgotten this dependency.
I've just committed Stefano's patches (v9) so hopefully that will help a bit.
> > OTOH I'm out of the office Thursday-Monday inclusive so unless you think
> > you will have this stuff ready before tomorrow early afternoon (BST, to
> > give me time to commit) then there is no rush. Or if on Tuesday you've
> > got the stuff up to #15 ready to repost you might as well go ahead with
> > it.
>
> I think it may not be possible for me to do it by tomorrow. I have to
> rebase and commit my changes on top of Stefano's v9 version.
Sure, no problem.
Ian.
^ permalink raw reply [flat|nested] 87+ messages in thread