[PATCH 0/1] Wa_1604555607 implementation and verification skip

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* [PATCH 0/1] Wa_1604555607 implementation and verification skip
@ 2019-11-22  4:02 ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-22  4:02 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson

Implements the Wa_1604555607 and skips its verification as the FF_MODE2
register is write only till TGL B0.

Michel Thierry (1):
  drm/i915/tgl: Implement Wa_1604555607

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 34 insertions(+), 4 deletions(-)

-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH 0/1] Wa_1604555607 implementation and verification skip
@ 2019-11-22  4:02 ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-22  4:02 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson

Implements the Wa_1604555607 and skips its verification as the FF_MODE2
register is write only till TGL B0.

Michel Thierry (1):
  drm/i915/tgl: Implement Wa_1604555607

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 34 insertions(+), 4 deletions(-)

-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  4:02   ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-22  4:02 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson; +Cc: Michel Thierry

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]
v6:
  __wa_write_masked_or used with varying parameter [Tvrtko]
  Added wa_add as a wrapper for __wa_add [Chris]
v7:
  WA verification is skipped on all stepping as of now [Lucas]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5]
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..b11540caa92d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 	}
 }
 
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
+{
+	wa_add(wal, reg, mask, val, read_mask);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	/*
+	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
+	 * enable verification of WA from the later steppings, which enables
+	 * the read of FF_MODE2.
+	 */
+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  4:02   ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-22  4:02 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson; +Cc: Michel Thierry

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]
v6:
  __wa_write_masked_or used with varying parameter [Tvrtko]
  Added wa_add as a wrapper for __wa_add [Chris]
v7:
  WA verification is skipped on all stepping as of now [Lucas]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5]
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..b11540caa92d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 	}
 }
 
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
+{
+	wa_add(wal, reg, mask, val, read_mask);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	/*
+	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
+	 * enable verification of WA from the later steppings, which enables
+	 * the read of FF_MODE2.
+	 */
+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  9:21     ` Tvrtko Ursulin
  0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-11-22  9:21 UTC (permalink / raw)
  To: Ramalingam C, intel-gfx, Chris Wilson; +Cc: Michel Thierry


On 22/11/2019 04:02, Ramalingam C wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>    uncore read is used [Tvrtko]
>    Macros as used for MASK definition [Chris]
> v5:
>    Skip the Wa_1604555607 verification [Ram]
>    i915 ptr retrieved from engine. [Tvrtko]
> v6:
>    __wa_write_masked_or used with varying parameter [Tvrtko]
>    Added wa_add as a wrapper for __wa_add [Chris]
> v7:
>    WA verification is skipped on all stepping as of now [Lucas]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5]
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h             |  4 +++
>   2 files changed, 34 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..b11540caa92d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>   	}
>   }
>   
> -static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -		   u32 val)
> +static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val, u32 read_mask)
>   {
>   	struct i915_wa wa = {
>   		.reg  = reg,
>   		.mask = mask,
>   		.val  = val,
> -		.read = mask,
> +		.read = read_mask,
>   	};
>   
>   	_wa_add(wal, &wa);
>   }
>   
> +static void
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		     u32 val, u32 read_mask)
> +{
> +	wa_add(wal, reg, mask, val, read_mask);
> +}
> +
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val)
> +{
> +	__wa_write_masked_or(wal, reg, mask, val, mask);

Minor point - not sure about the need for this helper now, you could 
just call wa_add from here.

> +}
> +
>   static void
>   wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>   {
> @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> +	u32 val;
> +
>   	/* Wa_1409142259:tgl */
>   	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>   			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +	/* Wa_1604555607:tgl */
> +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> +	val |= FF_MODE2_TDS_TIMER_128;
> +	/*
> +	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> +	 * enable verification of WA from the later steppings, which enables
> +	 * the read of FF_MODE2.
> +	 */
> +	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);

If I was a betting man I'd bet no one will ever remember to add the 
verification back. So I have to say I disagree with Lucas on this point. 
Someone do a casting vote please. :)

We know it will remain broken until at least after B0?

>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94d0f593eeb7..a99fdf8ea53b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7922,6 +7922,10 @@ enum {
>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>   #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>   
> +#define FF_MODE2			_MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
> +#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
>   /* PCH */
>   
>   #define PCH_DISPLAY_BASE	0xc0000u
> 

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  9:21     ` Tvrtko Ursulin
  0 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-11-22  9:21 UTC (permalink / raw)
  To: Ramalingam C, intel-gfx, Chris Wilson; +Cc: Michel Thierry


On 22/11/2019 04:02, Ramalingam C wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>    uncore read is used [Tvrtko]
>    Macros as used for MASK definition [Chris]
> v5:
>    Skip the Wa_1604555607 verification [Ram]
>    i915 ptr retrieved from engine. [Tvrtko]
> v6:
>    __wa_write_masked_or used with varying parameter [Tvrtko]
>    Added wa_add as a wrapper for __wa_add [Chris]
> v7:
>    WA verification is skipped on all stepping as of now [Lucas]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> [v5]
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 ++++++++++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h             |  4 +++
>   2 files changed, 34 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..b11540caa92d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>   	}
>   }
>   
> -static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -		   u32 val)
> +static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val, u32 read_mask)
>   {
>   	struct i915_wa wa = {
>   		.reg  = reg,
>   		.mask = mask,
>   		.val  = val,
> -		.read = mask,
> +		.read = read_mask,
>   	};
>   
>   	_wa_add(wal, &wa);
>   }
>   
> +static void
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		     u32 val, u32 read_mask)
> +{
> +	wa_add(wal, reg, mask, val, read_mask);
> +}
> +
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val)
> +{
> +	__wa_write_masked_or(wal, reg, mask, val, mask);

Minor point - not sure about the need for this helper now, you could 
just call wa_add from here.

> +}
> +
>   static void
>   wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>   {
> @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> +	u32 val;
> +
>   	/* Wa_1409142259:tgl */
>   	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>   			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +	/* Wa_1604555607:tgl */
> +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> +	val |= FF_MODE2_TDS_TIMER_128;
> +	/*
> +	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> +	 * enable verification of WA from the later steppings, which enables
> +	 * the read of FF_MODE2.
> +	 */
> +	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);

If I was a betting man I'd bet no one will ever remember to add the 
verification back. So I have to say I disagree with Lucas on this point. 
Someone do a casting vote please. :)

We know it will remain broken until at least after B0?

>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94d0f593eeb7..a99fdf8ea53b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7922,6 +7922,10 @@ enum {
>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>   #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>   
> +#define FF_MODE2			_MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
> +#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
>   /* PCH */
>   
>   #define PCH_DISPLAY_BASE	0xc0000u
> 

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  9:29       ` Chris Wilson
  0 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2019-11-22  9:29 UTC (permalink / raw)
  To: Ramalingam C, Tvrtko Ursulin, intel-gfx; +Cc: Michel Thierry

Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> 
> On 22/11/2019 04:02, Ramalingam C wrote:
> > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                                    struct i915_wa_list *wal)
> >   {
> > +     u32 val;
> > +
> >       /* Wa_1409142259:tgl */
> >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > +     /* Wa_1604555607:tgl */
> > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +     val |= FF_MODE2_TDS_TIMER_128;
> > +     /*
> > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > +      * enable verification of WA from the later steppings, which enables
> > +      * the read of FF_MODE2.
> > +      */
> > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> 
> If I was a betting man I'd bet no one will ever remember to add the 
> verification back. So I have to say I disagree with Lucas on this point. 
> Someone do a casting vote please. :)

I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by
the selftests if we have a new stepping that is unfixed -- and a blip in
CI is a much clearer reminder to come back and revisit this code. We
should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
and from there find this fixme. And so update for a new stepping in the
course of a day (because that's how long it takes for CI to approve a
patch).
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-22  9:29       ` Chris Wilson
  0 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2019-11-22  9:29 UTC (permalink / raw)
  To: Ramalingam C, Tvrtko Ursulin, intel-gfx; +Cc: Michel Thierry

Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> 
> On 22/11/2019 04:02, Ramalingam C wrote:
> > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                                    struct i915_wa_list *wal)
> >   {
> > +     u32 val;
> > +
> >       /* Wa_1409142259:tgl */
> >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > +     /* Wa_1604555607:tgl */
> > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +     val |= FF_MODE2_TDS_TIMER_128;
> > +     /*
> > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > +      * enable verification of WA from the later steppings, which enables
> > +      * the read of FF_MODE2.
> > +      */
> > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> 
> If I was a betting man I'd bet no one will ever remember to add the 
> verification back. So I have to say I disagree with Lucas on this point. 
> Someone do a casting vote please. :)

I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by
the selftests if we have a new stepping that is unfixed -- and a blip in
CI is a much clearer reminder to come back and revisit this code. We
should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
and from there find this fixme. And so update for a new stepping in the
course of a day (because that's how long it takes for CI to approve a
patch).
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-26  8:00         ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-26  8:00 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On 2019-11-22 at 09:29:43 +0000, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> > 
> > On 22/11/2019 04:02, Ramalingam C wrote:
> > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                    struct i915_wa_list *wal)
> > >   {
> > > +     u32 val;
> > > +
> > >       /* Wa_1409142259:tgl */
> > >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +     /* Wa_1604555607:tgl */
> > > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +     val |= FF_MODE2_TDS_TIMER_128;
> > > +     /*
> > > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > > +      * enable verification of WA from the later steppings, which enables
> > > +      * the read of FF_MODE2.
> > > +      */
> > > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> > 
> > If I was a betting man I'd bet no one will ever remember to add the 
> > verification back. So I have to say I disagree with Lucas on this point. 
> > Someone do a casting vote please. :)
> 
> I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by
> the selftests if we have a new stepping that is unfixed -- and a blip in
> CI is a much clearer reminder to come back and revisit this code. We
> should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
> and from there find this fixme. And so update for a new stepping in the
> course of a day (because that's how long it takes for CI to approve a
> patch).
Tvrtko and Chris,

So I take it as, we want to exclude the WA verification for the current
steppings alone that is A0 alone, when new stepping comes with
readability broken then we will excude the verification at that time.

Shall I revert to the previous version of patch, just to exclude the WA
verification for A0 alone.?

-Ram
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-26  8:00         ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-26  8:00 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On 2019-11-22 at 09:29:43 +0000, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> > 
> > On 22/11/2019 04:02, Ramalingam C wrote:
> > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                    struct i915_wa_list *wal)
> > >   {
> > > +     u32 val;
> > > +
> > >       /* Wa_1409142259:tgl */
> > >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +     /* Wa_1604555607:tgl */
> > > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +     val |= FF_MODE2_TDS_TIMER_128;
> > > +     /*
> > > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > > +      * enable verification of WA from the later steppings, which enables
> > > +      * the read of FF_MODE2.
> > > +      */
> > > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> > 
> > If I was a betting man I'd bet no one will ever remember to add the 
> > verification back. So I have to say I disagree with Lucas on this point. 
> > Someone do a casting vote please. :)
> 
> I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by
> the selftests if we have a new stepping that is unfixed -- and a blip in
> CI is a much clearer reminder to come back and revisit this code. We
> should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
> and from there find this fixme. And so update for a new stepping in the
> course of a day (because that's how long it takes for CI to approve a
> patch).
Tvrtko and Chris,

So I take it as, we want to exclude the WA verification for the current
steppings alone that is A0 alone, when new stepping comes with
readability broken then we will excude the verification at that time.

Shall I revert to the previous version of patch, just to exclude the WA
verification for A0 alone.?

-Ram
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-26  9:38         ` Lucas De Marchi
  0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2019-11-26  9:38 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On Fri, Nov 22, 2019 at 1:30 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> >
> > On 22/11/2019 04:02, Ramalingam C wrote:
> > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                    struct i915_wa_list *wal)
> > >   {
> > > +     u32 val;
> > > +
> > >       /* Wa_1409142259:tgl */
> > >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +     /* Wa_1604555607:tgl */
> > > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +     val |= FF_MODE2_TDS_TIMER_128;
> > > +     /*
> > > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > > +      * enable verification of WA from the later steppings, which enables
> > > +      * the read of FF_MODE2.
> > > +      */
> > > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> >
> > If I was a betting man I'd bet no one will ever remember to add the
> > verification back. So I have to say I disagree with Lucas on this point.
> > Someone do a casting vote please. :)
>
> I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by

then it is broken from start? In A2 it's not fixed yet.... not sure if
CI has A2.
But we should add at least A2 and A3 and make it pass on these.


Lucas De Marchi

> the selftests if we have a new stepping that is unfixed -- and a blip in
> CI is a much clearer reminder to come back and revisit this code. We
> should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
> and from there find this fixme. And so update for a new stepping in the
> course of a day (because that's how long it takes for CI to approve a
> patch).
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-26  9:38         ` Lucas De Marchi
  0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2019-11-26  9:38 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On Fri, Nov 22, 2019 at 1:30 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> >
> > On 22/11/2019 04:02, Ramalingam C wrote:
> > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > >                                    struct i915_wa_list *wal)
> > >   {
> > > +     u32 val;
> > > +
> > >       /* Wa_1409142259:tgl */
> > >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > +
> > > +     /* Wa_1604555607:tgl */
> > > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > +     val |= FF_MODE2_TDS_TIMER_128;
> > > +     /*
> > > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > > +      * enable verification of WA from the later steppings, which enables
> > > +      * the read of FF_MODE2.
> > > +      */
> > > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> >
> > If I was a betting man I'd bet no one will ever remember to add the
> > verification back. So I have to say I disagree with Lucas on this point.
> > Someone do a casting vote please. :)
>
> I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by

then it is broken from start? In A2 it's not fixed yet.... not sure if
CI has A2.
But we should add at least A2 and A3 and make it pass on these.


Lucas De Marchi

> the selftests if we have a new stepping that is unfixed -- and a blip in
> CI is a much clearer reminder to come back and revisit this code. We
> should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
> and from there find this fixme. And so update for a new stepping in the
> course of a day (because that's how long it takes for CI to approve a
> patch).
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-26 10:10           ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-26 10:10 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: Michel Thierry, intel-gfx

On 2019-11-26 at 01:38:20 -0800, Lucas De Marchi wrote:
> On Fri, Nov 22, 2019 at 1:30 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> > >
> > > On 22/11/2019 04:02, Ramalingam C wrote:
> > > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > >                                    struct i915_wa_list *wal)
> > > >   {
> > > > +     u32 val;
> > > > +
> > > >       /* Wa_1409142259:tgl */
> > > >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > > >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > > +
> > > > +     /* Wa_1604555607:tgl */
> > > > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > > > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > > +     val |= FF_MODE2_TDS_TIMER_128;
> > > > +     /*
> > > > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > > > +      * enable verification of WA from the later steppings, which enables
> > > > +      * the read of FF_MODE2.
> > > > +      */
> > > > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> > >
> > > If I was a betting man I'd bet no one will ever remember to add the
> > > verification back. So I have to say I disagree with Lucas on this point.
> > > Someone do a casting vote please. :)
> >
> > I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by
> 
> then it is broken from start? In A2 it's not fixed yet.... not sure if
> CI has A2.
> But we should add at least A2 and A3 and make it pass on these.
Lucas,

How to get the revision details for this A2 and A3 stepping? pointers
plz...

-Ram
> 
> 
> Lucas De Marchi
> 
> > the selftests if we have a new stepping that is unfixed -- and a blip in
> > CI is a much clearer reminder to come back and revisit this code. We
> > should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
> > and from there find this fixme. And so update for a new stepping in the
> > course of a day (because that's how long it takes for CI to approve a
> > patch).
> > -Chris
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [Intel-gfx] [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
@ 2019-11-26 10:10           ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-26 10:10 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: Michel Thierry, intel-gfx

On 2019-11-26 at 01:38:20 -0800, Lucas De Marchi wrote:
> On Fri, Nov 22, 2019 at 1:30 AM Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Quoting Tvrtko Ursulin (2019-11-22 09:21:45)
> > >
> > > On 22/11/2019 04:02, Ramalingam C wrote:
> > > > @@ -568,9 +581,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > >   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > >                                    struct i915_wa_list *wal)
> > > >   {
> > > > +     u32 val;
> > > > +
> > > >       /* Wa_1409142259:tgl */
> > > >       WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> > > >                         GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > > > +
> > > > +     /* Wa_1604555607:tgl */
> > > > +     val = intel_uncore_read(engine->uncore, FF_MODE2);
> > > > +     val &= ~FF_MODE2_TDS_TIMER_MASK;
> > > > +     val |= FF_MODE2_TDS_TIMER_128;
> > > > +     /*
> > > > +      * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > > > +      * enable verification of WA from the later steppings, which enables
> > > > +      * the read of FF_MODE2.
> > > > +      */
> > > > +     __wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, 0);
> > >
> > > If I was a betting man I'd bet no one will ever remember to add the
> > > verification back. So I have to say I disagree with Lucas on this point.
> > > Someone do a casting vote please. :)
> >
> > I would go with IS_TGL_REVID(A0, A0) as we expect it to be picked up by
> 
> then it is broken from start? In A2 it's not fixed yet.... not sure if
> CI has A2.
> But we should add at least A2 and A3 and make it pass on these.
Lucas,

How to get the revision details for this A2 and A3 stepping? pointers
plz...

-Ram
> 
> 
> Lucas De Marchi
> 
> > the selftests if we have a new stepping that is unfixed -- and a blip in
> > CI is a much clearer reminder to come back and revisit this code. We
> > should be able to go "oops, live_workarounds is red, failing on ctx:0xf00"
> > and from there find this fixme. And so update for a new stepping in the
> > course of a day (because that's how long it takes for CI to approve a
> > patch).
> > -Chris
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* ✓ Fi.CI.BAT: success for Wa_1604555607 implementation and verification skip (rev6)
@ 2019-11-22  4:46   ` Patchwork
  0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-22  4:46 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev6)
URL   : https://patchwork.freedesktop.org/series/69763/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7402 -> Patchwork_15387
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/index.html

Known issues
------------

  Here are the changes found in Patchwork_15387 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][1] -> [FAIL][2] ([fdo#111045] / [fdo#111096])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][3] ([fdo#103167]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u2:          [DMESG-WARN][5] ([fdo#110595]) -> [DMESG-WARN][6] ([fdo#106107] / [fdo#110595])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/fi-icl-u2/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/fi-icl-u2/igt@i915_pm_rpm@module-reload.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096


Participating hosts (50 -> 44)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7402 -> Patchwork_15387

  CI-20190529: 20190529
  CI_DRM_7402: d5f0845c4b92c5826d63b76f89866492e0935c1b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15387: 51b2b890786477d1b4d45715bddfa37272bb8848 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

51b2b8907864 drm/i915/tgl: Implement Wa_1604555607

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Wa_1604555607 implementation and verification skip (rev6)
@ 2019-11-22  4:46   ` Patchwork
  0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-22  4:46 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev6)
URL   : https://patchwork.freedesktop.org/series/69763/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7402 -> Patchwork_15387
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/index.html

Known issues
------------

  Here are the changes found in Patchwork_15387 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][1] -> [FAIL][2] ([fdo#111045] / [fdo#111096])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][3] ([fdo#103167]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u2:          [DMESG-WARN][5] ([fdo#110595]) -> [DMESG-WARN][6] ([fdo#106107] / [fdo#110595])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/fi-icl-u2/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/fi-icl-u2/igt@i915_pm_rpm@module-reload.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096


Participating hosts (50 -> 44)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7402 -> Patchwork_15387

  CI-20190529: 20190529
  CI_DRM_7402: d5f0845c4b92c5826d63b76f89866492e0935c1b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5299: 65fed6a79adea14f7bef6d55530da47d7731d370 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15387: 51b2b890786477d1b4d45715bddfa37272bb8848 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

51b2b8907864 drm/i915/tgl: Implement Wa_1604555607

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* ✓ Fi.CI.IGT: success for Wa_1604555607 implementation and verification skip (rev6)
@ 2019-11-23 11:45   ` Patchwork
  0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-23 11:45 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev6)
URL   : https://patchwork.freedesktop.org/series/69763/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7402_full -> Patchwork_15387_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_15387_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb4/igt@gem_ctx_isolation@vcs1-none.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110854])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb1/igt@gem_exec_balancer@smoke.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb5/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +15 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276]) +9 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +4 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-vebox:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html

  * igt@gem_exec_schedule@smoketest-all:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#111855])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb1/igt@gem_exec_schedule@smoketest-all.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb4/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-snb:          [PASS][15] -> [TIMEOUT][16] ([fdo#112068 ])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb6/igt@gem_userptr_blits@dmabuf-sync.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([fdo#112347])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl9/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@pipe-a-forked-bo:
    - shard-hsw:          [PASS][25] -> [INCOMPLETE][26] ([fdo#103540])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw6/igt@kms_cursor_legacy@pipe-a-forked-bo.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw6/igt@kms_cursor_legacy@pipe-a-forked-bo.html

  * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103184] / [fdo#103232])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb6/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb6/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([fdo#103184] / [fdo#103232] / [fdo#108472])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [PASS][31] -> [INCOMPLETE][32] ([fdo#111747] / [fdo#111832] / [fdo#111850])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb8/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-hsw:          [PASS][33] -> [FAIL][34] ([fdo#102887])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([fdo#103167]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [PASS][37] -> [FAIL][38] ([fdo#103167]) +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([fdo#111832] / [fdo#111850])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-glk:          [PASS][41] -> [INCOMPLETE][42] ([fdo#103359] / [k.org#198133])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][43] -> [DMESG-WARN][44] ([fdo#108566]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][45] -> [FAIL][46] ([fdo#108145])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][47] -> [SKIP][48] ([fdo#109441])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][49] ([fdo#112080]) -> [PASS][50] +13 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb3/igt@gem_busy@busy-vcs1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb1/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [SKIP][51] ([fdo#109276] / [fdo#112080]) -> [PASS][52] +4 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_shared@q-smoketest-all:
    - shard-tglb:         [INCOMPLETE][53] ([fdo#111735]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb6/igt@gem_ctx_shared@q-smoketest-all.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb9/igt@gem_ctx_shared@q-smoketest-all.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb2/igt@gem_eio@in-flight-suspend.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [SKIP][57] ([fdo#109276]) -> [PASS][58] +19 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [SKIP][59] ([fdo#112146]) -> [PASS][60] +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb2/igt@gem_exec_schedule@preempt-bsd.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb3/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111736] / [fdo#111850]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb2/igt@gem_exec_suspend@basic-s3.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb3/igt@gem_exec_suspend@basic-s3.html
    - shard-apl:          [DMESG-WARN][63] ([fdo#108566]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-apl4/igt@gem_exec_suspend@basic-s3.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-apl1/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-tglb:         [INCOMPLETE][65] ([fdo#111998]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb6/igt@gem_pipe_control_store_loop@reused-buffer.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb9/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [DMESG-WARN][67] ([fdo#111870]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][69] ([fdo#111870]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw2/igt@gem_userptr_blits@sync-unmap.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html

  * igt@i915_suspend@debugfs-reader:
    - shard-tglb:         [INCOMPLETE][71] ([fdo#111850]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb7/igt@i915_suspend@debugfs-reader.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb9/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][73] ([fdo#104873]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-glk4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-glk4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-skl:          [DMESG-WARN][75] ([fdo#105541]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl5/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl7/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled:
    - shard-skl:          [FAIL][77] ([fdo#103184] / [fdo#103232] / [fdo#108145]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][79] ([fdo#105363]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][81] ([fdo#103540]) -> [PASS][82] +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw2/igt@kms_flip@flip-vs-suspend.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw7/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-iclb:         [INCOMPLETE][83] ([fdo#107713] / [fdo#109507]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][85] ([fdo#103167]) -> [PASS][86] +8 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][87] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
    - shard-tglb:         [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-skl:          [FAIL][91] ([fdo#103167]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl9/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][93] ([fdo#108566]) -> [PASS][94] +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-snb:          [INCOMPLETE][95] ([fdo#105411]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][97] ([fdo#108145] / [fdo#110403]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][99] ([fdo#109642] / [fdo#111068]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb3/igt@kms_psr2_su@page_flip.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@suspend:
    - shard-tglb:         [INCOMPLETE][101] ([fdo#111832] / [fdo#111850]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb2/igt@kms_psr@suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb2/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][103] ([fdo#104108]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-skl:          [I

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for Wa_1604555607 implementation and verification skip (rev6)
@ 2019-11-23 11:45   ` Patchwork
  0 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-23 11:45 UTC (permalink / raw)
  To: Ramalingam C; +Cc: intel-gfx

== Series Details ==

Series: Wa_1604555607 implementation and verification skip (rev6)
URL   : https://patchwork.freedesktop.org/series/69763/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7402_full -> Patchwork_15387_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_15387_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-none:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb4/igt@gem_ctx_isolation@vcs1-none.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb3/igt@gem_ctx_isolation@vcs1-none.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#110854])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb1/igt@gem_exec_balancer@smoke.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb5/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_parallel@vcs1-fds:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +15 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb5/igt@gem_exec_parallel@vcs1-fds.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276]) +9 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146]) +4 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_schedule@preempt-queue-chain-vebox:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@gem_exec_schedule@preempt-queue-chain-vebox.html

  * igt@gem_exec_schedule@smoketest-all:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#111855])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb1/igt@gem_exec_schedule@smoketest-all.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb4/igt@gem_exec_schedule@smoketest-all.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-snb:          [PASS][15] -> [TIMEOUT][16] ([fdo#112068 ])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-snb:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb6/igt@gem_userptr_blits@dmabuf-sync.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb2/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([fdo#112347])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl9/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@pipe-a-forked-bo:
    - shard-hsw:          [PASS][25] -> [INCOMPLETE][26] ([fdo#103540])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw6/igt@kms_cursor_legacy@pipe-a-forked-bo.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw6/igt@kms_cursor_legacy@pipe-a-forked-bo.html

  * igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103184] / [fdo#103232])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb6/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb6/igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
    - shard-skl:          [PASS][29] -> [FAIL][30] ([fdo#103184] / [fdo#103232] / [fdo#108472])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl3/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [PASS][31] -> [INCOMPLETE][32] ([fdo#111747] / [fdo#111832] / [fdo#111850])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb8/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-hsw:          [PASS][33] -> [FAIL][34] ([fdo#102887])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([fdo#103167]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-tglb:         [PASS][37] -> [FAIL][38] ([fdo#103167]) +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb9/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [PASS][39] -> [INCOMPLETE][40] ([fdo#111832] / [fdo#111850])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-glk:          [PASS][41] -> [INCOMPLETE][42] ([fdo#103359] / [k.org#198133])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-glk4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-apl:          [PASS][43] -> [DMESG-WARN][44] ([fdo#108566]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][45] -> [FAIL][46] ([fdo#108145])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][47] -> [SKIP][48] ([fdo#109441])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb4/igt@kms_psr@psr2_primary_mmap_gtt.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][49] ([fdo#112080]) -> [PASS][50] +13 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb3/igt@gem_busy@busy-vcs1.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb1/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-queued:
    - shard-iclb:         [SKIP][51] ([fdo#109276] / [fdo#112080]) -> [PASS][52] +4 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html

  * igt@gem_ctx_shared@q-smoketest-all:
    - shard-tglb:         [INCOMPLETE][53] ([fdo#111735]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb6/igt@gem_ctx_shared@q-smoketest-all.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb9/igt@gem_ctx_shared@q-smoketest-all.html

  * igt@gem_eio@in-flight-suspend:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111832] / [fdo#111850] / [fdo#112081]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb2/igt@gem_eio@in-flight-suspend.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [SKIP][57] ([fdo#109276]) -> [PASS][58] +19 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [SKIP][59] ([fdo#112146]) -> [PASS][60] +3 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb2/igt@gem_exec_schedule@preempt-bsd.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb3/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111736] / [fdo#111850]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb2/igt@gem_exec_suspend@basic-s3.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb3/igt@gem_exec_suspend@basic-s3.html
    - shard-apl:          [DMESG-WARN][63] ([fdo#108566]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-apl4/igt@gem_exec_suspend@basic-s3.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-apl1/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_pipe_control_store_loop@reused-buffer:
    - shard-tglb:         [INCOMPLETE][65] ([fdo#111998]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb6/igt@gem_pipe_control_store_loop@reused-buffer.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb9/igt@gem_pipe_control_store_loop@reused-buffer.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [DMESG-WARN][67] ([fdo#111870]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][69] ([fdo#111870]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw2/igt@gem_userptr_blits@sync-unmap.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html

  * igt@i915_suspend@debugfs-reader:
    - shard-tglb:         [INCOMPLETE][71] ([fdo#111850]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb7/igt@i915_suspend@debugfs-reader.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb9/igt@i915_suspend@debugfs-reader.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][73] ([fdo#104873]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-glk4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-glk4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-skl:          [DMESG-WARN][75] ([fdo#105541]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl5/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl7/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled:
    - shard-skl:          [FAIL][77] ([fdo#103184] / [fdo#103232] / [fdo#108145]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl9/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][79] ([fdo#105363]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][81] ([fdo#103540]) -> [PASS][82] +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-hsw2/igt@kms_flip@flip-vs-suspend.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-hsw7/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-iclb:         [INCOMPLETE][83] ([fdo#107713] / [fdo#109507]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][85] ([fdo#103167]) -> [PASS][86] +8 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-tglb:         [INCOMPLETE][87] ([fdo#111832] / [fdo#111850] / [fdo#111884]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu:
    - shard-tglb:         [FAIL][89] ([fdo#103167]) -> [PASS][90] +5 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-skl:          [FAIL][91] ([fdo#103167]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl9/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][93] ([fdo#108566]) -> [PASS][94] +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-snb:          [INCOMPLETE][95] ([fdo#105411]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-snb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-snb7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][97] ([fdo#108145] / [fdo#110403]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][99] ([fdo#109642] / [fdo#111068]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-iclb3/igt@kms_psr2_su@page_flip.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@suspend:
    - shard-tglb:         [INCOMPLETE][101] ([fdo#111832] / [fdo#111850]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-tglb2/igt@kms_psr@suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-tglb2/igt@kms_psr@suspend.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][103] ([fdo#104108]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7402/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/shard-skl3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-skl:          [I

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15387/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 0/1] Wa_1604555607 implementation and verification skip
@ 2019-11-21 10:12 Ramalingam C
  2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
  0 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2019-11-21 10:12 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson

Implements the Wa_1604555607 and skips its verification as the FF_MODE2
register is write only till TGL B0.

Michel Thierry (1):
  drm/i915/tgl: Implement Wa_1604555607

 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
 2 files changed, 26 insertions(+), 3 deletions(-)

-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 10:12 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C
@ 2019-11-21 10:12 ` Ramalingam C
  2019-11-21 10:19   ` Chris Wilson
                     ` (2 more replies)
  0 siblings, 3 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-21 10:12 UTC (permalink / raw)
  To: intel-gfx, Tvrtko Ursulin, Chris Wilson; +Cc: Michel Thierry

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..7cfd2442b736 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 }
 
 static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
+		__wa_write_masked_or(wal, FF_MODE2,
+				     FF_MODE2_TDS_TIMER_MASK, val, 0);
+	else
+		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
@ 2019-11-21 10:19   ` Chris Wilson
  2019-11-21 10:51     ` Ramalingam C
  2019-11-21 10:19   ` Tvrtko Ursulin
  2019-11-21 11:12   ` Ramalingam C
  2 siblings, 1 reply; 25+ messages in thread
From: Chris Wilson @ 2019-11-21 10:19 UTC (permalink / raw)
  To: Ramalingam C, Tvrtko Ursulin, intel-gfx; +Cc: Michel Thierry

Quoting Ramalingam C (2019-11-21 10:12:26)
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>   uncore read is used [Tvrtko]
>   Macros as used for MASK definition [Chris]
> v5:
>   Skip the Wa_1604555607 verification [Ram]
>   i915 ptr retrieved from engine. [Tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
>  2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..7cfd2442b736 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>  }
>  
>  static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -                  u32 val)
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +                    u32 val, u32 read_mask)
>  {
>         struct i915_wa wa = {
>                 .reg  = reg,
>                 .mask = mask,
>                 .val  = val,
> -               .read = mask,
> +               .read = read_mask,
>         };
>  
>         _wa_add(wal, &wa);

You might as well call it wa_add() since it takes all the arguments to
_wa_add() and wraps them up into struct that we then copy.

>  }
>  
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +                  u32 val)
> +{
> +       __wa_write_masked_or(wal, reg, mask, val, mask);
> +}
> +
>  static void
>  wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>  {
> @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>                                      struct i915_wa_list *wal)
>  {
> +       u32 val;
> +
>         /* Wa_1409142259:tgl */
>         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +       /* Wa_1604555607:tgl */
> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> +       val |= FF_MODE2_TDS_TIMER_128;
> +       if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> +               __wa_write_masked_or(wal, FF_MODE2,
> +                                    FF_MODE2_TDS_TIMER_MASK, val, 0);
> +       else
> +               wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

I still have this plan to do this as MI_MATH ops... But it's not a
blocker.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 10:19   ` Chris Wilson
@ 2019-11-21 10:51     ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-21 10:51 UTC (permalink / raw)
  To: Chris Wilson; +Cc: Michel Thierry, intel-gfx

On 2019-11-21 at 10:19:13 +0000, Chris Wilson wrote:
> Quoting Ramalingam C (2019-11-21 10:12:26)
> > From: Michel Thierry <michel.thierry@intel.com>
> > 
> > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> > FF_MODE2 is part of the register state context, that's why it is
> > implemented here.
> > 
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> > 
> > v2: Rebased on top of the WA refactoring (Oscar)
> > v3: Correctly add to ctx_workarounds_init (Michel)
> > v4:
> >   uncore read is used [Tvrtko]
> >   Macros as used for MASK definition [Chris]
> > v5:
> >   Skip the Wa_1604555607 verification [Ram]
> >   i915 ptr retrieved from engine. [Tvrtko]
> > 
> > BSpec: 19363
> > HSDES: 1604555607
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
> >  drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
> >  2 files changed, 26 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 399acae2f33f..7cfd2442b736 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
> >  }
> >  
> >  static void
> > -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > -                  u32 val)
> > +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > +                    u32 val, u32 read_mask)
> >  {
> >         struct i915_wa wa = {
> >                 .reg  = reg,
> >                 .mask = mask,
> >                 .val  = val,
> > -               .read = mask,
> > +               .read = read_mask,
> >         };
> >  
> >         _wa_add(wal, &wa);
> 
> You might as well call it wa_add() since it takes all the arguments to
> _wa_add() and wraps them up into struct that we then copy.
> 
Something like this?

static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
                   u32 val, u32 read_mask)
{
        struct i915_wa wa = {
                .reg  = reg,
                .mask = mask,
                .val  = val,
                .read = read_mask,
        };

        _wa_add(wal, &wa);
}

static void
__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
                     u32 val, u32 read_mask)
{
        wa_add(wal, reg, mask, val, read_mask);
}


-Ram
> >  }
> >  
> > +static void
> > +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> > +                  u32 val)
> > +{
> > +       __wa_write_masked_or(wal, reg, mask, val, mask);
> > +}
> > +
> >  static void
> >  wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> >  {
> > @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >                                      struct i915_wa_list *wal)
> >  {
> > +       u32 val;
> > +
> >         /* Wa_1409142259:tgl */
> >         WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
> >                           GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > +
> > +       /* Wa_1604555607:tgl */
> > +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +       val |= FF_MODE2_TDS_TIMER_128;
> > +       if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> > +               __wa_write_masked_or(wal, FF_MODE2,
> > +                                    FF_MODE2_TDS_TIMER_MASK, val, 0);
> > +       else
> > +               wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> 
> I still have this plan to do this as MI_MATH ops... But it's not a
> blocker.
> -Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
  2019-11-21 10:19   ` Chris Wilson
@ 2019-11-21 10:19   ` Tvrtko Ursulin
  2019-11-21 11:12   ` Ramalingam C
  2 siblings, 0 replies; 25+ messages in thread
From: Tvrtko Ursulin @ 2019-11-21 10:19 UTC (permalink / raw)
  To: Ramalingam C, intel-gfx, Chris Wilson; +Cc: Michel Thierry


On 21/11/2019 10:12, Ramalingam C wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> v2: Rebased on top of the WA refactoring (Oscar)
> v3: Correctly add to ctx_workarounds_init (Michel)
> v4:
>    uncore read is used [Tvrtko]
>    Macros as used for MASK definition [Chris]
> v5:
>    Skip the Wa_1604555607 verification [Ram]
>    i915 ptr retrieved from engine. [Tvrtko]
> 
> BSpec: 19363
> HSDES: 1604555607
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++---
>   drivers/gpu/drm/i915/i915_reg.h             |  4 ++++
>   2 files changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 399acae2f33f..7cfd2442b736 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -147,19 +147,26 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>   }
>   
>   static void
> -wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> -		   u32 val)
> +__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		     u32 val, u32 read_mask)
>   {
>   	struct i915_wa wa = {
>   		.reg  = reg,
>   		.mask = mask,
>   		.val  = val,
> -		.read = mask,
> +		.read = read_mask,
>   	};
>   
>   	_wa_add(wal, &wa);
>   }
>   
> +static void
> +wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
> +		   u32 val)
> +{
> +	__wa_write_masked_or(wal, reg, mask, val, mask);
> +}
> +
>   static void
>   wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>   {
> @@ -568,9 +575,21 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> +	u32 val;
> +
>   	/* Wa_1409142259:tgl */
>   	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>   			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> +
> +	/* Wa_1604555607:tgl */
> +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> +	val |= FF_MODE2_TDS_TIMER_128;
> +	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
> +		__wa_write_masked_or(wal, FF_MODE2,
> +				     FF_MODE2_TDS_TIMER_MASK, val, 0);
> +	else
> +		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

Hm a hybrid solution. I was thinking:

  __wa_write_masked_or(wal,
		       FF_MODE2,
		       FF_MODE2_TDS_TIMER_MASK,
		       val,
		       IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ?
		       0 : FF_MODE2_TDS_TIMER_MASK);

But yours works as well.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94d0f593eeb7..a99fdf8ea53b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7922,6 +7922,10 @@ enum {
>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
>   #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
>   
> +#define FF_MODE2			_MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
> +#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> +
>   /* PCH */
>   
>   #define PCH_DISPLAY_BASE	0xc0000u
> 
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^ permalink raw reply	[flat|nested] 25+ messages in thread

* [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
  2019-11-21 10:19   ` Chris Wilson
  2019-11-21 10:19   ` Tvrtko Ursulin
@ 2019-11-21 11:12   ` Ramalingam C
  2019-11-21 18:29     ` Lucas De Marchi
  2 siblings, 1 reply; 25+ messages in thread
From: Ramalingam C @ 2019-11-21 11:12 UTC (permalink / raw)
  To: intel-gfx, Chris Wilson, Tvrtko Ursulin; +Cc: Michel Thierry, lucas.demarchi

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

v2: Rebased on top of the WA refactoring (Oscar)
v3: Correctly add to ctx_workarounds_init (Michel)
v4:
  uncore read is used [Tvrtko]
  Macros as used for MASK definition [Chris]
v5:
  Skip the Wa_1604555607 verification [Ram]
  i915 ptr retrieved from engine. [Tvrtko]
v6:
  __wa_write_masked_or used with varying parameter [Tvrtko]
  Added wa_add as a wrapper for __wa_add [Chris]

BSpec: 19363
HSDES: 1604555607
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Ramalingam C <ramlingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 ++++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h             |  4 +++
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 399acae2f33f..efb43eb99e22 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -146,20 +146,33 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
 	}
 }
 
-static void
-wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
-		   u32 val)
+static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val, u32 read_mask)
 {
 	struct i915_wa wa = {
 		.reg  = reg,
 		.mask = mask,
 		.val  = val,
-		.read = mask,
+		.read = read_mask,
 	};
 
 	_wa_add(wal, &wa);
 }
 
+static void
+__wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		     u32 val, u32 read_mask)
+{
+	wa_add(wal, reg, mask, val, read_mask);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	__wa_write_masked_or(wal, reg, mask, val, mask);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -568,9 +581,19 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
 	/* Wa_1409142259:tgl */
 	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
+			     FF_MODE2_TDS_TIMER_MASK);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94d0f593eeb7..a99fdf8ea53b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7922,6 +7922,10 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_MASK	REG_GENMASK(23, 16)
+#define   FF_MODE2_TDS_TIMER_128	REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 11:12   ` Ramalingam C
@ 2019-11-21 18:29     ` Lucas De Marchi
  2019-11-22  3:27       ` Ramalingam C
  0 siblings, 1 reply; 25+ messages in thread
From: Lucas De Marchi @ 2019-11-21 18:29 UTC (permalink / raw)
  To: Ramalingam C; +Cc: Michel Thierry, intel-gfx

On Thu, Nov 21, 2019 at 04:42:31PM +0530, Ramalingam C wrote:
>+	/* Wa_1604555607:tgl */
>+	val = intel_uncore_read(engine->uncore, FF_MODE2);
>+	val &= ~FF_MODE2_TDS_TIMER_MASK;
>+	val |= FF_MODE2_TDS_TIMER_128;
>+	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
>+			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:

isn't it broken until B0 rather than only on A0? I think we could just
disable the read back for all revs and then selectively enable it
for later.

Lucas De Marchi
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^ permalink raw reply	[flat|nested] 25+ messages in thread

* Re: [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607
  2019-11-21 18:29     ` Lucas De Marchi
@ 2019-11-22  3:27       ` Ramalingam C
  0 siblings, 0 replies; 25+ messages in thread
From: Ramalingam C @ 2019-11-22  3:27 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: Michel Thierry, intel-gfx

On 2019-11-21 at 10:29:09 -0800, Lucas De Marchi wrote:
> On Thu, Nov 21, 2019 at 04:42:31PM +0530, Ramalingam C wrote:
> > +	/* Wa_1604555607:tgl */
> > +	val = intel_uncore_read(engine->uncore, FF_MODE2);
> > +	val &= ~FF_MODE2_TDS_TIMER_MASK;
> > +	val |= FF_MODE2_TDS_TIMER_128;
> > +	__wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > +			     IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0) ? 0:
> 
> isn't it broken until B0 rather than only on A0? I think we could just
> disable the read back for all revs and then selectively enable it
> for later.

Thought of excluding the verification when the new stepping comes in.
Hence excluded for existing stepping alone.

Even your suggestion sounds good to me. I will go with it. With a FIXME
Note to indicate that we need to enable for capable steppings.

-Ram
> 
> Lucas De Marchi
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^ permalink raw reply	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2019-11-26 10:11 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
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2019-11-22  4:02 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C
2019-11-22  4:02 ` [Intel-gfx] " Ramalingam C
2019-11-22  4:02 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
2019-11-22  4:02   ` [Intel-gfx] " Ramalingam C
2019-11-22  9:21   ` Tvrtko Ursulin
2019-11-22  9:21     ` [Intel-gfx] " Tvrtko Ursulin
2019-11-22  9:29     ` Chris Wilson
2019-11-22  9:29       ` [Intel-gfx] " Chris Wilson
2019-11-26  8:00       ` Ramalingam C
2019-11-26  8:00         ` [Intel-gfx] " Ramalingam C
2019-11-26  9:38       ` Lucas De Marchi
2019-11-26  9:38         ` [Intel-gfx] " Lucas De Marchi
2019-11-26 10:10         ` Ramalingam C
2019-11-26 10:10           ` [Intel-gfx] " Ramalingam C
2019-11-22  4:46 ` ✓ Fi.CI.BAT: success for Wa_1604555607 implementation and verification skip (rev6) Patchwork
2019-11-22  4:46   ` [Intel-gfx] " Patchwork
2019-11-23 11:45 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-23 11:45   ` [Intel-gfx] " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2019-11-21 10:12 [PATCH 0/1] Wa_1604555607 implementation and verification skip Ramalingam C
2019-11-21 10:12 ` [PATCH 1/1] drm/i915/tgl: Implement Wa_1604555607 Ramalingam C
2019-11-21 10:19   ` Chris Wilson
2019-11-21 10:51     ` Ramalingam C
2019-11-21 10:19   ` Tvrtko Ursulin
2019-11-21 11:12   ` Ramalingam C
2019-11-21 18:29     ` Lucas De Marchi
2019-11-22  3:27       ` Ramalingam C

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