* [PATCH 0/4] x86, amd: family 0x15 L3 cache features @ 2011-01-24 15:05 Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld ` (3 more replies) 0 siblings, 4 replies; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-24 15:05 UTC (permalink / raw) To: hpa, tglx, mingo; +Cc: andreas.herrmann3, linux-kernel, x86, Hans Rosenfeld This patch set enables L3 cache index disable and adds support for L3 cache partitioning on AMD family 0x15 CPUs. This stuff applies against tip/master 3ff6dcac735704824c1dff64dc6863c390d364cc. Andreas Herrmann (1): x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld (3): x86, amd: Enable L3 cache index disable on family 0x15 x86, amd: Extend AMD northbridge caching code to support "Link Control" devices x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs arch/x86/include/asm/amd_nb.h | 4 ++ arch/x86/kernel/amd_nb.c | 69 ++++++++++++++++++++++++++++++- arch/x86/kernel/cpu/amd.c | 8 +++- arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++----- arch/x86/kernel/smpboot.c | 1 + include/linux/pci_ids.h | 1 + 6 files changed, 140 insertions(+), 16 deletions(-) ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors 2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld @ 2011-01-24 15:05 ` Hans Rosenfeld 2011-01-26 10:57 ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann 2011-02-04 22:07 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton 2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld ` (2 subsequent siblings) 3 siblings, 2 replies; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-24 15:05 UTC (permalink / raw) To: hpa, tglx, mingo; +Cc: andreas.herrmann3, linux-kernel, x86 From: Andreas Herrmann <andreas.herrmann3@amd.com> On multi-node CPUs we don't need the socket wide compute unit ID but the node-wide compute unit ID. Thus we need to normalize the value. This is similar to what we do with cpu_core_id. A compute unit is then identified by physical_package_id, node_id, and compute_unit_id. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> --- arch/x86/kernel/cpu/amd.c | 8 ++++++-- arch/x86/kernel/smpboot.c | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 7c7bedb..990cc48 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid) #ifdef CONFIG_X86_HT static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) { - u32 nodes; + u32 nodes, cores_per_cu; u8 node_id; int cpu = smp_processor_id(); @@ -276,6 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* get compute unit information */ smp_num_siblings = ((ebx >> 8) & 3) + 1; c->compute_unit_id = ebx & 0xff; + cores_per_cu = ((ebx >> 8) & 3) + 1; } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -288,15 +289,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* fixup multi-node processor information */ if (nodes > 1) { u32 cores_per_node; + u32 cus_per_node; set_cpu_cap(c, X86_FEATURE_AMD_DCM); cores_per_node = c->x86_max_cores / nodes; + cus_per_node = cores_per_node / cores_per_cu; /* store NodeID, use llc_shared_map to store sibling info */ per_cpu(cpu_llc_id, cpu) = node_id; /* core id to be in range from 0 to (cores_per_node - 1) */ - c->cpu_core_id = c->cpu_core_id % cores_per_node; + c->cpu_core_id %= cores_per_node; + c->compute_unit_id %= cus_per_node; } } #endif diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 0cbe8c0..fbaa222 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -414,6 +414,7 @@ void __cpuinit set_cpu_sibling_map(int cpu) if (cpu_has(c, X86_FEATURE_TOPOEXT)) { if (c->phys_proc_id == o->phys_proc_id && + per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && c->compute_unit_id == o->compute_unit_id) link_thread_siblings(cpu, i); } else if (c->phys_proc_id == o->phys_proc_id && -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [tip:x86/amd-nb] x86, amd: Normalize compute unit IDs on multi-node processors 2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld @ 2011-01-26 10:57 ` tip-bot for Andreas Herrmann 2011-02-14 14:30 ` Ingo Molnar 2011-02-04 22:07 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton 1 sibling, 1 reply; 21+ messages in thread From: tip-bot for Andreas Herrmann @ 2011-01-26 10:57 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, andreas.herrmann3, tglx, mingo Commit-ID: d518573de63fb119e5e9a3137386544671387681 Gitweb: http://git.kernel.org/tip/d518573de63fb119e5e9a3137386544671387681 Author: Andreas Herrmann <andreas.herrmann3@amd.com> AuthorDate: Mon, 24 Jan 2011 16:05:40 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Wed, 26 Jan 2011 08:28:22 +0100 x86, amd: Normalize compute unit IDs on multi-node processors On multi-node CPUs we don't need the socket wide compute unit ID but the node-wide compute unit ID. Thus we need to normalize the value. This is similar to what we do with cpu_core_id. A compute unit is then identified by physical_package_id, node_id, and compute_unit_id. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-2-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/cpu/amd.c | 8 ++++++-- arch/x86/kernel/smpboot.c | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 7c7bedb..990cc48 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid) #ifdef CONFIG_X86_HT static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) { - u32 nodes; + u32 nodes, cores_per_cu; u8 node_id; int cpu = smp_processor_id(); @@ -276,6 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* get compute unit information */ smp_num_siblings = ((ebx >> 8) & 3) + 1; c->compute_unit_id = ebx & 0xff; + cores_per_cu = ((ebx >> 8) & 3) + 1; } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -288,15 +289,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* fixup multi-node processor information */ if (nodes > 1) { u32 cores_per_node; + u32 cus_per_node; set_cpu_cap(c, X86_FEATURE_AMD_DCM); cores_per_node = c->x86_max_cores / nodes; + cus_per_node = cores_per_node / cores_per_cu; /* store NodeID, use llc_shared_map to store sibling info */ per_cpu(cpu_llc_id, cpu) = node_id; /* core id to be in range from 0 to (cores_per_node - 1) */ - c->cpu_core_id = c->cpu_core_id % cores_per_node; + c->cpu_core_id %= cores_per_node; + c->compute_unit_id %= cus_per_node; } } #endif diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 0cbe8c0..fbaa222 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -414,6 +414,7 @@ void __cpuinit set_cpu_sibling_map(int cpu) if (cpu_has(c, X86_FEATURE_TOPOEXT)) { if (c->phys_proc_id == o->phys_proc_id && + per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && c->compute_unit_id == o->compute_unit_id) link_thread_siblings(cpu, i); } else if (c->phys_proc_id == o->phys_proc_id && ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [tip:x86/amd-nb] x86, amd: Normalize compute unit IDs on multi-node processors 2011-01-26 10:57 ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann @ 2011-02-14 14:30 ` Ingo Molnar 2011-02-14 17:14 ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov 0 siblings, 1 reply; 21+ messages in thread From: Ingo Molnar @ 2011-02-14 14:30 UTC (permalink / raw) To: mingo, hpa, linux-kernel, andreas.herrmann3, tglx; +Cc: linux-tip-commits * tip-bot for Andreas Herrmann <andreas.herrmann3@amd.com> wrote: > Commit-ID: d518573de63fb119e5e9a3137386544671387681 > Gitweb: http://git.kernel.org/tip/d518573de63fb119e5e9a3137386544671387681 > Author: Andreas Herrmann <andreas.herrmann3@amd.com> > AuthorDate: Mon, 24 Jan 2011 16:05:40 +0100 Andreas, the build is now producing this warning: arch/x86/kernel/cpu/amd.c: In function 'amd_detect_cmp': arch/x86/kernel/cpu/amd.c:268: warning: 'cores_per_cu' may be used uninitialized in this function arch/x86/kernel/cpu/amd.c:268: note: 'cores_per_cu' was declared here Thanks, Ingo ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH] x86, amd: Fix uninitialized variable warning 2011-02-14 14:30 ` Ingo Molnar @ 2011-02-14 17:14 ` Borislav Petkov 2011-02-15 3:10 ` [tip:x86/amd-nb] x86, amd: Initialize variable properly tip-bot for Borislav Petkov 0 siblings, 1 reply; 21+ messages in thread From: Borislav Petkov @ 2011-02-14 17:14 UTC (permalink / raw) To: Ingo Molnar Cc: mingo, hpa, linux-kernel, andreas.herrmann3, tglx, linux-tip-commits On Mon, Feb 14, 2011 at 03:30:06PM +0100, Ingo Molnar wrote: > > * tip-bot for Andreas Herrmann <andreas.herrmann3@amd.com> wrote: > > > Commit-ID: d518573de63fb119e5e9a3137386544671387681 > > Gitweb: http://git.kernel.org/tip/d518573de63fb119e5e9a3137386544671387681 > > Author: Andreas Herrmann <andreas.herrmann3@amd.com> > > AuthorDate: Mon, 24 Jan 2011 16:05:40 +0100 > > Andreas, > > the build is now producing this warning: > > arch/x86/kernel/cpu/amd.c: In function 'amd_detect_cmp': > arch/x86/kernel/cpu/amd.c:268: warning: 'cores_per_cu' may be used uninitialized in this function > arch/x86/kernel/cpu/amd.c:268: note: 'cores_per_cu' was declared here Here's a quick fix against tip/amd-nb: -- From: Borislav Petkov <borislav.petkov@amd.com> Date: Mon, 14 Feb 2011 16:25:47 +0100 Subject: [PATCH] x86, amd: Fix uninitialized variable warning d518573de63fb119e5e9a3137386544671387681 introduced compute unit normalization but causes a valid compiler warning: arch/x86/kernel/cpu/amd.c: In function 'amd_detect_cmp': arch/x86/kernel/cpu/amd.c:268: warning: 'cores_per_cu' may be used uninitialized in this function arch/x86/kernel/cpu/amd.c:268: note: 'cores_per_cu' was declared here Initialize it with a proper value. Also, fixup comment while at it. Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> --- arch/x86/kernel/cpu/amd.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 990cc48..589bdd7 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid) #ifdef CONFIG_X86_HT static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) { - u32 nodes, cores_per_cu; + u32 nodes, cores_per_cu = 1; u8 node_id; int cpu = smp_processor_id(); @@ -276,7 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* get compute unit information */ smp_num_siblings = ((ebx >> 8) & 3) + 1; c->compute_unit_id = ebx & 0xff; - cores_per_cu = ((ebx >> 8) & 3) + 1; + cores_per_cu += ((ebx >> 8) & 3); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -298,7 +298,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* store NodeID, use llc_shared_map to store sibling info */ per_cpu(cpu_llc_id, cpu) = node_id; - /* core id to be in range from 0 to (cores_per_node - 1) */ + /* core id has to be in the [0 .. cores_per_node - 1] range */ c->cpu_core_id %= cores_per_node; c->compute_unit_id %= cus_per_node; } -- 1.7.4.rc2 -- Regards/Gruss, Boris. Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach General Managers: Alberto Bozzo, Andrew Bowd Registration: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [tip:x86/amd-nb] x86, amd: Initialize variable properly 2011-02-14 17:14 ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov @ 2011-02-15 3:10 ` tip-bot for Borislav Petkov 0 siblings, 0 replies; 21+ messages in thread From: tip-bot for Borislav Petkov @ 2011-02-15 3:10 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, andreas.herrmann3, bp, akpm, tglx, mingo, borislav.petkov Commit-ID: 9e81509efc4fefcdd75cc6a4121672fa71ae8745 Gitweb: http://git.kernel.org/tip/9e81509efc4fefcdd75cc6a4121672fa71ae8745 Author: Borislav Petkov <bp@amd64.org> AuthorDate: Mon, 14 Feb 2011 18:14:51 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Tue, 15 Feb 2011 03:03:19 +0100 x86, amd: Initialize variable properly Commit d518573de63f ("x86, amd: Normalize compute unit IDs on multi-node processors") introduced compute unit normalization but causes a compiler warning: arch/x86/kernel/cpu/amd.c: In function 'amd_detect_cmp': arch/x86/kernel/cpu/amd.c:268: warning: 'cores_per_cu' may be used uninitialized in this function arch/x86/kernel/cpu/amd.c:268: note: 'cores_per_cu' was declared here The compiler is right - initialize it with a proper value. Also, fix up a comment while at it. Reported-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> LKML-Reference: <20110214171451.GB10076@kryptos.osrc.amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/cpu/amd.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 990cc48..589bdd7 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid) #ifdef CONFIG_X86_HT static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) { - u32 nodes, cores_per_cu; + u32 nodes, cores_per_cu = 1; u8 node_id; int cpu = smp_processor_id(); @@ -276,7 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* get compute unit information */ smp_num_siblings = ((ebx >> 8) & 3) + 1; c->compute_unit_id = ebx & 0xff; - cores_per_cu = ((ebx >> 8) & 3) + 1; + cores_per_cu += ((ebx >> 8) & 3); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { u64 value; @@ -298,7 +298,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) /* store NodeID, use llc_shared_map to store sibling info */ per_cpu(cpu_llc_id, cpu) = node_id; - /* core id to be in range from 0 to (cores_per_node - 1) */ + /* core id has to be in the [0 .. cores_per_node - 1] range */ c->cpu_core_id %= cores_per_node; c->compute_unit_id %= cus_per_node; } ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors 2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld 2011-01-26 10:57 ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann @ 2011-02-04 22:07 ` Andrew Morton 1 sibling, 0 replies; 21+ messages in thread From: Andrew Morton @ 2011-02-04 22:07 UTC (permalink / raw) To: Hans Rosenfeld; +Cc: hpa, tglx, mingo, andreas.herrmann3, linux-kernel, x86 On Mon, 24 Jan 2011 16:05:40 +0100 Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > From: Andreas Herrmann <andreas.herrmann3@amd.com> > > On multi-node CPUs we don't need the socket wide compute unit ID but > the node-wide compute unit ID. Thus we need to normalize the value. > This is similar to what we do with cpu_core_id. > > A compute unit is then identified by physical_package_id, node_id, and > compute_unit_id. > > ... > > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid) > #ifdef CONFIG_X86_HT > static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) > { > - u32 nodes; > + u32 nodes, cores_per_cu; > u8 node_id; > int cpu = smp_processor_id(); > > @@ -276,6 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) > /* get compute unit information */ > smp_num_siblings = ((ebx >> 8) & 3) + 1; > c->compute_unit_id = ebx & 0xff; > + cores_per_cu = ((ebx >> 8) & 3) + 1; > } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { > u64 value; > > @@ -288,15 +289,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c) > /* fixup multi-node processor information */ > if (nodes > 1) { > u32 cores_per_node; > + u32 cus_per_node; > > set_cpu_cap(c, X86_FEATURE_AMD_DCM); > cores_per_node = c->x86_max_cores / nodes; > + cus_per_node = cores_per_node / cores_per_cu; > > /* store NodeID, use llc_shared_map to store sibling info */ > per_cpu(cpu_llc_id, cpu) = node_id; > > /* core id to be in range from 0 to (cores_per_node - 1) */ > - c->cpu_core_id = c->cpu_core_id % cores_per_node; > + c->cpu_core_id %= cores_per_node; > + c->compute_unit_id %= cus_per_node; > } > } > #endif arch/x86/kernel/cpu/amd.c: In function 'init_amd': arch/x86/kernel/cpu/amd.c:268: warning: 'cores_per_cu' may be used uninitialized in this function The code looks buggy to me. ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld @ 2011-01-24 15:05 ` Hans Rosenfeld 2011-01-26 10:58 ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld 3 siblings, 1 reply; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-24 15:05 UTC (permalink / raw) To: hpa, tglx, mingo; +Cc: andreas.herrmann3, linux-kernel, x86, Hans Rosenfeld AMD family 0x15 CPUs support L3 cache index disable, so enable it on them. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> --- arch/x86/kernel/amd_nb.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 0a99f71..a4f394c 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -85,6 +85,9 @@ int amd_cache_northbridges(void) boot_cpu_data.x86_mask >= 0x1)) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [tip:x86/amd-nb] x86, amd: Enable L3 cache index disable on family 0x15 2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld @ 2011-01-26 10:58 ` tip-bot for Hans Rosenfeld 0 siblings, 0 replies; 21+ messages in thread From: tip-bot for Hans Rosenfeld @ 2011-01-26 10:58 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hans.rosenfeld, hpa, mingo, andreas.herrmann3, tglx, mingo Commit-ID: b453de02b786c63b8928ec822401468131db0a9b Gitweb: http://git.kernel.org/tip/b453de02b786c63b8928ec822401468131db0a9b Author: Hans Rosenfeld <hans.rosenfeld@amd.com> AuthorDate: Mon, 24 Jan 2011 16:05:41 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Wed, 26 Jan 2011 08:28:23 +0100 x86, amd: Enable L3 cache index disable on family 0x15 AMD family 0x15 CPUs support L3 cache index disable, so enable it on them. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-3-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/kernel/amd_nb.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 0a99f71..a4f394c 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -85,6 +85,9 @@ int amd_cache_northbridges(void) boot_cpu_data.x86_mask >= 0x1)) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices 2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld @ 2011-01-24 15:05 ` Hans Rosenfeld 2011-01-26 10:58 ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld 3 siblings, 1 reply; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-24 15:05 UTC (permalink / raw) To: hpa, tglx, mingo; +Cc: andreas.herrmann3, linux-kernel, x86, Hans Rosenfeld "Link Control" devices (NB function 4) will be used by L3 cache partitioning on family 0x15. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> --- arch/x86/include/asm/amd_nb.h | 1 + arch/x86/kernel/amd_nb.c | 11 +++++++++-- include/linux/pci_ids.h | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 64dc82e..3e70700 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -26,6 +26,7 @@ extern void amd_get_nodes(struct bootnode *nodes); struct amd_northbridge { struct pci_dev *misc; + struct pci_dev *link; }; struct amd_northbridge_info { diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index a4f394c..4ae9a96 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -20,6 +20,11 @@ struct pci_device_id amd_nb_misc_ids[] = { }; EXPORT_SYMBOL(amd_nb_misc_ids); +static struct pci_device_id amd_nb_link_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) }, + {} +}; + const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { { 0x00, 0x18, 0x20 }, { 0xff, 0x00, 0x20 }, @@ -45,7 +50,7 @@ int amd_cache_northbridges(void) { int i = 0; struct amd_northbridge *nb; - struct pci_dev *misc; + struct pci_dev *misc, *link; if (amd_nb_num()) return 0; @@ -64,10 +69,12 @@ int amd_cache_northbridges(void) amd_northbridges.nb = nb; amd_northbridges.num = i; - misc = NULL; + link = misc = NULL; for (i = 0; i != amd_nb_num(); i++) { node_to_amd_nb(i)->misc = misc = next_northbridge(misc, amd_nb_misc_ids); + node_to_amd_nb(i)->link = link = + next_northbridge(link, amd_nb_link_ids); } /* some CPU families (e.g. family 0x11) do not support GART */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 3adb06e..580de67 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -518,6 +518,7 @@ #define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 #define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 #define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_LINK 0x1604 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [tip:x86/amd-nb] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices 2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld @ 2011-01-26 10:58 ` tip-bot for Hans Rosenfeld 0 siblings, 0 replies; 21+ messages in thread From: tip-bot for Hans Rosenfeld @ 2011-01-26 10:58 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hans.rosenfeld, hpa, mingo, andreas.herrmann3, tglx, mingo Commit-ID: 41b2610c3443e6c4760e61fc10eef73f96f9f6a5 Gitweb: http://git.kernel.org/tip/41b2610c3443e6c4760e61fc10eef73f96f9f6a5 Author: Hans Rosenfeld <hans.rosenfeld@amd.com> AuthorDate: Mon, 24 Jan 2011 16:05:42 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Wed, 26 Jan 2011 08:28:23 +0100 x86, amd: Extend AMD northbridge caching code to support "Link Control" devices "Link Control" devices (NB function 4) will be used by L3 cache partitioning on family 0x15. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-4-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/include/asm/amd_nb.h | 1 + arch/x86/kernel/amd_nb.c | 11 +++++++++-- include/linux/pci_ids.h | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 64dc82e..3e70700 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -26,6 +26,7 @@ extern void amd_get_nodes(struct bootnode *nodes); struct amd_northbridge { struct pci_dev *misc; + struct pci_dev *link; }; struct amd_northbridge_info { diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index a4f394c..4ae9a96 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -20,6 +20,11 @@ struct pci_device_id amd_nb_misc_ids[] = { }; EXPORT_SYMBOL(amd_nb_misc_ids); +static struct pci_device_id amd_nb_link_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) }, + {} +}; + const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { { 0x00, 0x18, 0x20 }, { 0xff, 0x00, 0x20 }, @@ -45,7 +50,7 @@ int amd_cache_northbridges(void) { int i = 0; struct amd_northbridge *nb; - struct pci_dev *misc; + struct pci_dev *misc, *link; if (amd_nb_num()) return 0; @@ -64,10 +69,12 @@ int amd_cache_northbridges(void) amd_northbridges.nb = nb; amd_northbridges.num = i; - misc = NULL; + link = misc = NULL; for (i = 0; i != amd_nb_num(); i++) { node_to_amd_nb(i)->misc = misc = next_northbridge(misc, amd_nb_misc_ids); + node_to_amd_nb(i)->link = link = + next_northbridge(link, amd_nb_link_ids); } /* some CPU families (e.g. family 0x11) do not support GART */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 3adb06e..580de67 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -518,6 +518,7 @@ #define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303 #define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304 #define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603 +#define PCI_DEVICE_ID_AMD_15H_NB_LINK 0x1604 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 #define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld ` (2 preceding siblings ...) 2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld @ 2011-01-24 15:05 ` Hans Rosenfeld 2011-01-26 10:56 ` Ingo Molnar 3 siblings, 1 reply; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-24 15:05 UTC (permalink / raw) To: hpa, tglx, mingo; +Cc: andreas.herrmann3, linux-kernel, x86, Hans Rosenfeld L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can be used for evictions by the L2 cache of each compute unit. By writing a 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\ cpuX/cache/index3/subcaches, the user can set the enabled subcaches for a CPU. The settings are directly read from and written to the hardware, so there is no way to have contradicting settings for two CPUs belonging to the same compute unit. Writing will always overwrite any previous setting for a compute unit. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> --- arch/x86/include/asm/amd_nb.h | 3 + arch/x86/kernel/amd_nb.c | 55 +++++++++++++++++++++++++ arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++----- 3 files changed, 119 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 3e70700..423f11c 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -18,6 +18,8 @@ extern int amd_cache_northbridges(void); extern void amd_flush_garts(void); extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); extern int amd_scan_nodes(void); +extern int amd_get_subcaches(int); +extern int amd_set_subcaches(int, int); #ifdef CONFIG_NUMA_EMU extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); @@ -38,6 +40,7 @@ extern struct amd_northbridge_info amd_northbridges; #define AMD_NB_GART 0x1 #define AMD_NB_L3_INDEX_DISABLE 0x2 +#define AMD_NB_L3_PARTITIONING 0x4 #ifdef CONFIG_AMD_NB diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 4ae9a96..ec799ee 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -95,6 +95,10 @@ int amd_cache_northbridges(void) if (boot_cpu_data.x86 == 0x15) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + /* L3 cache partitioning is supported on family 0x15 */ + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); @@ -112,6 +116,57 @@ int __init early_is_amd_nb(u32 device) return 0; } +int amd_get_subcaches(int cpu) +{ + struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; + unsigned int mask; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return 0; + + pci_read_config_dword(link, 0x1d4, &mask); + + return (mask >> (4 * cpu_data(cpu).compute_unit_id)) & 0xf; +} + +int amd_set_subcaches(int cpu, int mask) +{ + static unsigned int reset, ban; + unsigned int reg; + struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) + return -EINVAL; + + /* if necessary, collect reset state of L3 partitioning and BAN mode */ + if (reset == 0) { + pci_read_config_dword(nb->link, 0x1d4, &reset); + pci_read_config_dword(nb->misc, 0x1b8, &ban); + ban &= 0x180000; + } + + /* deactivate BAN mode if any subcaches are to be disabled */ + if (mask != 0xf) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); + } + + mask <<= 4 * cpu_data(cpu).compute_unit_id; + mask |= (0xf ^ (1 << cpu_data(cpu).compute_unit_id)) << 26; + + pci_write_config_dword(nb->link, 0x1d4, mask); + + /* reset BAN mode if L3 partitioning returned to reset state */ + pci_read_config_dword(nb->link, 0x1d4, ®); + if (reg == reset) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + reg &= ~0x180000; + pci_write_config_dword(nb->misc, 0x1b8, reg | ban); + } + + return 0; +} + int amd_cache_gart(void) { int i; diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index ec2c19a..4017a61 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -304,8 +304,9 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, struct _cache_attr { struct attribute attr; - ssize_t (*show)(struct _cpuid4_info *, char *); - ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count); + ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int); + ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count, + unsigned int); }; #ifdef CONFIG_AMD_NB @@ -400,7 +401,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf, #define SHOW_CACHE_DISABLE(slot) \ static ssize_t \ -show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \ +show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return show_cache_disable(this_leaf, buf, slot); \ } @@ -512,7 +514,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, #define STORE_CACHE_DISABLE(slot) \ static ssize_t \ store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \ - const char *buf, size_t count) \ + const char *buf, size_t count, \ + unsigned int cpu) \ { \ return store_cache_disable(this_leaf, buf, count, slot); \ } @@ -524,6 +527,41 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, show_cache_disable_1, store_cache_disable_1); +static ssize_t +show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu) +{ + if (!this_leaf->l3 || + !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); +} + +static ssize_t +store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count, + unsigned int cpu) +{ + unsigned long val; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (!this_leaf->l3 || + !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + if (strict_strtoul(buf, 16, &val) < 0) + return -EINVAL; + + if (amd_set_subcaches(cpu, val)) + return -EINVAL; + + return count; +} + +static struct _cache_attr subcaches = + __ATTR(subcaches, 0644, show_subcaches, store_subcaches); + #else /* CONFIG_AMD_NB */ #define amd_init_l3_cache(x, y) #endif /* CONFIG_AMD_NB */ @@ -870,8 +908,8 @@ static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject); #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y])) #define show_one_plus(file_name, object, val) \ -static ssize_t show_##file_name \ - (struct _cpuid4_info *this_leaf, char *buf) \ +static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \ } @@ -882,7 +920,8 @@ show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1); show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1); show_one_plus(number_of_sets, ecx.split.number_of_sets, 1); -static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { return sprintf(buf, "%luK\n", this_leaf->size / 1024); } @@ -906,17 +945,20 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, return n; } -static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 0, buf); } -static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 1, buf); } -static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { switch (this_leaf->eax.split.type) { case CACHE_TYPE_DATA: @@ -974,6 +1016,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) n += 2; + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + n += 1; + attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL); if (attrs == NULL) return attrs = default_attrs; @@ -986,6 +1031,10 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) attrs[n++] = &cache_disable_1.attr; } + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) { + attrs[n++] = &subcaches.attr; + } + return attrs; } #endif @@ -998,7 +1047,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) ret = fattr->show ? fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf) : + buf, this_leaf->cpu) : 0; return ret; } @@ -1012,7 +1061,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, ret = fattr->store ? fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf, count) : + buf, count, this_leaf->cpu) : 0; return ret; } -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld @ 2011-01-26 10:56 ` Ingo Molnar 2011-01-26 17:05 ` Hans Rosenfeld 2011-01-26 17:08 ` Hans Rosenfeld 0 siblings, 2 replies; 21+ messages in thread From: Ingo Molnar @ 2011-01-26 10:56 UTC (permalink / raw) To: Hans Rosenfeld; +Cc: hpa, tglx, andreas.herrmann3, linux-kernel, x86 * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can > be used for evictions by the L2 cache of each compute unit. By writing a > 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\ > cpuX/cache/index3/subcaches, the user can set the enabled subcaches for > a CPU. The settings are directly read from and written to the hardware, > so there is no way to have contradicting settings for two CPUs belonging > to the same compute unit. Writing will always overwrite any previous > setting for a compute unit. > > Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> > --- > arch/x86/include/asm/amd_nb.h | 3 + > arch/x86/kernel/amd_nb.c | 55 +++++++++++++++++++++++++ > arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++----- > 3 files changed, 119 insertions(+), 12 deletions(-) I have picked up the other 3 patches, but this one causes this build failure: arch/x86/kernel/amd_nb.c: In function ‘amd_get_subcaches’: arch/x86/kernel/amd_nb.c:129:36: error: ‘struct cpuinfo_x86’ has no member named ‘compute_unit_id’ arch/x86/kernel/amd_nb.c: In function ‘amd_set_subcaches’: arch/x86/kernel/amd_nb.c:154:28: error: ‘struct cpuinfo_x86’ has no member named ‘compute_unit_id’ arch/x86/kernel/amd_nb.c:155:36: error: ‘struct cpuinfo_x86’ has no member named ‘compute_unit_id’ arch/x86/kernel/amd_nb.c: In function ‘amd_get_subcaches’: arch/x86/kernel/amd_nb.c:130:1: warning: control reaches end of non-void function Thanks, Ingo ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-26 10:56 ` Ingo Molnar @ 2011-01-26 17:05 ` Hans Rosenfeld 2011-01-26 17:08 ` Hans Rosenfeld 1 sibling, 0 replies; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-26 17:05 UTC (permalink / raw) To: Ingo Molnar; +Cc: hpa, tglx, Herrmann3, Andreas, linux-kernel, x86 On Wed, Jan 26, 2011 at 05:56:37AM -0500, Ingo Molnar wrote: > > * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > > > L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can > > be used for evictions by the L2 cache of each compute unit. By writing a > > 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\ > > cpuX/cache/index3/subcaches, the user can set the enabled subcaches for > > a CPU. The settings are directly read from and written to the hardware, > > so there is no way to have contradicting settings for two CPUs belonging > > to the same compute unit. Writing will always overwrite any previous > > setting for a compute unit. > > > > Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> > > --- > > arch/x86/include/asm/amd_nb.h | 3 + > > arch/x86/kernel/amd_nb.c | 55 +++++++++++++++++++++++++ > > arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++----- > > 3 files changed, 119 insertions(+), 12 deletions(-) > > I have picked up the other 3 patches, but this one causes this build failure: > > arch/x86/kernel/amd_nb.c: In function ?amd_get_subcaches?: > arch/x86/kernel/amd_nb.c:129:36: error: ?struct cpuinfo_x86? has no member named ?compute_unit_id? > arch/x86/kernel/amd_nb.c: In function ?amd_set_subcaches?: > arch/x86/kernel/amd_nb.c:154:28: error: ?struct cpuinfo_x86? has no member named ?compute_unit_id? > arch/x86/kernel/amd_nb.c:155:36: error: ?struct cpuinfo_x86? has no member named ?compute_unit_id? > arch/x86/kernel/amd_nb.c: In function ?amd_get_subcaches?: > arch/x86/kernel/amd_nb.c:130:1: warning: control reaches end of non-void function Hrmpf. CONFIG_SMP. Sorry for the noise, fixed patch will follow shortly. Hans -- %SYSTEM-F-ANARCHISM, The operating system has been overthrown ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-26 10:56 ` Ingo Molnar 2011-01-26 17:05 ` Hans Rosenfeld @ 2011-01-26 17:08 ` Hans Rosenfeld 2011-01-26 20:56 ` Ingo Molnar 1 sibling, 1 reply; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-26 17:08 UTC (permalink / raw) To: mingo; +Cc: hpa, tglx, Andreas.Herrmann3, linux-kernel, x86, Hans Rosenfeld L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can be used for evictions by the L2 cache of each compute unit. By writing a 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\ cpuX/cache/index3/subcaches, the user can set the enabled subcaches for a CPU. The settings are directly read from and written to the hardware, so there is no way to have contradicting settings for two CPUs belonging to the same compute unit. Writing will always overwrite any previous setting for a compute unit. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> --- arch/x86/include/asm/amd_nb.h | 3 + arch/x86/kernel/amd_nb.c | 57 ++++++++++++++++++++++++ arch/x86/kernel/cpu/intel_cacheinfo.c | 77 +++++++++++++++++++++++++++----- 3 files changed, 125 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 3e70700..423f11c 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -18,6 +18,8 @@ extern int amd_cache_northbridges(void); extern void amd_flush_garts(void); extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); extern int amd_scan_nodes(void); +extern int amd_get_subcaches(int); +extern int amd_set_subcaches(int, int); #ifdef CONFIG_NUMA_EMU extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); @@ -38,6 +40,7 @@ extern struct amd_northbridge_info amd_northbridges; #define AMD_NB_GART 0x1 #define AMD_NB_L3_INDEX_DISABLE 0x2 +#define AMD_NB_L3_PARTITIONING 0x4 #ifdef CONFIG_AMD_NB diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 4ae9a96..63310de 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -95,6 +95,10 @@ int amd_cache_northbridges(void) if (boot_cpu_data.x86 == 0x15) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + /* L3 cache partitioning is supported on family 0x15 */ + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); @@ -112,6 +116,59 @@ int __init early_is_amd_nb(u32 device) return 0; } +#ifdef CONFIG_SMP +int amd_get_subcaches(int cpu) +{ + struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; + unsigned int mask; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return 0; + + pci_read_config_dword(link, 0x1d4, &mask); + + return (mask >> (4 * cpu_data(cpu).compute_unit_id)) & 0xf; +} + +int amd_set_subcaches(int cpu, int mask) +{ + static unsigned int reset, ban; + unsigned int reg; + struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) + return -EINVAL; + + /* if necessary, collect reset state of L3 partitioning and BAN mode */ + if (reset == 0) { + pci_read_config_dword(nb->link, 0x1d4, &reset); + pci_read_config_dword(nb->misc, 0x1b8, &ban); + ban &= 0x180000; + } + + /* deactivate BAN mode if any subcaches are to be disabled */ + if (mask != 0xf) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); + } + + mask <<= 4 * cpu_data(cpu).compute_unit_id; + mask |= (0xf ^ (1 << cpu_data(cpu).compute_unit_id)) << 26; + + pci_write_config_dword(nb->link, 0x1d4, mask); + + /* reset BAN mode if L3 partitioning returned to reset state */ + pci_read_config_dword(nb->link, 0x1d4, ®); + if (reg == reset) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + reg &= ~0x180000; + pci_write_config_dword(nb->misc, 0x1b8, reg | ban); + } + + return 0; +} +#endif + int amd_cache_gart(void) { int i; diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index ec2c19a..8455213 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -304,8 +304,9 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, struct _cache_attr { struct attribute attr; - ssize_t (*show)(struct _cpuid4_info *, char *); - ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count); + ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int); + ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count, + unsigned int); }; #ifdef CONFIG_AMD_NB @@ -400,7 +401,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf, #define SHOW_CACHE_DISABLE(slot) \ static ssize_t \ -show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \ +show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return show_cache_disable(this_leaf, buf, slot); \ } @@ -512,7 +514,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, #define STORE_CACHE_DISABLE(slot) \ static ssize_t \ store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \ - const char *buf, size_t count) \ + const char *buf, size_t count, \ + unsigned int cpu) \ { \ return store_cache_disable(this_leaf, buf, count, slot); \ } @@ -524,6 +527,43 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, show_cache_disable_1, store_cache_disable_1); +#ifdef CONFIG_SMP +static ssize_t +show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu) +{ + if (!this_leaf->l3 || + !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); +} + +static ssize_t +store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count, + unsigned int cpu) +{ + unsigned long val; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (!this_leaf->l3 || + !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + if (strict_strtoul(buf, 16, &val) < 0) + return -EINVAL; + + if (amd_set_subcaches(cpu, val)) + return -EINVAL; + + return count; +} + +static struct _cache_attr subcaches = + __ATTR(subcaches, 0644, show_subcaches, store_subcaches); +#endif + #else /* CONFIG_AMD_NB */ #define amd_init_l3_cache(x, y) #endif /* CONFIG_AMD_NB */ @@ -870,8 +910,8 @@ static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject); #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y])) #define show_one_plus(file_name, object, val) \ -static ssize_t show_##file_name \ - (struct _cpuid4_info *this_leaf, char *buf) \ +static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \ } @@ -882,7 +922,8 @@ show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1); show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1); show_one_plus(number_of_sets, ecx.split.number_of_sets, 1); -static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { return sprintf(buf, "%luK\n", this_leaf->size / 1024); } @@ -906,17 +947,20 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, return n; } -static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 0, buf); } -static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 1, buf); } -static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { switch (this_leaf->eax.split.type) { case CACHE_TYPE_DATA: @@ -974,6 +1018,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) n += 2; + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + n += 1; + attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL); if (attrs == NULL) return attrs = default_attrs; @@ -986,6 +1033,12 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) attrs[n++] = &cache_disable_1.attr; } +#ifdef CONFIG_SMP + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) { + attrs[n++] = &subcaches.attr; + } +#endif + return attrs; } #endif @@ -998,7 +1051,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) ret = fattr->show ? fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf) : + buf, this_leaf->cpu) : 0; return ret; } @@ -1012,7 +1065,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, ret = fattr->store ? fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf, count) : + buf, count, this_leaf->cpu) : 0; return ret; } -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-26 17:08 ` Hans Rosenfeld @ 2011-01-26 20:56 ` Ingo Molnar 2011-01-27 11:50 ` Hans Rosenfeld 0 siblings, 1 reply; 21+ messages in thread From: Ingo Molnar @ 2011-01-26 20:56 UTC (permalink / raw) To: Hans Rosenfeld; +Cc: hpa, tglx, Andreas.Herrmann3, linux-kernel, x86 * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can > be used for evictions by the L2 cache of each compute unit. By writing a > 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\ > cpuX/cache/index3/subcaches, the user can set the enabled subcaches for > a CPU. The settings are directly read from and written to the hardware, > so there is no way to have contradicting settings for two CPUs belonging > to the same compute unit. Writing will always overwrite any previous > setting for a compute unit. > > Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> > --- > arch/x86/include/asm/amd_nb.h | 3 + > arch/x86/kernel/amd_nb.c | 57 ++++++++++++++++++++++++ > arch/x86/kernel/cpu/intel_cacheinfo.c | 77 +++++++++++++++++++++++++++----- > 3 files changed, 125 insertions(+), 12 deletions(-) > > diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h > index 3e70700..423f11c 100644 > --- a/arch/x86/include/asm/amd_nb.h > +++ b/arch/x86/include/asm/amd_nb.h > @@ -18,6 +18,8 @@ extern int amd_cache_northbridges(void); > extern void amd_flush_garts(void); > extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); > extern int amd_scan_nodes(void); > +extern int amd_get_subcaches(int); > +extern int amd_set_subcaches(int, int); > > #ifdef CONFIG_NUMA_EMU > extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); > @@ -38,6 +40,7 @@ extern struct amd_northbridge_info amd_northbridges; > > #define AMD_NB_GART 0x1 > #define AMD_NB_L3_INDEX_DISABLE 0x2 > +#define AMD_NB_L3_PARTITIONING 0x4 > > #ifdef CONFIG_AMD_NB > > diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c > index 4ae9a96..63310de 100644 > --- a/arch/x86/kernel/amd_nb.c > +++ b/arch/x86/kernel/amd_nb.c > @@ -95,6 +95,10 @@ int amd_cache_northbridges(void) > if (boot_cpu_data.x86 == 0x15) > amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; > > + /* L3 cache partitioning is supported on family 0x15 */ > + if (boot_cpu_data.x86 == 0x15) > + amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; > + > return 0; > } > EXPORT_SYMBOL_GPL(amd_cache_northbridges); > @@ -112,6 +116,59 @@ int __init early_is_amd_nb(u32 device) > return 0; > } > > +#ifdef CONFIG_SMP > +int amd_get_subcaches(int cpu) Well, sprinkling it with CONFIG_SMP is pretty ugly. Also, there's no fundamental reason why this shouldnt work with UP. Yes, it makes most sense on SMP but such code should be SMP-invariant. Thanks, Ingo ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-26 20:56 ` Ingo Molnar @ 2011-01-27 11:50 ` Hans Rosenfeld 2011-01-27 12:47 ` Ingo Molnar 0 siblings, 1 reply; 21+ messages in thread From: Hans Rosenfeld @ 2011-01-27 11:50 UTC (permalink / raw) To: Ingo Molnar; +Cc: hpa, tglx, Herrmann3, Andreas, linux-kernel, x86 On Wed, Jan 26, 2011 at 03:56:08PM -0500, Ingo Molnar wrote: > * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > > +#ifdef CONFIG_SMP > > +int amd_get_subcaches(int cpu) > > Well, sprinkling it with CONFIG_SMP is pretty ugly. Also, there's no fundamental > reason why this shouldnt work with UP. Yes, it makes most sense on SMP but such code > should be SMP-invariant. True, it is pretty ugly. And while the feature is pretty useless for UP, it would still work for compute_unit_id 0 in that case. The problem is that cpuinfo_x86.compute_unit_id etc. don't exist unless CONFIG_SMP is enabled. I don't think there is any reason why this should be that way, but changing this just for this particular L3 feature seems too intrusive. Do you really want me to do that? Hans -- %SYSTEM-F-ANARCHISM, The operating system has been overthrown ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-27 11:50 ` Hans Rosenfeld @ 2011-01-27 12:47 ` Ingo Molnar 2011-02-01 15:14 ` Hans Rosenfeld 2011-02-07 17:10 ` Hans Rosenfeld 0 siblings, 2 replies; 21+ messages in thread From: Ingo Molnar @ 2011-01-27 12:47 UTC (permalink / raw) To: Hans Rosenfeld; +Cc: hpa, tglx, Herrmann3, Andreas, linux-kernel, x86 * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > On Wed, Jan 26, 2011 at 03:56:08PM -0500, Ingo Molnar wrote: > > * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote: > > > +#ifdef CONFIG_SMP > > > +int amd_get_subcaches(int cpu) > > > > Well, sprinkling it with CONFIG_SMP is pretty ugly. Also, there's no fundamental > > reason why this shouldnt work with UP. Yes, it makes most sense on SMP but such code > > should be SMP-invariant. > > True, it is pretty ugly. And while the feature is pretty useless for UP, > it would still work for compute_unit_id 0 in that case. > > The problem is that cpuinfo_x86.compute_unit_id etc. don't exist unless > CONFIG_SMP is enabled. I don't think there is any reason why this should > be that way, but changing this just for this particular L3 feature seems > too intrusive. Do you really want me to do that? All the CONFIG_X86_HT #ifdefs in arch/x86/kernel/cpu/amd.c look pretty ugly too - and it's not really a properly modularized solution. We generally want to unify the SMP and UP kernels as much as possible. 'CONFIG_SMP' is not really a property of the hardware, it's a property of the software. If some topology information should be excluded then it can already be done by turning off CONFIG_CPU_SUP_AMD under CONFIG_EXPERT. Thanks, Ingo ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-27 12:47 ` Ingo Molnar @ 2011-02-01 15:14 ` Hans Rosenfeld 2011-02-07 17:10 ` Hans Rosenfeld 1 sibling, 0 replies; 21+ messages in thread From: Hans Rosenfeld @ 2011-02-01 15:14 UTC (permalink / raw) To: Ingo Molnar; +Cc: hpa, tglx, Herrmann3, Andreas, linux-kernel, x86 On Thu, Jan 27, 2011 at 07:47:56AM -0500, Ingo Molnar wrote: > > The problem is that cpuinfo_x86.compute_unit_id etc. don't exist unless > > CONFIG_SMP is enabled. I don't think there is any reason why this should > > be that way, but changing this just for this particular L3 feature seems > > too intrusive. Do you really want me to do that? > > All the CONFIG_X86_HT #ifdefs in arch/x86/kernel/cpu/amd.c look pretty ugly too - > and it's not really a properly modularized solution. > > We generally want to unify the SMP and UP kernels as much as possible. 'CONFIG_SMP' > is not really a property of the hardware, it's a property of the software. > > If some topology information should be excluded then it can already be done by > turning off CONFIG_CPU_SUP_AMD under CONFIG_EXPERT. I see several solutions to resolve this issue: 1. Remove #ifdef CONFIG_SMP around compute_unit_id in struct cpuinfo_x86 and then use my original patch. This would work without introducing new #ifdef ugliness with the L3 cache partitioning, but it would increase #ifdef ugliness in struct cpuinfo_x86. Also, compute_unit_id would just so happen to be initialized to 0, there would be no other code using it for CONFIG_SMP. L3 cache partitioning would be the first SMP-specific feature to be available in non-SMP kernels. 2. Same as #1, but remove CONFIG_SMP completely from struct cpuinfo_x86. This would mean less #ifdef ugliness there, but then we would have a bunch of unused fields in there in non-SMP kernels, which would also just be initialized to 0. I don't think that would be correct for booted_cores, but as it is unused I don't see an immediate problem with that. Of course, this is also neither correct nor less ugly. 3. Same as #2, but also rework all code using those fields to be usable on non-SMP kernels. This would be essentially a rework of all that CONFIG_SMP stuff, and I think thats too much to ask for just for a little extra L3 feature. Maybe I'm missing something here, but I don't see how this could be done cleanly in any other way at this time. Of course, you could just take the modified patch I sent you. That would be ugly, but not more so than the existing code. If this is not acceptable, please tell me which of the other two ugly solutions you would prefer. Hans -- %SYSTEM-F-ANARCHISM, The operating system has been overthrown ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-01-27 12:47 ` Ingo Molnar 2011-02-01 15:14 ` Hans Rosenfeld @ 2011-02-07 17:10 ` Hans Rosenfeld 2011-02-08 12:03 ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld 1 sibling, 1 reply; 21+ messages in thread From: Hans Rosenfeld @ 2011-02-07 17:10 UTC (permalink / raw) To: mingo; +Cc: hpa, tglx, Andreas.Herrmann3, linux-kernel, x86, Hans Rosenfeld L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can be used for evictions by the L2 cache of each compute unit. By writing a 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/\ cpuX/cache/index3/subcaches, the user can set the enabled subcaches for a CPU. The settings are directly read from and written to the hardware, so there is no way to have contradicting settings for two CPUs belonging to the same compute unit. Writing will always overwrite any previous setting for a compute unit. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> --- arch/x86/include/asm/amd_nb.h | 3 + arch/x86/kernel/amd_nb.c | 63 ++++++++++++++++++++++++++++ arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++----- 3 files changed, 127 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 3e70700..423f11c 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -18,6 +18,8 @@ extern int amd_cache_northbridges(void); extern void amd_flush_garts(void); extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); extern int amd_scan_nodes(void); +extern int amd_get_subcaches(int); +extern int amd_set_subcaches(int, int); #ifdef CONFIG_NUMA_EMU extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); @@ -38,6 +40,7 @@ extern struct amd_northbridge_info amd_northbridges; #define AMD_NB_GART 0x1 #define AMD_NB_L3_INDEX_DISABLE 0x2 +#define AMD_NB_L3_PARTITIONING 0x4 #ifdef CONFIG_AMD_NB diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 4ae9a96..bf79a4a 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -95,6 +95,10 @@ int amd_cache_northbridges(void) if (boot_cpu_data.x86 == 0x15) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + /* L3 cache partitioning is supported on family 0x15 */ + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); @@ -112,6 +116,65 @@ int __init early_is_amd_nb(u32 device) return 0; } +int amd_get_subcaches(int cpu) +{ + struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; + unsigned int mask; + int cuid = 0; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return 0; + + pci_read_config_dword(link, 0x1d4, &mask); + +#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +#endif + return (mask >> (4 * cuid)) & 0xf; +} + +int amd_set_subcaches(int cpu, int mask) +{ + static unsigned int reset, ban; + struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); + unsigned int reg; + int cuid = 0; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) + return -EINVAL; + + /* if necessary, collect reset state of L3 partitioning and BAN mode */ + if (reset == 0) { + pci_read_config_dword(nb->link, 0x1d4, &reset); + pci_read_config_dword(nb->misc, 0x1b8, &ban); + ban &= 0x180000; + } + + /* deactivate BAN mode if any subcaches are to be disabled */ + if (mask != 0xf) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); + } + +#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +#endif + mask <<= 4 * cuid; + mask |= (0xf ^ (1 << cuid)) << 26; + + pci_write_config_dword(nb->link, 0x1d4, mask); + + /* reset BAN mode if L3 partitioning returned to reset state */ + pci_read_config_dword(nb->link, 0x1d4, ®); + if (reg == reset) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + reg &= ~0x180000; + pci_write_config_dword(nb->misc, 0x1b8, reg | ban); + } + + return 0; +} + int amd_cache_gart(void) { int i; diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index ec2c19a..4017a61 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -304,8 +304,9 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, struct _cache_attr { struct attribute attr; - ssize_t (*show)(struct _cpuid4_info *, char *); - ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count); + ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int); + ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count, + unsigned int); }; #ifdef CONFIG_AMD_NB @@ -400,7 +401,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf, #define SHOW_CACHE_DISABLE(slot) \ static ssize_t \ -show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \ +show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return show_cache_disable(this_leaf, buf, slot); \ } @@ -512,7 +514,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, #define STORE_CACHE_DISABLE(slot) \ static ssize_t \ store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \ - const char *buf, size_t count) \ + const char *buf, size_t count, \ + unsigned int cpu) \ { \ return store_cache_disable(this_leaf, buf, count, slot); \ } @@ -524,6 +527,41 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, show_cache_disable_1, store_cache_disable_1); +static ssize_t +show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu) +{ + if (!this_leaf->l3 || + !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); +} + +static ssize_t +store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count, + unsigned int cpu) +{ + unsigned long val; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (!this_leaf->l3 || + !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + if (strict_strtoul(buf, 16, &val) < 0) + return -EINVAL; + + if (amd_set_subcaches(cpu, val)) + return -EINVAL; + + return count; +} + +static struct _cache_attr subcaches = + __ATTR(subcaches, 0644, show_subcaches, store_subcaches); + #else /* CONFIG_AMD_NB */ #define amd_init_l3_cache(x, y) #endif /* CONFIG_AMD_NB */ @@ -870,8 +908,8 @@ static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject); #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y])) #define show_one_plus(file_name, object, val) \ -static ssize_t show_##file_name \ - (struct _cpuid4_info *this_leaf, char *buf) \ +static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \ } @@ -882,7 +920,8 @@ show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1); show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1); show_one_plus(number_of_sets, ecx.split.number_of_sets, 1); -static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { return sprintf(buf, "%luK\n", this_leaf->size / 1024); } @@ -906,17 +945,20 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, return n; } -static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 0, buf); } -static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 1, buf); } -static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { switch (this_leaf->eax.split.type) { case CACHE_TYPE_DATA: @@ -974,6 +1016,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) n += 2; + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + n += 1; + attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL); if (attrs == NULL) return attrs = default_attrs; @@ -986,6 +1031,10 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) attrs[n++] = &cache_disable_1.attr; } + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) { + attrs[n++] = &subcaches.attr; + } + return attrs; } #endif @@ -998,7 +1047,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) ret = fattr->show ? fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf) : + buf, this_leaf->cpu) : 0; return ret; } @@ -1012,7 +1061,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, ret = fattr->store ? fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf, count) : + buf, count, this_leaf->cpu) : 0; return ret; } -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [tip:x86/amd-nb] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs 2011-02-07 17:10 ` Hans Rosenfeld @ 2011-02-08 12:03 ` tip-bot for Hans Rosenfeld 0 siblings, 0 replies; 21+ messages in thread From: tip-bot for Hans Rosenfeld @ 2011-02-08 12:03 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hans.rosenfeld, hpa, mingo, Andreas.Herrmann3, tglx, mingo Commit-ID: cabb5bd7ff4d6963ec9e67f958fc30e7815425e6 Gitweb: http://git.kernel.org/tip/cabb5bd7ff4d6963ec9e67f958fc30e7815425e6 Author: Hans Rosenfeld <hans.rosenfeld@amd.com> AuthorDate: Mon, 7 Feb 2011 18:10:39 +0100 Committer: Ingo Molnar <mingo@elte.hu> CommitDate: Mon, 7 Feb 2011 19:16:22 +0100 x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs L3 Cache Partitioning allows selecting which of the 4 L3 subcaches can be used for evictions by the L2 cache of each compute unit. By writing a 4-bit hexadecimal mask into the the sysfs file /sys/devices/system/cpu/cpuX/cache/index3/subcaches, the user can set the enabled subcaches for a CPU. The settings are directly read from and written to the hardware, so there is no way to have contradicting settings for two CPUs belonging to the same compute unit. Writing will always overwrite any previous setting for a compute unit. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <Andreas.Herrmann3@amd.com> LKML-Reference: <1297098639-431383-1-git-send-email-hans.rosenfeld@amd.com> [ -v3: minor style fixes ] Signed-off-by: Ingo Molnar <mingo@elte.hu> --- arch/x86/include/asm/amd_nb.h | 3 + arch/x86/kernel/amd_nb.c | 63 +++++++++++++++++++++++++++ arch/x86/kernel/cpu/intel_cacheinfo.c | 76 ++++++++++++++++++++++++++------ 3 files changed, 127 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 3e70700..423f11c 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -18,6 +18,8 @@ extern int amd_cache_northbridges(void); extern void amd_flush_garts(void); extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn); extern int amd_scan_nodes(void); +extern int amd_get_subcaches(int); +extern int amd_set_subcaches(int, int); #ifdef CONFIG_NUMA_EMU extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes); @@ -38,6 +40,7 @@ extern struct amd_northbridge_info amd_northbridges; #define AMD_NB_GART 0x1 #define AMD_NB_L3_INDEX_DISABLE 0x2 +#define AMD_NB_L3_PARTITIONING 0x4 #ifdef CONFIG_AMD_NB diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 4ae9a96..bf79a4a 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -95,6 +95,10 @@ int amd_cache_northbridges(void) if (boot_cpu_data.x86 == 0x15) amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE; + /* L3 cache partitioning is supported on family 0x15 */ + if (boot_cpu_data.x86 == 0x15) + amd_northbridges.flags |= AMD_NB_L3_PARTITIONING; + return 0; } EXPORT_SYMBOL_GPL(amd_cache_northbridges); @@ -112,6 +116,65 @@ int __init early_is_amd_nb(u32 device) return 0; } +int amd_get_subcaches(int cpu) +{ + struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; + unsigned int mask; + int cuid = 0; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return 0; + + pci_read_config_dword(link, 0x1d4, &mask); + +#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +#endif + return (mask >> (4 * cuid)) & 0xf; +} + +int amd_set_subcaches(int cpu, int mask) +{ + static unsigned int reset, ban; + struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu)); + unsigned int reg; + int cuid = 0; + + if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) + return -EINVAL; + + /* if necessary, collect reset state of L3 partitioning and BAN mode */ + if (reset == 0) { + pci_read_config_dword(nb->link, 0x1d4, &reset); + pci_read_config_dword(nb->misc, 0x1b8, &ban); + ban &= 0x180000; + } + + /* deactivate BAN mode if any subcaches are to be disabled */ + if (mask != 0xf) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); + } + +#ifdef CONFIG_SMP + cuid = cpu_data(cpu).compute_unit_id; +#endif + mask <<= 4 * cuid; + mask |= (0xf ^ (1 << cuid)) << 26; + + pci_write_config_dword(nb->link, 0x1d4, mask); + + /* reset BAN mode if L3 partitioning returned to reset state */ + pci_read_config_dword(nb->link, 0x1d4, ®); + if (reg == reset) { + pci_read_config_dword(nb->misc, 0x1b8, ®); + reg &= ~0x180000; + pci_write_config_dword(nb->misc, 0x1b8, reg | ban); + } + + return 0; +} + int amd_cache_gart(void) { int i; diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index ec2c19a..90cc675 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -304,8 +304,9 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, struct _cache_attr { struct attribute attr; - ssize_t (*show)(struct _cpuid4_info *, char *); - ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count); + ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int); + ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count, + unsigned int); }; #ifdef CONFIG_AMD_NB @@ -400,7 +401,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf, #define SHOW_CACHE_DISABLE(slot) \ static ssize_t \ -show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \ +show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return show_cache_disable(this_leaf, buf, slot); \ } @@ -512,7 +514,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, #define STORE_CACHE_DISABLE(slot) \ static ssize_t \ store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \ - const char *buf, size_t count) \ + const char *buf, size_t count, \ + unsigned int cpu) \ { \ return store_cache_disable(this_leaf, buf, count, slot); \ } @@ -524,6 +527,39 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, show_cache_disable_1, store_cache_disable_1); +static ssize_t +show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu) +{ + if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); +} + +static ssize_t +store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count, + unsigned int cpu) +{ + unsigned long val; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + return -EINVAL; + + if (strict_strtoul(buf, 16, &val) < 0) + return -EINVAL; + + if (amd_set_subcaches(cpu, val)) + return -EINVAL; + + return count; +} + +static struct _cache_attr subcaches = + __ATTR(subcaches, 0644, show_subcaches, store_subcaches); + #else /* CONFIG_AMD_NB */ #define amd_init_l3_cache(x, y) #endif /* CONFIG_AMD_NB */ @@ -532,9 +568,9 @@ static int __cpuinit cpuid4_cache_lookup_regs(int index, struct _cpuid4_info_regs *this_leaf) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + union _cpuid4_leaf_eax eax; + union _cpuid4_leaf_ebx ebx; + union _cpuid4_leaf_ecx ecx; unsigned edx; if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { @@ -870,8 +906,8 @@ static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject); #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y])) #define show_one_plus(file_name, object, val) \ -static ssize_t show_##file_name \ - (struct _cpuid4_info *this_leaf, char *buf) \ +static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \ + unsigned int cpu) \ { \ return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \ } @@ -882,7 +918,8 @@ show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1); show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1); show_one_plus(number_of_sets, ecx.split.number_of_sets, 1); -static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { return sprintf(buf, "%luK\n", this_leaf->size / 1024); } @@ -906,17 +943,20 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, return n; } -static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 0, buf); } -static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf) +static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf, + unsigned int cpu) { return show_shared_cpu_map_func(leaf, 1, buf); } -static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) +static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf, + unsigned int cpu) { switch (this_leaf->eax.split.type) { case CACHE_TYPE_DATA: @@ -974,6 +1014,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) n += 2; + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + n += 1; + attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL); if (attrs == NULL) return attrs = default_attrs; @@ -986,6 +1029,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) attrs[n++] = &cache_disable_1.attr; } + if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING)) + attrs[n++] = &subcaches.attr; + return attrs; } #endif @@ -998,7 +1044,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) ret = fattr->show ? fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf) : + buf, this_leaf->cpu) : 0; return ret; } @@ -1012,7 +1058,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr, ret = fattr->store ? fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index), - buf, count) : + buf, count, this_leaf->cpu) : 0; return ret; } ^ permalink raw reply related [flat|nested] 21+ messages in thread
end of thread, other threads:[~2011-02-15 3:10 UTC | newest] Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld 2011-01-26 10:57 ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann 2011-02-14 14:30 ` Ingo Molnar 2011-02-14 17:14 ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov 2011-02-15 3:10 ` [tip:x86/amd-nb] x86, amd: Initialize variable properly tip-bot for Borislav Petkov 2011-02-04 22:07 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton 2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld 2011-01-26 10:58 ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld 2011-01-26 10:58 ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld 2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld 2011-01-26 10:56 ` Ingo Molnar 2011-01-26 17:05 ` Hans Rosenfeld 2011-01-26 17:08 ` Hans Rosenfeld 2011-01-26 20:56 ` Ingo Molnar 2011-01-27 11:50 ` Hans Rosenfeld 2011-01-27 12:47 ` Ingo Molnar 2011-02-01 15:14 ` Hans Rosenfeld 2011-02-07 17:10 ` Hans Rosenfeld 2011-02-08 12:03 ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
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