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From: Christoffer Dall <christoffer.dall@linaro.org>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Subject: Re: [PATCH v3 15/55] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection
Date: Tue, 10 May 2016 14:08:06 +0200	[thread overview]
Message-ID: <20160510120806.GC27623@cbox> (raw)
In-Reply-To: <1462531568-9799-16-git-send-email-andre.przywara@arm.com>

On Fri, May 06, 2016 at 11:45:28AM +0100, Andre Przywara wrote:
> From: Christoffer Dall <christoffer.dall@linaro.org>
> 
> Provide a vgic_queue_irq() function which decides whether a given
> IRQ needs to be queued to a VCPU's ap_list.
> This should be called whenever an IRQ becomes pending or enabled,
> either as a result of userspace injection, from in-kernel emulated
> devices like the architected timer or from MMIO accesses to the
> distributor emulation.
> Also provides the necessary functions to allow userland to inject an
> IRQ to a guest.
> Since this is the first code that starts using our locking mechanism, we
> add some (hopefully) clear documentation of our locking strategy and
> requirements along with this patch.
> 
> [Andre: refactor out vgic_queue_irq_unlock()]
> 
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changelog RFC..v1:
> - add spinlock checks protected by CONFIG_DEBUG_SPINLOCK
> - add more comments to vgic_target_oracle
> - remove BUG_ON() if IRQ is neither edge or level
> - rename vgic_queue_irq() to vgic_queue_irq_unlock()
> - simplify initial check in vgic_queue_irq_unlock()
> - extend retry loop to ask the oracle again
> - minor comment fixes
> 
> Changelog v1 .. v2:
> - move most IRQ injection code into vgic_update_irq_pending()
> 
>  include/kvm/vgic/vgic.h  |   3 +
>  virt/kvm/arm/vgic/vgic.c | 209 +++++++++++++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic.h |   1 +
>  3 files changed, 213 insertions(+)
> 
> diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
> index 39933ee..2bfb42c 100644
> --- a/include/kvm/vgic/vgic.h
> +++ b/include/kvm/vgic/vgic.h
> @@ -181,6 +181,9 @@ struct vgic_cpu {
>  	u64 live_lrs;
>  };
>  
> +int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
> +			bool level);
> +
>  #define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
>  #define vgic_initialized(k)	(false)
>  #define vgic_ready(k)		((k)->arch.vgic.ready)
> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
> index fb45537..92b78a0 100644
> --- a/virt/kvm/arm/vgic/vgic.c
> +++ b/virt/kvm/arm/vgic/vgic.c
> @@ -19,8 +19,31 @@
>  
>  #include "vgic.h"
>  
> +#define CREATE_TRACE_POINTS
> +#include "../trace.h"
> +
> +#ifdef CONFIG_DEBUG_SPINLOCK
> +#define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
> +#else
> +#define DEBUG_SPINLOCK_BUG_ON(p)
> +#endif
> +
>  struct vgic_global __section(.hyp.text) kvm_vgic_global_state;
>  
> +/*
> + * Locking order is always:
> + *   vgic_cpu->ap_list_lock
> + *     vgic_irq->irq_lock
> + *
> + * (that is, always take the ap_list_lock before the struct vgic_irq lock).
> + *
> + * When taking more than one ap_list_lock at the same time, always take the
> + * lowest numbered VCPU's ap_list_lock first, so:
> + *   vcpuX->vcpu_id < vcpuY->vcpu_id:
> + *     spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock);
> + *     spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock);
> + */
> +
>  struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  			      u32 intid)
>  {
> @@ -39,3 +62,189 @@ struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  	WARN(1, "Looking up struct vgic_irq for reserved INTID");
>  	return NULL;
>  }
> +
> +/**
> + * kvm_vgic_target_oracle - compute the target vcpu for an irq
> + *
> + * @irq:	The irq to route. Must be already locked.
> + *
> + * Based on the current state of the interrupt (enabled, pending,
> + * active, vcpu and target_vcpu), compute the next vcpu this should be
> + * given to. Return NULL if this shouldn't be injected at all.
> + *
> + * Requires the IRQ lock to be held.
> + */
> +static struct kvm_vcpu *vgic_target_oracle(struct vgic_irq *irq)
> +{
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
> +
> +	/* If the interrupt is active, it must stay on the current vcpu */
> +	if (irq->active)
> +		return irq->vcpu;
> +
> +	/*
> +	 * If the IRQ is not active but enabled and pending, we should direct
> +	 * it to its configured target VCPU.
> +	 */
> +	if (irq->enabled && irq->pending)
> +		return irq->target_vcpu;
> +
> +	/* If neither active nor pending and enabled, then this IRQ should not
> +	 * be queued to any VCPU.
> +	 */
> +	return NULL;
> +}
> +
> +/*
> + * Only valid injection if changing level for level-triggered IRQs or for a
> + * rising edge.
> + */
> +static bool vgic_validate_injection(struct vgic_irq *irq, bool level)
> +{
> +	switch (irq->config) {
> +	case VGIC_CONFIG_LEVEL:
> +		return irq->line_level != level;
> +	case VGIC_CONFIG_EDGE:
> +		return level;
> +	}
> +
> +	return false;
> +}
> +
> +/*
> + * Check whether an IRQ needs to (and can) be queued to a VCPU's ap list.
> + * Do the queuing if necessary, taking the right locks in the right order.
> + * Returns true when the IRQ was queued, false otherwise.
> + *
> + * Needs to be entered with the IRQ lock already held, but will return
> + * with all locks dropped.
> + */
> +bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq)
> +{
> +	struct kvm_vcpu *vcpu;
> +
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
> +
> +retry:
> +	vcpu = vgic_target_oracle(irq);
> +	if (irq->vcpu || !vcpu) {
> +		/*
> +		 * If this IRQ is already on a VCPU's ap_list, then it
> +		 * cannot be moved or modified and there is no more work for
> +		 * us to do.
> +		 *
> +		 * Otherwise, if the irq is not pending and enabled, it does
> +		 * not need to be inserted into an ap_list and there is also
> +		 * no more work for us to do.
> +		 */
> +		spin_unlock(&irq->irq_lock);
> +		return false;
> +	}
> +
> +	/*
> +	 * We must unlock the irq lock to take the ap_list_lock where
> +	 * we are going to insert this new pending interrupt.
> +	 */
> +	spin_unlock(&irq->irq_lock);
> +
> +	/* someone can do stuff here, which we re-check below */
> +
> +	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +	spin_lock(&irq->irq_lock);
> +
> +	/*
> +	 * Did something change behind our backs?
> +	 *
> +	 * There are two cases:
> +	 * 1) The irq became pending or active behind our backs and/or

but you're not checking the active state below?

so did you mean 'became pending and enabled' ?

> +	 *    the irq->vcpu field was set correspondingly when putting
> +	 *    the irq on an ap_list. Then drop the locks and return.
> +	 * 2) Someone changed the affinity on this irq behind our
> +	 *    backs and we are now holding the wrong ap_list_lock.
> +	 *    Then drop the locks and try the new VCPU.
> +	 */

I thought we agreed a long time ago to change this to:

        if (unlinkely(irq->vcpu || vcpu != vgic_target_oracle(irq))) {
		spin_unlock(&irq->irq_lock);
		spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
	
		spin_lock(&irq->irq_lock);
		goto retry;
	}

and get rid of two different if statements below ??

At least I don't understand why we are explicitly evaluating
!(irq->pending && irq->enabled) here, but using the oracle above?

In fact, I think if you did what I suggest above, then you can reuse
this for the active state, which frankly looks more complicated than we
had hoped for...

> +	if (irq->vcpu || !(irq->pending && irq->enabled)) {
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +		return false;
> +	}
> +
> +	if (irq->target_vcpu != vcpu) {
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +
> +		spin_lock(&irq->irq_lock);
> +		goto retry;
> +	}
> +
> +	list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head);
> +	irq->vcpu = vcpu;
> +
> +	spin_unlock(&irq->irq_lock);
> +	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +
> +	kvm_vcpu_kick(vcpu);
> +
> +	return true;
> +}
> +
> +static int vgic_update_irq_pending(struct kvm *kvm, int cpuid,
> +				   unsigned int intid, bool level,
> +				   bool mapped_irq)
> +{
> +	struct kvm_vcpu *vcpu;
> +	struct vgic_irq *irq;
> +	int ret;
> +
> +	trace_vgic_update_irq_pending(cpuid, intid, level);
> +
> +	vcpu = kvm_get_vcpu(kvm, cpuid);
> +	if (!vcpu && intid < VGIC_NR_PRIVATE_IRQS)
> +		return -EINVAL;
> +
> +	irq = vgic_get_irq(kvm, vcpu, intid);
> +	if (!irq)
> +		return -EINVAL;
> +
> +	if (irq->hw != mapped_irq)
> +		return -EINVAL;
> +
> +	spin_lock(&irq->irq_lock);
> +
> +	if (!vgic_validate_injection(irq, level)) {
> +		/* Nothing to see here, move along... */
> +		spin_unlock(&irq->irq_lock);
> +		return 0;
> +	}
> +
> +	if (irq->config == VGIC_CONFIG_LEVEL) {
> +		irq->line_level = level;
> +		irq->pending = level || irq->soft_pending;
> +	} else {
> +		irq->pending = true;
> +	}
> +
> +	vgic_queue_irq_unlock(kvm, irq);
> +
> +	return 0;
> +}
> +
> +/**
> + * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
> + * @kvm:     The VM structure pointer
> + * @cpuid:   The CPU for PPIs
> + * @intid:   The INTID to inject a new state to.
> + * @level:   Edge-triggered:  true:  to trigger the interrupt
> + *			      false: to ignore the call
> + *	     Level-sensitive  true:  raise the input signal
> + *			      false: lower the input signal
> + *
> + * The VGIC is not concerned with devices being active-LOW or active-HIGH for
> + * level-sensitive interrupts.  You can think of the level parameter as 1
> + * being HIGH and 0 being LOW and all devices being active-HIGH.
> + */
> +int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
> +			bool level)
> +{
> +	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
> +}
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index 61b8d22..c625767 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -18,5 +18,6 @@
>  
>  struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  			      u32 intid);
> +bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
>  
>  #endif
> -- 
> 2.7.3
> 

WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 15/55] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection
Date: Tue, 10 May 2016 14:08:06 +0200	[thread overview]
Message-ID: <20160510120806.GC27623@cbox> (raw)
In-Reply-To: <1462531568-9799-16-git-send-email-andre.przywara@arm.com>

On Fri, May 06, 2016 at 11:45:28AM +0100, Andre Przywara wrote:
> From: Christoffer Dall <christoffer.dall@linaro.org>
> 
> Provide a vgic_queue_irq() function which decides whether a given
> IRQ needs to be queued to a VCPU's ap_list.
> This should be called whenever an IRQ becomes pending or enabled,
> either as a result of userspace injection, from in-kernel emulated
> devices like the architected timer or from MMIO accesses to the
> distributor emulation.
> Also provides the necessary functions to allow userland to inject an
> IRQ to a guest.
> Since this is the first code that starts using our locking mechanism, we
> add some (hopefully) clear documentation of our locking strategy and
> requirements along with this patch.
> 
> [Andre: refactor out vgic_queue_irq_unlock()]
> 
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changelog RFC..v1:
> - add spinlock checks protected by CONFIG_DEBUG_SPINLOCK
> - add more comments to vgic_target_oracle
> - remove BUG_ON() if IRQ is neither edge or level
> - rename vgic_queue_irq() to vgic_queue_irq_unlock()
> - simplify initial check in vgic_queue_irq_unlock()
> - extend retry loop to ask the oracle again
> - minor comment fixes
> 
> Changelog v1 .. v2:
> - move most IRQ injection code into vgic_update_irq_pending()
> 
>  include/kvm/vgic/vgic.h  |   3 +
>  virt/kvm/arm/vgic/vgic.c | 209 +++++++++++++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic.h |   1 +
>  3 files changed, 213 insertions(+)
> 
> diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
> index 39933ee..2bfb42c 100644
> --- a/include/kvm/vgic/vgic.h
> +++ b/include/kvm/vgic/vgic.h
> @@ -181,6 +181,9 @@ struct vgic_cpu {
>  	u64 live_lrs;
>  };
>  
> +int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
> +			bool level);
> +
>  #define irqchip_in_kernel(k)	(!!((k)->arch.vgic.in_kernel))
>  #define vgic_initialized(k)	(false)
>  #define vgic_ready(k)		((k)->arch.vgic.ready)
> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
> index fb45537..92b78a0 100644
> --- a/virt/kvm/arm/vgic/vgic.c
> +++ b/virt/kvm/arm/vgic/vgic.c
> @@ -19,8 +19,31 @@
>  
>  #include "vgic.h"
>  
> +#define CREATE_TRACE_POINTS
> +#include "../trace.h"
> +
> +#ifdef CONFIG_DEBUG_SPINLOCK
> +#define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
> +#else
> +#define DEBUG_SPINLOCK_BUG_ON(p)
> +#endif
> +
>  struct vgic_global __section(.hyp.text) kvm_vgic_global_state;
>  
> +/*
> + * Locking order is always:
> + *   vgic_cpu->ap_list_lock
> + *     vgic_irq->irq_lock
> + *
> + * (that is, always take the ap_list_lock before the struct vgic_irq lock).
> + *
> + * When taking more than one ap_list_lock at the same time, always take the
> + * lowest numbered VCPU's ap_list_lock first, so:
> + *   vcpuX->vcpu_id < vcpuY->vcpu_id:
> + *     spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock);
> + *     spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock);
> + */
> +
>  struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  			      u32 intid)
>  {
> @@ -39,3 +62,189 @@ struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  	WARN(1, "Looking up struct vgic_irq for reserved INTID");
>  	return NULL;
>  }
> +
> +/**
> + * kvm_vgic_target_oracle - compute the target vcpu for an irq
> + *
> + * @irq:	The irq to route. Must be already locked.
> + *
> + * Based on the current state of the interrupt (enabled, pending,
> + * active, vcpu and target_vcpu), compute the next vcpu this should be
> + * given to. Return NULL if this shouldn't be injected at all.
> + *
> + * Requires the IRQ lock to be held.
> + */
> +static struct kvm_vcpu *vgic_target_oracle(struct vgic_irq *irq)
> +{
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
> +
> +	/* If the interrupt is active, it must stay on the current vcpu */
> +	if (irq->active)
> +		return irq->vcpu;
> +
> +	/*
> +	 * If the IRQ is not active but enabled and pending, we should direct
> +	 * it to its configured target VCPU.
> +	 */
> +	if (irq->enabled && irq->pending)
> +		return irq->target_vcpu;
> +
> +	/* If neither active nor pending and enabled, then this IRQ should not
> +	 * be queued to any VCPU.
> +	 */
> +	return NULL;
> +}
> +
> +/*
> + * Only valid injection if changing level for level-triggered IRQs or for a
> + * rising edge.
> + */
> +static bool vgic_validate_injection(struct vgic_irq *irq, bool level)
> +{
> +	switch (irq->config) {
> +	case VGIC_CONFIG_LEVEL:
> +		return irq->line_level != level;
> +	case VGIC_CONFIG_EDGE:
> +		return level;
> +	}
> +
> +	return false;
> +}
> +
> +/*
> + * Check whether an IRQ needs to (and can) be queued to a VCPU's ap list.
> + * Do the queuing if necessary, taking the right locks in the right order.
> + * Returns true when the IRQ was queued, false otherwise.
> + *
> + * Needs to be entered with the IRQ lock already held, but will return
> + * with all locks dropped.
> + */
> +bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq)
> +{
> +	struct kvm_vcpu *vcpu;
> +
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
> +
> +retry:
> +	vcpu = vgic_target_oracle(irq);
> +	if (irq->vcpu || !vcpu) {
> +		/*
> +		 * If this IRQ is already on a VCPU's ap_list, then it
> +		 * cannot be moved or modified and there is no more work for
> +		 * us to do.
> +		 *
> +		 * Otherwise, if the irq is not pending and enabled, it does
> +		 * not need to be inserted into an ap_list and there is also
> +		 * no more work for us to do.
> +		 */
> +		spin_unlock(&irq->irq_lock);
> +		return false;
> +	}
> +
> +	/*
> +	 * We must unlock the irq lock to take the ap_list_lock where
> +	 * we are going to insert this new pending interrupt.
> +	 */
> +	spin_unlock(&irq->irq_lock);
> +
> +	/* someone can do stuff here, which we re-check below */
> +
> +	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +	spin_lock(&irq->irq_lock);
> +
> +	/*
> +	 * Did something change behind our backs?
> +	 *
> +	 * There are two cases:
> +	 * 1) The irq became pending or active behind our backs and/or

but you're not checking the active state below?

so did you mean 'became pending and enabled' ?

> +	 *    the irq->vcpu field was set correspondingly when putting
> +	 *    the irq on an ap_list. Then drop the locks and return.
> +	 * 2) Someone changed the affinity on this irq behind our
> +	 *    backs and we are now holding the wrong ap_list_lock.
> +	 *    Then drop the locks and try the new VCPU.
> +	 */

I thought we agreed a long time ago to change this to:

        if (unlinkely(irq->vcpu || vcpu != vgic_target_oracle(irq))) {
		spin_unlock(&irq->irq_lock);
		spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
	
		spin_lock(&irq->irq_lock);
		goto retry;
	}

and get rid of two different if statements below ??

At least I don't understand why we are explicitly evaluating
!(irq->pending && irq->enabled) here, but using the oracle above?

In fact, I think if you did what I suggest above, then you can reuse
this for the active state, which frankly looks more complicated than we
had hoped for...

> +	if (irq->vcpu || !(irq->pending && irq->enabled)) {
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +		return false;
> +	}
> +
> +	if (irq->target_vcpu != vcpu) {
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +
> +		spin_lock(&irq->irq_lock);
> +		goto retry;
> +	}
> +
> +	list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head);
> +	irq->vcpu = vcpu;
> +
> +	spin_unlock(&irq->irq_lock);
> +	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +
> +	kvm_vcpu_kick(vcpu);
> +
> +	return true;
> +}
> +
> +static int vgic_update_irq_pending(struct kvm *kvm, int cpuid,
> +				   unsigned int intid, bool level,
> +				   bool mapped_irq)
> +{
> +	struct kvm_vcpu *vcpu;
> +	struct vgic_irq *irq;
> +	int ret;
> +
> +	trace_vgic_update_irq_pending(cpuid, intid, level);
> +
> +	vcpu = kvm_get_vcpu(kvm, cpuid);
> +	if (!vcpu && intid < VGIC_NR_PRIVATE_IRQS)
> +		return -EINVAL;
> +
> +	irq = vgic_get_irq(kvm, vcpu, intid);
> +	if (!irq)
> +		return -EINVAL;
> +
> +	if (irq->hw != mapped_irq)
> +		return -EINVAL;
> +
> +	spin_lock(&irq->irq_lock);
> +
> +	if (!vgic_validate_injection(irq, level)) {
> +		/* Nothing to see here, move along... */
> +		spin_unlock(&irq->irq_lock);
> +		return 0;
> +	}
> +
> +	if (irq->config == VGIC_CONFIG_LEVEL) {
> +		irq->line_level = level;
> +		irq->pending = level || irq->soft_pending;
> +	} else {
> +		irq->pending = true;
> +	}
> +
> +	vgic_queue_irq_unlock(kvm, irq);
> +
> +	return 0;
> +}
> +
> +/**
> + * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
> + * @kvm:     The VM structure pointer
> + * @cpuid:   The CPU for PPIs
> + * @intid:   The INTID to inject a new state to.
> + * @level:   Edge-triggered:  true:  to trigger the interrupt
> + *			      false: to ignore the call
> + *	     Level-sensitive  true:  raise the input signal
> + *			      false: lower the input signal
> + *
> + * The VGIC is not concerned with devices being active-LOW or active-HIGH for
> + * level-sensitive interrupts.  You can think of the level parameter as 1
> + * being HIGH and 0 being LOW and all devices being active-HIGH.
> + */
> +int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
> +			bool level)
> +{
> +	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
> +}
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index 61b8d22..c625767 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -18,5 +18,6 @@
>  
>  struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  			      u32 intid);
> +bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
>  
>  #endif
> -- 
> 2.7.3
> 

  parent reply	other threads:[~2016-05-10 12:08 UTC|newest]

Thread overview: 400+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-06 10:45 [PATCH v3 00/55] KVM: arm/arm64: Rework virtual GIC emulation Andre Przywara
2016-05-06 10:45 ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 01/55] KVM: arm/arm64: vgic: streamline vgic_update_irq_pending() interface Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 02/55] KVM: arm/arm64: vgic: avoid map in kvm_vgic_inject_mapped_irq() Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 03/55] KVM: arm/arm64: vgic: avoid map in kvm_vgic_map_is_active() Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 04/55] KVM: arm/arm64: vgic: avoid map in kvm_vgic_unmap_phys_irq() Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 05/55] KVM: arm/arm64: Remove the IRQ field from struct irq_phys_map Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 06/55] KVM: arm/arm64: arch_timer: Remove irq_phys_map Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  8:33   ` Eric Auger
2016-05-10  8:33     ` Eric Auger
2016-05-06 10:45 ` [PATCH v3 07/55] KVM: arm/arm64: vgic: Remove irq_phys_map from interface Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 08/55] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-18 10:43   ` Andre Przywara
2016-05-18 10:43     ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 09/55] KVM: arm/arm64: Fix MMIO emulation data handling Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  8:57   ` Marc Zyngier
2016-05-10  8:57     ` Marc Zyngier
2016-05-18 11:02   ` Andre Przywara
2016-05-18 11:02     ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 10/55] KVM: arm/arm64: Export mmio_read/write_bus Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  8:59   ` Marc Zyngier
2016-05-10  8:59     ` Marc Zyngier
2016-05-18 14:18   ` Andre Przywara
2016-05-18 14:18     ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 11/55] KVM: arm/arm64: pmu: abstract access to number of SPIs Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:00   ` Marc Zyngier
2016-05-10  9:00     ` Marc Zyngier
2016-05-10  9:52   ` Eric Auger
2016-05-10  9:52     ` Eric Auger
2016-05-10 10:04     ` Marc Zyngier
2016-05-10 10:04       ` Marc Zyngier
2016-05-10 14:35     ` [PATCH v3a] " Andre Przywara
2016-05-10 14:35       ` Andre Przywara
2016-05-10 14:58       ` Andrew Jones
2016-05-10 14:58         ` Andrew Jones
2016-05-11 13:52         ` Andre Przywara
2016-05-11 13:52           ` Andre Przywara
2016-05-10 15:22       ` Marc Zyngier
2016-05-10 15:22         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 12/55] KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:02   ` Marc Zyngier
2016-05-10  9:02     ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:05   ` Marc Zyngier
2016-05-10  9:05     ` Marc Zyngier
2016-05-12 12:12   ` Christoffer Dall
2016-05-12 12:12     ` Christoffer Dall
2016-05-12 12:17     ` Marc Zyngier
2016-05-12 12:17       ` Marc Zyngier
2016-05-12 12:23       ` Christoffer Dall
2016-05-12 12:23         ` Christoffer Dall
2016-05-12 13:25     ` Andre Przywara
2016-05-12 13:25       ` Andre Przywara
2016-05-12 13:48       ` Christoffer Dall
2016-05-12 13:48         ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 14/55] KVM: arm/arm64: vgic-new: Add acccessor to new struct vgic_irq instance Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:22   ` Marc Zyngier
2016-05-10  9:22     ` Marc Zyngier
2016-05-11  9:20     ` Andre Przywara
2016-05-11  9:20       ` Andre Przywara
2016-05-10  9:35   ` Eric Auger
2016-05-10  9:35     ` Eric Auger
2016-05-06 10:45 ` [PATCH v3 15/55] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:25   ` Eric Auger
2016-05-10  9:25     ` Eric Auger
2016-05-10  9:39   ` Marc Zyngier
2016-05-10  9:39     ` Marc Zyngier
2016-05-10 12:08   ` Christoffer Dall [this message]
2016-05-10 12:08     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 16/55] KVM: arm/arm64: vgic-new: Add IRQ sorting Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:29   ` Eric Auger
2016-05-10  9:29     ` Eric Auger
2016-05-10  9:48   ` Marc Zyngier
2016-05-10  9:48     ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 17/55] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 13:11   ` Christoffer Dall
2016-05-10 13:11     ` Christoffer Dall
2016-05-10 13:53   ` Eric Auger
2016-05-10 13:53     ` Eric Auger
2016-05-10 15:20   ` Eric Auger
2016-05-10 15:20     ` Eric Auger
2016-05-10 17:32     ` Marc Zyngier
2016-05-10 17:32       ` Marc Zyngier
2016-05-12 11:46   ` Christoffer Dall
2016-05-12 11:46     ` Christoffer Dall
2016-05-12 15:08     ` Andre Przywara
2016-05-12 15:08       ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 18/55] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 13:30   ` Christoffer Dall
2016-05-10 13:30     ` Christoffer Dall
2016-05-10 13:42     ` Marc Zyngier
2016-05-10 13:42       ` Marc Zyngier
2016-05-10 13:49       ` Eric Auger
2016-05-10 13:49         ` Eric Auger
2016-05-10 14:11       ` Christoffer Dall
2016-05-10 14:11         ` Christoffer Dall
2016-05-10 14:35         ` Marc Zyngier
2016-05-10 14:35           ` Marc Zyngier
2016-05-10 14:45           ` Marc Zyngier
2016-05-10 14:45             ` Marc Zyngier
2016-05-11  9:38             ` Christoffer Dall
2016-05-11  9:38               ` Christoffer Dall
2016-05-10 14:10   ` Eric Auger
2016-05-10 14:10     ` Eric Auger
2016-05-11 11:30     ` Andre Przywara
2016-05-11 11:30       ` Andre Przywara
2016-05-11 11:38       ` Eric Auger
2016-05-11 11:38         ` Eric Auger
2016-05-11 13:09         ` Andre Przywara
2016-05-11 13:09           ` Andre Przywara
2016-05-11 12:26       ` Christoffer Dall
2016-05-11 12:26         ` Christoffer Dall
2016-05-11 13:13         ` Andre Przywara
2016-05-11 13:13           ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 19/55] KVM: arm/arm64: vgic-new: Add GICv3 " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 19:07   ` Tom Hanson
2016-05-06 19:07     ` Tom Hanson
2016-05-10 14:04   ` Christoffer Dall
2016-05-10 14:04     ` Christoffer Dall
2016-05-10 14:15     ` Peter Maydell
2016-05-10 14:15       ` Peter Maydell
2016-05-10 14:22       ` Marc Zyngier
2016-05-10 14:22         ` Marc Zyngier
2016-05-11  9:39       ` Christoffer Dall
2016-05-11  9:39         ` Christoffer Dall
2016-05-10 15:28   ` Eric Auger
2016-05-10 15:28     ` Eric Auger
2016-05-10 17:35     ` Marc Zyngier
2016-05-10 17:35       ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 20/55] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 10:22   ` Marc Zyngier
2016-05-10 10:22     ` Marc Zyngier
2016-05-10 14:18   ` Christoffer Dall
2016-05-10 14:18     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 21/55] KVM: arm/arm64: vgic-new: Add MMIO handling framework Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11  9:46   ` Christoffer Dall
2016-05-11  9:46     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 22/55] KVM: arm/arm64: vgic-new: Add GICv2 " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11  9:50   ` Christoffer Dall
2016-05-11  9:50     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 23/55] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11 12:05   ` Christoffer Dall
2016-05-11 12:05     ` Christoffer Dall
2016-05-11 12:47     ` Andre Przywara
2016-05-11 12:47       ` Andre Przywara
2016-05-11 12:51     ` Marc Zyngier
2016-05-11 12:51       ` Marc Zyngier
2016-05-11 13:15       ` Christoffer Dall
2016-05-11 13:15         ` Christoffer Dall
2016-05-11 13:27         ` Marc Zyngier
2016-05-11 13:27           ` Marc Zyngier
2016-05-11 13:36           ` Andre Przywara
2016-05-11 13:36             ` Andre Przywara
2016-05-11 14:40             ` Marc Zyngier
2016-05-11 14:40               ` Marc Zyngier
2016-05-11 13:38           ` Christoffer Dall
2016-05-11 13:38             ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 24/55] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 10:28   ` Marc Zyngier
2016-05-10 10:28     ` Marc Zyngier
2016-05-11 12:34   ` Christoffer Dall
2016-05-11 12:34     ` Christoffer Dall
2016-05-11 13:04     ` Andre Przywara
2016-05-11 13:04       ` Andre Przywara
2016-05-11 13:14       ` Christoffer Dall
2016-05-11 13:14         ` Christoffer Dall
2016-05-11 13:24         ` Andre Przywara
2016-05-11 13:24           ` Andre Przywara
2016-05-11 13:41           ` Christoffer Dall
2016-05-11 13:41             ` Christoffer Dall
2016-05-11 13:16       ` Christoffer Dall
2016-05-11 13:16         ` Christoffer Dall
2016-05-11 13:13     ` Marc Zyngier
2016-05-11 13:13       ` Marc Zyngier
2016-05-11 13:39       ` Andre Przywara
2016-05-11 13:39         ` Andre Przywara
2016-05-11 14:26         ` Marc Zyngier
2016-05-11 14:26           ` Marc Zyngier
2016-05-11 13:47       ` Christoffer Dall
2016-05-11 13:47         ` Christoffer Dall
2016-05-11 14:18       ` Andre Przywara
2016-05-11 14:18         ` Andre Przywara
2016-05-11 14:28         ` Andre Przywara
2016-05-11 14:28           ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 25/55] KVM: arm/arm64: vgic-new: Add PENDING " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 10:49   ` Marc Zyngier
2016-05-10 10:49     ` Marc Zyngier
2016-05-11 13:11   ` Christoffer Dall
2016-05-11 13:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 26/55] KVM: arm/arm64: vgic-new: Add ACTIVE " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 12:09   ` Christoffer Dall
2016-05-10 12:09     ` Christoffer Dall
2016-05-10 12:14   ` Marc Zyngier
2016-05-10 12:14     ` Marc Zyngier
2016-05-10 13:04     ` Andre Przywara
2016-05-10 13:04       ` Andre Przywara
2016-05-10 13:12       ` Christoffer Dall
2016-05-10 13:12         ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 27/55] KVM: arm/arm64: vgic-new: Add PRIORITY " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11 13:37   ` Christoffer Dall
2016-05-11 13:37     ` Christoffer Dall
2016-05-12  9:10   ` Marc Zyngier
2016-05-12  9:10     ` Marc Zyngier
2016-05-12  9:56     ` Peter Maydell
2016-05-12  9:56       ` Peter Maydell
2016-05-12 10:09       ` Marc Zyngier
2016-05-12 10:09         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 28/55] KVM: arm/arm64: vgic-new: Add CONFIG " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  8:32   ` Christoffer Dall
2016-05-12  8:32     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 29/55] KVM: arm/arm64: vgic-new: Add TARGET " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  8:35   ` Christoffer Dall
2016-05-12  8:35     ` Christoffer Dall
2016-05-12  8:39     ` Marc Zyngier
2016-05-12  8:39       ` Marc Zyngier
2016-05-12  8:54     ` Christoffer Dall
2016-05-12  8:54       ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 30/55] KVM: arm/arm64: vgic-new: Add SGIR register handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  8:40   ` Christoffer Dall
2016-05-12  8:40     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 31/55] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  9:09   ` Christoffer Dall
2016-05-12  9:09     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 32/55] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-09 17:18   ` Marc Zyngier
2016-05-09 17:18     ` Marc Zyngier
2016-05-09 17:51     ` Chalamarla, Tirumalesh
2016-05-09 17:51       ` Chalamarla, Tirumalesh
2016-05-10 10:58     ` [PATCH] KVM: arm/arm64: vgic-new: fix overlap check for device addresses Andre Przywara
2016-05-10 10:58       ` Andre Przywara
2016-05-10 13:16       ` Marc Zyngier
2016-05-10 13:16         ` Marc Zyngier
2016-05-10 17:18         ` [PATCH v2] " Andre Przywara
2016-05-10 17:18           ` Andre Przywara
2016-05-12 19:43           ` Christoffer Dall
2016-05-12 19:43             ` Christoffer Dall
2016-05-12 10:26   ` [PATCH v3 32/55] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Christoffer Dall
2016-05-12 10:26     ` Christoffer Dall
2016-05-12 10:52     ` Andre Przywara
2016-05-12 10:52       ` Andre Przywara
2016-05-12 10:58       ` Marc Zyngier
2016-05-12 10:58         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 33/55] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 11:47   ` Christoffer Dall
2016-05-12 11:47     ` Christoffer Dall
2016-05-12 12:33     ` Andre Przywara
2016-05-12 12:33       ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 34/55] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 11:59   ` Christoffer Dall
2016-05-12 11:59     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 35/55] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 12:12   ` Christoffer Dall
2016-05-12 12:12     ` Christoffer Dall
2016-05-12 12:37     ` Andre Przywara
2016-05-12 12:37       ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 36/55] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 12:21   ` Christoffer Dall
2016-05-12 12:21     ` Christoffer Dall
2016-05-12 12:37     ` Marc Zyngier
2016-05-12 12:37       ` Marc Zyngier
2016-05-12 13:41       ` Christoffer Dall
2016-05-12 13:41         ` Christoffer Dall
2016-05-12 14:00       ` Andre Przywara
2016-05-12 14:00         ` Andre Przywara
2016-05-12 14:20         ` Marc Zyngier
2016-05-12 14:20           ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 37/55] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 12:40   ` Christoffer Dall
2016-05-12 12:40     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 38/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:11   ` Christoffer Dall
2016-05-13 10:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 39/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:11   ` Christoffer Dall
2016-05-13 10:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 40/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:11   ` Christoffer Dall
2016-05-13 10:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 41/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:12   ` Christoffer Dall
2016-05-13 10:12     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 42/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:12   ` Christoffer Dall
2016-05-13 10:12     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 43/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 18:30   ` Christoffer Dall
2016-05-12 18:30     ` Christoffer Dall
2016-05-13 12:24     ` Andre Przywara
2016-05-13 12:24       ` Andre Przywara
2016-05-13 12:29       ` Christoffer Dall
2016-05-13 12:29         ` Christoffer Dall
2016-05-13 12:30       ` Marc Zyngier
2016-05-13 12:30         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 44/55] KVM: arm/arm64: vgic-new: Export register access interface Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 45/55] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 18:41   ` Christoffer Dall
2016-05-12 18:41     ` Christoffer Dall
2016-05-12 19:10     ` Andre Przywara
2016-05-12 19:10       ` Andre Przywara
2016-05-13  7:51       ` Christoffer Dall
2016-05-13  7:51         ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 46/55] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 18:43   ` Christoffer Dall
2016-05-12 18:43     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 47/55] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-09 17:27   ` Marc Zyngier
2016-05-09 17:27     ` Marc Zyngier
2016-05-11  8:24     ` Andre Przywara
2016-05-11  8:24       ` Andre Przywara
2016-05-12 18:47   ` Christoffer Dall
2016-05-12 18:47     ` Christoffer Dall
2016-05-12 18:52     ` Andre Przywara
2016-05-12 18:52       ` Andre Przywara
2016-05-13  7:53       ` Christoffer Dall
2016-05-13  7:53         ` Christoffer Dall
2016-05-13 10:44         ` Andre Przywara
2016-05-13 10:44           ` Andre Przywara
2016-05-13 11:54           ` Christoffer Dall
2016-05-13 11:54             ` Christoffer Dall
2016-05-13 12:23             ` Andre Przywara
2016-05-13 12:23               ` Andre Przywara
2016-05-13 12:32               ` Christoffer Dall
2016-05-13 12:32                 ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 48/55] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:00   ` Christoffer Dall
2016-05-12 19:00     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 49/55] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:08   ` Christoffer Dall
2016-05-12 19:08     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 50/55] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:25   ` Christoffer Dall
2016-05-12 19:25     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 51/55] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:28   ` Christoffer Dall
2016-05-12 19:28     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 52/55] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:30   ` Christoffer Dall
2016-05-12 19:30     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 53/55] KVM: arm/arm64: vgic-new: Wire up irqfd injection Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:33   ` Christoffer Dall
2016-05-12 19:33     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 54/55] KVM: arm/arm64: vgic-new: implement mapped IRQ handling Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:36   ` Christoffer Dall
2016-05-12 19:36     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 55/55] KVM: arm/arm64: vgic-new: enable build Andre Przywara
2016-05-06 10:46   ` Andre Przywara

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