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From: Eric Auger <eric.auger@linaro.org>
To: Andre Przywara <andre.przywara@arm.com>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Cc: kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 17/55] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework
Date: Tue, 10 May 2016 17:20:30 +0200	[thread overview]
Message-ID: <5731FC3E.7020700@linaro.org> (raw)
In-Reply-To: <1462531568-9799-18-git-send-email-andre.przywara@arm.com>

On 05/06/2016 12:45 PM, Andre Przywara wrote:
> From: Marc Zyngier <marc.zyngier@arm.com>
> 
> Implement the framework for syncing IRQs between our emulation and
> the list registers, which represent the guest's view of IRQs.
> This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate,
> which gets called on guest entry and exit.
> The code talking to the actual GICv2/v3 hardware is added in the
> following patches.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Eric Auger <eric.auger@linaro.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changelog RFC..v1:
> - split out vgic_clear_lr() from vgic_populate_lr()
> - rename vgic_populate_lrs() to vgic_flush_lr_state()
> - clean all LRs when the distributor is disabled
> - use list_del() instead of list_del_init()
> - add comments to explain the direction of sync/flush_hwstate
> - remove unneeded BUG_ON(in_interrupt()
> 
> Changelog v2 .. v3:
> - remove bogus v2 specific rebase leftovers
> 
>  include/kvm/vgic/vgic.h  |   4 +
>  virt/kvm/arm/vgic/vgic.c | 193 +++++++++++++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic.h |   2 +
>  3 files changed, 199 insertions(+)
> 
> diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
> index 2bfb42c..5fae4a9 100644
> --- a/include/kvm/vgic/vgic.h
> +++ b/include/kvm/vgic/vgic.h
> @@ -190,6 +190,10 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
>  #define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
>  			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
>  
> +bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
> +void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
> +void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
> +
>  /**
>   * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
>   *
> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
> index 4fb20fd..c6f8b9b 100644
> --- a/virt/kvm/arm/vgic/vgic.c
> +++ b/virt/kvm/arm/vgic/vgic.c
> @@ -305,3 +305,196 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
>  {
>  	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
>  }
> +
> +/**
> + * vgic_prune_ap_list - Remove non-relevant interrupts from the list
> + *
> + * @vcpu: The VCPU pointer
> + *
> + * Go over the list of "interesting" interrupts, and prune those that we
> + * won't have to consider in the near future.
> + */
> +static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_irq *irq, *tmp;
> +
> +retry:
> +	spin_lock(&vgic_cpu->ap_list_lock);
> +
> +	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
> +		struct kvm_vcpu *target_vcpu, *vcpuA, *vcpuB;
> +
> +		spin_lock(&irq->irq_lock);
> +
> +		BUG_ON(vcpu != irq->vcpu);
> +
> +		target_vcpu = vgic_target_oracle(irq);
> +
> +		if (!target_vcpu) {
> +			/*
> +			 * We don't need to process this interrupt any
> +			 * further, move it off the list.
> +			 */
> +			list_del(&irq->ap_list);
> +			irq->vcpu = NULL;
> +			spin_unlock(&irq->irq_lock);
> +			continue;
> +		}
> +
> +		if (target_vcpu == vcpu) {
> +			/* We're on the right CPU */
> +			spin_unlock(&irq->irq_lock);
> +			continue;
> +		}
> +
> +		/* This interrupt looks like it has to be migrated. */
> +
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vgic_cpu->ap_list_lock);
> +
> +		/*
> +		 * Ensure locking order by always locking the smallest
> +		 * ID first.
> +		 */
> +		if (vcpu->vcpu_id < target_vcpu->vcpu_id) {
> +			vcpuA = vcpu;
> +			vcpuB = target_vcpu;
> +		} else {
> +			vcpuA = target_vcpu;
> +			vcpuB = vcpu;
> +		}
> +
> +		spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
> +		spin_lock(&vcpuB->arch.vgic_cpu.ap_list_lock);
> +		spin_lock(&irq->irq_lock);
> +
> +		/*
> +		 * If the affinity has been preserved, move the
> +		 * interrupt around. Otherwise, it means things have
> +		 * changed while the interrupt was unlocked, and we
> +		 * need to replay this.
> +		 *
> +		 * In all cases, we cannot trust the list not to have
> +		 * changed, so we restart from the beginning.
> +		 */
> +		if (target_vcpu == vgic_target_oracle(irq)) {
> +			struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic_cpu;
> +
> +			list_del(&irq->ap_list);
> +			irq->vcpu = target_vcpu;
> +			list_add_tail(&irq->ap_list, &new_cpu->ap_list_head);
> +		}
> +
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
> +		spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
> +		goto retry;
> +	}
> +
> +	spin_unlock(&vgic_cpu->ap_list_lock);
> +}
> +
> +static inline void vgic_process_maintenance_interrupt(struct kvm_vcpu *vcpu)
> +{
> +}
> +
> +static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
> +{
> +}
> +
> +/* Requires the ap_list_lock and the irq_lock to be held. */
why is it needed to hold the ap_list lock here?
> +static inline void vgic_populate_lr(struct kvm_vcpu *vcpu,
> +				    struct vgic_irq *irq, int lr)
> +{
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vcpu->arch.vgic_cpu.ap_list_lock));
?

Eric
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
> +}
> +
> +static inline void vgic_clear_lr(struct kvm_vcpu *vcpu, int lr)
> +{
> +}
> +
> +static inline void vgic_set_underflow(struct kvm_vcpu *vcpu)
> +{
> +}
> +
> +static int compute_ap_list_depth(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_irq *irq;
> +	int count = 0;
> +
> +	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
> +		spin_lock(&irq->irq_lock);
> +		/* GICv2 SGIs can count for more than one... */
> +		if (vgic_irq_is_sgi(irq->intid) && irq->source)
> +			count += hweight8(irq->source);
> +		else
> +			count++;
> +		spin_unlock(&irq->irq_lock);
> +	}
> +	return count;
> +}
> +
> +/* Requires the VCPU's ap_list_lock to be held. */
> +static void vgic_flush_lr_state(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_irq *irq;
> +	int count = 0;
> +
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock));
> +
> +	if (unlikely(!vcpu->kvm->arch.vgic.enabled))
> +		goto out_clean;
> +
> +	if (compute_ap_list_depth(vcpu) > kvm_vgic_global_state.nr_lr) {
> +		vgic_set_underflow(vcpu);
> +		vgic_sort_ap_list(vcpu);
> +	}
> +
> +	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
> +		spin_lock(&irq->irq_lock);
> +
> +		if (unlikely(vgic_target_oracle(irq) != vcpu))
> +			goto next;
> +
> +		/*
> +		 * If we get an SGI with multiple sources, try to get
> +		 * them in all at once.
> +		 */
> +		do {
> +			vgic_populate_lr(vcpu, irq, count++);
> +		} while (irq->source && count < kvm_vgic_global_state.nr_lr);
> +
> +next:
> +		spin_unlock(&irq->irq_lock);
> +
> +		if (count == kvm_vgic_global_state.nr_lr)
> +			break;
> +	}
> +
> +out_clean:
> +	vcpu->arch.vgic_cpu.used_lrs = count;
> +
> +	/* Nuke remaining LRs */
> +	for ( ; count < kvm_vgic_global_state.nr_lr; count++)
> +		vgic_clear_lr(vcpu, count);
> +}
> +
> +/* Sync back the hardware VGIC state into our emulation after a guest's run. */
> +void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
> +{
> +	vgic_process_maintenance_interrupt(vcpu);
> +	vgic_fold_lr_state(vcpu);
> +	vgic_prune_ap_list(vcpu);
> +}
> +
> +/* Flush our emulation state into the GIC hardware before entering the guest. */
> +void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
> +{
> +	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +	vgic_flush_lr_state(vcpu);
> +	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +}
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index c625767..29b96b9 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -16,6 +16,8 @@
>  #ifndef __KVM_ARM_VGIC_NEW_H__
>  #define __KVM_ARM_VGIC_NEW_H__
>  
> +#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
> +
>  struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  			      u32 intid);
>  bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
> 

WARNING: multiple messages have this Message-ID (diff)
From: eric.auger@linaro.org (Eric Auger)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 17/55] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework
Date: Tue, 10 May 2016 17:20:30 +0200	[thread overview]
Message-ID: <5731FC3E.7020700@linaro.org> (raw)
In-Reply-To: <1462531568-9799-18-git-send-email-andre.przywara@arm.com>

On 05/06/2016 12:45 PM, Andre Przywara wrote:
> From: Marc Zyngier <marc.zyngier@arm.com>
> 
> Implement the framework for syncing IRQs between our emulation and
> the list registers, which represent the guest's view of IRQs.
> This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate,
> which gets called on guest entry and exit.
> The code talking to the actual GICv2/v3 hardware is added in the
> following patches.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Eric Auger <eric.auger@linaro.org>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Changelog RFC..v1:
> - split out vgic_clear_lr() from vgic_populate_lr()
> - rename vgic_populate_lrs() to vgic_flush_lr_state()
> - clean all LRs when the distributor is disabled
> - use list_del() instead of list_del_init()
> - add comments to explain the direction of sync/flush_hwstate
> - remove unneeded BUG_ON(in_interrupt()
> 
> Changelog v2 .. v3:
> - remove bogus v2 specific rebase leftovers
> 
>  include/kvm/vgic/vgic.h  |   4 +
>  virt/kvm/arm/vgic/vgic.c | 193 +++++++++++++++++++++++++++++++++++++++++++++++
>  virt/kvm/arm/vgic/vgic.h |   2 +
>  3 files changed, 199 insertions(+)
> 
> diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
> index 2bfb42c..5fae4a9 100644
> --- a/include/kvm/vgic/vgic.h
> +++ b/include/kvm/vgic/vgic.h
> @@ -190,6 +190,10 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
>  #define vgic_valid_spi(k, i)	(((i) >= VGIC_NR_PRIVATE_IRQS) && \
>  			((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS))
>  
> +bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
> +void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
> +void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
> +
>  /**
>   * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
>   *
> diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
> index 4fb20fd..c6f8b9b 100644
> --- a/virt/kvm/arm/vgic/vgic.c
> +++ b/virt/kvm/arm/vgic/vgic.c
> @@ -305,3 +305,196 @@ int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid,
>  {
>  	return vgic_update_irq_pending(kvm, cpuid, intid, level, false);
>  }
> +
> +/**
> + * vgic_prune_ap_list - Remove non-relevant interrupts from the list
> + *
> + * @vcpu: The VCPU pointer
> + *
> + * Go over the list of "interesting" interrupts, and prune those that we
> + * won't have to consider in the near future.
> + */
> +static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_irq *irq, *tmp;
> +
> +retry:
> +	spin_lock(&vgic_cpu->ap_list_lock);
> +
> +	list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
> +		struct kvm_vcpu *target_vcpu, *vcpuA, *vcpuB;
> +
> +		spin_lock(&irq->irq_lock);
> +
> +		BUG_ON(vcpu != irq->vcpu);
> +
> +		target_vcpu = vgic_target_oracle(irq);
> +
> +		if (!target_vcpu) {
> +			/*
> +			 * We don't need to process this interrupt any
> +			 * further, move it off the list.
> +			 */
> +			list_del(&irq->ap_list);
> +			irq->vcpu = NULL;
> +			spin_unlock(&irq->irq_lock);
> +			continue;
> +		}
> +
> +		if (target_vcpu == vcpu) {
> +			/* We're on the right CPU */
> +			spin_unlock(&irq->irq_lock);
> +			continue;
> +		}
> +
> +		/* This interrupt looks like it has to be migrated. */
> +
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vgic_cpu->ap_list_lock);
> +
> +		/*
> +		 * Ensure locking order by always locking the smallest
> +		 * ID first.
> +		 */
> +		if (vcpu->vcpu_id < target_vcpu->vcpu_id) {
> +			vcpuA = vcpu;
> +			vcpuB = target_vcpu;
> +		} else {
> +			vcpuA = target_vcpu;
> +			vcpuB = vcpu;
> +		}
> +
> +		spin_lock(&vcpuA->arch.vgic_cpu.ap_list_lock);
> +		spin_lock(&vcpuB->arch.vgic_cpu.ap_list_lock);
> +		spin_lock(&irq->irq_lock);
> +
> +		/*
> +		 * If the affinity has been preserved, move the
> +		 * interrupt around. Otherwise, it means things have
> +		 * changed while the interrupt was unlocked, and we
> +		 * need to replay this.
> +		 *
> +		 * In all cases, we cannot trust the list not to have
> +		 * changed, so we restart from the beginning.
> +		 */
> +		if (target_vcpu == vgic_target_oracle(irq)) {
> +			struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic_cpu;
> +
> +			list_del(&irq->ap_list);
> +			irq->vcpu = target_vcpu;
> +			list_add_tail(&irq->ap_list, &new_cpu->ap_list_head);
> +		}
> +
> +		spin_unlock(&irq->irq_lock);
> +		spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
> +		spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
> +		goto retry;
> +	}
> +
> +	spin_unlock(&vgic_cpu->ap_list_lock);
> +}
> +
> +static inline void vgic_process_maintenance_interrupt(struct kvm_vcpu *vcpu)
> +{
> +}
> +
> +static inline void vgic_fold_lr_state(struct kvm_vcpu *vcpu)
> +{
> +}
> +
> +/* Requires the ap_list_lock and the irq_lock to be held. */
why is it needed to hold the ap_list lock here?
> +static inline void vgic_populate_lr(struct kvm_vcpu *vcpu,
> +				    struct vgic_irq *irq, int lr)
> +{
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vcpu->arch.vgic_cpu.ap_list_lock));
?

Eric
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&irq->irq_lock));
> +}
> +
> +static inline void vgic_clear_lr(struct kvm_vcpu *vcpu, int lr)
> +{
> +}
> +
> +static inline void vgic_set_underflow(struct kvm_vcpu *vcpu)
> +{
> +}
> +
> +static int compute_ap_list_depth(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_irq *irq;
> +	int count = 0;
> +
> +	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
> +		spin_lock(&irq->irq_lock);
> +		/* GICv2 SGIs can count for more than one... */
> +		if (vgic_irq_is_sgi(irq->intid) && irq->source)
> +			count += hweight8(irq->source);
> +		else
> +			count++;
> +		spin_unlock(&irq->irq_lock);
> +	}
> +	return count;
> +}
> +
> +/* Requires the VCPU's ap_list_lock to be held. */
> +static void vgic_flush_lr_state(struct kvm_vcpu *vcpu)
> +{
> +	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> +	struct vgic_irq *irq;
> +	int count = 0;
> +
> +	DEBUG_SPINLOCK_BUG_ON(!spin_is_locked(&vgic_cpu->ap_list_lock));
> +
> +	if (unlikely(!vcpu->kvm->arch.vgic.enabled))
> +		goto out_clean;
> +
> +	if (compute_ap_list_depth(vcpu) > kvm_vgic_global_state.nr_lr) {
> +		vgic_set_underflow(vcpu);
> +		vgic_sort_ap_list(vcpu);
> +	}
> +
> +	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
> +		spin_lock(&irq->irq_lock);
> +
> +		if (unlikely(vgic_target_oracle(irq) != vcpu))
> +			goto next;
> +
> +		/*
> +		 * If we get an SGI with multiple sources, try to get
> +		 * them in all at once.
> +		 */
> +		do {
> +			vgic_populate_lr(vcpu, irq, count++);
> +		} while (irq->source && count < kvm_vgic_global_state.nr_lr);
> +
> +next:
> +		spin_unlock(&irq->irq_lock);
> +
> +		if (count == kvm_vgic_global_state.nr_lr)
> +			break;
> +	}
> +
> +out_clean:
> +	vcpu->arch.vgic_cpu.used_lrs = count;
> +
> +	/* Nuke remaining LRs */
> +	for ( ; count < kvm_vgic_global_state.nr_lr; count++)
> +		vgic_clear_lr(vcpu, count);
> +}
> +
> +/* Sync back the hardware VGIC state into our emulation after a guest's run. */
> +void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
> +{
> +	vgic_process_maintenance_interrupt(vcpu);
> +	vgic_fold_lr_state(vcpu);
> +	vgic_prune_ap_list(vcpu);
> +}
> +
> +/* Flush our emulation state into the GIC hardware before entering the guest. */
> +void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
> +{
> +	spin_lock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +	vgic_flush_lr_state(vcpu);
> +	spin_unlock(&vcpu->arch.vgic_cpu.ap_list_lock);
> +}
> diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
> index c625767..29b96b9 100644
> --- a/virt/kvm/arm/vgic/vgic.h
> +++ b/virt/kvm/arm/vgic/vgic.h
> @@ -16,6 +16,8 @@
>  #ifndef __KVM_ARM_VGIC_NEW_H__
>  #define __KVM_ARM_VGIC_NEW_H__
>  
> +#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
> +
>  struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
>  			      u32 intid);
>  bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
> 

  parent reply	other threads:[~2016-05-10 15:20 UTC|newest]

Thread overview: 400+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-06 10:45 [PATCH v3 00/55] KVM: arm/arm64: Rework virtual GIC emulation Andre Przywara
2016-05-06 10:45 ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 01/55] KVM: arm/arm64: vgic: streamline vgic_update_irq_pending() interface Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 02/55] KVM: arm/arm64: vgic: avoid map in kvm_vgic_inject_mapped_irq() Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 03/55] KVM: arm/arm64: vgic: avoid map in kvm_vgic_map_is_active() Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 04/55] KVM: arm/arm64: vgic: avoid map in kvm_vgic_unmap_phys_irq() Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 05/55] KVM: arm/arm64: Remove the IRQ field from struct irq_phys_map Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 06/55] KVM: arm/arm64: arch_timer: Remove irq_phys_map Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  8:33   ` Eric Auger
2016-05-10  8:33     ` Eric Auger
2016-05-06 10:45 ` [PATCH v3 07/55] KVM: arm/arm64: vgic: Remove irq_phys_map from interface Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 08/55] KVM: arm/arm64: Get rid of vgic_cpu->nr_lr Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-18 10:43   ` Andre Przywara
2016-05-18 10:43     ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 09/55] KVM: arm/arm64: Fix MMIO emulation data handling Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  8:57   ` Marc Zyngier
2016-05-10  8:57     ` Marc Zyngier
2016-05-18 11:02   ` Andre Przywara
2016-05-18 11:02     ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 10/55] KVM: arm/arm64: Export mmio_read/write_bus Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  8:59   ` Marc Zyngier
2016-05-10  8:59     ` Marc Zyngier
2016-05-18 14:18   ` Andre Przywara
2016-05-18 14:18     ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 11/55] KVM: arm/arm64: pmu: abstract access to number of SPIs Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:00   ` Marc Zyngier
2016-05-10  9:00     ` Marc Zyngier
2016-05-10  9:52   ` Eric Auger
2016-05-10  9:52     ` Eric Auger
2016-05-10 10:04     ` Marc Zyngier
2016-05-10 10:04       ` Marc Zyngier
2016-05-10 14:35     ` [PATCH v3a] " Andre Przywara
2016-05-10 14:35       ` Andre Przywara
2016-05-10 14:58       ` Andrew Jones
2016-05-10 14:58         ` Andrew Jones
2016-05-11 13:52         ` Andre Przywara
2016-05-11 13:52           ` Andre Przywara
2016-05-10 15:22       ` Marc Zyngier
2016-05-10 15:22         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 12/55] KVM: arm/arm64: move GICv2 emulation defines into arm-gic-v3.h Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:02   ` Marc Zyngier
2016-05-10  9:02     ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 13/55] KVM: arm/arm64: vgic-new: Add data structure definitions Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:05   ` Marc Zyngier
2016-05-10  9:05     ` Marc Zyngier
2016-05-12 12:12   ` Christoffer Dall
2016-05-12 12:12     ` Christoffer Dall
2016-05-12 12:17     ` Marc Zyngier
2016-05-12 12:17       ` Marc Zyngier
2016-05-12 12:23       ` Christoffer Dall
2016-05-12 12:23         ` Christoffer Dall
2016-05-12 13:25     ` Andre Przywara
2016-05-12 13:25       ` Andre Przywara
2016-05-12 13:48       ` Christoffer Dall
2016-05-12 13:48         ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 14/55] KVM: arm/arm64: vgic-new: Add acccessor to new struct vgic_irq instance Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:22   ` Marc Zyngier
2016-05-10  9:22     ` Marc Zyngier
2016-05-11  9:20     ` Andre Przywara
2016-05-11  9:20       ` Andre Przywara
2016-05-10  9:35   ` Eric Auger
2016-05-10  9:35     ` Eric Auger
2016-05-06 10:45 ` [PATCH v3 15/55] KVM: arm/arm64: vgic-new: Implement virtual IRQ injection Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:25   ` Eric Auger
2016-05-10  9:25     ` Eric Auger
2016-05-10  9:39   ` Marc Zyngier
2016-05-10  9:39     ` Marc Zyngier
2016-05-10 12:08   ` Christoffer Dall
2016-05-10 12:08     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 16/55] KVM: arm/arm64: vgic-new: Add IRQ sorting Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10  9:29   ` Eric Auger
2016-05-10  9:29     ` Eric Auger
2016-05-10  9:48   ` Marc Zyngier
2016-05-10  9:48     ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 17/55] KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 13:11   ` Christoffer Dall
2016-05-10 13:11     ` Christoffer Dall
2016-05-10 13:53   ` Eric Auger
2016-05-10 13:53     ` Eric Auger
2016-05-10 15:20   ` Eric Auger [this message]
2016-05-10 15:20     ` Eric Auger
2016-05-10 17:32     ` Marc Zyngier
2016-05-10 17:32       ` Marc Zyngier
2016-05-12 11:46   ` Christoffer Dall
2016-05-12 11:46     ` Christoffer Dall
2016-05-12 15:08     ` Andre Przywara
2016-05-12 15:08       ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 18/55] KVM: arm/arm64: vgic-new: Add GICv2 world switch backend Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 13:30   ` Christoffer Dall
2016-05-10 13:30     ` Christoffer Dall
2016-05-10 13:42     ` Marc Zyngier
2016-05-10 13:42       ` Marc Zyngier
2016-05-10 13:49       ` Eric Auger
2016-05-10 13:49         ` Eric Auger
2016-05-10 14:11       ` Christoffer Dall
2016-05-10 14:11         ` Christoffer Dall
2016-05-10 14:35         ` Marc Zyngier
2016-05-10 14:35           ` Marc Zyngier
2016-05-10 14:45           ` Marc Zyngier
2016-05-10 14:45             ` Marc Zyngier
2016-05-11  9:38             ` Christoffer Dall
2016-05-11  9:38               ` Christoffer Dall
2016-05-10 14:10   ` Eric Auger
2016-05-10 14:10     ` Eric Auger
2016-05-11 11:30     ` Andre Przywara
2016-05-11 11:30       ` Andre Przywara
2016-05-11 11:38       ` Eric Auger
2016-05-11 11:38         ` Eric Auger
2016-05-11 13:09         ` Andre Przywara
2016-05-11 13:09           ` Andre Przywara
2016-05-11 12:26       ` Christoffer Dall
2016-05-11 12:26         ` Christoffer Dall
2016-05-11 13:13         ` Andre Przywara
2016-05-11 13:13           ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 19/55] KVM: arm/arm64: vgic-new: Add GICv3 " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 19:07   ` Tom Hanson
2016-05-06 19:07     ` Tom Hanson
2016-05-10 14:04   ` Christoffer Dall
2016-05-10 14:04     ` Christoffer Dall
2016-05-10 14:15     ` Peter Maydell
2016-05-10 14:15       ` Peter Maydell
2016-05-10 14:22       ` Marc Zyngier
2016-05-10 14:22         ` Marc Zyngier
2016-05-11  9:39       ` Christoffer Dall
2016-05-11  9:39         ` Christoffer Dall
2016-05-10 15:28   ` Eric Auger
2016-05-10 15:28     ` Eric Auger
2016-05-10 17:35     ` Marc Zyngier
2016-05-10 17:35       ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 20/55] KVM: arm/arm64: vgic-new: Implement kvm_vgic_vcpu_pending_irq Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 10:22   ` Marc Zyngier
2016-05-10 10:22     ` Marc Zyngier
2016-05-10 14:18   ` Christoffer Dall
2016-05-10 14:18     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 21/55] KVM: arm/arm64: vgic-new: Add MMIO handling framework Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11  9:46   ` Christoffer Dall
2016-05-11  9:46     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 22/55] KVM: arm/arm64: vgic-new: Add GICv2 " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11  9:50   ` Christoffer Dall
2016-05-11  9:50     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 23/55] KVM: arm/arm64: vgic-new: Add CTLR, TYPER and IIDR handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11 12:05   ` Christoffer Dall
2016-05-11 12:05     ` Christoffer Dall
2016-05-11 12:47     ` Andre Przywara
2016-05-11 12:47       ` Andre Przywara
2016-05-11 12:51     ` Marc Zyngier
2016-05-11 12:51       ` Marc Zyngier
2016-05-11 13:15       ` Christoffer Dall
2016-05-11 13:15         ` Christoffer Dall
2016-05-11 13:27         ` Marc Zyngier
2016-05-11 13:27           ` Marc Zyngier
2016-05-11 13:36           ` Andre Przywara
2016-05-11 13:36             ` Andre Przywara
2016-05-11 14:40             ` Marc Zyngier
2016-05-11 14:40               ` Marc Zyngier
2016-05-11 13:38           ` Christoffer Dall
2016-05-11 13:38             ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 24/55] KVM: arm/arm64: vgic-new: Add ENABLE registers handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 10:28   ` Marc Zyngier
2016-05-10 10:28     ` Marc Zyngier
2016-05-11 12:34   ` Christoffer Dall
2016-05-11 12:34     ` Christoffer Dall
2016-05-11 13:04     ` Andre Przywara
2016-05-11 13:04       ` Andre Przywara
2016-05-11 13:14       ` Christoffer Dall
2016-05-11 13:14         ` Christoffer Dall
2016-05-11 13:24         ` Andre Przywara
2016-05-11 13:24           ` Andre Przywara
2016-05-11 13:41           ` Christoffer Dall
2016-05-11 13:41             ` Christoffer Dall
2016-05-11 13:16       ` Christoffer Dall
2016-05-11 13:16         ` Christoffer Dall
2016-05-11 13:13     ` Marc Zyngier
2016-05-11 13:13       ` Marc Zyngier
2016-05-11 13:39       ` Andre Przywara
2016-05-11 13:39         ` Andre Przywara
2016-05-11 14:26         ` Marc Zyngier
2016-05-11 14:26           ` Marc Zyngier
2016-05-11 13:47       ` Christoffer Dall
2016-05-11 13:47         ` Christoffer Dall
2016-05-11 14:18       ` Andre Przywara
2016-05-11 14:18         ` Andre Przywara
2016-05-11 14:28         ` Andre Przywara
2016-05-11 14:28           ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 25/55] KVM: arm/arm64: vgic-new: Add PENDING " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 10:49   ` Marc Zyngier
2016-05-10 10:49     ` Marc Zyngier
2016-05-11 13:11   ` Christoffer Dall
2016-05-11 13:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 26/55] KVM: arm/arm64: vgic-new: Add ACTIVE " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-10 12:09   ` Christoffer Dall
2016-05-10 12:09     ` Christoffer Dall
2016-05-10 12:14   ` Marc Zyngier
2016-05-10 12:14     ` Marc Zyngier
2016-05-10 13:04     ` Andre Przywara
2016-05-10 13:04       ` Andre Przywara
2016-05-10 13:12       ` Christoffer Dall
2016-05-10 13:12         ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 27/55] KVM: arm/arm64: vgic-new: Add PRIORITY " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-11 13:37   ` Christoffer Dall
2016-05-11 13:37     ` Christoffer Dall
2016-05-12  9:10   ` Marc Zyngier
2016-05-12  9:10     ` Marc Zyngier
2016-05-12  9:56     ` Peter Maydell
2016-05-12  9:56       ` Peter Maydell
2016-05-12 10:09       ` Marc Zyngier
2016-05-12 10:09         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 28/55] KVM: arm/arm64: vgic-new: Add CONFIG " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  8:32   ` Christoffer Dall
2016-05-12  8:32     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 29/55] KVM: arm/arm64: vgic-new: Add TARGET " Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  8:35   ` Christoffer Dall
2016-05-12  8:35     ` Christoffer Dall
2016-05-12  8:39     ` Marc Zyngier
2016-05-12  8:39       ` Marc Zyngier
2016-05-12  8:54     ` Christoffer Dall
2016-05-12  8:54       ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 30/55] KVM: arm/arm64: vgic-new: Add SGIR register handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  8:40   ` Christoffer Dall
2016-05-12  8:40     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 31/55] KVM: arm/arm64: vgic-new: Add SGIPENDR register handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12  9:09   ` Christoffer Dall
2016-05-12  9:09     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 32/55] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-09 17:18   ` Marc Zyngier
2016-05-09 17:18     ` Marc Zyngier
2016-05-09 17:51     ` Chalamarla, Tirumalesh
2016-05-09 17:51       ` Chalamarla, Tirumalesh
2016-05-10 10:58     ` [PATCH] KVM: arm/arm64: vgic-new: fix overlap check for device addresses Andre Przywara
2016-05-10 10:58       ` Andre Przywara
2016-05-10 13:16       ` Marc Zyngier
2016-05-10 13:16         ` Marc Zyngier
2016-05-10 17:18         ` [PATCH v2] " Andre Przywara
2016-05-10 17:18           ` Andre Przywara
2016-05-12 19:43           ` Christoffer Dall
2016-05-12 19:43             ` Christoffer Dall
2016-05-12 10:26   ` [PATCH v3 32/55] KVM: arm/arm64: vgic-new: Add GICv3 MMIO handling framework Christoffer Dall
2016-05-12 10:26     ` Christoffer Dall
2016-05-12 10:52     ` Andre Przywara
2016-05-12 10:52       ` Andre Przywara
2016-05-12 10:58       ` Marc Zyngier
2016-05-12 10:58         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 33/55] KVM: arm/arm64: vgic-new: Add GICv3 CTLR, IIDR, TYPER handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 11:47   ` Christoffer Dall
2016-05-12 11:47     ` Christoffer Dall
2016-05-12 12:33     ` Andre Przywara
2016-05-12 12:33       ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 34/55] KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 11:59   ` Christoffer Dall
2016-05-12 11:59     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 35/55] KVM: arm/arm64: vgic-new: Add GICv3 IDREGS register handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 12:12   ` Christoffer Dall
2016-05-12 12:12     ` Christoffer Dall
2016-05-12 12:37     ` Andre Przywara
2016-05-12 12:37       ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 36/55] KVM: arm/arm64: vgic-new: Add GICv3 IROUTER register handlers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 12:21   ` Christoffer Dall
2016-05-12 12:21     ` Christoffer Dall
2016-05-12 12:37     ` Marc Zyngier
2016-05-12 12:37       ` Marc Zyngier
2016-05-12 13:41       ` Christoffer Dall
2016-05-12 13:41         ` Christoffer Dall
2016-05-12 14:00       ` Andre Przywara
2016-05-12 14:00         ` Andre Przywara
2016-05-12 14:20         ` Marc Zyngier
2016-05-12 14:20           ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 37/55] KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 12:40   ` Christoffer Dall
2016-05-12 12:40     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 38/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM device ops registration Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:11   ` Christoffer Dall
2016-05-13 10:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 39/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_NR_IRQS Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:11   ` Christoffer Dall
2016-05-13 10:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 40/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_CTRL Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:11   ` Christoffer Dall
2016-05-13 10:11     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 41/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: implement kvm_vgic_addr Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:12   ` Christoffer Dall
2016-05-13 10:12     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 42/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: KVM_DEV_ARM_VGIC_GRP_ADDR Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-13 10:12   ` Christoffer Dall
2016-05-13 10:12     ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 43/55] KVM: arm/arm64: vgic-new: vgic_kvm_device: access to VGIC registers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 18:30   ` Christoffer Dall
2016-05-12 18:30     ` Christoffer Dall
2016-05-13 12:24     ` Andre Przywara
2016-05-13 12:24       ` Andre Przywara
2016-05-13 12:29       ` Christoffer Dall
2016-05-13 12:29         ` Christoffer Dall
2016-05-13 12:30       ` Marc Zyngier
2016-05-13 12:30         ` Marc Zyngier
2016-05-06 10:45 ` [PATCH v3 44/55] KVM: arm/arm64: vgic-new: Export register access interface Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-06 10:45 ` [PATCH v3 45/55] KVM: arm/arm64: vgic-new: Add userland access to VGIC dist registers Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 18:41   ` Christoffer Dall
2016-05-12 18:41     ` Christoffer Dall
2016-05-12 19:10     ` Andre Przywara
2016-05-12 19:10       ` Andre Przywara
2016-05-13  7:51       ` Christoffer Dall
2016-05-13  7:51         ` Christoffer Dall
2016-05-06 10:45 ` [PATCH v3 46/55] KVM: arm/arm64: vgic-new: Add GICH_VMCR accessors Andre Przywara
2016-05-06 10:45   ` Andre Przywara
2016-05-12 18:43   ` Christoffer Dall
2016-05-12 18:43     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 47/55] KVM: arm/arm64: vgic-new: Add userland GIC CPU interface access Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-09 17:27   ` Marc Zyngier
2016-05-09 17:27     ` Marc Zyngier
2016-05-11  8:24     ` Andre Przywara
2016-05-11  8:24       ` Andre Przywara
2016-05-12 18:47   ` Christoffer Dall
2016-05-12 18:47     ` Christoffer Dall
2016-05-12 18:52     ` Andre Przywara
2016-05-12 18:52       ` Andre Przywara
2016-05-13  7:53       ` Christoffer Dall
2016-05-13  7:53         ` Christoffer Dall
2016-05-13 10:44         ` Andre Przywara
2016-05-13 10:44           ` Andre Przywara
2016-05-13 11:54           ` Christoffer Dall
2016-05-13 11:54             ` Christoffer Dall
2016-05-13 12:23             ` Andre Przywara
2016-05-13 12:23               ` Andre Przywara
2016-05-13 12:32               ` Christoffer Dall
2016-05-13 12:32                 ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 48/55] KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:00   ` Christoffer Dall
2016-05-12 19:00     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 49/55] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:08   ` Christoffer Dall
2016-05-12 19:08     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 50/55] KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:25   ` Christoffer Dall
2016-05-12 19:25     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 51/55] KVM: arm/arm64: vgic-new: vgic_init: implement map_resources Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:28   ` Christoffer Dall
2016-05-12 19:28     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 52/55] KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:30   ` Christoffer Dall
2016-05-12 19:30     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 53/55] KVM: arm/arm64: vgic-new: Wire up irqfd injection Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:33   ` Christoffer Dall
2016-05-12 19:33     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 54/55] KVM: arm/arm64: vgic-new: implement mapped IRQ handling Andre Przywara
2016-05-06 10:46   ` Andre Przywara
2016-05-12 19:36   ` Christoffer Dall
2016-05-12 19:36     ` Christoffer Dall
2016-05-06 10:46 ` [PATCH v3 55/55] KVM: arm/arm64: vgic-new: enable build Andre Przywara
2016-05-06 10:46   ` Andre Przywara

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