* [Qemu-devel] [PATCH v4 1/5] target/ppc: return a nil HPT base address on sPAPR machines
2018-04-24 11:30 [Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
@ 2018-04-24 11:30 ` Cédric Le Goater
2018-05-02 14:59 ` David Gibson
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 2/5] target/ppc: add basic support for PTCR on POWER9 Cédric Le Goater
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 11:30 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
commit e57ca75ce3b2 ("target/ppc: Manage external HPT via virtual
hypervisor") exported a set of methods to manipulate the HPT from the
core hash MMU. But SPR_SDR1 is still used under some circumstances to
get the base address of the HPT, which is incorrect for the sPAPR
machines.
Only the logging should be impacted.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Changes since v3:
- removed spapr_hpt_base() ops and just return zero instead
target/ppc/mmu-hash64.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index f23b78d78754..53dcec5b9316 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -101,6 +101,9 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
{
+ if (cpu->vhyp) {
+ return 0;
+ }
return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 1/5] target/ppc: return a nil HPT base address on sPAPR machines
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 1/5] target/ppc: return a nil HPT base address on sPAPR machines Cédric Le Goater
@ 2018-05-02 14:59 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2018-05-02 14:59 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
[-- Attachment #1: Type: text/plain, Size: 1441 bytes --]
On Tue, Apr 24, 2018 at 01:30:41PM +0200, Cédric Le Goater wrote:
> commit e57ca75ce3b2 ("target/ppc: Manage external HPT via virtual
> hypervisor") exported a set of methods to manipulate the HPT from the
> core hash MMU. But SPR_SDR1 is still used under some circumstances to
> get the base address of the HPT, which is incorrect for the sPAPR
> machines.
>
> Only the logging should be impacted.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Even better would be having an asserT(!vhyp) here, but that would
require some irritating fiddling with the callers.
This is a fine interim step, applued.
> ---
>
> Changes since v3:
>
> - removed spapr_hpt_base() ops and just return zero instead
>
> target/ppc/mmu-hash64.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index f23b78d78754..53dcec5b9316 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -101,6 +101,9 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
>
> static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
> {
> + if (cpu->vhyp) {
> + return 0;
> + }
> return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 2/5] target/ppc: add basic support for PTCR on POWER9
2018-04-24 11:30 [Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 1/5] target/ppc: return a nil HPT base address on sPAPR machines Cédric Le Goater
@ 2018-04-24 11:30 ` Cédric Le Goater
2018-05-02 15:00 ` David Gibson
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 3/5] target/ppc: add hash MMU definitions for ISA v3.0 Cédric Le Goater
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 11:30 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
The Partition Table Control Register (PTCR) is a hypervisor privileged
SPR. It contains the host real address of the Partition Table and its
size.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 12 ++++++++++++
target/ppc/mmu-book3s-v3.h | 6 ++++++
target/ppc/mmu_helper.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate.c | 3 +++
target/ppc/translate_init.c | 18 ++++++++++++++++++
7 files changed, 71 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 740939a08583..7ccd2f460ed6 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1295,6 +1295,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
+void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
#endif /* !defined(CONFIG_USER_ONLY) */
void ppc_store_msr (CPUPPCState *env, target_ulong value);
@@ -1585,6 +1586,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
+#define SPR_PTCR (0x1D0)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5b739179b8b5..19453c68138a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
+DEF_HELPER_2(store_ptcr, void, env, tl)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
DEF_HELPER_2(store_pidr, void, env, tl)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 0e4217821b8e..8c8cba5cc6f1 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
}
}
+#if defined(TARGET_PPC64)
+void helper_store_ptcr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ if (env->spr[SPR_PTCR] != val) {
+ ppc_store_ptcr(env, val);
+ tlb_flush(CPU(cpu));
+ }
+}
+#endif /* defined(TARGET_PPC64) */
+
void helper_store_pidr(CPUPPCState *env, target_ulong val)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index 56095dab522c..fdf80987d7b2 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -22,6 +22,12 @@
#ifndef CONFIG_USER_ONLY
+/*
+ * Partition table definitions
+ */
+#define PTCR_PATB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
+#define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
+
/* Partition Table Entry Fields */
#define PATBE1_GR 0x8000000000000000
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 8075b7149abc..98ce17985b13 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2028,6 +2028,35 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
env->spr[SPR_SDR1] = value;
}
+#if defined(TARGET_PPC64)
+void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
+ target_ulong patbsize = value & PTCR_PATS;
+
+ qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
+
+ assert(!cpu->vhyp);
+ assert(env->mmu_model & POWERPC_MMU_3_00);
+
+ if (value & ~ptcr_mask) {
+ error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
+ value & ~ptcr_mask);
+ value &= ptcr_mask;
+ }
+
+ if (patbsize > 24) {
+ error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
+ " stored in PTCR", patbsize);
+ return;
+ }
+
+ env->spr[SPR_PTCR] = value;
+}
+
+#endif /* defined(TARGET_PPC64) */
+
/* Segment registers load and store */
target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
{
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3beaa1e2f0c8..2a4140f42062 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7136,6 +7136,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
}
+ if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
+ cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
+ }
cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
env->spr[SPR_DAR], env->spr[SPR_DSISR]);
break;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 95e8dba97a35..118631efbeb6 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -420,6 +420,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
tcg_temp_free(t0);
}
+static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
+}
+
#endif
#endif
@@ -8167,6 +8172,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
#endif
}
+static void gen_spr_power9_mmu(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ /* Partition Table Control */
+ spr_register_hv(env, SPR_PTCR, "PTCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_ptcr,
+ 0x00000000);
+#endif
+}
+
static void init_proc_book3s_common(CPUPPCState *env)
{
gen_spr_ne_601(env);
@@ -8719,6 +8736,7 @@ static void init_proc_POWER9(CPUPPCState *env)
gen_spr_power8_ic(env);
gen_spr_power8_book4(env);
gen_spr_power8_rpr(env);
+ gen_spr_power9_mmu(env);
/* POWER9 Specific registers */
spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
--
2.13.6
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 2/5] target/ppc: add basic support for PTCR on POWER9
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 2/5] target/ppc: add basic support for PTCR on POWER9 Cédric Le Goater
@ 2018-05-02 15:00 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2018-05-02 15:00 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
[-- Attachment #1: Type: text/plain, Size: 7182 bytes --]
On Tue, Apr 24, 2018 at 01:30:42PM +0200, Cédric Le Goater wrote:
> The Partition Table Control Register (PTCR) is a hypervisor privileged
> SPR. It contains the host real address of the Partition Table and its
> size.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Applied, thanks.
> ---
> target/ppc/cpu.h | 2 ++
> target/ppc/helper.h | 1 +
> target/ppc/misc_helper.c | 12 ++++++++++++
> target/ppc/mmu-book3s-v3.h | 6 ++++++
> target/ppc/mmu_helper.c | 29 +++++++++++++++++++++++++++++
> target/ppc/translate.c | 3 +++
> target/ppc/translate_init.c | 18 ++++++++++++++++++
> 7 files changed, 71 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 740939a08583..7ccd2f460ed6 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1295,6 +1295,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
>
> #if !defined(CONFIG_USER_ONLY)
> void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
> #endif /* !defined(CONFIG_USER_ONLY) */
> void ppc_store_msr (CPUPPCState *env, target_ulong value);
>
> @@ -1585,6 +1586,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
> #define SPR_BOOKE_GIVOR13 (0x1BC)
> #define SPR_BOOKE_GIVOR14 (0x1BD)
> #define SPR_TIR (0x1BE)
> +#define SPR_PTCR (0x1D0)
> #define SPR_BOOKE_SPEFSCR (0x200)
> #define SPR_Exxx_BBEAR (0x201)
> #define SPR_Exxx_BBTAR (0x202)
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 5b739179b8b5..19453c68138a 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
> #if !defined(CONFIG_USER_ONLY)
> #if defined(TARGET_PPC64)
> DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
> +DEF_HELPER_2(store_ptcr, void, env, tl)
> #endif
> DEF_HELPER_2(store_sdr1, void, env, tl)
> DEF_HELPER_2(store_pidr, void, env, tl)
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 0e4217821b8e..8c8cba5cc6f1 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -88,6 +88,18 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
> }
> }
>
> +#if defined(TARGET_PPC64)
> +void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> +{
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> + if (env->spr[SPR_PTCR] != val) {
> + ppc_store_ptcr(env, val);
> + tlb_flush(CPU(cpu));
> + }
> +}
> +#endif /* defined(TARGET_PPC64) */
> +
> void helper_store_pidr(CPUPPCState *env, target_ulong val)
> {
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> index 56095dab522c..fdf80987d7b2 100644
> --- a/target/ppc/mmu-book3s-v3.h
> +++ b/target/ppc/mmu-book3s-v3.h
> @@ -22,6 +22,12 @@
>
> #ifndef CONFIG_USER_ONLY
>
> +/*
> + * Partition table definitions
> + */
> +#define PTCR_PATB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
> +#define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
> +
> /* Partition Table Entry Fields */
> #define PATBE1_GR 0x8000000000000000
>
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 8075b7149abc..98ce17985b13 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -2028,6 +2028,35 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> env->spr[SPR_SDR1] = value;
> }
>
> +#if defined(TARGET_PPC64)
> +void ppc_store_ptcr(CPUPPCState *env, target_ulong value)
> +{
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
> + target_ulong patbsize = value & PTCR_PATS;
> +
> + qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
> +
> + assert(!cpu->vhyp);
> + assert(env->mmu_model & POWERPC_MMU_3_00);
> +
> + if (value & ~ptcr_mask) {
> + error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
> + value & ~ptcr_mask);
> + value &= ptcr_mask;
> + }
> +
> + if (patbsize > 24) {
> + error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
> + " stored in PTCR", patbsize);
> + return;
> + }
> +
> + env->spr[SPR_PTCR] = value;
> +}
> +
> +#endif /* defined(TARGET_PPC64) */
> +
> /* Segment registers load and store */
> target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
> {
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 3beaa1e2f0c8..2a4140f42062 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7136,6 +7136,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
> if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
> }
> + if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
> + cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
> + }
> cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
> env->spr[SPR_DAR], env->spr[SPR_DSISR]);
> break;
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 95e8dba97a35..118631efbeb6 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -420,6 +420,11 @@ static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
> tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
> tcg_temp_free(t0);
> }
> +static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
> +}
> +
> #endif
> #endif
>
> @@ -8167,6 +8172,18 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power9_mmu(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + /* Partition Table Control */
> + spr_register_hv(env, SPR_PTCR, "PTCR",
> + SPR_NOACCESS, SPR_NOACCESS,
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_ptcr,
> + 0x00000000);
> +#endif
> +}
> +
> static void init_proc_book3s_common(CPUPPCState *env)
> {
> gen_spr_ne_601(env);
> @@ -8719,6 +8736,7 @@ static void init_proc_POWER9(CPUPPCState *env)
> gen_spr_power8_ic(env);
> gen_spr_power8_book4(env);
> gen_spr_power8_rpr(env);
> + gen_spr_power9_mmu(env);
>
> /* POWER9 Specific registers */
> spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 3/5] target/ppc: add hash MMU definitions for ISA v3.0
2018-04-24 11:30 [Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 1/5] target/ppc: return a nil HPT base address on sPAPR machines Cédric Le Goater
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 2/5] target/ppc: add basic support for PTCR on POWER9 Cédric Le Goater
@ 2018-04-24 11:30 ` Cédric Le Goater
2018-05-03 0:48 ` David Gibson
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines Cédric Le Goater
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 5/5] target/ppc: generalize check on radix when in HV mode Cédric Le Goater
4 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 11:30 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
The HPTE bits definitions are slightly modified in ISA v3.0. Let's add
some helpers to hide the differences in the hash MMU code.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_hcall.c | 5 +++--
target/ppc/mmu-hash64.c | 30 ++++++++++++++++++++++--------
target/ppc/mmu-hash64.h | 30 ++++++++++++++++++++++++++++++
3 files changed, 55 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 16bccdd5c012..929f4e05492d 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -94,7 +94,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return H_PARAMETER;
}
- raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
+ raddr = (ptel & ppc_hash64_hpte_r_rpn(cpu)) & ~((1ULL << apshift) - 1);
if (is_ram_address(spapr, raddr)) {
/* Regular RAM - should have WIMG=0010 */
@@ -586,7 +586,8 @@ static int rehash_hpte(PowerPCCPU *cpu,
base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
- avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
+ avpn = ppc_hash64_hpte_v_avpn_val(cpu, pte0) &
+ ~(((1ULL << base_pg_shift) - 1) >> 23);
if (pte0 & HPTE64_V_SECONDARY) {
pteg = ~pteg;
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a1db20e3a8ed..ecea2ae04dd3 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -452,7 +452,8 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
false, n * HASH_PTE_SIZE_64);
}
-static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
+static unsigned hpte_page_shift(PowerPCCPU *cpu,
+ const PPCHash64SegmentPageSizes *sps,
uint64_t pte0, uint64_t pte1)
{
int i;
@@ -479,7 +480,7 @@ static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
continue;
}
- mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
+ mask = ((1ULL << ps->page_shift) - 1) & ppc_hash64_hpte_r_rpn(cpu);
if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
return ps->page_shift;
@@ -489,6 +490,18 @@ static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
return 0; /* Bad page size encoding */
}
+static bool ppc_hash64_hpte_v_compare(PowerPCCPU *cpu, target_ulong pte0,
+ target_ulong ptem)
+{
+ CPUPPCState *env = &cpu->env;
+
+ if (env->mmu_model & POWERPC_MMU_3_00) {
+ return HPTE64_V_COMPARE_3_0(pte0, ptem);
+ } else {
+ return HPTE64_V_COMPARE(pte0, ptem);
+ }
+}
+
static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
const PPCHash64SegmentPageSizes *sps,
target_ulong ptem,
@@ -509,8 +522,8 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
pte1 = ppc_hash64_hpte1(cpu, pteg, i);
/* This compares V, B, H (secondary) and the AVPN */
- if (HPTE64_V_COMPARE(pte0, ptem)) {
- *pshift = hpte_page_shift(sps, pte0, pte1);
+ if (ppc_hash64_hpte_v_compare(cpu, pte0, ptem)) {
+ *pshift = hpte_page_shift(cpu, sps, pte0, pte1);
/*
* If there is no match, ignore the PTE, it could simply
* be for a different segment size encoding and the
@@ -570,7 +583,8 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
hash = vsid ^ (epn >> sps->page_shift);
}
- ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
+ ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) &
+ ppc_hash64_hpte_v_avpn(cpu));
ptem |= HPTE64_V_VALID;
/* Page address translation */
@@ -624,7 +638,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
break;
}
- shift = hpte_page_shift(sps, pte0, pte1);
+ shift = hpte_page_shift(cpu, sps, pte0, pte1);
if (shift) {
return shift;
}
@@ -860,7 +874,7 @@ skip_slb_search:
/* 7. Determine the real address from the PTE */
- raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
+ raddr = deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, eaddr);
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, 1ULL << apshift);
@@ -910,7 +924,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
return -1;
}
- return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
+ return deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, addr)
& TARGET_PAGE_MASK;
}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 53dcec5b9316..a3a0de452b94 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -70,8 +70,12 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
#define HPTE64_V_SSIZE_SHIFT 62
#define HPTE64_V_AVPN_SHIFT 7
#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
+#define HPTE64_V_AVPN_3_0 0x000fffffffffff80ULL
#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
+#define HPTE64_V_AVPN_VAL_3_0(x) \
+ (((x) & HPTE64_V_AVPN_3_0) >> HPTE64_V_AVPN_SHIFT)
#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
+#define HPTE64_V_COMPARE_3_0(x, y) (!(((x) ^ (y)) & 0x3fffffffffffff83ULL))
#define HPTE64_V_BOLTED 0x0000000000000010ULL
#define HPTE64_V_LARGE 0x0000000000000004ULL
#define HPTE64_V_SECONDARY 0x0000000000000002ULL
@@ -82,6 +86,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
#define HPTE64_R_KEY_HI 0x3000000000000000ULL
#define HPTE64_R_RPN_SHIFT 12
#define HPTE64_R_RPN 0x0ffffffffffff000ULL
+#define HPTE64_R_RPN_3_0 0x01fffffffffff000ULL
#define HPTE64_R_FLAGS 0x00000000000003ffULL
#define HPTE64_R_PP 0x0000000000000003ULL
#define HPTE64_R_N 0x0000000000000004ULL
@@ -99,6 +104,31 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
+static inline target_ulong ppc_hash64_hpte_r_rpn(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ return env->mmu_model & POWERPC_MMU_3_00 ?
+ HPTE64_R_RPN_3_0 : HPTE64_R_RPN;
+}
+
+static inline target_ulong ppc_hash64_hpte_v_avpn(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ return env->mmu_model & POWERPC_MMU_3_00 ?
+ HPTE64_V_AVPN_3_0 : HPTE64_V_AVPN;
+}
+
+static inline target_ulong ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
+ target_ulong pte0)
+{
+ CPUPPCState *env = &cpu->env;
+
+ return env->mmu_model & POWERPC_MMU_3_00 ?
+ HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
+}
+
static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
{
if (cpu->vhyp) {
--
2.13.6
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 3/5] target/ppc: add hash MMU definitions for ISA v3.0
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 3/5] target/ppc: add hash MMU definitions for ISA v3.0 Cédric Le Goater
@ 2018-05-03 0:48 ` David Gibson
0 siblings, 0 replies; 15+ messages in thread
From: David Gibson @ 2018-05-03 0:48 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
[-- Attachment #1: Type: text/plain, Size: 8502 bytes --]
On Tue, Apr 24, 2018 at 01:30:43PM +0200, Cédric Le Goater wrote:
> The HPTE bits definitions are slightly modified in ISA v3.0. Let's add
> some helpers to hide the differences in the hash MMU code.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/spapr_hcall.c | 5 +++--
> target/ppc/mmu-hash64.c | 30 ++++++++++++++++++++++--------
> target/ppc/mmu-hash64.h | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 55 insertions(+), 10 deletions(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 16bccdd5c012..929f4e05492d 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -94,7 +94,7 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> return H_PARAMETER;
> }
>
> - raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
> + raddr = (ptel & ppc_hash64_hpte_r_rpn(cpu)) & ~((1ULL << apshift) - 1);
Doesn't H_ENTER always use the old format? I thought it did that so
PAPR guests never saw the new format, only powernv.
> if (is_ram_address(spapr, raddr)) {
> /* Regular RAM - should have WIMG=0010 */
> @@ -586,7 +586,8 @@ static int rehash_hpte(PowerPCCPU *cpu,
>
> base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
> assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
> - avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
> + avpn = ppc_hash64_hpte_v_avpn_val(cpu, pte0) &
> + ~(((1ULL << base_pg_shift) - 1) >> 23);
Likwise rehash_hpte is only used for PAPR guests, so I don't think it
needs to handle the new format.
> if (pte0 & HPTE64_V_SECONDARY) {
> pteg = ~pteg;
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index a1db20e3a8ed..ecea2ae04dd3 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -452,7 +452,8 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
> false, n * HASH_PTE_SIZE_64);
> }
>
> -static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
> +static unsigned hpte_page_shift(PowerPCCPU *cpu,
> + const PPCHash64SegmentPageSizes *sps,
> uint64_t pte0, uint64_t pte1)
> {
> int i;
> @@ -479,7 +480,7 @@ static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
> continue;
> }
>
> - mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
> + mask = ((1ULL << ps->page_shift) - 1) & ppc_hash64_hpte_r_rpn(cpu);
>
> if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
> return ps->page_shift;
> @@ -489,6 +490,18 @@ static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
> return 0; /* Bad page size encoding */
> }
>
> +static bool ppc_hash64_hpte_v_compare(PowerPCCPU *cpu, target_ulong pte0,
> + target_ulong ptem)
> +{
> + CPUPPCState *env = &cpu->env;
> +
> + if (env->mmu_model & POWERPC_MMU_3_00) {
> + return HPTE64_V_COMPARE_3_0(pte0, ptem);
> + } else {
> + return HPTE64_V_COMPARE(pte0, ptem);
> + }
> +}
Ugh, and here we get more complications, because I guess we need to
check for (mmu_model == 3.00) && (!vhyp) to exclude PAPR guests. And
a bunch of similar places.
> +
> static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
> const PPCHash64SegmentPageSizes *sps,
> target_ulong ptem,
> @@ -509,8 +522,8 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
> pte1 = ppc_hash64_hpte1(cpu, pteg, i);
>
> /* This compares V, B, H (secondary) and the AVPN */
> - if (HPTE64_V_COMPARE(pte0, ptem)) {
> - *pshift = hpte_page_shift(sps, pte0, pte1);
> + if (ppc_hash64_hpte_v_compare(cpu, pte0, ptem)) {
> + *pshift = hpte_page_shift(cpu, sps, pte0, pte1);
> /*
> * If there is no match, ignore the PTE, it could simply
> * be for a different segment size encoding and the
> @@ -570,7 +583,8 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
> epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
> hash = vsid ^ (epn >> sps->page_shift);
> }
> - ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
> + ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) &
> + ppc_hash64_hpte_v_avpn(cpu));
> ptem |= HPTE64_V_VALID;
>
> /* Page address translation */
> @@ -624,7 +638,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
> break;
> }
>
> - shift = hpte_page_shift(sps, pte0, pte1);
> + shift = hpte_page_shift(cpu, sps, pte0, pte1);
> if (shift) {
> return shift;
> }
> @@ -860,7 +874,7 @@ skip_slb_search:
>
> /* 7. Determine the real address from the PTE */
>
> - raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
> + raddr = deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, eaddr);
>
> tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> prot, mmu_idx, 1ULL << apshift);
> @@ -910,7 +924,7 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
> return -1;
> }
>
> - return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
> + return deposit64(pte.pte1 & ppc_hash64_hpte_r_rpn(cpu), 0, apshift, addr)
> & TARGET_PAGE_MASK;
> }
>
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 53dcec5b9316..a3a0de452b94 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -70,8 +70,12 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
> #define HPTE64_V_SSIZE_SHIFT 62
> #define HPTE64_V_AVPN_SHIFT 7
> #define HPTE64_V_AVPN 0x3fffffffffffff80ULL
> +#define HPTE64_V_AVPN_3_0 0x000fffffffffff80ULL
> #define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
> +#define HPTE64_V_AVPN_VAL_3_0(x) \
> + (((x) & HPTE64_V_AVPN_3_0) >> HPTE64_V_AVPN_SHIFT)
> #define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
> +#define HPTE64_V_COMPARE_3_0(x, y) (!(((x) ^ (y)) & 0x3fffffffffffff83ULL))
> #define HPTE64_V_BOLTED 0x0000000000000010ULL
> #define HPTE64_V_LARGE 0x0000000000000004ULL
> #define HPTE64_V_SECONDARY 0x0000000000000002ULL
> @@ -82,6 +86,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
> #define HPTE64_R_KEY_HI 0x3000000000000000ULL
> #define HPTE64_R_RPN_SHIFT 12
> #define HPTE64_R_RPN 0x0ffffffffffff000ULL
> +#define HPTE64_R_RPN_3_0 0x01fffffffffff000ULL
> #define HPTE64_R_FLAGS 0x00000000000003ffULL
> #define HPTE64_R_PP 0x0000000000000003ULL
> #define HPTE64_R_N 0x0000000000000004ULL
> @@ -99,6 +104,31 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
> #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
> #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
>
> +static inline target_ulong ppc_hash64_hpte_r_rpn(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> +
> + return env->mmu_model & POWERPC_MMU_3_00 ?
> + HPTE64_R_RPN_3_0 : HPTE64_R_RPN;
> +}
> +
> +static inline target_ulong ppc_hash64_hpte_v_avpn(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> +
> + return env->mmu_model & POWERPC_MMU_3_00 ?
> + HPTE64_V_AVPN_3_0 : HPTE64_V_AVPN;
> +}
> +
> +static inline target_ulong ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
> + target_ulong pte0)
> +{
> + CPUPPCState *env = &cpu->env;
> +
> + return env->mmu_model & POWERPC_MMU_3_00 ?
> + HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
> +}
> +
> static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
> {
> if (cpu->vhyp) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-04-24 11:30 [Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
` (2 preceding siblings ...)
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 3/5] target/ppc: add hash MMU definitions for ISA v3.0 Cédric Le Goater
@ 2018-04-24 11:30 ` Cédric Le Goater
2018-04-24 12:03 ` Cédric Le Goater
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 5/5] target/ppc: generalize check on radix when in HV mode Cédric Le Goater
4 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 11:30 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
On a POWER9 processor, the Partition Table is composed of a pair of
doublewords per partition. The first doubleword indicates whether the
partition uses HPT or Radix Trees translation and contains the address
of the host's translation table structure and size.
The first doubleword of the PTCR holds the Hash Page Table base
address for the host when the hash MMU is in use. Add an helper to
retrieve the HPT base address depending on the MMU revision.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/mmu-book3s-v3.h | 5 +++++
target/ppc/mmu-hash64.c | 20 ++++++++++++++++++++
target/ppc/mmu-hash64.h | 6 ++++--
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index fdf80987d7b2..a7ab580c3140 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -54,6 +54,11 @@ static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx);
+static inline hwaddr ppc64_v3_get_patbe0(PowerPCCPU *cpu)
+{
+ return ldq_phys(CPU(cpu)->as, cpu->env.spr[SPR_PTCR] & PTCR_PATB);
+}
+
#endif /* TARGET_PPC64 */
#endif /* CONFIG_USER_ONLY */
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index ecea2ae04dd3..fae164d30706 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -290,6 +290,26 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
return rt;
}
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ /* We should not reach this routine on sPAPR machines */
+ assert(!cpu->vhyp);
+
+ /* PowerNV machine */
+ if (msr_hv) {
+ if (env->mmu_model & POWERPC_MMU_3_00) {
+ return ppc64_v3_get_patbe0(cpu);
+ } else {
+ return cpu->env.spr[SPR_SDR1];
+ }
+ } else {
+ error_report("PowerNV guest support Unimplemented");
+ exit(1);
+ }
+}
+
/* Check No-Execute or Guarded Storage */
static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
ppc_hash_pte64_t pte)
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index a3a0de452b94..daf3ba27e2cc 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -129,12 +129,14 @@ static inline target_ulong ppc_hash64_hpte_v_avpn_val(PowerPCCPU *cpu,
HPTE64_V_AVPN_VAL_3_0(pte0) : HPTE64_V_AVPN_VAL(pte0);
}
+hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu);
+
static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
{
if (cpu->vhyp) {
return 0;
}
- return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
+ return ppc_hash64_hpt_reg(cpu) & SDR_64_HTABORG;
}
static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
@@ -144,7 +146,7 @@ static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
return vhc->hpt_mask(cpu->vhyp);
}
- return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
+ return (1ULL << ((ppc_hash64_hpt_reg(cpu) & SDR_64_HTABSIZE) + 18 - 7)) - 1;
}
struct ppc_hash_pte64 {
--
2.13.6
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines Cédric Le Goater
@ 2018-04-24 12:03 ` Cédric Le Goater
2018-04-24 12:41 ` Cédric Le Goater
0 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 12:03 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson; +Cc: Suraj Jitindar Singh
> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> +
> + /* We should not reach this routine on sPAPR machines */
> + assert(!cpu->vhyp);
> +
> + /* PowerNV machine */
> + if (msr_hv) {
> + if (env->mmu_model & POWERPC_MMU_3_00) {
> + return ppc64_v3_get_patbe0(cpu);
> + } else {
> + return cpu->env.spr[SPR_SDR1];
> + }
> + } else {
> + error_report("PowerNV guest support Unimplemented");
> + exit(1);
I just noticed that this breaks 970 CPUs ...
C.
> + }
> +}
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-04-24 12:03 ` Cédric Le Goater
@ 2018-04-24 12:41 ` Cédric Le Goater
2018-05-03 0:58 ` David Gibson
0 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 12:41 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson; +Cc: Suraj Jitindar Singh
On 04/24/2018 02:03 PM, Cédric Le Goater wrote:
>> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
>> +{
>> + CPUPPCState *env = &cpu->env;
>> +
>> + /* We should not reach this routine on sPAPR machines */
>> + assert(!cpu->vhyp);
>> +
>> + /* PowerNV machine */
>> + if (msr_hv) {
>> + if (env->mmu_model & POWERPC_MMU_3_00) {
>> + return ppc64_v3_get_patbe0(cpu);
>> + } else {
>> + return cpu->env.spr[SPR_SDR1];
>> + }
>> + } else {
>> + error_report("PowerNV guest support Unimplemented");
>> + exit(1);
>
> I just noticed that this breaks 970 CPUs ...
How about ?
if (env->mmu_model < POWERPC_MMU_2_07) {
return cpu->env.spr[SPR_SDR1];
}
/* P8/P9 PowerNV machine */
if (msr_hv) {
if (env->mmu_model == POWERPC_MMU_3_00) {
return ppc64_v3_get_patbe0(cpu);
} else {
return cpu->env.spr[SPR_SDR1];
}
} else {
error_report("PowerNV guest support Unimplemented");
exit(1);
}
and I have to fix all the :
env->mmu_model & POWERPC_MMU_3_00
by :
env->mmu_model == POWERPC_MMU_3_00
I tripped over with the recent changes
C.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-04-24 12:41 ` Cédric Le Goater
@ 2018-05-03 0:58 ` David Gibson
2018-05-03 5:52 ` Cédric Le Goater
0 siblings, 1 reply; 15+ messages in thread
From: David Gibson @ 2018-05-03 0:58 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
[-- Attachment #1: Type: text/plain, Size: 1886 bytes --]
On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote:
> On 04/24/2018 02:03 PM, Cédric Le Goater wrote:
> >> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
> >> +{
> >> + CPUPPCState *env = &cpu->env;
> >> +
> >> + /* We should not reach this routine on sPAPR machines */
> >> + assert(!cpu->vhyp);
> >> +
> >> + /* PowerNV machine */
> >> + if (msr_hv) {
> >> + if (env->mmu_model & POWERPC_MMU_3_00) {
> >> + return ppc64_v3_get_patbe0(cpu);
> >> + } else {
> >> + return cpu->env.spr[SPR_SDR1];
> >> + }
> >> + } else {
> >> + error_report("PowerNV guest support Unimplemented");
> >> + exit(1);
> >
> > I just noticed that this breaks 970 CPUs ...
>
> How about ?
Hmm.. I'm not actually seeing why it breaks 970.
I really want to ditch 970 support, but we have to go through the
deprecation process first.
>
> if (env->mmu_model < POWERPC_MMU_2_07) {
> return cpu->env.spr[SPR_SDR1];
> }
>
> /* P8/P9 PowerNV machine */
> if (msr_hv) {
> if (env->mmu_model == POWERPC_MMU_3_00) {
> return ppc64_v3_get_patbe0(cpu);
> } else {
> return cpu->env.spr[SPR_SDR1];
> }
> } else {
> error_report("PowerNV guest support Unimplemented");
> exit(1);
> }
>
> and I have to fix all the :
>
> env->mmu_model & POWERPC_MMU_3_00
>
> by :
>
> env->mmu_model == POWERPC_MMU_3_00
>
> I tripped over with the recent changes
Right.. eventually I actually want this to be something more like
if (cpu->radix64_opts)
but I'm not sure on the details yet.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-05-03 0:58 ` David Gibson
@ 2018-05-03 5:52 ` Cédric Le Goater
2018-05-03 6:36 ` David Gibson
0 siblings, 1 reply; 15+ messages in thread
From: Cédric Le Goater @ 2018-05-03 5:52 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
On 05/03/2018 02:58 AM, David Gibson wrote:
> On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote:
>> On 04/24/2018 02:03 PM, Cédric Le Goater wrote:
>>>> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
>>>> +{
>>>> + CPUPPCState *env = &cpu->env;
>>>> +
>>>> + /* We should not reach this routine on sPAPR machines */
>>>> + assert(!cpu->vhyp);
>>>> +
>>>> + /* PowerNV machine */
>>>> + if (msr_hv) {
>>>> + if (env->mmu_model & POWERPC_MMU_3_00) {
>>>> + return ppc64_v3_get_patbe0(cpu);
>>>> + } else {
>>>> + return cpu->env.spr[SPR_SDR1];
>>>> + }
>>>> + } else {
>>>> + error_report("PowerNV guest support Unimplemented");
>>>> + exit(1);
>>>
>>> I just noticed that this breaks 970 CPUs ...
>>
>> How about ?
>
> Hmm.. I'm not actually seeing why it breaks 970.
it does not have MSR_SHV bit.
> I really want to ditch 970 support, but we have to go through the
> deprecation process first.
Is it causing a lot of maintenance issues ?
>>
>> if (env->mmu_model < POWERPC_MMU_2_07) {
>> return cpu->env.spr[SPR_SDR1];
>> }
>>
>> /* P8/P9 PowerNV machine */
>> if (msr_hv) {
>> if (env->mmu_model == POWERPC_MMU_3_00) {
>> return ppc64_v3_get_patbe0(cpu);
>> } else {
>> return cpu->env.spr[SPR_SDR1];
>> }
>> } else {
>> error_report("PowerNV guest support Unimplemented");
>> exit(1);
>> }
>>
>> and I have to fix all the :
>>
>> env->mmu_model & POWERPC_MMU_3_00
>>
>> by :
>>
>> env->mmu_model == POWERPC_MMU_3_00
>>
>> I tripped over with the recent changes
>
> Right.. eventually I actually want this to be something more like
> if (cpu->radix64_opts)
> but I'm not sure on the details yet.
OK.
C.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-05-03 5:52 ` Cédric Le Goater
@ 2018-05-03 6:36 ` David Gibson
2018-05-03 8:05 ` Cédric Le Goater
0 siblings, 1 reply; 15+ messages in thread
From: David Gibson @ 2018-05-03 6:36 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
[-- Attachment #1: Type: text/plain, Size: 1539 bytes --]
On Thu, May 03, 2018 at 07:52:32AM +0200, Cédric Le Goater wrote:
> On 05/03/2018 02:58 AM, David Gibson wrote:
> > On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote:
> >> On 04/24/2018 02:03 PM, Cédric Le Goater wrote:
> >>>> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
> >>>> +{
> >>>> + CPUPPCState *env = &cpu->env;
> >>>> +
> >>>> + /* We should not reach this routine on sPAPR machines */
> >>>> + assert(!cpu->vhyp);
> >>>> +
> >>>> + /* PowerNV machine */
> >>>> + if (msr_hv) {
> >>>> + if (env->mmu_model & POWERPC_MMU_3_00) {
> >>>> + return ppc64_v3_get_patbe0(cpu);
> >>>> + } else {
> >>>> + return cpu->env.spr[SPR_SDR1];
> >>>> + }
> >>>> + } else {
> >>>> + error_report("PowerNV guest support Unimplemented");
> >>>> + exit(1);
> >>>
> >>> I just noticed that this breaks 970 CPUs ...
> >>
> >> How about ?
> >
> > Hmm.. I'm not actually seeing why it breaks 970.
>
> it does not have MSR_SHV bit.
It does, actually. At least, as long as it's not strapped into "Apple
mode".
> > I really want to ditch 970 support, but we have to go through the
> > deprecation process first.
>
> Is it causing a lot of maintenance issues ?
Enough. The explicit RMA allocation stuff is a particular pain.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines
2018-05-03 6:36 ` David Gibson
@ 2018-05-03 8:05 ` Cédric Le Goater
0 siblings, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2018-05-03 8:05 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Suraj Jitindar Singh
On 05/03/2018 08:36 AM, David Gibson wrote:
> On Thu, May 03, 2018 at 07:52:32AM +0200, Cédric Le Goater wrote:
>> On 05/03/2018 02:58 AM, David Gibson wrote:
>>> On Tue, Apr 24, 2018 at 02:41:47PM +0200, Cédric Le Goater wrote:
>>>> On 04/24/2018 02:03 PM, Cédric Le Goater wrote:
>>>>>> +hwaddr ppc_hash64_hpt_reg(PowerPCCPU *cpu)
>>>>>> +{
>>>>>> + CPUPPCState *env = &cpu->env;
>>>>>> +
>>>>>> + /* We should not reach this routine on sPAPR machines */
>>>>>> + assert(!cpu->vhyp);
>>>>>> +
>>>>>> + /* PowerNV machine */
>>>>>> + if (msr_hv) {
>>>>>> + if (env->mmu_model & POWERPC_MMU_3_00) {
>>>>>> + return ppc64_v3_get_patbe0(cpu);
>>>>>> + } else {
>>>>>> + return cpu->env.spr[SPR_SDR1];
>>>>>> + }
>>>>>> + } else {
>>>>>> + error_report("PowerNV guest support Unimplemented");
>>>>>> + exit(1);
>>>>>
>>>>> I just noticed that this breaks 970 CPUs ...
>>>>
>>>> How about ?
>>>
>>> Hmm.. I'm not actually seeing why it breaks 970.
>>
>> it does not have MSR_SHV bit.
>
> It does, actually. At least, as long as it's not strapped into "Apple
> mode".
ah. this is why the tests are failing then :
tests/boot-serial-test.c: { "ppc64", "mac99", "", "PowerPC,970FX" },
C.
>
>>> I really want to ditch 970 support, but we have to go through the
>>> deprecation process first.
>>
>> Is it causing a lot of maintenance issues ?
>
> Enough. The explicit RMA allocation stuff is a particular pain.
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v4 5/5] target/ppc: generalize check on radix when in HV mode
2018-04-24 11:30 [Qemu-devel] [PATCH v4 0/5] target/ppc: add hash MMU support for the POWER9 PowerNV machine Cédric Le Goater
` (3 preceding siblings ...)
2018-04-24 11:30 ` [Qemu-devel] [PATCH v4 4/5] target/ppc: add hash MMU support for PowerNV POWER9 machines Cédric Le Goater
@ 2018-04-24 11:30 ` Cédric Le Goater
4 siblings, 0 replies; 15+ messages in thread
From: Cédric Le Goater @ 2018-04-24 11:30 UTC (permalink / raw)
To: qemu-ppc, qemu-devel, David Gibson
Cc: Suraj Jitindar Singh, Cédric Le Goater
On a POWER9 processor, the first doubleword of the partition table
entry (as pointed to by the PTCR) indicates whether the host uses HPT
or Radix Tree translation for that partition. Use that bit to check
for radix mode on pseries and powernv QEMU machines.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/mmu-book3s-v3.c | 23 +++++++++++++++++++++--
target/ppc/mmu-book3s-v3.h | 4 +++-
target/ppc/mmu_helper.c | 4 ++--
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
index b60df4408f3b..89edbb6abc5c 100644
--- a/target/ppc/mmu-book3s-v3.c
+++ b/target/ppc/mmu-book3s-v3.c
@@ -19,16 +19,35 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "qemu/error-report.h"
#include "mmu-hash64.h"
#include "mmu-book3s-v3.h"
#include "mmu-radix64.h"
+bool ppc64_v3_radix(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ /* sPAPR machine */
+ if (cpu->vhyp) {
+ return ppc64_radix_guest(cpu);
+ }
+
+ /* PowerNV machine - only HV mode is supported */
+ if (msr_hv) {
+ return ppc64_v3_get_patbe0(cpu) & PATBE0_HR;
+ } else {
+ error_report("PowerNV guest support Unimplemented");
+ exit(1);
+ }
+}
+
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx)
{
- if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
+ if (ppc64_v3_radix(cpu)) {
return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
- } else { /* Guest uses hash */
+ } else {
return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
}
}
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index a7ab580c3140..9721791d2dd3 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -29,7 +29,8 @@
#define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
/* Partition Table Entry Fields */
-#define PATBE1_GR 0x8000000000000000
+#define PATBE0_HR PPC_BIT(0) /* 1:Host Radix 0:HPT */
+#define PATBE1_GR PPC_BIT(0) /* 1:Guest Radix 0:HPT */
/* Process Table Entry */
struct prtb_entry {
@@ -50,6 +51,7 @@ static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
}
+bool ppc64_v3_radix(PowerPCCPU *cpu);
int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
int mmu_idx);
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 98ce17985b13..e081cfbe64d5 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1285,7 +1285,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
break;
case POWERPC_MMU_3_00:
- if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+ if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
/* TODO - Unsupported */
} else {
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
@@ -1431,7 +1431,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case POWERPC_MMU_2_07:
return ppc_hash64_get_phys_page_debug(cpu, addr);
case POWERPC_MMU_3_00:
- if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+ if (ppc64_v3_radix(ppc_env_get_cpu(env))) {
return ppc_radix64_get_phys_page_debug(cpu, addr);
} else {
return ppc_hash64_get_phys_page_debug(cpu, addr);
--
2.13.6
^ permalink raw reply related [flat|nested] 15+ messages in thread