[U-Boot] [PATCH 13/93] arm: Remove theadorable_debug board

[Simon Glass <sjg@chromium.org>]

This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 board/theadorable/MAINTAINERS       |   6 -
 board/theadorable/Makefile          |   6 -
 board/theadorable/fpga.c            | 178 ---------------
 board/theadorable/theadorable.c     | 336 ----------------------------
 board/theadorable/theadorable.h     |  11 -
 configs/theadorable_debug_defconfig |  74 ------
 include/configs/theadorable.h       | 125 -----------
 7 files changed, 736 deletions(-)
 delete mode 100644 board/theadorable/MAINTAINERS
 delete mode 100644 board/theadorable/Makefile
 delete mode 100644 board/theadorable/fpga.c
 delete mode 100644 board/theadorable/theadorable.c
 delete mode 100644 board/theadorable/theadorable.h
 delete mode 100644 configs/theadorable_debug_defconfig
 delete mode 100644 include/configs/theadorable.h

diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS
deleted file mode 100644
index 1e8df93d379..00000000000
--- a/board/theadorable/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-THEADORABLE BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/theadorable/
-F:	include/configs/theadorable.h
-F:	configs/theadorable_debug_defconfig
diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile
deleted file mode 100644
index b85faa676d7..00000000000
--- a/board/theadorable/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
-
-obj-y	:= theadorable.o
-obj-y	+= fpga.o
diff --git a/board/theadorable/fpga.c b/board/theadorable/fpga.c
deleted file mode 100644
index 4f8bf5e778f..00000000000
--- a/board/theadorable/fpga.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <altera.h>
-#include <errno.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-mvebu/spi.h>
-#include "theadorable.h"
-
-/*
- * FPGA programming support
- */
-static int fpga_pre_fn(int cookie)
-{
-	int gpio_config = COOKIE2CONFIG(cookie);
-	int gpio_done = COOKIE2DONE(cookie);
-	int ret;
-
-	debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n",
-	      __func__, __LINE__, cookie, gpio_config, gpio_done);
-
-	/* Configure config pin */
-	/* Set to output */
-	ret = gpio_request(gpio_config, "CONFIG");
-	if (ret < 0)
-		return ret;
-	gpio_direction_output(gpio_config, 1);
-
-	/* Configure done pin */
-	/* Set to input */
-	ret = gpio_request(gpio_done, "DONE");
-	if (ret < 0)
-		return ret;
-
-	gpio_direction_input(gpio_done);
-
-	return 0;
-}
-
-static int fpga_config_fn(int assert, int flush, int cookie)
-{
-	int gpio_config = COOKIE2CONFIG(cookie);
-
-	debug("%s (%d): cookie=%08x gpio_config=%d\n",
-	      __func__, __LINE__, cookie, gpio_config);
-
-	if (assert)
-		gpio_set_value(gpio_config, 1);
-	else
-		gpio_set_value(gpio_config, 0);
-
-	return 0;
-}
-
-static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	int spi_bus = COOKIE2SPI_BUS(cookie);
-	int spi_dev = COOKIE2SPI_DEV(cookie);
-	struct kwspi_registers *reg;
-	u32 control_reg;
-	u32 config_reg;
-	void *dst;
-
-	/*
-	 * Write data to FPGA attached to SPI bus via SPI direct write.
-	 * This results in the fastest and easiest way to program the
-	 * bitstream into the FPGA.
-	 */
-	debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n",
-	      __func__, __LINE__, cookie, spi_bus, spi_dev);
-
-	if (spi_bus == 0) {
-		reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600);
-		dst = (void *)SPI_BUS0_DEV1_BASE;
-	} else {
-		reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680);
-		dst = (void *)SPI_BUS1_DEV2_BASE;
-	}
-
-	/* Configure SPI controller for direct access mode */
-	control_reg = readl(&reg->ctrl);
-	config_reg = readl(&reg->cfg);
-	writel(0x00000214, &reg->cfg);		/* 27MHz clock */
-	writel(0x00000000, &reg->dw_cfg);	/* don't de-asset CS */
-	writel(KWSPI_CSN_ACT, &reg->ctrl);	/* activate CS */
-
-	/* Copy data to the SPI direct mapped window */
-	memcpy(dst, buf, len);
-
-	/* Restore original register values */
-	writel(control_reg, &reg->ctrl);
-	writel(config_reg, &reg->cfg);
-
-	return 0;
-}
-
-/* Returns the state of CONF_DONE Pin */
-static int fpga_done_fn(int cookie)
-{
-	int gpio_done = COOKIE2DONE(cookie);
-	unsigned long ts;
-
-	debug("%s (%d): cookie=%08x gpio_done=%d\n",
-	      __func__, __LINE__, cookie, gpio_done);
-
-	ts = get_timer(0);
-	do {
-		if (gpio_get_value(gpio_done))
-			return 0;
-	} while (get_timer(ts) < 1000);
-
-	/* timeout so return error */
-	return -ENODEV;
-}
-
-static altera_board_specific_func stratixv_fns = {
-	.pre = fpga_pre_fn,
-	.config = fpga_config_fn,
-	.write = fpga_write_fn,
-	.done = fpga_done_fn,
-};
-
-static Altera_desc altera_fpga[] = {
-	{
-		/* Family */
-		Altera_StratixV,
-		/* Interface type */
-		passive_serial,
-		/* No limitation as additional data will be ignored */
-		-1,
-		/* Device function table */
-		(void *)&stratixv_fns,
-		/* Base interface address specified in driver */
-		NULL,
-		/* Cookie implementation */
-		/*
-		 * In this 32bit word the following information is coded:
-		 * Bit 31 ... Bit 0
-		 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
-		 */
-		FPGA_COOKIE(0, 1, 26, 7)
-	},
-	{
-		/* Family */
-		Altera_StratixV,
-		/* Interface type */
-		passive_serial,
-		/* No limitation as additional data will be ignored */
-		-1,
-		/* Device function table */
-		(void *)&stratixv_fns,
-		/* Base interface address specified in driver */
-		NULL,
-		/* Cookie implementation */
-		/*
-		 * In this 32bit word the following information is coded:
-		 * Bit 31 ... Bit 0
-		 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
-		 */
-		FPGA_COOKIE(1, 2, 29, 9)
-	},
-};
-
-/* Add device descriptor to FPGA device table */
-void board_fpga_add(void)
-{
-	int i;
-
-	fpga_init();
-	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
-		fpga_add(fpga_altera, &altera_fpga[i]);
-}
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
deleted file mode 100644
index b59589ae829..00000000000
--- a/board/theadorable/theadorable.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <pci.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <linux/crc8.h>
-#include <linux/mbus.h>
-#ifdef CONFIG_NET
-#include <netdev.h>
-#endif
-#include "theadorable.h"
-
-#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
-#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
-#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
-	(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
-
-#define THEADORABLE_GPP_OUT_ENA_LOW	0x00336780
-#define THEADORABLE_GPP_OUT_ENA_MID	0x00003cf0
-#define THEADORABLE_GPP_OUT_ENA_HIGH	(~(0x0))
-
-#define THEADORABLE_GPP_OUT_VAL_LOW	0x2c0c983f
-#define THEADORABLE_GPP_OUT_VAL_MID	0x0007000c
-#define THEADORABLE_GPP_OUT_VAL_HIGH	0x00000000
-
-#define GPIO_USB0_PWR_ON		18
-#define GPIO_USB1_PWR_ON		19
-
-#define PEX_SWITCH_NOT_FOUNT_LIMIT	3
-
-#define STM_I2C_BUS	1
-#define STM_I2C_ADDR	0x27
-#define REBOOT_DELAY	1000		/* reboot-delay in ms */
-
-/* DDR3 static configuration */
-static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
-	{0x00001400, 0x7301ca28},	/* DDR SDRAM Configuration Register */
-	{0x00001404, 0x30000800},	/* Dunit Control Low Register */
-	{0x00001408, 0x44149887},	/* DDR SDRAM Timing (Low) Register */
-	{0x0000140C, 0x38d93fc7},	/* DDR SDRAM Timing (High) Register */
-	{0x00001410, 0x1b100001},	/* DDR SDRAM Address Control Register */
-	{0x00001424, 0x0000f3ff},	/* Dunit Control High Register */
-	{0x00001428, 0x000f8830},	/* ODT Timing (Low) Register */
-	{0x0000142C, 0x014c50f4},	/* DDR3 Timing Register */
-	{0x0000147C, 0x0000c671},	/* ODT Timing (High) Register */
-
-	{0x00001494, 0x00010000},	/* DDR SDRAM ODT Control (Low) Reg */
-	{0x0000149C, 0x00000001},	/* DDR Dunit ODT Control Register */
-	{0x000014A0, 0x00000001},	/* DRAM FIFO Control Register */
-	{0x000014A8, 0x00000101},	/* AXI Control Register */
-
-	/*
-	 * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
-	 * training sequence
-	 */
-	{0x000200e8, 0x3fff0e01},
-	{0x00020184, 0x3fffffe0},	/* Close fast path Window to - 2G */
-
-	{0x0001504, 0x7fffffe1},	/* CS0 Size */
-	{0x000150C, 0x00000000},	/* CS1 Size */
-	{0x0001514, 0x00000000},	/* CS2 Size */
-	{0x000151C, 0x00000000},	/* CS3 Size */
-
-	{0x00020220, 0x00000007},	/* Reserved */
-
-	{0x00001538, 0x00000009},	/* Read Data Sample Delays Register */
-	{0x0000153C, 0x00000009},	/* Read Data Ready Delay Register */
-
-	{0x000015D0, 0x00000650},	/* MR0 */
-	{0x000015D4, 0x00000044},	/* MR1 */
-	{0x000015D8, 0x00000010},	/* MR2 */
-	{0x000015DC, 0x00000000},	/* MR3 */
-	{0x000015E0, 0x00000001},
-	{0x000015E4, 0x00203c18},	/* ZQDS Configuration Register */
-	{0x000015EC, 0xf800a225},	/* DDR PHY */
-
-	/* Recommended Settings from Marvell for 4 x 16 bit devices: */
-	{0x000014C0, 0x192424c9},	/* DRAM addr and Ctrl Driving Strenght*/
-	{0x000014C4, 0x0aaa24c9},	/* DRAM Data and DQS Driving Strenght */
-
-	{0x0, 0x0}
-};
-
-static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
-	{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable,  NULL},
-};
-
-extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
-
-/*
- * Lane0 - PCIE0.0 X1 (to WIFI Module)
- * Lane5 - SATA0
- * Lane6 - SATA1
- * Lane7 - SGMII0 (to Ethernet Phy)
- * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
- * all other lanes are disabled
- */
-MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
-	{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
-	  { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
-	    PEX_BUS_DISABLED },
-	  0x0060, serdes_change_m_phy
-	},
-};
-
-/*
- * Define a board-specific detection pulse-width array for the SerDes PCIe
- * interfaces. If not defined in the board code, the default of currently 2
- * is used. Values from 0...3 are possible (2 bits).
- */
-u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
-
-MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
-{
-	/* Only one mode supported for this board */
-	return &board_ddr_modes[0];
-}
-
-MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
-{
-	return &theadorable_serdes_cfg[0];
-}
-
-u8 board_sat_r_get(u8 dev_num, u8 reg)
-{
-	/* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
-	return 0x01;
-}
-
-int board_early_init_f(void)
-{
-	/* Configure MPP */
-	writel(0x00000000, MVEBU_MPP_BASE + 0x00);
-	writel(0x03300000, MVEBU_MPP_BASE + 0x04);
-	writel(0x00000033, MVEBU_MPP_BASE + 0x08);
-	writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
-	writel(0x11110000, MVEBU_MPP_BASE + 0x10);
-	writel(0x00221100, MVEBU_MPP_BASE + 0x14);
-	writel(0x00000000, MVEBU_MPP_BASE + 0x18);
-	writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
-	writel(0x00000000, MVEBU_MPP_BASE + 0x20);
-
-	/* Configure GPIO */
-	writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
-	writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
-	writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
-	writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
-	writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
-	writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	int ret;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
-	/*
-	 * Map SPI devices via MBUS so that they can be accessed via
-	 * the SPI direct access mode
-	 */
-	mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
-			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
-	mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
-			  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
-
-	/*
-	 * Set RX Channel Control 0 Register:
-	 * Tests have shown, that setting the LPF_COEF from 0 (1/8)
-	 * to 3 (1/1) results in a more stable USB connection.
-	 */
-	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
-	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
-	setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
-
-	/* Toggle USB power */
-	ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
-	if (ret < 0)
-		return ret;
-	gpio_direction_output(GPIO_USB0_PWR_ON, 0);
-	ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
-	if (ret < 0)
-		return ret;
-	gpio_direction_output(GPIO_USB1_PWR_ON, 0);
-	mdelay(1);
-	gpio_set_value(GPIO_USB0_PWR_ON, 1);
-	gpio_set_value(GPIO_USB1_PWR_ON, 1);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	board_fpga_add();
-
-	return 0;
-}
-
-#ifdef CONFIG_NET
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in controller(s) come first */
-	return pci_eth_init(bis);
-}
-#endif
-
-int board_video_init(void)
-{
-	struct mvebu_lcd_info lcd_info;
-
-	/* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
-	lcd_info.fb_base	= gd->ram_size;
-	lcd_info.x_res		= 240;
-	lcd_info.x_fp		= 1;
-	lcd_info.x_bp		= 45;
-	lcd_info.y_res		= 320;
-	lcd_info.y_fp		= 1;
-	lcd_info.y_bp		= 3;
-
-	return mvebu_lcd_register_init(&lcd_info);
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	pci_dev_t bdf;
-	ulong bootcount;
-
-	/*
-	 * Check if the PEX switch is detected (somtimes its not available
-	 * on the PCIe bus). In this case, try to recover by issuing a
-	 * soft-reset or even a power-cycle, depending on the bootcounter
-	 * value.
-	 */
-	bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
-	if (bdf == -1) {
-		u8 i2c_buf[8];
-		int ret;
-
-		/* PEX switch not found! */
-		bootcount = bootcount_load();
-		printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
-		       bootcount);
-		if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
-			printf("Issuing power-switch via uC!\n");
-
-			printf("Issuing power-switch via uC!\n");
-			i2c_set_bus_num(STM_I2C_BUS);
-			i2c_buf[0] = STM_I2C_ADDR << 1;
-			i2c_buf[1] = 0xc5;	/* cmd */
-			i2c_buf[2] = 0x01;	/* enable */
-			/* Delay before reboot */
-			i2c_buf[3] = REBOOT_DELAY & 0x00ff;
-			i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
-			/* Delay before shutdown */
-			i2c_buf[5] = 0x00;
-			i2c_buf[6] = 0x00;
-			i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
-
-			ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
-			if (ret) {
-				printf("I2C write error (ret=%d)\n", ret);
-				printf("Issuing soft-reset...\n");
-				/* default handling: SOFT reset */
-				do_reset(NULL, 0, 0, NULL);
-			}
-
-			/* Wait for power-cycle to occur... */
-			printf("Waiting for power-cycle via uC...\n");
-			while (1)
-				;
-		} else {
-			printf("Issuing soft-reset...\n");
-			/* default handling: SOFT reset */
-			do_reset(NULL, 0, 0, NULL);
-		}
-	}
-
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
-int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	pci_dev_t bdf;
-	u16 ven_id, dev_id;
-
-	if (argc != 3)
-		return cmd_usage(cmdtp);
-
-	ven_id = simple_strtoul(argv[1], NULL, 16);
-	dev_id = simple_strtoul(argv[2], NULL, 16);
-
-	printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
-	       ven_id, dev_id);
-
-	/*
-	 * Check if the PCIe device is detected (somtimes its not available
-	 * on the PCIe bus)
-	 */
-	bdf = pci_find_device(ven_id, dev_id, 0);
-	if (bdf == -1) {
-		/* PCIe device not found! */
-		printf("Failed to find PCIe device\n");
-	} else {
-		/* PCIe device found! */
-		printf("PCIe device found, resetting board...\n");
-
-		/* default handling: SOFT reset */
-		do_reset(NULL, 0, 0, NULL);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	pcie,   3,   0,     do_pcie_test,
-	"Test for presence of a PCIe device",
-	"<VendorID> <DeviceID>"
-);
-#endif
diff --git a/board/theadorable/theadorable.h b/board/theadorable/theadorable.h
deleted file mode 100644
index d3c959de984..00000000000
--- a/board/theadorable/theadorable.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Stefan Roese <sr@denx.de>
- */
-
-/* Base addresses for the SPI direct access mode */
-#define SPI_BUS0_DEV1_BASE	0xe0000000
-#define SPI_BUS0_DEV1_SIZE	(1 << 20)
-#define SPI_BUS1_DEV2_BASE	(SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE)
-
-void board_fpga_add(void);
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
deleted file mode 100644
index 9e99618998c..00000000000
--- a/configs/theadorable_debug_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_SYS_TEXT_BASE=0x00800000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_THEADORABLE=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=250000000
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEBUG_UART=y
-CONFIG_NR_DRAM_BANKS=2
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-# CONFIG_SPL_PARTITION_UUIDS is not set
-CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_SATA_MV=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_RAM=y
-CONFIG_FPGA_ALTERA=y
-CONFIG_DM_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_MVNETA=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO_MVEBU=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
deleted file mode 100644
index 2526a000840..00000000000
--- a/include/configs/theadorable.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- */
-
-#ifndef _CONFIG_THEADORABLE_H
-#define _CONFIG_THEADORABLE_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-/*
- * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
- * for DDR ECC byte filling in the SPL before loading the main
- * U-Boot into it.
- */
-#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
-
-/*
- * Commands configuration
- */
-
-/*
- * The debugging version enables USB support via defconfig.
- * This version should also enable all other non-production
- * interfaces / features.
- */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
-#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
-#define CONFIG_SYS_I2C_SLAVE		0x0
-#define CONFIG_SYS_I2C_SPEED		100000
-
-/* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-
-/* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
-
-/* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
-#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
-#define CONFIG_ENV_OVERWRITE
-
-#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
-
-#define CONFIG_PREBOOT
-
-/* Keep device tree and initrd in lower memory so the kernel can access them */
-#define CONFIG_EXTRA_ENV_SETTINGS	\
-	"fdt_high=0x10000000\0"		\
-	"initrd_high=0x10000000\0"
-
-/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_LBA48
-
-/* PCIe support */
-#ifdef CONFIG_CMD_PCI
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_PCI_MVEBU
-#endif
-#endif
-
-/* Enable LCD and reserve 512KB from top of memory*/
-#define CONFIG_SYS_MEM_TOP_HIDE		0x80000
-
-/* FPGA programming support */
-#define CONFIG_FPGA_STRATIX_V
-
-/*
- * Bootcounter
- */
-/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
-#define BOOTCOUNT_ADDR			0x1000
-
-/*
- * mv-common.h should be defined after CMD configs since it used them
- * to enable certain macros
- */
-#include "mv-common.h"
-
-/*
- * Memory layout while starting into the bin_hdr via the
- * BootROM:
- *
- * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
- * 0x4000.4030			bin_hdr start address
- * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
- * 0x4007.fffc			BootROM stack top
- *
- * The address space between 0x4007.fffc and 0x400f.fff is not locked in
- * L2 cache thus cannot be used.
- */
-
-/* SPL */
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x40004030
-#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
-
-/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
-#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
-
-/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */
-
-#endif /* _CONFIG_THEADORABLE_H */
-- 
2.19.1.1215.g8438c0b245-goog