[U-Boot] [PATCH 30/93] arm: Remove apalis_imx6_nospl_it board

From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 30/93] arm: Remove apalis_imx6_nospl_it board
Date: Mon, 19 Nov 2018 08:53:10 -0700	[thread overview]
Message-ID: <20181119155413.158098-31-sjg@chromium.org> (raw)
In-Reply-To: <20181119155413.158098-1-sjg@chromium.org>

This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/arm/mach-imx/mx6/Kconfig                 |    1 -
 .../toradex/apalis_imx6/1066mhz_4x128mx16.cfg |   47 -
 .../toradex/apalis_imx6/1066mhz_4x256mx16.cfg |   47 -
 board/toradex/apalis_imx6/Kconfig             |   55 -
 board/toradex/apalis_imx6/MAINTAINERS         |    9 -
 board/toradex/apalis_imx6/Makefile            |    5 -
 board/toradex/apalis_imx6/apalis_imx6.c       | 1236 -----------------
 board/toradex/apalis_imx6/apalis_imx6q.cfg    |   33 -
 board/toradex/apalis_imx6/clocks.cfg          |   41 -
 board/toradex/apalis_imx6/ddr-setup.cfg       |   96 --
 board/toradex/apalis_imx6/do_fuse.c           |   97 --
 board/toradex/apalis_imx6/pf0100.c            |  230 ---
 board/toradex/apalis_imx6/pf0100.h            |   52 -
 board/toradex/apalis_imx6/pf0100_otp.inc      |  190 ---
 configs/apalis_imx6_defconfig                 |   75 -
 configs/apalis_imx6_nospl_com_defconfig       |   63 -
 configs/apalis_imx6_nospl_it_defconfig        |   63 -
 include/configs/apalis_imx6.h                 |  277 ----
 18 files changed, 2617 deletions(-)
 delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
 delete mode 100644 board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
 delete mode 100644 board/toradex/apalis_imx6/Kconfig
 delete mode 100644 board/toradex/apalis_imx6/MAINTAINERS
 delete mode 100644 board/toradex/apalis_imx6/Makefile
 delete mode 100644 board/toradex/apalis_imx6/apalis_imx6.c
 delete mode 100644 board/toradex/apalis_imx6/apalis_imx6q.cfg
 delete mode 100644 board/toradex/apalis_imx6/clocks.cfg
 delete mode 100644 board/toradex/apalis_imx6/ddr-setup.cfg
 delete mode 100644 board/toradex/apalis_imx6/do_fuse.c
 delete mode 100644 board/toradex/apalis_imx6/pf0100.c
 delete mode 100644 board/toradex/apalis_imx6/pf0100.h
 delete mode 100644 board/toradex/apalis_imx6/pf0100_otp.inc
 delete mode 100644 configs/apalis_imx6_defconfig
 delete mode 100644 configs/apalis_imx6_nospl_com_defconfig
 delete mode 100644 configs/apalis_imx6_nospl_it_defconfig
 delete mode 100644 include/configs/apalis_imx6.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index de9bf156ce2..0cfb565dd70 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -556,7 +556,6 @@ source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tqc/tqma6/Kconfig"
-source "board/toradex/apalis_imx6/Kconfig"
 source "board/toradex/colibri-imx6ull/Kconfig"
 source "board/k+p/kp_imx6q_tpc/Kconfig"
 source "board/udoo/Kconfig"
diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
deleted file mode 100644
index 29d1c3126c5..00000000000
--- a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
-DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
deleted file mode 100644
index 02e90dd5e65..00000000000
--- a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016 Toradex AG
- */
-
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
-DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308
-
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46
-
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46
-
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
-
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig
deleted file mode 100644
index 14f8c10c64c..00000000000
--- a/board/toradex/apalis_imx6/Kconfig
+++ /dev/null
@@ -1,55 +0,0 @@
-if TARGET_APALIS_IMX6
-
-config SYS_BOARD
-	default "apalis_imx6"
-
-config SYS_CONFIG_NAME
-	default "apalis_imx6"
-
-config SYS_CPU
-	default "armv7"
-
-config SYS_SOC
-	default "mx6"
-
-config SYS_VENDOR
-	default "toradex"
-
-config TDX_CFG_BLOCK
-	default y
-
-config TDX_HAVE_MMC
-	default y
-
-config TDX_CFG_BLOCK_DEV
-	default "0"
-
-config TDX_CFG_BLOCK_PART
-	default "1"
-
-# Toradex config block in eMMC, at the end of 1st "boot sector"
-config TDX_CFG_BLOCK_OFFSET
-	default "-512"
-
-config TDX_CMD_IMX_MFGR
-	bool "Enable factory testing commands for Toradex iMX 6 modules"
-	help
-	  This adds the commands
-	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
-	  If executed on already fused modules it doesn't change any fuse setting.
-	default y
-
-config TDX_APALIS_IMX6_V1_0
-	bool "Apalis iMX6 V1.0 HW"
-	help
-	  Apalis iMX6 V1.0 HW has a different pinout for the UART.
-	    The UARTs must be used in DCE mode, RTS/CTS are swapped and
-	    thus unusable on standard carrier boards.
-	    This option configures DCE mode unconditionally. Whithout this
-	    option the config block stating V1.0 HW selects DCE mode,
-	    otherwise the UARTs are configuered in DTE mode.
-	default n
-
-source "board/toradex/common/Kconfig"
-
-endif
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
deleted file mode 100644
index 2c70ab4fbd9..00000000000
--- a/board/toradex/apalis_imx6/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-Apalis iMX6
-M:	Max Krummenacher <max.krummenacher@toradex.com>
-W:	http://developer.toradex.com/software/linux/linux-software
-S:	Maintained
-F:	board/toradex/apalis_imx6/
-F:	include/configs/apalis_imx6.h
-F:	configs/apalis_imx6_defconfig
-F:	configs/apalis_imx6_nospl_com_defconfig
-F:	configs/apalis_imx6_nospl_it_defconfig
diff --git a/board/toradex/apalis_imx6/Makefile b/board/toradex/apalis_imx6/Makefile
deleted file mode 100644
index 128f1794d16..00000000000
--- a/board/toradex/apalis_imx6/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2012-2014 Toradex, Inc.
-# SPDX-License-Identifier:      GPL-2.0+
-
-obj-y  := apalis_imx6.o do_fuse.o
-obj-$(CONFIG_TDX_CMD_IMX_MFGR)  += pf0100.o
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
deleted file mode 100644
index 368db9c488c..00000000000
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ /dev/null
@@ -1,1236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
- * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
- * Copyright (C) 2014-2016, Toradex AG
- * copied from nitrogen6x
- */
-
-#include <common.h>
-#include <dm.h>
-#include <environment.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/bootm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/mach-imx/sata.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/video.h>
-#include <dm/platform_data/serial_mxc.h>
-#include <dm/platdata.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <input.h>
-#include <imx_thermal.h>
-#include <linux/errno.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-#include "../common/tdx-cfg-block.h"
-#ifdef CONFIG_TDX_CMD_IMX_MFGR
-#include "pf0100.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_SRE_SLOW)
-
-#define NO_PULLUP	(					\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_SRE_SLOW)
-
-#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
-
-#define TRISTATE	(PAD_CTL_HYS | PAD_CTL_SPEED_MED)
-
-#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
-
-#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
-	/* use the DDR controllers configured size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    (ulong)imx_ddr_size());
-
-	return 0;
-}
-
-/* Apalis UART1 */
-iomux_v3_cfg_t const uart1_pads_dce[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-iomux_v3_cfg_t const uart1_pads_dte[] = {
-	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* Apalis I2C1 */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
-		.gp = IMX_GPIO_NR(5, 26)
-	}
-};
-
-/* Apalis local, PMIC, SGTL5000, STMPE811 */
-struct i2c_pads_info i2c_pad_info_loc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* Apalis I2C3 / CAM */
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
-		.gp = IMX_GPIO_NR(3, 17)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-/* Apalis I2C2 / DDC */
-struct i2c_pads_info i2c_pad_info_ddc = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
-		.gp = IMX_GPIO_NR(3, 16)
-	}
-};
-
-/* Apalis MMC1 */
-iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-#	define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
-};
-
-/* Apalis SD1 */
-iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-#	define GPIO_SD_CD IMX_GPIO_NR(6, 14)
-};
-
-/* eMMC */
-iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
-};
-
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	/* control data pad skew - devaddr = 0x02, register = 0x04 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
-	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
-	ksz9031_phy_extended_write(phydev, 0x02,
-				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
-	return 0;
-}
-
-iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/* KSZ9031 PHY Reset */
-	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
-#	define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
-};
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static int reset_enet_phy(struct mii_dev *bus)
-{
-	/* Reset KSZ9031 PHY */
-	gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
-	mdelay(10);
-	gpio_set_value(GPIO_ENET_PHY_RESET, 1);
-
-	return 0;
-}
-
-/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
-iomux_v3_cfg_t const gpio_pads[] = {
-	/* Apalis GPIO1 - GPIO8 */
-	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN),
-	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
-	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
-};
-
-static void setup_iomux_gpio(void)
-{
-	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
-}
-
-iomux_v3_cfg_t const usb_pads[] = {
-	/* USBH_EN */
-	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#	define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
-	/* USB_VBUS_DET */
-	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#	define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
-	/* USBO1_ID */
-	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
-	/* USBO1_EN */
-	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#	define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
-};
-
-/*
- * UARTs are used in DTE mode, switch the mode on all UARTs before
- * any pinmuxing connects a (DCE) output to a transceiver output.
- */
-#define UFCR		0x90	/* FIFO Control Register */
-#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
-
-static void setup_dtemode_uart(void)
-{
-	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
-	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
-	setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
-	setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
-}
-static void setup_dcemode_uart(void)
-{
-	clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
-	clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
-	clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
-	clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
-}
-
-static void setup_iomux_dte_uart(void)
-{
-	setup_dtemode_uart();
-	imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
-					 ARRAY_SIZE(uart1_pads_dte));
-}
-
-static void setup_iomux_dce_uart(void)
-{
-	setup_dcemode_uart();
-	imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
-					 ARRAY_SIZE(uart1_pads_dce));
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
-{
-	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
-	return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		/* control OTG power */
-		gpio_direction_output(GPIO_USBO_EN, on);
-		mdelay(100);
-		break;
-	case 1:
-		/* Control MXM USBH */
-		gpio_direction_output(GPIO_USBH_EN, on);
-		mdelay(2);
-		/* Control onboard USB Hub VBUS */
-		gpio_direction_output(GPIO_USB_VBUS_DET, on);
-		mdelay(100);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-/* use the following sequence: eMMC, MMC, SD */
-struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC1_BASE_ADDR},
-	{USDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = true; /* default: assume inserted */
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		gpio_direction_input(GPIO_MMC_CD);
-		ret = !gpio_get_value(GPIO_MMC_CD);
-		break;
-	case USDHC2_BASE_ADDR:
-		gpio_direction_input(GPIO_SD_CD);
-		ret = !gpio_get_value(GPIO_SD_CD);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
-	s32 status = 0;
-	u32 index = 0;
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
-	usdhc_cfg[0].max_bus_width = 8;
-	usdhc_cfg[1].max_bus_width = 8;
-	usdhc_cfg[2].max_bus_width = 4;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-		switch (index) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
-			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-			return status;
-		}
-
-		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-	}
-
-	return status;
-#else
-	struct src *psrc = (struct src *)SRC_BASE_ADDR;
-	unsigned reg = readl(&psrc->sbmr1) >> 11;
-	/*
-	 * Upon reading BOOT_CFG register the following map is done:
-	 * Bit 11 and 12 of BOOT_CFG register can determine the current
-	 * mmc port
-	 * 0x1                  SD1
-	 * 0x2                  SD2
-	 * 0x3                  SD4
-	 */
-
-	switch (reg & 0x3) {
-	case 0x0:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	case 0x1:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	case 0x2:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-		break;
-	default:
-		puts("MMC boot device not available");
-	}
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-#endif
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	uint32_t base = IMX_FEC_BASE;
-	struct mii_dev *bus = NULL;
-	struct phy_device *phydev = NULL;
-	int ret;
-
-	setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
-	bus = fec_get_miibus(base, -1);
-	if (!bus)
-		return 0;
-	bus->reset = reset_enet_phy;
-	/* scan PHY 4,5,6,7 */
-	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
-	if (!phydev) {
-		free(bus);
-		puts("no PHY found\n");
-		return 0;
-	}
-	printf("using PHY@%d\n", phydev->addr);
-	ret = fec_probe(bis, -1, base, bus, phydev);
-	if (ret) {
-		printf("FEC MXC: %s:failed\n", __func__);
-		free(phydev);
-		free(bus);
-	}
-#endif
-	return 0;
-}
-
-static iomux_v3_cfg_t const pwr_intb_pads[] = {
-	/*
-	 * the bootrom sets the iomux to vselect, potentially connecting
-	 * two outputs. Set this back to GPIO
-	 */
-	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static iomux_v3_cfg_t const backlight_pads[] = {
-	/* Backlight on RGB connector: J15 */
-	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
-	/* additional CPU pin on BKL_PWM, keep in tristate */
-	MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
-	/* Backlight PWM, used as GPIO in U-Boot */
-	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
-	/* buffer output enable 0: buffer enabled */
-	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
-#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
-	/* PSAVE# integrated VDAC */
-	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
-};
-
-static iomux_v3_cfg_t const rgb_pads[] = {
-	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
-	MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
-};
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
-	imx_enable_hdmi_phy();
-}
-
-static int detect_i2c(struct display_info_t const *dev)
-{
-	return (0 == i2c_set_bus_num(dev->bus)) &&
-	       (0 == i2c_probe(dev->addr));
-}
-
-static void enable_lvds(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)
-				IOMUXC_BASE_ADDR;
-	u32 reg = readl(&iomux->gpr[2]);
-	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
-	writel(reg, &iomux->gpr[2]);
-	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
-	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
-	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
-}
-
-static void enable_rgb(struct display_info_t const *dev)
-{
-	imx_iomux_v3_setup_multiple_pads(
-		rgb_pads,
-		ARRAY_SIZE(rgb_pads));
-	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
-	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
-	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
-}
-
-static int detect_default(struct display_info_t const *dev)
-{
-	(void) dev;
-	return 1;
-}
-
-struct display_info_t const displays[] = {{
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
-	.enable	= do_enable_hdmi,
-	.mode	= {
-		.name           = "HDMI",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= -1,
-	.addr	= 0,
-	.di	= 1,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_default,
-	.enable	= enable_rgb,
-	.mode	= {
-		.name           = "vga-rgb",
-		.refresh        = 60,
-		.xres           = 640,
-		.yres           = 480,
-		.pixclock       = 33000,
-		.left_margin    = 48,
-		.right_margin   = 16,
-		.upper_margin   = 31,
-		.lower_margin   = 11,
-		.hsync_len      = 96,
-		.vsync_len      = 2,
-		.sync           = 0,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= -1,
-	.addr	= 0,
-	.di	= 1,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.enable	= enable_rgb,
-	.mode	= {
-		.name           = "wvga-rgb",
-		.refresh        = 60,
-		.xres           = 800,
-		.yres           = 480,
-		.pixclock       = 25000,
-		.left_margin    = 40,
-		.right_margin   = 88,
-		.upper_margin   = 33,
-		.lower_margin   = 10,
-		.hsync_len      = 128,
-		.vsync_len      = 2,
-		.sync           = 0,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_LVDS666,
-	.detect	= detect_i2c,
-	.enable	= enable_lvds,
-	.mode	= {
-		.name           = "wsvga-lvds",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 600,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int reg;
-
-	enable_ipu_clock();
-	imx_setup_hdmi();
-	/* Turn on LDB0,IPU,IPU DI0 clocks */
-	reg = __raw_readl(&mxc_ccm->CCGR3);
-	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
-	writel(reg, &mxc_ccm->CCGR3);
-
-	/* set LDB0, LDB1 clk select to 011/011 */
-	reg = readl(&mxc_ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
-		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
-	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->cs2cdr);
-
-	reg = readl(&mxc_ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-	writel(reg, &mxc_ccm->cscmr2);
-
-	reg = readl(&mxc_ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
-	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
-	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
-	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
-	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
-	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
-	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
-	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
-	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
-			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
-	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
-	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-
-	/* backlight unconditionally on for now */
-	imx_iomux_v3_setup_multiple_pads(backlight_pads,
-					 ARRAY_SIZE(backlight_pads));
-	/* use 0 for EDT 7", use 1 for LG fullHD panel */
-	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
-	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
-	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
-}
-#endif /* defined(CONFIG_VIDEO_IPUV3) */
-
-int board_early_init_f(void)
-{
-	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
-					 ARRAY_SIZE(pwr_intb_pads));
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
-	setup_iomux_dte_uart();
-#else
-	setup_iomux_dce_uart();
-#endif
-	return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
-	return 1;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
-#endif
-
-#ifdef CONFIG_TDX_CMD_IMX_MFGR
-	(void) pmic_init();
-#endif
-
-#ifdef CONFIG_SATA
-	setup_sata();
-#endif
-
-	setup_iomux_gpio();
-
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#if defined(CONFIG_REVISION_TAG) && \
-    defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
-	char env_str[256];
-	u32 rev;
-
-	rev = get_board_rev();
-	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
-	env_set("board_rev", env_str);
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
-	if ((rev & 0xfff0) == 0x0100) {
-		char *fdt_env;
-
-		/* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
-		setup_iomux_dce_uart();
-
-		/* if using the default device tree, use version for V1.0 HW */
-		fdt_env = env_get("fdt_file");
-		if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
-			env_set("fdt_file", FDT_FILE_V1_0);
-			printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
-#ifndef CONFIG_ENV_IS_NOWHERE
-			env_save();
-#endif
-		}
-	}
-#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
-#endif /* CONFIG_REVISION_TAG */
-
-	return 0;
-}
-#endif /* CONFIG_BOARD_LATE_INIT */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
-int ft_system_setup(void *blob, bd_t *bd)
-{
-	return 0;
-}
-#endif
-
-int checkboard(void)
-{
-	char it[] = " IT";
-	int minc, maxc;
-
-	switch (get_cpu_temp_grade(&minc, &maxc)) {
-	case TEMP_AUTOMOTIVE:
-	case TEMP_INDUSTRIAL:
-		break;
-	case TEMP_EXTCOMMERCIAL:
-	default:
-		it[0] = 0;
-	};
-	printf("Model: Toradex Apalis iMX6 %s %s%s\n",
-	       is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
-	       (gd->ram_size == 0x80000000) ? "2GB" :
-	       (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
-	return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	return ft_common_board_setup(blob, bd);
-}
-#endif
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* 4-bit bus width */
-	{"mmc",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
-	{"sd",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
-	{NULL,	0},
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_LDO_BYPASS_CHECK
-/* TODO, use external pmic, for now always ldo_enable */
-void ldo_mode_set(int ldo_bypass)
-{
-	return;
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#include <spl.h>
-#include <linux/libfdt.h>
-#include "asm/arch/mx6q-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-static int mx6_com_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR	con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x128mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x555A7954,
-MX6_MMDC_P0_MDCFG1, 0xDB328F64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x005A1023,
-MX6_MMDC_P0_MDOTC, 0x09555050,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000027,
-MX6_MMDC_P0_MDCTL, 0x831A0000,
-MX6_MMDC_P0_MDSCR, 0x04088032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00428031,
-MX6_MMDC_P0_MDSCR, 0x19308030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00005800,
-MX6_MMDC_P0_MPODTCTRL, 0x00000000,
-MX6_MMDC_P1_MPODTCTRL, 0x00000000,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
-MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
-MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
-MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
-MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-static int mx6_it_dcd_table[] = {
-/* ddr-setup.cfg */
-MX6_IOM_DRAM_SDQS0, 0x00000030,
-MX6_IOM_DRAM_SDQS1, 0x00000030,
-MX6_IOM_DRAM_SDQS2, 0x00000030,
-MX6_IOM_DRAM_SDQS3, 0x00000030,
-MX6_IOM_DRAM_SDQS4, 0x00000030,
-MX6_IOM_DRAM_SDQS5, 0x00000030,
-MX6_IOM_DRAM_SDQS6, 0x00000030,
-MX6_IOM_DRAM_SDQS7, 0x00000030,
-
-MX6_IOM_GRP_B0DS, 0x00000030,
-MX6_IOM_GRP_B1DS, 0x00000030,
-MX6_IOM_GRP_B2DS, 0x00000030,
-MX6_IOM_GRP_B3DS, 0x00000030,
-MX6_IOM_GRP_B4DS, 0x00000030,
-MX6_IOM_GRP_B5DS, 0x00000030,
-MX6_IOM_GRP_B6DS, 0x00000030,
-MX6_IOM_GRP_B7DS, 0x00000030,
-MX6_IOM_GRP_ADDDS, 0x00000030,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_CTLDS, 0x00000030,
-
-MX6_IOM_DRAM_DQM0, 0x00020030,
-MX6_IOM_DRAM_DQM1, 0x00020030,
-MX6_IOM_DRAM_DQM2, 0x00020030,
-MX6_IOM_DRAM_DQM3, 0x00020030,
-MX6_IOM_DRAM_DQM4, 0x00020030,
-MX6_IOM_DRAM_DQM5, 0x00020030,
-MX6_IOM_DRAM_DQM6, 0x00020030,
-MX6_IOM_DRAM_DQM7, 0x00020030,
-
-MX6_IOM_DRAM_CAS, 0x00020030,
-MX6_IOM_DRAM_RAS, 0x00020030,
-MX6_IOM_DRAM_SDCLK_0, 0x00020030,
-MX6_IOM_DRAM_SDCLK_1, 0x00020030,
-
-MX6_IOM_DRAM_RESET, 0x00020030,
-MX6_IOM_DRAM_SDCKE0, 0x00003000,
-MX6_IOM_DRAM_SDCKE1, 0x00003000,
-
-MX6_IOM_DRAM_SDODT0, 0x00003030,
-MX6_IOM_DRAM_SDODT1, 0x00003030,
-
-/* (differential input) */
-MX6_IOM_DDRMODE_CTL, 0x00020000,
-/* (differential input) */
-MX6_IOM_GRP_DDRMODE, 0x00020000,
-/* disable ddr pullups */
-MX6_IOM_GRP_DDRPKE, 0x00000000,
-MX6_IOM_DRAM_SDBA2, 0x00000000,
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
-
-/* Read data DQ Byte0-3 delay */
-MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
-MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-MX6_MMDC_P0_MDMISC, 0x00081740,
-
-/*
- * MDSCR	con_req
- */
-MX6_MMDC_P0_MDSCR, 0x00008000,
-
-/* 1066mhz_4x256mx16.cfg */
-
-MX6_MMDC_P0_MDPDC, 0x00020036,
-MX6_MMDC_P0_MDCFG0, 0x898E78f5,
-MX6_MMDC_P0_MDCFG1, 0xff328f64,
-MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
-MX6_MMDC_P0_MDRWD, 0x000026D2,
-MX6_MMDC_P0_MDOR, 0x008E1023,
-MX6_MMDC_P0_MDOTC, 0x09444040,
-MX6_MMDC_P0_MDPDC, 0x00025576,
-MX6_MMDC_P0_MDASP, 0x00000047,
-MX6_MMDC_P0_MDCTL, 0x841A0000,
-MX6_MMDC_P0_MDSCR, 0x02888032,
-MX6_MMDC_P0_MDSCR, 0x00008033,
-MX6_MMDC_P0_MDSCR, 0x00048031,
-MX6_MMDC_P0_MDSCR, 0x19408030,
-MX6_MMDC_P0_MDSCR, 0x04008040,
-MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
-MX6_MMDC_P0_MDREF, 0x00007800,
-MX6_MMDC_P0_MPODTCTRL, 0x00022227,
-MX6_MMDC_P1_MPODTCTRL, 0x00022227,
-
-MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
-MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
-MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
-MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
-
-MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
-MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
-
-MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
-MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
-
-MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
-MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
-MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
-MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
-
-MX6_MMDC_P0_MPMUR0, 0x00000800,
-MX6_MMDC_P1_MPMUR0, 0x00000800,
-MX6_MMDC_P0_MDSCR, 0x00000000,
-MX6_MMDC_P0_MAPSR, 0x00011006,
-};
-
-
-static void ccgr_init(void)
-{
-	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	writel(0x00C03F3F, &ccm->CCGR0);
-	writel(0x0030FC03, &ccm->CCGR1);
-	writel(0x0FFFFFF3, &ccm->CCGR2);
-	writel(0x3FF0300F, &ccm->CCGR3);
-	writel(0x00FFF300, &ccm->CCGR4);
-	writel(0x0F0000F3, &ccm->CCGR5);
-	writel(0x000003FF, &ccm->CCGR6);
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-	writel(0x000000FB, &ccm->ccosr);
-}
-
-static void ddr_init(int *table, int size)
-{
-	int i;
-
-	for (i = 0; i < size / 2 ; i++)
-		writel(table[2 * i + 1], table[2 * i]);
-}
-
-static void spl_dram_init(void)
-{
-	int minc, maxc;
-
-	switch (get_cpu_temp_grade(&minc, &maxc)) {
-	case TEMP_COMMERCIAL:
-	case TEMP_EXTCOMMERCIAL:
-		puts("Commercial temperature grade DDR3 timings.\n");
-		ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
-		break;
-	case TEMP_INDUSTRIAL:
-	case TEMP_AUTOMOTIVE:
-	default:
-		puts("Industrial temperature grade DDR3 timings.\n");
-		ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
-		break;
-	};
-	udelay(100);
-}
-
-void board_init_f(ulong dummy)
-{
-	/* setup AIPS and disable watchdog */
-	arch_cpu_init();
-
-	ccgr_init();
-	gpr_init();
-
-	/* iomux and setup of i2c */
-	board_early_init_f();
-
-	/* setup GP timer */
-	timer_init();
-
-	/* UART clocks enabled and gd valid - init serial console */
-	preloader_console_init();
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
-	/* Make sure we use dte mode */
-	setup_dtemode_uart();
-#endif
-
-	/* DDR initialization */
-	spl_dram_init();
-
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	/* load/boot image from boot device */
-	board_init_r(NULL, 0);
-}
-
-void reset_cpu(ulong addr)
-{
-}
-
-#endif
-
-static struct mxc_serial_platdata mxc_serial_plat = {
-	.reg = (struct mxc_uart *)UART1_BASE,
-	.use_dte = true,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
-	.name = "serial_mxc",
-	.platdata = &mxc_serial_plat,
-};
diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg
deleted file mode 100644
index 739b1b70615..00000000000
--- a/board/toradex/apalis_imx6/apalis_imx6q.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-#include "ddr-setup.cfg"
-#if CONFIG_DDR_MB == 2048
-#include "1066mhz_4x256mx16.cfg"
-#else
-#include "1066mhz_4x128mx16.cfg"
-#endif
-#include "clocks.cfg"
diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg
deleted file mode 100644
index 1bcbc4fa380..00000000000
--- a/board/toradex/apalis_imx6/clocks.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg
deleted file mode 100644
index e42e3ce4387..00000000000
--- a/board/toradex/apalis_imx6/ddr-setup.cfg
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2014-2016, Toradex AG
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/*
- * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 32 bits	x16/x32
- */
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-/*
- * MDSCR	con_req
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c
deleted file mode 100644
index e6793e366a3..00000000000
--- a/board/toradex/apalis_imx6/do_fuse.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for i.MX OTP fusing during module production
-*/
-
-#include <common.h>
-#ifndef CONFIG_SPL_BUILD
-#include <console.h>
-#include <fuse.h>
-
-static int mfgr_fuse(void)
-{
-	unsigned val, val6;
-
-	fuse_sense(0, 5, &val);
-	printf("Fuse 0, 5: %8x\n", val);
-	fuse_sense(0, 6, &val6);
-	printf("Fuse 0, 6: %8x\n", val6);
-	fuse_sense(4, 3, &val);
-	printf("Fuse 4, 3: %8x\n", val);
-	fuse_sense(4, 2, &val);
-	printf("Fuse 4, 2: %8x\n", val);
-	if (val6 & 0x10) {
-		puts("BT_FUSE_SEL already fused, will do nothing\n");
-		return CMD_RET_FAILURE;
-	}
-	/* boot cfg */
-	fuse_prog(0, 5, 0x00005072);
-	/* BT_FUSE_SEL */
-	fuse_prog(0, 6, 0x00000010);
-	return CMD_RET_SUCCESS;
-}
-
-int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
-		char * const argv[])
-{
-	int ret;
-	puts("Fusing...\n");
-	ret = mfgr_fuse();
-	if (ret == CMD_RET_SUCCESS)
-		puts("done.\n");
-	else
-		puts("failed.\n");
-	return ret;
-}
-
-int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
-		char * const argv[])
-{
-	unsigned val;
-	int ret;
-	int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
-
-	/* can be used in scripts for command availability check */
-	if (argc >= 1 && !strcmp(argv[1], "-n"))
-		return CMD_RET_SUCCESS;
-
-	/* boot cfg */
-	fuse_sense(0, 5, &val);
-	printf("Fuse 0, 5: %8x\n", val);
-	if (val & 0x10) {
-		puts("Fast boot mode already fused, no need to fuse\n");
-		return CMD_RET_SUCCESS;
-	}
-	if (!confirmed) {
-		puts("Warning: Programming fuses is an irreversible operation!\n"
-				"         Updating to fast boot mode prevents easy\n"
-				"         downgrading to previous BSP versions.\n"
-				"\nReally perform this fuse programming? <y/N>\n");
-		if (!confirm_yesno())
-			return CMD_RET_FAILURE;
-	}
-	puts("Fusing fast boot mode...\n");
-	ret = fuse_prog(0, 5, 0x00005072);
-	if (ret == CMD_RET_SUCCESS)
-		puts("done.\n");
-	else
-		puts("failed.\n");
-	return ret;
-}
-
-U_BOOT_CMD(
-	mfgr_fuse, 1, 0, do_mfgr_fuse,
-	"OTP fusing during module production",
-	""
-);
-
-U_BOOT_CMD(
-	updt_fuse, 2, 0, do_updt_fuse,
-	"OTP fusing during module update",
-	"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
-);
-#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
deleted file mode 100644
index 7334e92f2ef..00000000000
--- a/board/toradex/apalis_imx6/pf0100.c
+++ /dev/null
@@ -1,230 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for Freescale PMIC PF0100
-*/
-
-#include <common.h>
-#include <i2c.h>
-#include <linux/compiler.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-
-#include "pf0100_otp.inc"
-#include "pf0100.h"
-
-/* define for PMIC register dump */
-/*#define DEBUG */
-
-/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
-static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
-	MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-#	define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
-};
-
-unsigned pmic_init(void)
-{
-	unsigned programmed = 0;
-	uchar bus = 1;
-	uchar devid, revid, val;
-
-	puts("PMIC: ");
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
-		return 0;
-	}
-	/* get device ident */
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
-		puts("i2c pmic devid read failed\n");
-		return 0;
-	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
-		puts("i2c pmic revid read failed\n");
-		return 0;
-	}
-	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
-
-#ifdef DEBUG
-	{
-		unsigned i, j;
-
-		for (i = 0; i < 16; i++)
-			printf("\t%x", i);
-		for (j = 0; j < 0x80; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 1");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE1;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\nEXT Page 2");
-
-		val = PFUZE100_PAGE_REGISTER_PAGE2;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return 0;
-		}
-
-		for (j = 0x80; j < 0x100; ) {
-			printf("\n%2x", j);
-			for (i = 0; i < 16; i++) {
-				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
-				printf("\t%2x", val);
-			}
-			j += 0x10;
-		}
-		printf("\n");
-	}
-#endif
-	/* get device programmed state */
-	val = PFUZE100_PAGE_REGISTER_PAGE1;
-	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
-		puts("i2c write failed\n");
-		return 0;
-	}
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
-		puts("i2c fuse_por read failed\n");
-		return 0;
-	}
-	if (val & PFUZE100_FUSE_POR_M)
-		programmed++;
-
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
-		puts("i2c fuse_por read failed\n");
-		return programmed;
-	}
-	if (val & PFUZE100_FUSE_POR_M)
-		programmed++;
-
-	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
-		puts("i2c fuse_por read failed\n");
-		return programmed;
-	}
-	if (val & PFUZE100_FUSE_POR_M)
-		programmed++;
-
-	switch (programmed) {
-	case 0:
-		printf("PMIC: not programmed\n");
-		break;
-	case 3:
-		printf("PMIC: programmed\n");
-		break;
-	default:
-		printf("PMIC: undefined programming state\n");
-		break;
-	}
-
-	/* The following is needed during production */
-	if (programmed != 3) {
-		/* set VGEN1 to 1.2V */
-		val = PFUZE100_VGEN1_VAL;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-			return programmed;
-		}
-
-		/* set SWBST to 5.0V */
-		val = PFUZE100_SWBST_VAL;
-		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1,
-			      &val, 1)) {
-			puts("i2c write failed\n");
-		}
-	}
-	return programmed;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static int pf0100_prog(void)
-{
-	unsigned char bus = 1;
-	unsigned char val;
-	unsigned int i;
-
-	if (pmic_init() == 3) {
-		puts("PMIC already programmed, exiting\n");
-		return CMD_RET_FAILURE;
-	}
-	/* set up gpio to manipulate vprog, initially off */
-	imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
-					 ARRAY_SIZE(pmic_prog_pads));
-	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
-
-	if (!((0 == i2c_set_bus_num(bus)) &&
-	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
-		puts("i2c bus failed\n");
-		return CMD_RET_FAILURE;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
-		switch (pmic_otp_prog[i].cmd) {
-		case pmic_i2c:
-			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
-			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
-				      1, &val, 1)) {
-				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
-				       pmic_otp_prog[i].reg, val);
-				return CMD_RET_FAILURE;
-			}
-			break;
-		case pmic_delay:
-			udelay(pmic_otp_prog[i].value * 1000);
-			break;
-		case pmic_vpgm:
-			gpio_direction_output(PMIC_PROG_VOLTAGE,
-					      pmic_otp_prog[i].value);
-			break;
-		case pmic_pwr:
-			/* TODO */
-			break;
-		}
-	}
-	return CMD_RET_SUCCESS;
-}
-
-static int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
-		char * const argv[])
-{
-	int ret;
-	puts("Programming PMIC OTP...");
-	ret = pf0100_prog();
-	if (ret == CMD_RET_SUCCESS)
-		puts("done.\n");
-	else
-		puts("failed.\n");
-	return ret;
-}
-
-U_BOOT_CMD(
-	pf0100_otp_prog, 1, 0, do_pf0100_prog,
-	"Program the OTP fuses on the PMIC PF0100",
-	""
-);
-#endif
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
deleted file mode 100644
index c0efb79bbc9..00000000000
--- a/board/toradex/apalis_imx6/pf0100.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-/*
- * Helpers for Freescale PMIC PF0100
-*/
-
-#ifndef PF0100_H_
-#define PF0100_H_
-
-/* 7-bit I2C bus slave address */
-#define PFUZE100_I2C_ADDR		(0x08)
-/* Register Addresses */
-#define PFUZE100_DEVICEID		(0x0)
-#define PFUZE100_REVID			(0x3)
-#define PFUZE100_SW1AMODE		(0x23)
-#define PFUZE100_SW1ACON		36
-#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
-#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
-#define PFUZE100_SW1CCON		49
-#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
-#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
-#define PFUZE100_SW1AVOL		32
-#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
-#define PFUZE100_SW1CVOL		46
-#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
-#define PFUZE100_VGEN1CTL		(0x6c)
-#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
-#define PFUZE100_SWBSTCTL		(0x66)
-/* Always ON, Auto Switching Mode, 5.0V */
-#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00)
-
-/* chooses the extended page (registers 0x80..0xff) */
-#define PFUZE100_PAGE_REGISTER		0x7f
-#define PFUZE100_PAGE_REGISTER_PAGE_M	(0x1f << 0)
-#define PFUZE100_PAGE_REGISTER_PAGE1	(0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
-#define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
-
-/* extended page 1 */
-#define PFUZE100_FUSE_POR1		0xe4
-#define PFUZE100_FUSE_POR2		0xe5
-#define PFUZE100_FUSE_POR3		0xe6
-#define PFUZE100_FUSE_POR_M		(0x1 << 1)
-
-
-/* output some informational messages, return the number FUSE_POR=1 */
-/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
-unsigned pmic_init(void);
-
-#endif /* PF0100_H_ */
diff --git a/board/toradex/apalis_imx6/pf0100_otp.inc b/board/toradex/apalis_imx6/pf0100_otp.inc
deleted file mode 100644
index a7790fd6c60..00000000000
--- a/board/toradex/apalis_imx6/pf0100_otp.inc
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2016, Toradex AG
- */
-
-// Register Output for PF0100 programmer
-// Customer: Toradex AG
-// Program: Apalis iMX6
-// Sample marking:
-// Date: 12.02.2014
-// Time: 17:16:41
-// Generated from Spreadsheet Revision: P1.8
-
-/* sed commands to get from programmer script to struct */
-/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
-   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
-   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
-
-enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
-struct pmic_otp_prog_t{
-	unsigned char cmd;
-	unsigned char reg;
-	unsigned short value;
-};
-
-struct pmic_otp_prog_t pmic_otp_prog[] = {
-{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
-{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
-{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
-{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
-{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
-{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
-{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
-{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
-{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
-{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
-{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
-{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
-{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
-{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
-{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
-{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
-{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
-{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
-{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
-{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
-{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
-{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
-{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
-{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
-{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
-{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
-{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
-{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
-{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
-{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
-{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
-{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
-
-#if 0 /* TBB mode */
-{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
-{pmic_delay, 0, 10},
-#else
-// Write OTP
-{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
-{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
-{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
-{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
-{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
-{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
-{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
-{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
-//VPGM:DOWN:n
-//VPGM:UP:n
-{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
-//-----------------------------------------------------------------------------------
-// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
-//-----------------------------------------------------------------------------------
-// BANK 1
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
-{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 2
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
-{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 3
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
-{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 4
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
-{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 5
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
-{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 6
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
-{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 7
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
-{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 8
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
-{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 9
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
-{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-// BANK 10
-//-----------------------------------------------------------------------------------
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
-{pmic_delay, 0, 10}, // Allow time for bank programming to complete
-{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
-{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
-//-----------------------------------------------------------------------------------
-{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
-{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
-{pmic_i2c, 0xD0, 0x00}, // Clear
-{pmic_i2c, 0xD1, 0x00}, // Clear
-{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
-{pmic_delay, 0, 500},
-{pmic_pwr, 0, 1},
-#endif
-};
\ No newline at end of file
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
deleted file mode 100644
index 133fc1a4dbd..00000000000
--- a/configs/apalis_imx6_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_DMA_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_USB_HOST_SUPPORT=y
-CONFIG_SPL_USB_GADGET_SUPPORT=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_SDP=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig
deleted file mode 100644
index 6e72422e0eb..00000000000
--- a/configs/apalis_imx6_nospl_com_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig
deleted file mode 100644
index bc04aabbbc7..00000000000
--- a/configs/apalis_imx6_nospl_it_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_APALIS_IMX6=y
-CONFIG_CMD_HDMIDETECT=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
-CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_MISC_INIT_R=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Apalis iMX6 # "
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CRC32_VERIFY=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_MII=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Toradex"
-CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x4020
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_VIDEO=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
deleted file mode 100644
index 135b3c9584d..00000000000
--- a/include/configs/apalis_imx6.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2015 Toradex, Inc.
- *
- * Configuration settings for the Toradex Apalis iMX6
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "mx6_common.h"
-
-#undef CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_MACH_TYPE		4886
-
-#include <asm/arch/imx-regs.h>
-#include <asm/mach-imx/gpio.h>
-
-#ifdef CONFIG_SPL
-#include "imx6_spl.h"
-#endif
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SERIAL_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE		UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED		100000
-
-/* OCOTP Configs */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
-/* MMC Configs */
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_USDHC_NUM	3
-
-#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
-
-/*
- * SATA Configs
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE	1
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/* Network */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RGMII
-#define CONFIG_ETHPRIME			"FEC"
-#define CONFIG_FEC_MXC_PHYADDR		6
-#define CONFIG_IP_DEFRAG
-#define CONFIG_TFTP_BLOCKSIZE		4096
-#define CONFIG_TFTP_TSIZE
-
-/* USB Configs */
-/* Host */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
-#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS		0
-/* Client */
-#define CONFIG_USBD_HS
-
-#define CONFIG_USB_GADGET_MASS_STORAGE
-/* USB DFU */
-#define CONFIG_DFU_MMC
-
-/* Miscellaneous commands */
-
-/* Framebuffer and LCD */
-#define CONFIG_VIDEO_IPUV3
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_IMX_HDMI
-#define CONFIG_IMX_VIDEO_SKIP
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition */
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FLASH
-
-#undef CONFIG_IPADDR
-#define CONFIG_IPADDR			192.168.10.2
-#define CONFIG_NETMASK			255.255.255.0
-#undef CONFIG_SERVERIP
-#define CONFIG_SERVERIP			192.168.10.1
-
-#define CONFIG_LOADADDR			0x12000000
-
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DRIVE_SATA "sata "
-#else
-#define CONFIG_DRIVE_SATA
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
-#else
-#define CONFIG_DRIVE_MMC
-#endif
-
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
-
-#define DFU_ALT_EMMC_INFO \
-	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
-	"boot part 0 1;" \
-	"rootfs part 0 2;" \
-	"uImage fat 0 1;" \
-	"imx6q-colibri-eval-v3.dtb fat 0 1;" \
-	"imx6q-colibri-cam-eval-v3.dtb fat 0 1"
-
-#define EMMC_BOOTCMD \
-	"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext3 " \
-		"rootwait\0" \
-	"emmcboot=run setup; " \
-		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
-		"${vidargs}; echo Booting from internal eMMC chip...; "	\
-		"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
-		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
-	"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
-		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define MEM_LAYOUT_ENV_SETTINGS \
-	"bootm_size=0x20000000\0" \
-	"fdt_addr_r=0x12000000\0" \
-	"fdt_high=0xffffffff\0" \
-	"initrd_high=0xffffffff\0" \
-	"kernel_addr_r=0x11000000\0" \
-	"ramdisk_addr_r=0x12100000\0"
-
-#define NFS_BOOTCMD \
-	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
-	"nfsboot=run setup; " \
-		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
-		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
-		"run nfsdtbload; dhcp ${kernel_addr_r} " \
-		"&& run fdt_fixup && bootm ${kernel_addr_r} ${dtbparam}\0" \
-	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
-		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define SD_BOOTCMD						\
-	"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext3 " \
-		"rootwait\0" \
-	"sdboot=run setup; " \
-		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
-		"${vidargs}; echo Booting from SD card; " \
-		"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
-		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
-	"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
-		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#define USB_BOOTCMD \
-	"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext3 " \
-		"rootwait\0" \
-	"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
-		"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
-		"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
-		"${boot_file} && run fdt_fixup && " \
-		"bootm ${kernel_addr_r} ${dtbparam}\0" \
-	"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
-		"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
-
-#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
-#define FDT_FILE "imx6q-apalis-eval.dtb"
-#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
-#else
-#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"bootcmd=run emmcboot ; echo ; echo emmcboot failed ; " \
-		"run nfsboot ; echo ; echo nfsboot failed ; " \
-		"usb start ;" \
-		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
-	"boot_file=uImage\0" \
-	"console=ttymxc0\0" \
-	"defargs=enable_wait_mode=off vmalloc=400M\0" \
-	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
-	EMMC_BOOTCMD \
-	"fdt_file=" FDT_FILE "\0" \
-	"fdt_fixup=;\0" \
-	MEM_LAYOUT_ENV_SETTINGS \
-	NFS_BOOTCMD \
-	SD_BOOTCMD \
-	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
-		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
-		"flash_eth.img && source ${loadaddr}\0" \
-	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
-		"${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
-		"source ${loadaddr}\0" \
-	"setup=setenv setupargs fec_mac=${ethaddr} " \
-		"consoleblank=0 no_console_suspend=1 console=tty1 " \
-		"console=${console},${baudrate}n8\0 " \
-	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
-	"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
-		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
-		"source ${loadaddr}\0" \
-	"splashpos=m,m\0" \
-	"vidargs=mxc_hdmi.only_cea=1 " \
-		"video=mxcfb0:dev=hdmi,1920x1080M at 60,if=RGB24 " \
-		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
-		"fbmem=32M\0 "
-
-/* Miscellaneous configurable options */
-#undef CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_CBSIZE		1024
-#undef CONFIG_SYS_MAXARGS
-#define CONFIG_SYS_MAXARGS		48
-
-#define CONFIG_SYS_MEMTEST_START	0x10000000
-#define CONFIG_SYS_MEMTEST_END		0x10010000
-#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
-
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-
-#define CONFIG_ENV_SIZE			(8 * 1024)
-
-#if defined(CONFIG_ENV_IS_IN_MMC)
-/* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
-					 CONFIG_TDX_CFG_BLOCK_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_SYS_MMC_ENV_PART		1
-#endif
-
-#define CONFIG_OF_SYSTEM_SETUP
-
-#define CONFIG_CMD_TIME
-
-#endif	/* __CONFIG_H */
-- 
2.19.1.1215.g8438c0b245-goog
