[U-Boot] [PATCH 06/93] arm: Remove ls1046ardb_sdcard_SECURE_BOOT board

[Simon Glass <sjg@chromium.org>]

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/arm/Kconfig                              |   1 -
 board/freescale/ls1046ardb/Kconfig            |  31 ---
 board/freescale/ls1046ardb/MAINTAINERS        |  20 --
 board/freescale/ls1046ardb/Makefile           |  10 -
 board/freescale/ls1046ardb/README             |  76 ------
 board/freescale/ls1046ardb/cpld.c             | 166 -------------
 board/freescale/ls1046ardb/cpld.h             |  49 ----
 board/freescale/ls1046ardb/ddr.c              | 119 ----------
 board/freescale/ls1046ardb/ddr.h              |  62 -----
 board/freescale/ls1046ardb/eth.c              | 127 ----------
 board/freescale/ls1046ardb/ls1046ardb.c       | 182 ---------------
 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg |  22 --
 .../ls1046ardb/ls1046ardb_qspi_pbi.cfg        |  26 ---
 .../ls1046ardb/ls1046ardb_rcw_emmc.cfg        |   7 -
 .../ls1046ardb/ls1046ardb_rcw_qspi.cfg        |   7 -
 .../ls1046ardb/ls1046ardb_rcw_sd.cfg          |   7 -
 configs/ls1046ardb_emmc_defconfig             |  63 -----
 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig |  49 ----
 configs/ls1046ardb_qspi_defconfig             |  49 ----
 configs/ls1046ardb_qspi_spl_defconfig         |  66 ------
 .../ls1046ardb_sdcard_SECURE_BOOT_defconfig   |  64 -----
 configs/ls1046ardb_sdcard_defconfig           |  62 -----
 include/configs/ls1046ardb.h                  | 220 ------------------
 23 files changed, 1485 deletions(-)
 delete mode 100644 board/freescale/ls1046ardb/Kconfig
 delete mode 100644 board/freescale/ls1046ardb/MAINTAINERS
 delete mode 100644 board/freescale/ls1046ardb/Makefile
 delete mode 100644 board/freescale/ls1046ardb/README
 delete mode 100644 board/freescale/ls1046ardb/cpld.c
 delete mode 100644 board/freescale/ls1046ardb/cpld.h
 delete mode 100644 board/freescale/ls1046ardb/ddr.c
 delete mode 100644 board/freescale/ls1046ardb/ddr.h
 delete mode 100644 board/freescale/ls1046ardb/eth.c
 delete mode 100644 board/freescale/ls1046ardb/ls1046ardb.c
 delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
 delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
 delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
 delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
 delete mode 100644 board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
 delete mode 100644 configs/ls1046ardb_emmc_defconfig
 delete mode 100644 configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
 delete mode 100644 configs/ls1046ardb_qspi_defconfig
 delete mode 100644 configs/ls1046ardb_qspi_spl_defconfig
 delete mode 100644 configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
 delete mode 100644 configs/ls1046ardb_sdcard_defconfig
 delete mode 100644 include/configs/ls1046ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 08d6db1cadf..54ec8243084 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1513,7 +1513,6 @@ source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1021aiot/Kconfig"
 source "board/freescale/ls1046aqds/Kconfig"
-source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
deleted file mode 100644
index 4c31e0e8857..00000000000
--- a/board/freescale/ls1046ardb/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-
-if TARGET_LS1046ARDB
-
-config SYS_BOARD
-	default "ls1046ardb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_SOC
-	default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
-	default "ls1046ardb"
-
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
-	hex "PPA Firmware Addr"
-	default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-	default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
-	hex "PPA Firmware HDR Addr"
-	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
-	default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
-source "board/freescale/common/Kconfig"
-endif
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
deleted file mode 100644
index aac649a9428..00000000000
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-LS1046A BOARD
-M:	Mingkai Hu <mingkai.hu@nxp.com>
-S:	Maintained
-F:	board/freescale/ls1046ardb/
-F:	board/freescale/ls1046ardb/ls1046ardb.c
-F:	include/configs/ls1046ardb.h
-F:	configs/ls1046ardb_qspi_defconfig
-F:	configs/ls1046ardb_qspi_spl_defconfig
-F:	configs/ls1046ardb_sdcard_defconfig
-F:	configs/ls1046ardb_emmc_defconfig
-
-LS1046A_SECURE_BOOT BOARD
-M:	Ruchika Gupta <ruchika.gupta@nxp.com>
-S:	Maintained
-F:	configs/ls1046ardb_SECURE_BOOT_defconfig
-F:	configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
-
-M:	Sumit Garg <sumit.garg@nxp.com>
-S:	Maintained
-F:	configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile
deleted file mode 100644
index 1c13ed6b6f0..00000000000
--- a/board/freescale/ls1046ardb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2016 Freescale Semiconductor
-
-obj-y += ddr.o
-obj-y += ls1046ardb.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_NET) += eth.o
-obj-y += cpld.o
-endif
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
deleted file mode 100644
index a38c9d48300..00000000000
--- a/board/freescale/ls1046ardb/README
+++ /dev/null
@@ -1,76 +0,0 @@
-Overview
---------
-The LS1046A Reference Design Board (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS1046A
-LayerScape Architecture processor. The LS1046ARDB provides SW development
-platform for the Freescale LS1046A processor series, with a complete
-debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
-
-LS1046A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
-SoC overview.
-
- LS1046ARDB board Overview
- -----------------------
- - SERDES1 Connections, 4 lanes supporting:
-      - Lane0: XFI with x1 RJ45 connector
-      - Lane1: XFI Cage
-      - Lane2: SGMII.5
-      - Lane3: SGMII.6
- - SERDES2 Connections, 4 lanes supporting:
-      - Lane0: PCIe1 with miniPCIe slot
-      - Lane1: PCIe2 with PCIe x2 slot
-      - Lane2: PCIe3 with PCIe x4 slot
-      - Lane3: SATA
- - DDR Controller
-     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
- -IFC/Local Bus
-    - One 512 MB NAND flash with ECC support
-    - CPLD connection
- - USB 3.0
-    - one Type A port, one Micro-AB port
- - SDHC: connects directly to a full SD/MMC slot
- - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 4 I2C controllers
- - UART
-   - Two 4-pin serial ports at up to 115.2 Kbit/s
-   - Two DB9 D-Type connectors supporting one Serial port each
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-Start Address	 End Address	 Description		Size
-0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
-0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
-0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0 		64KB
-0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1 		64KB
-0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
-0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
-0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
-0x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
-0x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
-0x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
-0x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
-0x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
-0x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
-0x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G
-
-QSPI flash map:
-Start Address    End Address     Description		Size
-0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
-0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
-0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
-0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
-0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
-				 + bootscript		3MB
-0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
-0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
-0x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
-0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
-
-Booting Options
----------------
-a) QSPI boot
-b) SD boot
-c) eMMC boot
diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c
deleted file mode 100644
index a65751986a1..00000000000
--- a/board/freescale/ls1046ardb/cpld.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor
- *
- * Freescale LS1046ARDB board-specific CPLD controlling supports.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
-	return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
-	void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
-	out_8(p + reg, value);
-}
-
-/* Set the boot bank to the alternate bank */
-void cpld_set_altbank(void)
-{
-	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
-	u8 reg4 = CPLD_READ(soft_mux_on);
-	u8 reg5 = (u8)(reg >> 1);
-	u8 reg6 = (u8)(reg & 1);
-	u8 reg7 = CPLD_READ(vbank);
-
-	cpld_rev_bit(&reg5);
-
-	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
-	CPLD_WRITE(cfg_rcw_src1, reg5);
-	CPLD_WRITE(cfg_rcw_src2, reg6);
-
-	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
-	CPLD_WRITE(vbank, reg7);
-
-	CPLD_WRITE(system_rst, 1);
-}
-
-/* Set the boot bank to the default bank */
-void cpld_set_defbank(void)
-{
-	u16 reg = CPLD_CFG_RCW_SRC_QSPI;
-	u8 reg4 = CPLD_READ(soft_mux_on);
-	u8 reg5 = (u8)(reg >> 1);
-	u8 reg6 = (u8)(reg & 1);
-
-	cpld_rev_bit(&reg5);
-
-	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
-	CPLD_WRITE(cfg_rcw_src1, reg5);
-	CPLD_WRITE(cfg_rcw_src2, reg6);
-
-	CPLD_WRITE(vbank, 0);
-
-	CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_set_sd(void)
-{
-	u16 reg = CPLD_CFG_RCW_SRC_SD;
-	u8 reg5 = (u8)(reg >> 1);
-	u8 reg6 = (u8)(reg & 1);
-
-	cpld_rev_bit(&reg5);
-
-	CPLD_WRITE(soft_mux_on, 1);
-
-	CPLD_WRITE(cfg_rcw_src1, reg5);
-	CPLD_WRITE(cfg_rcw_src2, reg6);
-
-	CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_select_core_volt(bool en_0v9)
-{
-	u8 reg17 = en_0v9;
-
-	CPLD_WRITE(vdd_en, 1);
-	CPLD_WRITE(vdd_sel, reg17);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
-	printf("cpld_ver	= %x\n", CPLD_READ(cpld_ver));
-	printf("cpld_ver_sub	= %x\n", CPLD_READ(cpld_ver_sub));
-	printf("pcba_ver	= %x\n", CPLD_READ(pcba_ver));
-	printf("soft_mux_on	= %x\n", CPLD_READ(soft_mux_on));
-	printf("cfg_rcw_src1	= %x\n", CPLD_READ(cfg_rcw_src1));
-	printf("cfg_rcw_src2	= %x\n", CPLD_READ(cfg_rcw_src2));
-	printf("vbank		= %x\n", CPLD_READ(vbank));
-	printf("sysclk_sel	= %x\n", CPLD_READ(sysclk_sel));
-	printf("uart_sel	= %x\n", CPLD_READ(uart_sel));
-	printf("sd1refclk_sel	= %x\n", CPLD_READ(sd1refclk_sel));
-	printf("rgmii_1588_sel	= %x\n", CPLD_READ(rgmii_1588_sel));
-	printf("1588_clk_sel	= %x\n", CPLD_READ(reg_1588_clk_sel));
-	printf("status_led	= %x\n", CPLD_READ(status_led));
-	printf("sd_emmc		= %x\n", CPLD_READ(sd_emmc));
-	printf("vdd_en		= %x\n", CPLD_READ(vdd_en));
-	printf("vdd_sel		= %x\n", CPLD_READ(vdd_sel));
-	putc('\n');
-}
-#endif
-
-void cpld_rev_bit(unsigned char *value)
-{
-	u8 rev_val, val;
-	int i;
-
-	val = *value;
-	rev_val = val & 1;
-	for (i = 1; i <= 7; i++) {
-		val >>= 1;
-		rev_val <<= 1;
-		rev_val |= val & 1;
-	}
-
-	*value = rev_val;
-}
-
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rc = 0;
-
-	if (argc <= 1)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[1], "reset") == 0) {
-		if (strcmp(argv[2], "altbank") == 0)
-			cpld_set_altbank();
-		else if (strcmp(argv[2], "sd") == 0)
-			cpld_set_sd();
-		else
-			cpld_set_defbank();
-#ifdef DEBUG
-	} else if (strcmp(argv[1], "dump") == 0) {
-		cpld_dump_regs();
-#endif
-	} else {
-		rc = cmd_usage(cmdtp);
-	}
-
-	return rc;
-}
-
-U_BOOT_CMD(
-	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
-	"Reset the board or alternate bank",
-	"reset: reset to default bank\n"
-	"cpld reset altbank: reset to alternate bank\n"
-	"cpld reset sd: reset to boot from SD card\n"
-#ifdef DEBUG
-	"cpld dump - display the CPLD registers\n"
-#endif
-);
diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h
deleted file mode 100644
index e87044f5c0d..00000000000
--- a/board/freescale/ls1046ardb/cpld.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor
- */
-
-#ifndef __CPLD_H__
-#define __CPLD_H__
-
-/*
- * CPLD register set of LS1046ARDB board-specific.
- * CPLD Revision:  V2.1
- */
-struct cpld_data {
-	u8 cpld_ver;		/* 0x0 - CPLD Major Revision Register */
-	u8 cpld_ver_sub;	/* 0x1 - CPLD Minor Revision Register */
-	u8 pcba_ver;		/* 0x2 - PCBA Revision Register */
-	u8 system_rst;		/* 0x3 - system reset register */
-	u8 soft_mux_on;		/* 0x4 - Switch Control Enable Register */
-	u8 cfg_rcw_src1;	/* 0x5 - RCW Source Location POR Regsiter 1 */
-	u8 cfg_rcw_src2;	/* 0x6 - RCW Source Location POR Regsiter 2 */
-	u8 vbank;		/* 0x7 - QSPI Flash Bank Setting Register */
-	u8 sysclk_sel;		/* 0x8 - System clock POR Register */
-	u8 uart_sel;		/* 0x9 - UART1 Connection Control Register */
-	u8 sd1refclk_sel;	/* 0xA - */
-	u8 rgmii_1588_sel;	/* 0xB - */
-	u8 reg_1588_clk_sel;	/* 0xC - */
-	u8 status_led;		/* 0xD - */
-	u8 global_rst;		/* 0xE - */
-	u8 sd_emmc;             /* 0xF - SD/EMMC Interface Control Regsiter */
-	u8 vdd_en;              /* 0x10 - VDD Voltage Control Enable Register */
-	u8 vdd_sel;             /* 0x11 - VDD Voltage Control Register */
-};
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-void cpld_rev_bit(unsigned char *value);
-void cpld_select_core_volt(bool en_0v9);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value)  \
-	cpld_write(offsetof(struct cpld_data, reg), value)
-
-/* CPLD on IFC */
-#define CPLD_SW_MUX_BANK_SEL	0x40
-#define CPLD_BANK_SEL_MASK	0x07
-#define CPLD_BANK_SEL_ALTBANK	0x04
-#define CPLD_CFG_RCW_SRC_QSPI	0x044
-#define CPLD_CFG_RCW_SRC_SD	0x040
-#endif
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
deleted file mode 100644
index 82b1b1d9eaa..00000000000
--- a/board/freescale/ls1046ardb/ddr.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-#ifdef CONFIG_FSL_DEEP_SLEEP
-#include <fsl_sleep.h>
-#endif
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-			   dimm_params_t *pdimm,
-			   unsigned int ctrl_num)
-{
-	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num > 1) {
-		printf("Not supported controller number %d\n", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	if (popts->registered_dimm_en)
-		pbsp = rdimms[0];
-	else
-		pbsp = udimms[0];
-
-	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found for %lu MT/s\n",
-		       ddr_freq);
-		printf("Trying to use the highest speed (%u) parameters\n",
-		       pbsp_highest->datarate_mhz_high);
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
-		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-found:
-	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
-	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
-
-	popts->data_bus_width = 0;	/* 64-bit data bus */
-	popts->bstopre = 0;		/* enable auto precharge */
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
-	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
-			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
-
-	/* optimize cpo for erratum A-009942 */
-	popts->cpo_sample = 0x61;
-}
-
-int fsl_initdram(void)
-{
-	phys_size_t dram_size;
-
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	gd->ram_size = fsl_ddr_sdram_size();
-
-	return 0;
-#else
-	puts("Initializing DDR....using SPD\n");
-
-	dram_size = fsl_ddr_sdram();
-#endif
-
-	erratum_a008850_post();
-
-	gd->ram_size = dram_size;
-
-	return 0;
-}
diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
deleted file mode 100644
index 3b4d44d4658..00000000000
--- a/board/freescale/ls1046ardb/ddr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-
-void erratum_a008850_post(void);
-
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
-	 */
-	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2300, 0, 8,     9, 0x0A0B0C10, 0x1213140E,},
-	{}
-};
-
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
-	 */
-	{2,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
-	{2,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
-	{2,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
-	{1,  1666, 0, 0x8,     0x0D, 0x0C0B0A08, 0x0A0B0C08,},
-	{1,  1900, 0, 0x8,     0x0E, 0x0D0C0B09, 0x0B0C0D09,},
-	{1,  2300, 0, 0xa,     0x12, 0x100F0D0C, 0x0E0F100C,},
-	{}
-};
-
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-};
-
-#endif
diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c
deleted file mode 100644
index 7dbfcac307b..00000000000
--- a/board/freescale/ls1046ardb/eth.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	int i;
-	struct memac_mdio_info dtsec_mdio_info;
-	struct memac_mdio_info tgec_mdio_info;
-	struct mii_dev *dev;
-	u32 srds_s1;
-	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	dtsec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
-	tgec_mdio_info.regs =
-		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
-	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
-	/* Register the 10G MDIO bus */
-	fm_memac_mdio_init(bis, &tgec_mdio_info);
-
-	/* Set the two on-board RGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
-	/* Set the two on-board SGMII PHY address */
-	fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
-	fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
-
-	/* Set the on-board AQ PHY address */
-	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-
-	switch (srds_s1) {
-	case 0x1133:
-		break;
-	default:
-		printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
-		       srds_s1);
-		break;
-	}
-
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
-		fm_info_set_mdio(i, dev);
-
-	/* XFI on lane A, MAC 9 */
-	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
-	fm_info_set_mdio(FM1_10GEC1, dev);
-
-	cpu_eth_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_FMAN_ENET
-int fdt_update_ethernet_dt(void *blob)
-{
-	u32 srds_s1;
-	int i, prop;
-	int offset, nodeoff;
-	const char *path;
-	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
-	srds_s1 = in_be32(&gur->rcwsr[4]) &
-			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
-	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
-	/* Cycle through all aliases */
-	for (prop = 0; ; prop++) {
-		const char *name;
-
-		/* FDT might have been edited, recompute the offset */
-		offset = fdt_first_property_offset(blob,
-						   fdt_path_offset(blob,
-								   "/aliases")
-						   );
-		/* Select property number 'prop' */
-		for (i = 0; i < prop; i++)
-			offset = fdt_next_property_offset(blob, offset);
-
-		if (offset < 0)
-			break;
-
-		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
-		nodeoff = fdt_path_offset(blob, path);
-
-		switch (srds_s1) {
-		case 0x1133:
-			if (!strcmp(name, "ethernet0"))
-				fdt_status_disabled(blob, nodeoff);
-
-			if (!strcmp(name, "ethernet1"))
-				fdt_status_disabled(blob, nodeoff);
-		break;
-		default:
-			printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
-			       __func__, srds_s1);
-		break;
-		}
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
deleted file mode 100644
index 0a73fe859d9..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ppa.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <hwconfig.h>
-#include <ahci.h>
-#include <mmc.h>
-#include <scsi.h>
-#include <fm_eth.h>
-#include <fsl_csu.h>
-#include <fsl_esdhc.h>
-#include <power/mc34vr500_pmic.h>
-#include "cpld.h"
-#include <fsl_sec.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	fsl_lsch2_early_init_f();
-
-	return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int checkboard(void)
-{
-	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
-	u8 cfg_rcw_src1, cfg_rcw_src2;
-	u16 cfg_rcw_src;
-	u8 sd1refclk_sel;
-
-	puts("Board: LS1046ARDB, boot from ");
-
-	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
-	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
-	cpld_rev_bit(&cfg_rcw_src1);
-	cfg_rcw_src = cfg_rcw_src1;
-	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
-
-	if (cfg_rcw_src == 0x44)
-		printf("QSPI vBank %d\n", CPLD_READ(vbank));
-	else if (cfg_rcw_src == 0x40)
-		puts("SD\n");
-	else
-		puts("Invalid setting of SW5\n");
-
-	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
-	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
-
-	puts("SERDES Reference Clocks:\n");
-	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
-	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-#ifdef CONFIG_SECURE_BOOT
-	/*
-	 * In case of Secure Boot, the IBR configures the SMMU
-	 * to allow only Secure transactions.
-	 * SMMU must be reset in bypass mode.
-	 * Set the ClientPD bit and Clear the USFCFG Bit
-	 */
-	u32 val;
-	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
-	out_le32(SMMU_SCR0, val);
-	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
-	out_le32(SMMU_NSCR0, val);
-#endif
-
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
-#ifdef CONFIG_FSL_LS_PPA
-	ppa_init();
-#endif
-
-	/* invert AQR105 IRQ pins polarity */
-	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
-
-	return 0;
-}
-
-int board_setup_core_volt(u32 vdd)
-{
-	bool en_0v9;
-
-	en_0v9 = (vdd == 900) ? true : false;
-	cpld_select_core_volt(en_0v9);
-
-	return 0;
-}
-
-int get_serdes_volt(void)
-{
-	return mc34vr500_get_sw_volt(SW4);
-}
-
-int set_serdes_volt(int svdd)
-{
-	return mc34vr500_set_sw_volt(SW4, svdd);
-}
-
-int power_init_board(void)
-{
-	int ret;
-
-	ret = power_mc34vr500_init(0);
-	if (ret)
-		return ret;
-
-	setup_chip_volt();
-
-	return 0;
-}
-
-void config_board_mux(void)
-{
-#ifdef CONFIG_HAS_FSL_XHCI_USB
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-	u32 usb_pwrfault;
-
-	/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
-	out_be32(&scfg->rcwpmuxcr0, 0x3300);
-	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
-	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
-			SCFG_USBPWRFAULT_USB3_SHIFT) |
-			(SCFG_USBPWRFAULT_DEDICATED <<
-			SCFG_USBPWRFAULT_USB2_SHIFT) |
-			(SCFG_USBPWRFAULT_SHARED <<
-			SCFG_USBPWRFAULT_USB1_SHIFT);
-	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
-#endif
-}
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-	config_board_mux();
-	return 0;
-}
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	u64 base[CONFIG_NR_DRAM_BANKS];
-	u64 size[CONFIG_NR_DRAM_BANKS];
-
-	/* fixup DT for the two DDR banks */
-	base[0] = gd->bd->bi_dram[0].start;
-	size[0] = gd->bd->bi_dram[0].size;
-	base[1] = gd->bd->bi_dram[1].start;
-	size[1] = gd->bd->bi_dram[1].size;
-
-	fdt_fixup_memory_banks(blob, base, size, 2);
-	ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-#endif
-
-	fdt_fixup_icid(blob);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
deleted file mode 100644
index 5478217524d..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-#Configure Scratch register
-09570600 00000000
-09570604 10000000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009e
-0957041c 0000009e
-09570420 0000009e
-#Serdes SATA
-09eb1300 80104e20
-09eb08dc 00502880
-#PEX gen3 link
-09570158 00000300
-89400890 01048000
-89500890 01048000
-89600890 01048000
-#Alt base register
-09570158 00001000
-#flush PBI data
-096100c0 000fffff
diff --git a/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg b/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
deleted file mode 100644
index 735d46c9f9b..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#QSPI clk
-0957015c 40100000
-#Configure Scratch register
-09570600 00000000
-09570604 10000000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009e
-0957041c 0000009e
-09570420 0000009e
-#Serdes SATA
-09eb1300 80104e20
-09eb08dc 00502880
-#PEX gen3 link
-09570158 00000300
-89400890 01048000
-89500890 01048000
-89600890 01048000
-#Alt base register
-09570158 00001000
-#flush PBI data
-096100c0 000fffff
-#Change endianness
-09550000 000f400c
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
deleted file mode 100644
index ccedf87e849..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c150012 0e000000 00000000 00000000
-11335559 40000012 60040000 c1000000
-00000000 00000000 00000000 00238800
-20124000 00003000 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
deleted file mode 100644
index 7b9be0ad3f8..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c150010 0e000000 00000000 00000000
-11335559 40005012 40025000 c1000000
-00000000 00000000 00000000 00238800
-20124000 00003101 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
deleted file mode 100644
index d3b152282f2..00000000000
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c150012 0e000000 00000000 00000000
-11335559 40005012 60040000 c1000000
-00000000 00000000 00000000 00238800
-20124000 00003101 00000096 00000001
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
deleted file mode 100644
index f7a35c7e194..00000000000
--- a/configs/ls1046ardb_emmc_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,EMMC_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
deleted file mode 100644
index 80f52807e12..00000000000
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
deleted file mode 100644
index e780acc446b..00000000000
--- a/configs/ls1046ardb_qspi_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
deleted file mode 100644
index f7cd33d8af5..00000000000
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
-CONFIG_QSPI_AHB_INIT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_QSPI_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_OS_BASE=0x40980000
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SPL_ENV_IS_NOWHERE=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_SPL_GZIP=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
deleted file mode 100644
index 24a08b6e013..00000000000
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
deleted file mode 100644
index 61da6ae517b..00000000000
--- a/configs/ls1046ardb_sdcard_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1046ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
deleted file mode 100644
index dcb58540461..00000000000
--- a/include/configs/ls1046ardb.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Freescale Semiconductor
- */
-
-#ifndef __LS1046ARDB_H__
-#define __LS1046ARDB_H__
-
-#include "ls1046a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ		100000000
-#define CONFIG_DDR_CLK_FREQ		100000000
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-/* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL	4
-
-#define CONFIG_DDR_SPD
-#define SPD_EEPROM_ADDRESS		0x51
-#define CONFIG_SYS_SPD_BUS_NUM		0
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
-#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
-#ifndef CONFIG_SPL
-#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
-#ifdef CONFIG_EMMC_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
-	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
-#endif
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FSL_PBL_RCW \
-	board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
-#define CONFIG_SYS_FSL_PBL_PBI \
-	board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
-#define CONFIG_SYS_UBOOT_BASE		0x40100000
-#define CONFIG_SYS_SPL_ARGS_ADDR	0x90000000
-#endif
-
-#ifndef SPL_NO_IFC
-/* IFC */
-#define CONFIG_FSL_IFC
-/*
- * NAND Flash Definitions
- */
-#define CONFIG_NAND_FSL_IFC
-#endif
-
-#define CONFIG_SYS_NAND_BASE		0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
-				| CSPR_PORT_SIZE_8	\
-				| CSPR_MSEL_NAND	\
-				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
-				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
-				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
-				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
-				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
-				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
-				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
-					FTIM0_NAND_TWP(0x18)   | \
-					FTIM0_NAND_TWCHT(0x7) | \
-					FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
-					FTIM1_NAND_TWBE(0x39)  | \
-					FTIM1_NAND_TRR(0xe)   | \
-					FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
-					FTIM2_NAND_TREH(0xa) | \
-					FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3		0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-
-/*
- * CPLD
- */
-#define CONFIG_SYS_CPLD_BASE		0x7fb00000
-#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE
-
-#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
-#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
-					CSPR_PORT_SIZE_8 | \
-					CSPR_MSEL_GPCM | \
-					CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)
-
-/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
-					FTIM0_GPCM_TEADC(0x0e) | \
-					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
-					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
-					FTIM2_GPCM_TCH(0xf) | \
-					FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CPLD_FTIM3		0x0
-
-/* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM		0
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
-#define I2C_RETIMER_ADDR			0x18
-
-/* PMIC */
-#define CONFIG_POWER
-#ifdef CONFIG_POWER
-#define CONFIG_POWER_I2C
-#endif
-
-/*
- * Environment
- */
-#ifndef SPL_NO_ENV
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#if defined(CONFIG_SD_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
-#define CONFIG_ENV_SIZE			0x2000
-#else
-#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
-#define CONFIG_ENV_OFFSET		0x300000	/* 3MB */
-#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
-#endif
-
-#define AQR105_IRQ_MASK			0x80000000
-/* FMan */
-#ifndef SPL_NO_FMAN
-
-#ifdef CONFIG_NET
-#define CONFIG_PHY_REALTEK
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define RGMII_PHY1_ADDR			0x1
-#define RGMII_PHY2_ADDR			0x2
-
-#define SGMII_PHY1_ADDR			0x3
-#define SGMII_PHY2_ADDR			0x4
-
-#define FM1_10GEC1_PHY_ADDR		0x0
-
-#define FDT_SEQ_MACADDR_FROM_ENV
-
-#define CONFIG_ETHPRIME			"FM1 at DTSEC3"
-#endif
-
-#endif
-
-/* QSPI device */
-#ifndef SPL_NO_QSPI
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE		(1 << 26)
-#define FSL_QSPI_FLASH_NUM		2
-#endif
-#endif
-
-#ifndef SPL_NO_MISC
-#undef CONFIG_BOOTCOMMAND
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
-			   "env exists secureboot && esbc_halt;;"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "	\
-			   "env exists secureboot && esbc_halt;"
-#endif
-#endif
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __LS1046ARDB_H__ */
-- 
2.19.1.1215.g8438c0b245-goog