From: "Ramuthevar,Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com> To: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, vigneshr@ti.com Cc: mark.rutland@arm.com, robh+dt@kernel.org, devicetree@vger.kernel.org, dan.carpenter@oracle.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Subject: [PATCH v9 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Date: Fri, 14 Feb 2020 19:46:17 +0800 [thread overview] Message-ID: <20200214114618.29704-2-vadivel.muruganx.ramuthevar@linux.intel.com> (raw) In-Reply-To: <20200214114618.29704-1-vadivel.muruganx.ramuthevar@linux.intel.com> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Add dt-bindings documentation for Cadence-QSPI controller to support spi based flash memories. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 147 +++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml new file mode 100644 index 000000000000..1a4d6e8d0d0b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence QSPI Flash Controller support + +maintainers: + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> + +allOf: + - $ref: "spi-controller.yaml#" + +description: | + Binding Documentation for Cadence QSPI controller,This controller is + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver + has been tested On Intel's LGM SoC. + + - compatible : should be one of the following: + Generic default - "cdns,qspi-nor". + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,k2g-qspi + - const: cdns,qspi-nor + + - items: + - enum: + - ti,am654-ospi + - const: cdns,qspi-nor + + - items: + - enum: + - intel,lgm-qspi + - const: cdns,qspi-nor + + - items: + - const: cdns,qspi-nor + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cdns,fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the data FIFO in words. + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bus width of the data FIFO in bytes. + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 32-bit indirect AHB trigger address. + + cdns,rclk-en: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Flag to indicate that QSPI return clock is used to latch the read data + rather than the QSPI clock. Make sure that QSPI return clock is populated + on the board before using this property. + +# subnode's properties +patternProperties: + "^.*@[0-9a-fA-F]+$": + type: object + description: + flash device uses the subnodes below defined properties. + + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay for read capture logic, in clock cycles. + + cdns,tshsl-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds for the length that the master mode chip select + outputs are de-asserted between transactions. + + cdns,tsd2d-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds between setting qspi_n_ss_out low and + first bit transfer. + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + +examples: + - | + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + + flash0: n25q00@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + }; + -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: "Ramuthevar,Vadivel MuruganX" <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> To: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, vigneshr-l0cyMroinI0@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org, cheol.yong.kim-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, qi-ming.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Subject: [PATCH v9 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Date: Fri, 14 Feb 2020 19:46:17 +0800 [thread overview] Message-ID: <20200214114618.29704-2-vadivel.muruganx.ramuthevar@linux.intel.com> (raw) In-Reply-To: <20200214114618.29704-1-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Add dt-bindings documentation for Cadence-QSPI controller to support spi based flash memories. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 147 +++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml new file mode 100644 index 000000000000..1a4d6e8d0d0b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence QSPI Flash Controller support + +maintainers: + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> + +allOf: + - $ref: "spi-controller.yaml#" + +description: | + Binding Documentation for Cadence QSPI controller,This controller is + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver + has been tested On Intel's LGM SoC. + + - compatible : should be one of the following: + Generic default - "cdns,qspi-nor". + For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,k2g-qspi + - const: cdns,qspi-nor + + - items: + - enum: + - ti,am654-ospi + - const: cdns,qspi-nor + + - items: + - enum: + - intel,lgm-qspi + - const: cdns,qspi-nor + + - items: + - const: cdns,qspi-nor + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cdns,fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the data FIFO in words. + + cdns,fifo-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bus width of the data FIFO in bytes. + + cdns,trigger-address: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + 32-bit indirect AHB trigger address. + + cdns,rclk-en: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Flag to indicate that QSPI return clock is used to latch the read data + rather than the QSPI clock. Make sure that QSPI return clock is populated + on the board before using this property. + +# subnode's properties +patternProperties: + "^.*@[0-9a-fA-F]+$": + type: object + description: + flash device uses the subnodes below defined properties. + + cdns,read-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay for read capture logic, in clock cycles. + + cdns,tshsl-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds for the length that the master mode chip select + outputs are de-asserted between transactions. + + cdns,tsd2d-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds between one chip select being de-activated + and the activation of another. + + cdns,tchsh-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds between last bit of current transaction and + deasserting the device chip select (qspi_n_ss_out). + + cdns,tslch-ns: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Delay in nanoseconds between setting qspi_n_ss_out low and + first bit transfer. + +required: + - compatible + - reg + - interrupts + - clocks + - cdns,fifo-depth + - cdns,fifo-width + - cdns,trigger-address + +examples: + - | + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + + flash0: n25q00@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + }; + -- 2.11.0
next prev parent reply other threads:[~2020-02-14 11:46 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-14 11:46 [PATCH v9 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX 2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX 2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX [this message] 2020-02-14 11:46 ` [PATCH v9 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX 2020-02-14 14:08 ` Mark Brown 2020-02-14 14:08 ` Mark Brown 2020-02-14 11:46 ` [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX 2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX 2020-02-14 13:09 ` Mark Brown 2020-02-14 13:09 ` Mark Brown 2020-02-17 9:18 ` Ramuthevar, Vadivel MuruganX 2020-02-17 9:18 ` Ramuthevar, Vadivel MuruganX 2020-02-17 17:09 ` Mark Brown 2020-02-17 17:09 ` Mark Brown 2020-02-18 3:17 ` Ramuthevar, Vadivel MuruganX 2020-02-18 3:17 ` Ramuthevar, Vadivel MuruganX 2020-02-14 12:02 ` [PATCH v9 0/2] " Simon Goldschmidt 2020-02-14 12:02 ` Simon Goldschmidt 2020-02-14 12:11 ` Mark Brown 2020-02-14 12:11 ` Mark Brown 2020-02-14 12:50 ` Simon Goldschmidt 2020-02-14 12:50 ` Simon Goldschmidt 2020-02-14 13:15 ` Mark Brown 2020-02-14 13:15 ` Mark Brown 2020-02-14 13:49 ` Simon Goldschmidt 2020-02-14 13:49 ` Simon Goldschmidt 2020-02-14 14:16 ` Mark Brown 2020-02-14 14:16 ` Mark Brown 2020-02-17 10:09 ` Ramuthevar, Vadivel MuruganX 2020-02-17 10:09 ` Ramuthevar, Vadivel MuruganX [not found] ` <4712cdc4-34cd-990b-3d53-3d394ae1250b@linux.intel.com> 2020-02-17 11:52 ` Mark Brown 2020-02-17 11:52 ` Mark Brown 2020-02-17 12:18 ` Vignesh Raghavendra 2020-02-17 12:18 ` Vignesh Raghavendra 2020-02-18 8:56 ` Ramuthevar, Vadivel MuruganX 2020-02-18 8:56 ` Ramuthevar, Vadivel MuruganX 2020-02-17 10:11 ` Ramuthevar, Vadivel MuruganX 2020-02-17 10:11 ` Ramuthevar, Vadivel MuruganX
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20200214114618.29704-2-vadivel.muruganx.ramuthevar@linux.intel.com \ --to=vadivel.muruganx.ramuthevar@linux.intel.com \ --cc=broonie@kernel.org \ --cc=cheol.yong.kim@intel.com \ --cc=dan.carpenter@oracle.com \ --cc=devicetree@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-spi@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=qi-ming.wu@intel.com \ --cc=robh+dt@kernel.org \ --cc=vigneshr@ti.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.