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From: Mark Brown <broonie@kernel.org>
To: "Ramuthevar,
	Vadivel MuruganX"  <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
	vigneshr@ti.com, mark.rutland@arm.com, robh+dt@kernel.org,
	devicetree@vger.kernel.org, dan.carpenter@oracle.com,
	cheol.yong.kim@intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Mon, 17 Feb 2020 17:09:01 +0000	[thread overview]
Message-ID: <20200217170901.GS9304@sirena.org.uk> (raw)
In-Reply-To: <3530edcd-eb67-8ea5-0fce-89c83400441c@linux.intel.com>

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On Mon, Feb 17, 2020 at 05:18:10PM +0800, Ramuthevar, Vadivel MuruganX wrote:
> On 14/2/2020 9:09 PM, Mark Brown wrote:

> > This will unconditionally handle the interrupt regardless of if the
> > hardware was actually flagging an interrupt which will break shared
> > interrupts and the fault handling code in genirq.

> Yes, you're correct, it doesn't check unconditionally, will update the
> INT flag in the INT_STATUS register after successful completion of
> read/write operation.
> but in this case it is dedicated to qspi-interrupt,not shared with any other
> HW/SW interrupts.

Currently, on the system you're looking at.  Given that this is already
a widely reused IP there's no guarantee that this will always be the
case, and like I say even without sharing it also defeats the fault
handling code.

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WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: "Ramuthevar,
	Vadivel MuruganX"
	<vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	vigneshr-l0cyMroinI0@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org,
	cheol.yong.kim-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
	qi-ming.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Mon, 17 Feb 2020 17:09:01 +0000	[thread overview]
Message-ID: <20200217170901.GS9304@sirena.org.uk> (raw)
In-Reply-To: <3530edcd-eb67-8ea5-0fce-89c83400441c-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>

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On Mon, Feb 17, 2020 at 05:18:10PM +0800, Ramuthevar, Vadivel MuruganX wrote:
> On 14/2/2020 9:09 PM, Mark Brown wrote:

> > This will unconditionally handle the interrupt regardless of if the
> > hardware was actually flagging an interrupt which will break shared
> > interrupts and the fault handling code in genirq.

> Yes, you're correct, it doesn't check unconditionally, will update the
> INT flag in the INT_STATUS register after successful completion of
> read/write operation.
> but in this case it is dedicated to qspi-interrupt,not shared with any other
> HW/SW interrupts.

Currently, on the system you're looking at.  Given that this is already
a widely reused IP there's no guarantee that this will always be the
case, and like I say even without sharing it also defeats the fault
handling code.

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  reply	other threads:[~2020-02-17 17:09 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 11:46 [PATCH v9 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` [PATCH v9 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
2020-02-14 11:46   ` Ramuthevar,Vadivel MuruganX
2020-02-14 14:08   ` Mark Brown
2020-02-14 14:08     ` Mark Brown
2020-02-14 11:46 ` [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-14 11:46   ` Ramuthevar,Vadivel MuruganX
2020-02-14 13:09   ` Mark Brown
2020-02-14 13:09     ` Mark Brown
2020-02-17  9:18     ` Ramuthevar, Vadivel MuruganX
2020-02-17  9:18       ` Ramuthevar, Vadivel MuruganX
2020-02-17 17:09       ` Mark Brown [this message]
2020-02-17 17:09         ` Mark Brown
2020-02-18  3:17         ` Ramuthevar, Vadivel MuruganX
2020-02-18  3:17           ` Ramuthevar, Vadivel MuruganX
2020-02-14 12:02 ` [PATCH v9 0/2] " Simon Goldschmidt
2020-02-14 12:02   ` Simon Goldschmidt
2020-02-14 12:11   ` Mark Brown
2020-02-14 12:11     ` Mark Brown
2020-02-14 12:50     ` Simon Goldschmidt
2020-02-14 12:50       ` Simon Goldschmidt
2020-02-14 13:15       ` Mark Brown
2020-02-14 13:15         ` Mark Brown
2020-02-14 13:49         ` Simon Goldschmidt
2020-02-14 13:49           ` Simon Goldschmidt
2020-02-14 14:16           ` Mark Brown
2020-02-14 14:16             ` Mark Brown
2020-02-17 10:09     ` Ramuthevar, Vadivel MuruganX
2020-02-17 10:09       ` Ramuthevar, Vadivel MuruganX
     [not found]     ` <4712cdc4-34cd-990b-3d53-3d394ae1250b@linux.intel.com>
2020-02-17 11:52       ` Mark Brown
2020-02-17 11:52         ` Mark Brown
2020-02-17 12:18         ` Vignesh Raghavendra
2020-02-17 12:18           ` Vignesh Raghavendra
2020-02-18  8:56           ` Ramuthevar, Vadivel MuruganX
2020-02-18  8:56             ` Ramuthevar, Vadivel MuruganX
2020-02-17 10:11   ` Ramuthevar, Vadivel MuruganX
2020-02-17 10:11     ` Ramuthevar, Vadivel MuruganX

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