From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: Mark Brown <broonie@kernel.org>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: linux-kernel <linux-kernel@vger.kernel.org>,
linux-spi@vger.kernel.org, Vignesh R <vigneshr@ti.com>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
dan.carpenter@oracle.com, cheol.yong.kim@intel.com,
qi-ming.wu@intel.com
Subject: Re: [PATCH v9 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Mon, 17 Feb 2020 18:09:08 +0800 [thread overview]
Message-ID: <7d264baf-1ea8-8ada-d93f-df55600a59e9@linux.intel.com> (raw)
In-Reply-To: <20200214121145.GF4827@sirena.org.uk>
Hi Mark,
On 14/2/2020 8:11 PM, Mark Brown wrote:
> On Fri, Feb 14, 2020 at 01:02:22PM +0100, Simon Goldschmidt wrote:
>> On Fri, Feb 14, 2020 at 12:46 PM Ramuthevar,Vadivel MuruganX
>> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>>> Add support for the Cadence QSPI controller. This controller is
>>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs.
>>> This driver has been tested on the Intel LGM SoCs.
>> This is v9 and still, none of the altera maintainers are on CC?
>> How will it be ensured that this doesn't break altera if it is merged?
> Given that this is a new driver I'd be very surprised if it broke other
> users? I can imagine it might not work for them and it would definitely
> be much better to get their review but it shouldn't be any worse than
> the current lack of support.
Thanks for the clarification, Please kindly see the below discussion b/w
Vignesh and Dinh in the earlier mail chain.
[Vignesh] The legacy driver under drivers/mtd/spi-nor will be removed
as we cannot
support both SPI NOR and SPI NAND with single driver if its under
spi-nor. New driver should be functionally equivalent to existing one.
So I suggest you test this driver on legcay SoCFPGA products.
[Dinh] I don't have the original patch series, but will monitor going
forward.
As long as the new driver does not break legacy SoCFPGA products that
use the cadence-quadspi driver then it should be ok.
Regards
vadivel
WARNING: multiple messages have this Message-ID (diff)
From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Simon Goldschmidt
<simon.k.r.goldschmidt-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: linux-kernel
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org,
cheol.yong.kim-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
qi-ming.wu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org
Subject: Re: [PATCH v9 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Mon, 17 Feb 2020 18:09:08 +0800 [thread overview]
Message-ID: <7d264baf-1ea8-8ada-d93f-df55600a59e9@linux.intel.com> (raw)
In-Reply-To: <20200214121145.GF4827-GFdadSzt00ze9xe1eoZjHA@public.gmane.org>
Hi Mark,
On 14/2/2020 8:11 PM, Mark Brown wrote:
> On Fri, Feb 14, 2020 at 01:02:22PM +0100, Simon Goldschmidt wrote:
>> On Fri, Feb 14, 2020 at 12:46 PM Ramuthevar,Vadivel MuruganX
>> <vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> wrote:
>>> Add support for the Cadence QSPI controller. This controller is
>>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs.
>>> This driver has been tested on the Intel LGM SoCs.
>> This is v9 and still, none of the altera maintainers are on CC?
>> How will it be ensured that this doesn't break altera if it is merged?
> Given that this is a new driver I'd be very surprised if it broke other
> users? I can imagine it might not work for them and it would definitely
> be much better to get their review but it shouldn't be any worse than
> the current lack of support.
Thanks for the clarification, Please kindly see the below discussion b/w
Vignesh and Dinh in the earlier mail chain.
[Vignesh] The legacy driver under drivers/mtd/spi-nor will be removed
as we cannot
support both SPI NOR and SPI NAND with single driver if its under
spi-nor. New driver should be functionally equivalent to existing one.
So I suggest you test this driver on legcay SoCFPGA products.
[Dinh] I don't have the original patch series, but will monitor going
forward.
As long as the new driver does not break legacy SoCFPGA products that
use the cadence-quadspi driver then it should be ok.
Regards
vadivel
next prev parent reply other threads:[~2020-02-17 10:09 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 11:46 [PATCH v9 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` [PATCH v9 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX
2020-02-14 14:08 ` Mark Brown
2020-02-14 14:08 ` Mark Brown
2020-02-14 11:46 ` [PATCH v9 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-02-14 11:46 ` Ramuthevar,Vadivel MuruganX
2020-02-14 13:09 ` Mark Brown
2020-02-14 13:09 ` Mark Brown
2020-02-17 9:18 ` Ramuthevar, Vadivel MuruganX
2020-02-17 9:18 ` Ramuthevar, Vadivel MuruganX
2020-02-17 17:09 ` Mark Brown
2020-02-17 17:09 ` Mark Brown
2020-02-18 3:17 ` Ramuthevar, Vadivel MuruganX
2020-02-18 3:17 ` Ramuthevar, Vadivel MuruganX
2020-02-14 12:02 ` [PATCH v9 0/2] " Simon Goldschmidt
2020-02-14 12:02 ` Simon Goldschmidt
2020-02-14 12:11 ` Mark Brown
2020-02-14 12:11 ` Mark Brown
2020-02-14 12:50 ` Simon Goldschmidt
2020-02-14 12:50 ` Simon Goldschmidt
2020-02-14 13:15 ` Mark Brown
2020-02-14 13:15 ` Mark Brown
2020-02-14 13:49 ` Simon Goldschmidt
2020-02-14 13:49 ` Simon Goldschmidt
2020-02-14 14:16 ` Mark Brown
2020-02-14 14:16 ` Mark Brown
2020-02-17 10:09 ` Ramuthevar, Vadivel MuruganX [this message]
2020-02-17 10:09 ` Ramuthevar, Vadivel MuruganX
[not found] ` <4712cdc4-34cd-990b-3d53-3d394ae1250b@linux.intel.com>
2020-02-17 11:52 ` Mark Brown
2020-02-17 11:52 ` Mark Brown
2020-02-17 12:18 ` Vignesh Raghavendra
2020-02-17 12:18 ` Vignesh Raghavendra
2020-02-18 8:56 ` Ramuthevar, Vadivel MuruganX
2020-02-18 8:56 ` Ramuthevar, Vadivel MuruganX
2020-02-17 10:11 ` Ramuthevar, Vadivel MuruganX
2020-02-17 10:11 ` Ramuthevar, Vadivel MuruganX
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