[PATCH v4 00/12] phy: atheros: dt bindings and cleanup

[PATCH v4 00/12] phy: atheros: dt bindings and cleanup

[Michael Walle]

This patch series superseeds the following two:
From Vladimir Oltean
  https://patchwork.ozlabs.org/cover/1031360/
From me:
  https://patchwork.ozlabs.org/cover/1184507/

Although the first is marked as accepted into u-boot-net I guess it was
removed due to broken boards ("DT as ABI", RGMII delay was fixed and thus
breaks the board).

After disussing with Vladimir, I've integrated his patches with this
series. Also the first one
  Address packet drops at low traffic rate due to SmartEEE feature
was dropped because it will likely be fixed by making u-boot support the
eee-broken-X device tree properties. Apart from that, only the subject was
changed and a note about possible board breakage was added the patch which
changes the delay behaviour.

For all of those, who will test this patchset, the device tree binding
needs the phydev->node property, which needs to be set in every network
driver. If the device tree binding is not working for you have a look at
the
  ar803x_of_init: found PHY node: phy at 0
output. In the case above "phy at 0" is the phy node in the device tree. If
instead the node of your network device is displayed, you have to set
the phydev->node property in your network device driver.

For the fsl_enetc driver this patchset will add it:
  https://patchwork.ozlabs.org/cover/1188043/

changes since v3:
 - add acked-by's, thanks Joe!

changes since v2:
 - rebased onto latest master, esp. #include <dm/device_compat.h>

changes since v1:
 - pull all Vladimirs Oltan's patches and rebase mine onto them
 - fix the CLK_25M settings for the AR8035
 - add two new patches "fix AR8021 PHY ID mask" and "use defines for PHY
   IDs"
 - use the new kernel device tree binding for the AR803x PHYs:
   https://patchwork.ozlabs.org/patch/1188293/
 - add debugging output

Michael Walle (7):
  phy: atheros: fix AR8021 PHY ID mask
  phy: atheros: use defines for PHY IDs
  phy: atheros: introduce debug read and write functions
  phy: atheros: move delay config to common function
  phy: atheros: add device tree bindings and config
  phy: atheros: ar8035: remove static clock config
  phy: atheros: consolidate {ar8031|ar8035}_config()

Vladimir Oltean (5):
  phy: atheros: Make RGMII Tx delays actually configurable for AR8035
  phy: atheros: Use common functions for RGMII internal delays
  phy: atheros: Clarify the configuration of the CLK_25M output pin
  phy: atheros: Explicitly disable RGMII delays
  phy: atheros: Clarify the intention of ar8021_config

 doc/device-tree-bindings/net/phy/atheros.txt |  35 ++
 drivers/net/phy/atheros.c                    | 350 ++++++++++++++++---
 include/dt-bindings/net/qca-ar803x.h         |  13 +
 3 files changed, 345 insertions(+), 53 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt
 create mode 100644 include/dt-bindings/net/qca-ar803x.h

-- 
2.20.1

[PATCH v4 01/12] phy: atheros: Make RGMII Tx delays actually configurable for AR8035

[Michael Walle]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Delete the extraneous write to debug reg 5 that enables Tx delay

When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.

Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
and RGMII_RXID", the author did not notice that code for enabling Tx
delay code was already. Therefore, the if condition for Tx delay has
always been useless for this PHY since this commit introduced it.

Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled.
After this patch, only those who define the interface as RGMII_TXID or
RGMII_ID will. This is to be expected, but will nonetheless break the
setups of those who didn't know they rely on Tx delay implicitly.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3783d155e7..537c1a9125 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -63,10 +63,6 @@ static int ar8035_config(struct phy_device *phydev)
 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
 
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
-
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 		/* select debug reg 5 */
-- 
2.20.1

[PATCH v4 02/12] phy: atheros: Use common functions for RGMII internal delays

[Michael Walle]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 69 +++++++++++++++++++++++----------------
 1 file changed, 41 insertions(+), 28 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 537c1a9125..c0c2b4db39 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -12,16 +12,45 @@
 #define AR803x_PHY_DEBUG_DATA_REG	0x1e
 
 #define AR803x_DEBUG_REG_5		0x5
-#define AR803x_RGMII_TX_CLK_DLY		0x100
+#define AR803x_RGMII_TX_CLK_DLY		BIT(8)
 
 #define AR803x_DEBUG_REG_0		0x0
-#define AR803x_RGMII_RX_CLK_DLY		0x8000
+#define AR803x_RGMII_RX_CLK_DLY		BIT(15)
+
+static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+{
+	int regval;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+		  AR803x_DEBUG_REG_0);
+	regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+	if (on)
+		regval |= AR803x_RGMII_RX_CLK_DLY;
+	else
+		regval &= ~AR803x_RGMII_RX_CLK_DLY;
+	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+}
+
+static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
+{
+	int regval;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+		  AR803x_DEBUG_REG_5);
+	regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+	if (on)
+		regval |= AR803x_RGMII_TX_CLK_DLY;
+	else
+		regval &= ~AR803x_RGMII_TX_CLK_DLY;
+	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+}
 
 static int ar8021_config(struct phy_device *phydev)
 {
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
+	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+		  AR803x_DEBUG_REG_5);
+	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
 
 	phydev->supported = phydev->drv->features;
 	return 0;
@@ -30,20 +59,12 @@ static int ar8021_config(struct phy_device *phydev)
 static int ar8031_config(struct phy_device *phydev)
 {
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
-		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-			  AR803x_DEBUG_REG_5);
-		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
-			  AR803x_RGMII_TX_CLK_DLY);
-	}
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		ar803x_enable_tx_delay(phydev, true);
 
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
-		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-			  AR803x_DEBUG_REG_0);
-		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
-			  AR803x_RGMII_RX_CLK_DLY);
-	}
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+		ar803x_enable_rx_delay(phydev, true);
 
 	phydev->supported = phydev->drv->features;
 
@@ -64,20 +85,12 @@ static int ar8035_config(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
-		/* select debug reg 5 */
-		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
-		/* enable tx delay */
-		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
-	}
+	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
+		ar803x_enable_tx_delay(phydev, true);
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
-		/* select debug reg 0 */
-		phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
-		/* enable rx delay */
-		phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
-	}
+	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
+		ar803x_enable_rx_delay(phydev, true);
 
 	phydev->supported = phydev->drv->features;
 
-- 
2.20.1

[PATCH v4 03/12] phy: atheros: Clarify the configuration of the CLK_25M output pin

[Michael Walle]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index c0c2b4db39..1da18eb5d4 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -17,6 +17,15 @@
 #define AR803x_DEBUG_REG_0		0x0
 #define AR803x_RGMII_RX_CLK_DLY		BIT(15)
 
+/* CLK_25M register is at MMD 7, address 0x8016 */
+#define AR803x_CLK_25M_SEL_REG		0x8016
+/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
+#define AR8035_CLK_25M_FREQ_25M		(0 | 0)
+#define AR8035_CLK_25M_FREQ_50M		(0 | BIT(3))
+#define AR8035_CLK_25M_FREQ_62M		(BIT(4) | 0)
+#define AR8035_CLK_25M_FREQ_125M	(BIT(4) | BIT(3))
+#define AR8035_CLK_25M_MASK		GENMASK(4, 3)
+
 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
 {
 	int regval;
@@ -78,11 +87,11 @@ static int ar8035_config(struct phy_device *phydev)
 {
 	int regval;
 
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
+	/* Configure CLK_25M output clock at 125 MHz */
+	regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
+	regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
+	regval |= AR8035_CLK_25M_FREQ_125M;
+	phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
-- 
2.20.1

[PATCH v4 04/12] phy: atheros: Explicitly disable RGMII delays

[Michael Walle]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.

If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 1da18eb5d4..3e59c3f391 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -70,10 +70,14 @@ static int ar8031_config(struct phy_device *phydev)
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 		ar803x_enable_tx_delay(phydev, true);
+	else
+		ar803x_enable_tx_delay(phydev, false);
 
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 		ar803x_enable_rx_delay(phydev, true);
+	else
+		ar803x_enable_rx_delay(phydev, false);
 
 	phydev->supported = phydev->drv->features;
 
@@ -96,10 +100,14 @@ static int ar8035_config(struct phy_device *phydev)
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 		ar803x_enable_tx_delay(phydev, true);
+	else
+		ar803x_enable_tx_delay(phydev, false);
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 		ar803x_enable_rx_delay(phydev, true);
+	else
+		ar803x_enable_rx_delay(phydev, false);
 
 	phydev->supported = phydev->drv->features;
 
-- 
2.20.1

[PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config

[Michael Walle]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3e59c3f391..3cc162828c 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -56,10 +56,10 @@ static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
 
 static int ar8021_config(struct phy_device *phydev)
 {
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-		  AR803x_DEBUG_REG_5);
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
+		  BMCR_ANENABLE | BMCR_ANRESTART);
+
+	ar803x_enable_tx_delay(phydev, true);
 
 	phydev->supported = phydev->drv->features;
 	return 0;
-- 
2.20.1

[PATCH v4 06/12] phy: atheros: fix AR8021 PHY ID mask

[Michael Walle]

The upper bits are all the OUI.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3cc162828c..01953a1390 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -120,7 +120,7 @@ static int ar8035_config(struct phy_device *phydev)
 static struct phy_driver AR8021_driver =  {
 	.name = "AR8021",
 	.uid = 0x4dd040,
-	.mask = 0x4ffff0,
+	.mask = 0xfffffff0,
 	.features = PHY_GBIT_FEATURES,
 	.config = ar8021_config,
 	.startup = genphy_startup,
-- 
2.20.1

[PATCH v4 07/12] phy: atheros: use defines for PHY IDs

[Michael Walle]

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 01953a1390..5ff5875d3d 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -26,6 +26,10 @@
 #define AR8035_CLK_25M_FREQ_125M	(BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASK		GENMASK(4, 3)
 
+#define AR8021_PHY_ID 0x004dd040
+#define AR8031_PHY_ID 0x004dd074
+#define AR8035_PHY_ID 0x004dd072
+
 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
 {
 	int regval;
@@ -119,7 +123,7 @@ static int ar8035_config(struct phy_device *phydev)
 
 static struct phy_driver AR8021_driver =  {
 	.name = "AR8021",
-	.uid = 0x4dd040,
+	.uid = AR8021_PHY_ID,
 	.mask = 0xfffffff0,
 	.features = PHY_GBIT_FEATURES,
 	.config = ar8021_config,
@@ -129,7 +133,7 @@ static struct phy_driver AR8021_driver =  {
 
 static struct phy_driver AR8031_driver =  {
 	.name = "AR8031/AR8033",
-	.uid = 0x4dd074,
+	.uid = AR8031_PHY_ID,
 	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
 	.config = ar8031_config,
@@ -139,7 +143,7 @@ static struct phy_driver AR8031_driver =  {
 
 static struct phy_driver AR8035_driver =  {
 	.name = "AR8035",
-	.uid = 0x4dd072,
+	.uid = AR8035_PHY_ID,
 	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
 	.config = ar8035_config,
-- 
2.20.1

[PATCH v4 08/12] phy: atheros: introduce debug read and write functions

[Michael Walle]

Provide functions to read and write the Atheros debug registers.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 57 ++++++++++++++++++++++++++++-----------
 1 file changed, 41 insertions(+), 16 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 5ff5875d3d..660dcd9491 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -30,32 +30,57 @@
 #define AR8031_PHY_ID 0x004dd074
 #define AR8035_PHY_ID 0x004dd072
 
-static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 {
-	int regval;
+	int ret;
+
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+			reg);
+	if (ret < 0)
+		return ret;
+
+	return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
+}
+
+static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+				 u16 clear, u16 set)
+{
+	int val;
+
+	val = ar803x_debug_reg_read(phydev, reg);
+	if (val < 0)
+		return val;
+
+	val &= 0xffff;
+	val &= ~clear;
+	val |= set;
+
+	return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+			 val);
+}
+
+static int ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
+{
+	u16 clear = 0, set = 0;
 
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-		  AR803x_DEBUG_REG_0);
-	regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
 	if (on)
-		regval |= AR803x_RGMII_RX_CLK_DLY;
+		set = AR803x_RGMII_RX_CLK_DLY;
 	else
-		regval &= ~AR803x_RGMII_RX_CLK_DLY;
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+		clear = AR803x_RGMII_RX_CLK_DLY;
+
+	return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, clear, set);
 }
 
-static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
+static int ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
 {
-	int regval;
+	u16 clear = 0, set = 0;
 
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
-		  AR803x_DEBUG_REG_5);
-	regval = phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG);
 	if (on)
-		regval |= AR803x_RGMII_TX_CLK_DLY;
+		set = AR803x_RGMII_TX_CLK_DLY;
 	else
-		regval &= ~AR803x_RGMII_TX_CLK_DLY;
-	phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, regval);
+		clear = AR803x_RGMII_TX_CLK_DLY;
+
+	return ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, clear, set);
 }
 
 static int ar8021_config(struct phy_device *phydev)
-- 
2.20.1

[PATCH v4 09/12] phy: atheros: move delay config to common function

[Michael Walle]

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 38 ++++++++++++++++++++++----------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 660dcd9491..22035c2496 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -94,19 +94,32 @@ static int ar8021_config(struct phy_device *phydev)
 	return 0;
 }
 
-static int ar8031_config(struct phy_device *phydev)
+static int ar803x_delay_config(struct phy_device *phydev)
 {
+	int ret;
+
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
-		ar803x_enable_tx_delay(phydev, true);
+		ret = ar803x_enable_tx_delay(phydev, true);
 	else
-		ar803x_enable_tx_delay(phydev, false);
+		ret = ar803x_enable_tx_delay(phydev, false);
 
 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
-		ar803x_enable_rx_delay(phydev, true);
+		ret = ar803x_enable_rx_delay(phydev, true);
 	else
-		ar803x_enable_rx_delay(phydev, false);
+		ret = ar803x_enable_rx_delay(phydev, false);
+
+	return ret;
+}
+
+static int ar8031_config(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = ar803x_delay_config(phydev);
+	if (ret < 0)
+		return ret;
 
 	phydev->supported = phydev->drv->features;
 
@@ -118,6 +131,7 @@ static int ar8031_config(struct phy_device *phydev)
 
 static int ar8035_config(struct phy_device *phydev)
 {
+	int ret;
 	int regval;
 
 	/* Configure CLK_25M output clock at 125 MHz */
@@ -126,17 +140,9 @@ static int ar8035_config(struct phy_device *phydev)
 	regval |= AR8035_CLK_25M_FREQ_125M;
 	phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
 
-	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
-		ar803x_enable_tx_delay(phydev, true);
-	else
-		ar803x_enable_tx_delay(phydev, false);
-
-	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
-	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
-		ar803x_enable_rx_delay(phydev, true);
-	else
-		ar803x_enable_rx_delay(phydev, false);
+	ret = ar803x_delay_config(phydev);
+	if (ret < 0)
+		return ret;
 
 	phydev->supported = phydev->drv->features;
 
-- 
2.20.1

[PATCH v4 10/12] phy: atheros: add device tree bindings and config

[Michael Walle]

Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.

By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.

Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 doc/device-tree-bindings/net/phy/atheros.txt |  35 +++
 drivers/net/phy/atheros.c                    | 224 ++++++++++++++++++-
 include/dt-bindings/net/qca-ar803x.h         |  13 ++
 3 files changed, 270 insertions(+), 2 deletions(-)
 create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt
 create mode 100644 include/dt-bindings/net/qca-ar803x.h

diff --git a/doc/device-tree-bindings/net/phy/atheros.txt b/doc/device-tree-bindings/net/phy/atheros.txt
new file mode 100644
index 0000000000..97e97b8c13
--- /dev/null
+++ b/doc/device-tree-bindings/net/phy/atheros.txt
@@ -0,0 +1,35 @@
+* Qualcomm Atheros PHY Device Tree binding
+
+Required properties:
+- reg: PHY address
+
+Optional properties:
+- qca,clk-out-frequency: Clock frequency of the CLK_25M pin in Hz.
+	Either 25000000, 50000000, 62500000 or 125000000.
+- qca,clk-out-strength: Clock output buffer driver strength.
+    Supported values are defined in dt-bindings/net/qca-ar803x.h
+- qca,keep-pll-enabled: Keep the PLL running if no link is present.
+	Don't go into hibernation mode.
+	Only supported on the AR8031/AR8033.
+- vddio-supply: RGMII I/O voltage regulator
+	Only supported on the AR8031/AR8033.
+
+Optional subnodes:
+- vddio-regulator: Initial data for the VDDIO regulator, as covered
+    doc/device-tree-bindings/regulator/regulator.txt
+
+Example:
+	#include <dt-bindings/net/qca-ar803x.h>
+
+	ethernet-phy at 0 {
+		reg = <0>;
+		qca-clk-out-frequency = <125000000>;
+		qca,keep-pll-enabled;
+
+		vddio-supply = <&vddio>;
+
+		vddio: vddio-regulator {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+	};
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 22035c2496..3cd301c50e 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -4,21 +4,41 @@
  *
  * Copyright 2011, 2013 Freescale Semiconductor, Inc.
  * author Andy Fleming
+ * Copyright (c) 2019 Michael Walle <michael@walle.cc>
  */
 #include <common.h>
 #include <phy.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <dt-bindings/net/qca-ar803x.h>
 
 #define AR803x_PHY_DEBUG_ADDR_REG	0x1d
 #define AR803x_PHY_DEBUG_DATA_REG	0x1e
 
+/* Debug registers */
+#define AR803x_DEBUG_REG_0		0x0
+#define AR803x_RGMII_RX_CLK_DLY		BIT(15)
+
 #define AR803x_DEBUG_REG_5		0x5
 #define AR803x_RGMII_TX_CLK_DLY		BIT(8)
 
-#define AR803x_DEBUG_REG_0		0x0
-#define AR803x_RGMII_RX_CLK_DLY		BIT(15)
+#define AR803x_DEBUG_REG_1F		0x1f
+#define AR803x_PLL_ON			BIT(2)
+#define AR803x_RGMII_1V8		BIT(3)
 
 /* CLK_25M register is at MMD 7, address 0x8016 */
 #define AR803x_CLK_25M_SEL_REG		0x8016
+
+#define AR803x_CLK_25M_MASK		GENMASK(4, 2)
+#define AR803x_CLK_25M_25MHZ_XTAL	0
+#define AR803x_CLK_25M_25MHZ_DSP	1
+#define AR803x_CLK_25M_50MHZ_PLL	2
+#define AR803x_CLK_25M_50MHZ_DSP	3
+#define AR803x_CLK_25M_62_5MHZ_PLL	4
+#define AR803x_CLK_25M_62_5MHZ_DSP	5
+#define AR803x_CLK_25M_125MHZ_PLL	6
+#define AR803x_CLK_25M_125MHZ_DSP	7
+
 /* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
 #define AR8035_CLK_25M_FREQ_25M		(0 | 0)
 #define AR8035_CLK_25M_FREQ_50M		(0 | BIT(3))
@@ -26,10 +46,23 @@
 #define AR8035_CLK_25M_FREQ_125M	(BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASK		GENMASK(4, 3)
 
+#define AR803x_CLK_25M_DR_MASK		GENMASK(8, 7)
+#define AR803x_CLK_25M_DR_FULL		0
+#define AR803x_CLK_25M_DR_HALF		1
+#define AR803x_CLK_25M_DR_QUARTER	2
+
 #define AR8021_PHY_ID 0x004dd040
 #define AR8031_PHY_ID 0x004dd074
 #define AR8035_PHY_ID 0x004dd072
 
+struct ar803x_priv {
+	int flags;
+#define AR803x_FLAG_KEEP_PLL_ENABLED	BIT(0) /* don't turn off internal PLL */
+#define AR803x_FLAG_RGMII_1V8		BIT(1) /* use 1.8V RGMII I/O voltage */
+	u16 clk_25m_reg;
+	u16 clk_25m_mask;
+};
+
 static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg)
 {
 	int ret;
@@ -113,14 +146,193 @@ static int ar803x_delay_config(struct phy_device *phydev)
 	return ret;
 }
 
+static int ar803x_regs_config(struct phy_device *phydev)
+{
+	struct ar803x_priv *priv = phydev->priv;
+	u16 set = 0, clear = 0;
+	int val;
+	int ret;
+
+	/* no configuration available */
+	if (!priv)
+		return 0;
+
+	/*
+	 * Only supported on the AR8031, AR8035 has strappings for the PLL mode
+	 * as well as the RGMII voltage.
+	 */
+	if (phydev->drv->uid == AR8031_PHY_ID) {
+		if (priv->flags & AR803x_FLAG_KEEP_PLL_ENABLED)
+			set |= AR803x_PLL_ON;
+		else
+			clear |= AR803x_PLL_ON;
+
+		if (priv->flags & AR803x_FLAG_RGMII_1V8)
+			set |= AR803x_RGMII_1V8;
+		else
+			clear |= AR803x_RGMII_1V8;
+
+		ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_1F, clear,
+					    set);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* save the write access if the mask is empty */
+	if (priv->clk_25m_mask) {
+		val = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
+		if (val < 0)
+			return val;
+		val &= ~priv->clk_25m_mask;
+		val |= priv->clk_25m_reg;
+		ret = phy_write_mmd(phydev, MDIO_MMD_AN,
+				    AR803x_CLK_25M_SEL_REG, val);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ar803x_of_init(struct phy_device *phydev)
+{
+#if defined(CONFIG_DM_ETH)
+	struct ar803x_priv *priv;
+	ofnode node, vddio_reg_node;
+	u32 strength, freq, min_uV, max_uV;
+	int sel;
+
+	node = phy_get_ofnode(phydev);
+	if (!ofnode_valid(node))
+		return -EINVAL;
+
+	priv = malloc(sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+	memset(priv, 0, sizeof(*priv));
+
+	phydev->priv = priv;
+
+	debug("%s: found PHY node: %s\n", __func__, ofnode_get_name(node));
+
+	if (ofnode_read_bool(node, "qca,keep-pll-enabled"))
+		priv->flags |= AR803x_FLAG_KEEP_PLL_ENABLED;
+
+	/*
+	 * We can't use the regulator framework because the regulator is
+	 * a subnode of the PHY. So just read the two properties we are
+	 * interested in.
+	 */
+	vddio_reg_node = ofnode_find_subnode(node, "vddio-regulator");
+	if (ofnode_valid(vddio_reg_node)) {
+		min_uV = ofnode_read_u32_default(vddio_reg_node,
+						 "regulator-min-microvolt", 0);
+		max_uV = ofnode_read_u32_default(vddio_reg_node,
+						 "regulator-max-microvolt", 0);
+
+		if (min_uV != max_uV) {
+			free(priv);
+			return -EINVAL;
+		}
+
+		switch (min_uV) {
+		case 1500000:
+			break;
+		case 1800000:
+			priv->flags |= AR803x_FLAG_RGMII_1V8;
+			break;
+		default:
+			free(priv);
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * Get the CLK_25M frequency from the device tree. Only XTAL and PLL
+	 * sources are supported right now. There is also the possibilty to use
+	 * the DSP as frequency reference, this is used for synchronous
+	 * ethernet.
+	 */
+	if (!ofnode_read_u32(node, "qca,clk-out-frequency", &freq)) {
+		switch (freq) {
+		case 25000000:
+			sel = AR803x_CLK_25M_25MHZ_XTAL;
+			break;
+		case 50000000:
+			sel = AR803x_CLK_25M_50MHZ_PLL;
+			break;
+		case 62500000:
+			sel = AR803x_CLK_25M_62_5MHZ_PLL;
+			break;
+		case 125000000:
+			sel = AR803x_CLK_25M_125MHZ_PLL;
+			break;
+		default:
+			dev_err(phydev->dev,
+				"invalid qca,clk-out-frequency\n");
+			free(priv);
+			return -EINVAL;
+		}
+
+		priv->clk_25m_mask |= AR803x_CLK_25M_MASK;
+		priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_MASK, sel);
+		/*
+		 * Fixup for the AR8035 which only has two bits. The two
+		 * remaining bits map to the same frequencies.
+		 */
+		if (phydev->drv->uid == AR8035_PHY_ID) {
+			u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
+
+			priv->clk_25m_mask &= ~clear;
+			priv->clk_25m_reg &= ~clear;
+		}
+	}
+
+	if (phydev->drv->uid == AR8031_PHY_ID &&
+	    !ofnode_read_u32(node, "qca,clk-out-strength", &strength)) {
+		switch (strength) {
+		case AR803X_STRENGTH_FULL:
+			sel = AR803x_CLK_25M_DR_FULL;
+			break;
+		case AR803X_STRENGTH_HALF:
+			sel = AR803x_CLK_25M_DR_HALF;
+			break;
+		case AR803X_STRENGTH_QUARTER:
+			sel = AR803x_CLK_25M_DR_QUARTER;
+			break;
+		default:
+			dev_err(phydev->dev,
+				"invalid qca,clk-out-strength\n");
+			free(priv);
+			return -EINVAL;
+		}
+		priv->clk_25m_mask |= AR803x_CLK_25M_DR_MASK;
+		priv->clk_25m_reg |= FIELD_PREP(AR803x_CLK_25M_DR_MASK, sel);
+	}
+
+	debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__,
+	      priv->flags, priv->clk_25m_reg, priv->clk_25m_mask);
+#endif
+
+	return 0;
+}
+
 static int ar8031_config(struct phy_device *phydev)
 {
 	int ret;
 
+	ret = ar803x_of_init(phydev);
+	if (ret < 0)
+		return ret;
+
 	ret = ar803x_delay_config(phydev);
 	if (ret < 0)
 		return ret;
 
+	ret = ar803x_regs_config(phydev);
+	if (ret < 0)
+		return ret;
+
 	phydev->supported = phydev->drv->features;
 
 	genphy_config_aneg(phydev);
@@ -134,6 +346,10 @@ static int ar8035_config(struct phy_device *phydev)
 	int ret;
 	int regval;
 
+	ret = ar803x_of_init(phydev);
+	if (ret < 0)
+		return ret;
+
 	/* Configure CLK_25M output clock@125 MHz */
 	regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
 	regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
@@ -144,6 +360,10 @@ static int ar8035_config(struct phy_device *phydev)
 	if (ret < 0)
 		return ret;
 
+	ret = ar803x_regs_config(phydev);
+	if (ret < 0)
+		return ret;
+
 	phydev->supported = phydev->drv->features;
 
 	genphy_config_aneg(phydev);
diff --git a/include/dt-bindings/net/qca-ar803x.h b/include/dt-bindings/net/qca-ar803x.h
new file mode 100644
index 0000000000..9c046c7242
--- /dev/null
+++ b/include/dt-bindings/net/qca-ar803x.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Device Tree constants for the Qualcomm Atheros AR803x PHYs
+ */
+
+#ifndef _DT_BINDINGS_QCA_AR803X_H
+#define _DT_BINDINGS_QCA_AR803X_H
+
+#define AR803X_STRENGTH_FULL		0
+#define AR803X_STRENGTH_HALF		1
+#define AR803X_STRENGTH_QUARTER		2
+
+#endif
-- 
2.20.1

[PATCH v4 11/12] phy: atheros: ar8035: remove static clock config

[Michael Walle]

We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.

If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3cd301c50e..3142733105 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -38,12 +38,6 @@
 #define AR803x_CLK_25M_62_5MHZ_DSP	5
 #define AR803x_CLK_25M_125MHZ_PLL	6
 #define AR803x_CLK_25M_125MHZ_DSP	7
-
-/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
-#define AR8035_CLK_25M_FREQ_25M		(0 | 0)
-#define AR8035_CLK_25M_FREQ_50M		(0 | BIT(3))
-#define AR8035_CLK_25M_FREQ_62M		(BIT(4) | 0)
-#define AR8035_CLK_25M_FREQ_125M	(BIT(4) | BIT(3))
 #define AR8035_CLK_25M_MASK		GENMASK(4, 3)
 
 #define AR803x_CLK_25M_DR_MASK		GENMASK(8, 7)
@@ -344,18 +338,11 @@ static int ar8031_config(struct phy_device *phydev)
 static int ar8035_config(struct phy_device *phydev)
 {
 	int ret;
-	int regval;
 
 	ret = ar803x_of_init(phydev);
 	if (ret < 0)
 		return ret;
 
-	/* Configure CLK_25M output clock@125 MHz */
-	regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
-	regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
-	regval |= AR8035_CLK_25M_FREQ_125M;
-	phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
-
 	ret = ar803x_delay_config(phydev);
 	if (ret < 0)
 		return ret;
-- 
2.20.1

[PATCH v4 12/12] phy: atheros: consolidate {ar8031|ar8035}_config()

[Michael Walle]

The two functions are now exactly the same, remove one of them.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 30 +++---------------------------
 1 file changed, 3 insertions(+), 27 deletions(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3142733105..47ff9f8d44 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -311,31 +311,7 @@ static int ar803x_of_init(struct phy_device *phydev)
 	return 0;
 }
 
-static int ar8031_config(struct phy_device *phydev)
-{
-	int ret;
-
-	ret = ar803x_of_init(phydev);
-	if (ret < 0)
-		return ret;
-
-	ret = ar803x_delay_config(phydev);
-	if (ret < 0)
-		return ret;
-
-	ret = ar803x_regs_config(phydev);
-	if (ret < 0)
-		return ret;
-
-	phydev->supported = phydev->drv->features;
-
-	genphy_config_aneg(phydev);
-	genphy_restart_aneg(phydev);
-
-	return 0;
-}
-
-static int ar8035_config(struct phy_device *phydev)
+static int ar803x_config(struct phy_device *phydev)
 {
 	int ret;
 
@@ -374,7 +350,7 @@ static struct phy_driver AR8031_driver =  {
 	.uid = AR8031_PHY_ID,
 	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
-	.config = ar8031_config,
+	.config = ar803x_config,
 	.startup = genphy_startup,
 	.shutdown = genphy_shutdown,
 };
@@ -384,7 +360,7 @@ static struct phy_driver AR8035_driver =  {
 	.uid = AR8035_PHY_ID,
 	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
-	.config = ar8035_config,
+	.config = ar803x_config,
 	.startup = genphy_startup,
 	.shutdown = genphy_shutdown,
 };
-- 
2.20.1

[PATCH v4 01/12] phy: atheros: Make RGMII Tx delays actually configurable for AR8035

[Tom Rini]

On Thu, May 07, 2020 at 12:11:48AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Delete the extraneous write to debug reg 5 that enables Tx delay
> 
> When the driver was originally introduced in commit "6027384a phylib:
> Add Atheros AR8035 GETH PHY support", the Tx delay was being
> unconditionally enabled.
> 
> Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
> and RGMII_RXID", the author did not notice that code for enabling Tx
> delay code was already. Therefore, the if condition for Tx delay has
> always been useless for this PHY since this commit introduced it.
> 
> Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled.
> After this patch, only those who define the interface as RGMII_TXID or
> RGMII_ID will. This is to be expected, but will nonetheless break the
> setups of those who didn't know they rely on Tx delay implicitly.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/960fd7e7/attachment.sig>

[PATCH v4 02/12] phy: atheros: Use common functions for RGMII internal delays

[Tom Rini]

On Thu, May 07, 2020 at 12:11:49AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/4542793c/attachment.sig>

[PATCH v4 03/12] phy: atheros: Clarify the configuration of the CLK_25M output pin

[Tom Rini]

On Thu, May 07, 2020 at 12:11:50AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Also take the opportunity to use the phy_read_mmd and phy_write_mmd
> convenience functions.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/7487622e/attachment.sig>

[PATCH v4 04/12] phy: atheros: Explicitly disable RGMII delays

[Tom Rini]

On Thu, May 07, 2020 at 12:11:51AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> To eliminate any doubts about the out-of-reset value of the PHY, that
> the driver previously relied on.
> 
> If bisecting shows that this commit breaks your board you probably have
> a wrong PHY interface mode. You probably want the
> PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/8f22c586/attachment.sig>

[PATCH v4 05/12] phy: atheros: Clarify the intention of ar8021_config

[Tom Rini]

On Thu, May 07, 2020 at 12:11:52AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> 
> Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
> the other bit positions, just like the other PHYs in the family do.
> Therefore, it is not necessary to hardcode the reserved values, but
> instead simply follow the read-modify-write procedure from the common
> function.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/f47f8383/attachment.sig>

[PATCH v4 06/12] phy: atheros: fix AR8021 PHY ID mask

[Tom Rini]

On Thu, May 07, 2020 at 12:11:53AM +0200, Michael Walle wrote:

> The upper bits are all the OUI.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/2fbb062b/attachment.sig>

[PATCH v4 07/12] phy: atheros: use defines for PHY IDs

[Tom Rini]

On Thu, May 07, 2020 at 12:11:54AM +0200, Michael Walle wrote:

> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/9ab48dc8/attachment.sig>

[PATCH v4 08/12] phy: atheros: introduce debug read and write functions

[Tom Rini]

On Thu, May 07, 2020 at 12:11:55AM +0200, Michael Walle wrote:

> Provide functions to read and write the Atheros debug registers.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/80444d61/attachment.sig>

[PATCH v4 09/12] phy: atheros: move delay config to common function

[Tom Rini]

On Thu, May 07, 2020 at 12:11:56AM +0200, Michael Walle wrote:

> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/ba444b17/attachment.sig>

[PATCH v4 10/12] phy: atheros: add device tree bindings and config

[Tom Rini]

On Thu, May 07, 2020 at 12:11:57AM +0200, Michael Walle wrote:

> Add support for configuring the CLK_25M pin as well as the RGMII I/O
> voltage by the device tree.
> 
> By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
> But this output can also be changed by software to other frequencies.
> This commit introduces a generic way to configure this output.
> 
> Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
> An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
> option needs an external supply voltage. This commit adds support to
> switch the internal LDO to 1.8V.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/45cac5b4/attachment.sig>

[PATCH v4 11/12] phy: atheros: ar8035: remove static clock config

[Tom Rini]

On Thu, May 07, 2020 at 12:11:58AM +0200, Michael Walle wrote:

> We can configure the clock output in the device tree. Disable the
> hardcoded one in here. This is highly board-specific and should have
> never been enabled in the PHY driver.
> 
> If bisecting shows that this commit breaks your board it probably
> depends on the clock output of your Atheros AR8035 PHY. Please have a
> look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
> "clk-out-frequency = <125000000>" because that value was the hardcoded
> value until this commit.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/60655c1d/attachment.sig>

[PATCH v4 12/12] phy: atheros: consolidate {ar8031|ar8035}_config()

[Tom Rini]

On Thu, May 07, 2020 at 12:11:59AM +0200, Michael Walle wrote:

> The two functions are now exactly the same, remove one of them.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Applied to u-boot/master, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200507/8b6cc20b/attachment.sig>