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From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Cc: daniele.ceraolospurio@intel.com, john.c.harrison@intel.com
Subject: [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled
Date: Thu, 24 Jun 2021 00:05:01 -0700	[thread overview]
Message-ID: <20210624070516.21893-33-matthew.brost@intel.com> (raw)
In-Reply-To: <20210624070516.21893-1-matthew.brost@intel.com>

If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 .../gpu/drm/i915/gt/intel_engine_heartbeat.c  | 63 +++++++++++++++----
 .../gpu/drm/i915/gt/intel_engine_heartbeat.h  |  4 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  9 +++
 drivers/gpu/drm/i915/i915_scheduler.c         |  6 ++
 drivers/gpu/drm/i915/i915_scheduler.h         |  6 ++
 drivers/gpu/drm/i915/i915_scheduler_types.h   |  5 ++
 6 files changed, 80 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index b6a305e6a974..a8495364d906 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -70,12 +70,30 @@ static void show_heartbeat(const struct i915_request *rq,
 {
 	struct drm_printer p = drm_debug_printer("heartbeat");
 
-	intel_engine_dump(engine, &p,
-			  "%s heartbeat {seqno:%llx:%lld, prio:%d} not ticking\n",
-			  engine->name,
-			  rq->fence.context,
-			  rq->fence.seqno,
-			  rq->sched.attr.priority);
+	if (!rq) {
+		intel_engine_dump(engine, &p,
+				  "%s heartbeat not ticking\n",
+				  engine->name);
+	} else {
+		intel_engine_dump(engine, &p,
+				  "%s heartbeat {seqno:%llx:%lld, prio:%d} not ticking\n",
+				  engine->name,
+				  rq->fence.context,
+				  rq->fence.seqno,
+				  rq->sched.attr.priority);
+	}
+}
+
+static void
+reset_engine(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		show_heartbeat(rq, engine);
+
+	intel_gt_handle_error(engine->gt, engine->mask,
+			      I915_ERROR_CAPTURE,
+			      "stopped heartbeat on %s",
+			      engine->name);
 }
 
 static void heartbeat(struct work_struct *wrk)
@@ -102,6 +120,11 @@ static void heartbeat(struct work_struct *wrk)
 	if (intel_gt_is_wedged(engine->gt))
 		goto out;
 
+	if (i915_sched_engine_disabled(engine->sched_engine)) {
+		reset_engine(engine, engine->heartbeat.systole);
+		goto out;
+	}
+
 	if (engine->heartbeat.systole) {
 		long delay = READ_ONCE(engine->props.heartbeat_interval_ms);
 
@@ -139,13 +162,7 @@ static void heartbeat(struct work_struct *wrk)
 			engine->sched_engine->schedule(rq, &attr);
 			local_bh_enable();
 		} else {
-			if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
-				show_heartbeat(rq, engine);
-
-			intel_gt_handle_error(engine->gt, engine->mask,
-					      I915_ERROR_CAPTURE,
-					      "stopped heartbeat on %s",
-					      engine->name);
+			reset_engine(engine, rq);
 		}
 
 		rq->emitted_jiffies = jiffies;
@@ -194,6 +211,26 @@ void intel_engine_park_heartbeat(struct intel_engine_cs *engine)
 		i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
 }
 
+void intel_gt_unpark_heartbeats(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	for_each_engine(engine, gt, id)
+		if (intel_engine_pm_is_awake(engine))
+			intel_engine_unpark_heartbeat(engine);
+
+}
+
+void intel_gt_park_heartbeats(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	for_each_engine(engine, gt, id)
+		intel_engine_park_heartbeat(engine);
+}
+
 void intel_engine_init_heartbeat(struct intel_engine_cs *engine)
 {
 	INIT_DELAYED_WORK(&engine->heartbeat.work, heartbeat);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index a488ea3e84a3..5da6d809a87a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -7,6 +7,7 @@
 #define INTEL_ENGINE_HEARTBEAT_H
 
 struct intel_engine_cs;
+struct intel_gt;
 
 void intel_engine_init_heartbeat(struct intel_engine_cs *engine);
 
@@ -16,6 +17,9 @@ int intel_engine_set_heartbeat(struct intel_engine_cs *engine,
 void intel_engine_park_heartbeat(struct intel_engine_cs *engine);
 void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine);
 
+void intel_gt_park_heartbeats(struct intel_gt *gt);
+void intel_gt_unpark_heartbeats(struct intel_gt *gt);
+
 int intel_engine_pulse(struct intel_engine_cs *engine);
 int intel_engine_flush_barriers(struct intel_engine_cs *engine);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b8c894ad8caf..59fca9748c15 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -10,6 +10,7 @@
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_context.h"
 #include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_heartbeat.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
 #include "gt/intel_gt_pm.h"
@@ -605,6 +606,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
 		/* Reset called during driver load? GuC not yet initialised! */
 		return;
 
+	intel_gt_park_heartbeats(guc_to_gt(guc));
 	disable_submission(guc);
 	guc->interrupts.disable(guc);
 
@@ -890,6 +892,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
 	atomic_set(&guc->outstanding_submission_g2h, 0);
 
 	enable_submission(guc);
+	intel_gt_unpark_heartbeats(guc_to_gt(guc));
 }
 
 /*
@@ -1859,6 +1862,11 @@ static int guc_resume(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
+{
+	return !sched_engine->tasklet.callback;
+}
+
 static void guc_set_default_submission(struct intel_engine_cs *engine)
 {
 	engine->submit_request = guc_submit_request;
@@ -2009,6 +2017,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
 			return -ENOMEM;
 
 		guc->sched_engine->schedule = i915_schedule;
+		guc->sched_engine->disabled = guc_sched_engine_disabled;
 		guc->sched_engine->private_data = guc;
 		tasklet_setup(&guc->sched_engine->tasklet,
 			      guc_submission_tasklet);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 3a58a9130309..3fb009ea2cb2 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -440,6 +440,11 @@ void i915_sched_engine_free(struct kref *kref)
 	kfree(sched_engine);
 }
 
+static bool default_disabled(struct i915_sched_engine *sched_engine)
+{
+	return false;
+}
+
 struct i915_sched_engine *
 i915_sched_engine_create(unsigned int subclass)
 {
@@ -453,6 +458,7 @@ i915_sched_engine_create(unsigned int subclass)
 
 	sched_engine->queue = RB_ROOT_CACHED;
 	sched_engine->queue_priority_hint = INT_MIN;
+	sched_engine->disabled = default_disabled;
 
 	INIT_LIST_HEAD(&sched_engine->requests);
 	INIT_LIST_HEAD(&sched_engine->hold);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 650ab8e0db9f..72105a53b0e1 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -98,4 +98,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
 				     const char *prefix,
 				     int indent);
 
+static inline bool
+i915_sched_engine_disabled(struct i915_sched_engine *sched_engine)
+{
+	return sched_engine->disabled(sched_engine);
+}
+
 #endif /* _I915_SCHEDULER_H_ */
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 5935c3152bdc..cfaf52e528d0 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -163,6 +163,11 @@ struct i915_sched_engine {
 	 */
 	void *private_data;
 
+	/**
+	 * @disabled: check if backend has disabled submission
+	 */
+	bool	(*disabled)(struct i915_sched_engine *sched_engine);
+
 	/**
 	 * @kick_backend: kick backend after a request's priority has changed
 	 */
-- 
2.28.0


WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org>
Subject: [Intel-gfx] [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled
Date: Thu, 24 Jun 2021 00:05:01 -0700	[thread overview]
Message-ID: <20210624070516.21893-33-matthew.brost@intel.com> (raw)
In-Reply-To: <20210624070516.21893-1-matthew.brost@intel.com>

If submission is disabled by the backend for any reason, reset the GPU
immediately in the heartbeat code as the backend can't be reenabled
until the GPU is reset.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 .../gpu/drm/i915/gt/intel_engine_heartbeat.c  | 63 +++++++++++++++----
 .../gpu/drm/i915/gt/intel_engine_heartbeat.h  |  4 ++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  9 +++
 drivers/gpu/drm/i915/i915_scheduler.c         |  6 ++
 drivers/gpu/drm/i915/i915_scheduler.h         |  6 ++
 drivers/gpu/drm/i915/i915_scheduler_types.h   |  5 ++
 6 files changed, 80 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index b6a305e6a974..a8495364d906 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -70,12 +70,30 @@ static void show_heartbeat(const struct i915_request *rq,
 {
 	struct drm_printer p = drm_debug_printer("heartbeat");
 
-	intel_engine_dump(engine, &p,
-			  "%s heartbeat {seqno:%llx:%lld, prio:%d} not ticking\n",
-			  engine->name,
-			  rq->fence.context,
-			  rq->fence.seqno,
-			  rq->sched.attr.priority);
+	if (!rq) {
+		intel_engine_dump(engine, &p,
+				  "%s heartbeat not ticking\n",
+				  engine->name);
+	} else {
+		intel_engine_dump(engine, &p,
+				  "%s heartbeat {seqno:%llx:%lld, prio:%d} not ticking\n",
+				  engine->name,
+				  rq->fence.context,
+				  rq->fence.seqno,
+				  rq->sched.attr.priority);
+	}
+}
+
+static void
+reset_engine(struct intel_engine_cs *engine, struct i915_request *rq)
+{
+	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		show_heartbeat(rq, engine);
+
+	intel_gt_handle_error(engine->gt, engine->mask,
+			      I915_ERROR_CAPTURE,
+			      "stopped heartbeat on %s",
+			      engine->name);
 }
 
 static void heartbeat(struct work_struct *wrk)
@@ -102,6 +120,11 @@ static void heartbeat(struct work_struct *wrk)
 	if (intel_gt_is_wedged(engine->gt))
 		goto out;
 
+	if (i915_sched_engine_disabled(engine->sched_engine)) {
+		reset_engine(engine, engine->heartbeat.systole);
+		goto out;
+	}
+
 	if (engine->heartbeat.systole) {
 		long delay = READ_ONCE(engine->props.heartbeat_interval_ms);
 
@@ -139,13 +162,7 @@ static void heartbeat(struct work_struct *wrk)
 			engine->sched_engine->schedule(rq, &attr);
 			local_bh_enable();
 		} else {
-			if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
-				show_heartbeat(rq, engine);
-
-			intel_gt_handle_error(engine->gt, engine->mask,
-					      I915_ERROR_CAPTURE,
-					      "stopped heartbeat on %s",
-					      engine->name);
+			reset_engine(engine, rq);
 		}
 
 		rq->emitted_jiffies = jiffies;
@@ -194,6 +211,26 @@ void intel_engine_park_heartbeat(struct intel_engine_cs *engine)
 		i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
 }
 
+void intel_gt_unpark_heartbeats(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	for_each_engine(engine, gt, id)
+		if (intel_engine_pm_is_awake(engine))
+			intel_engine_unpark_heartbeat(engine);
+
+}
+
+void intel_gt_park_heartbeats(struct intel_gt *gt)
+{
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	for_each_engine(engine, gt, id)
+		intel_engine_park_heartbeat(engine);
+}
+
 void intel_engine_init_heartbeat(struct intel_engine_cs *engine)
 {
 	INIT_DELAYED_WORK(&engine->heartbeat.work, heartbeat);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
index a488ea3e84a3..5da6d809a87a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
@@ -7,6 +7,7 @@
 #define INTEL_ENGINE_HEARTBEAT_H
 
 struct intel_engine_cs;
+struct intel_gt;
 
 void intel_engine_init_heartbeat(struct intel_engine_cs *engine);
 
@@ -16,6 +17,9 @@ int intel_engine_set_heartbeat(struct intel_engine_cs *engine,
 void intel_engine_park_heartbeat(struct intel_engine_cs *engine);
 void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine);
 
+void intel_gt_park_heartbeats(struct intel_gt *gt);
+void intel_gt_unpark_heartbeats(struct intel_gt *gt);
+
 int intel_engine_pulse(struct intel_engine_cs *engine);
 int intel_engine_flush_barriers(struct intel_engine_cs *engine);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b8c894ad8caf..59fca9748c15 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -10,6 +10,7 @@
 #include "gt/intel_breadcrumbs.h"
 #include "gt/intel_context.h"
 #include "gt/intel_engine_pm.h"
+#include "gt/intel_engine_heartbeat.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
 #include "gt/intel_gt_pm.h"
@@ -605,6 +606,7 @@ void intel_guc_submission_reset_prepare(struct intel_guc *guc)
 		/* Reset called during driver load? GuC not yet initialised! */
 		return;
 
+	intel_gt_park_heartbeats(guc_to_gt(guc));
 	disable_submission(guc);
 	guc->interrupts.disable(guc);
 
@@ -890,6 +892,7 @@ void intel_guc_submission_reset_finish(struct intel_guc *guc)
 	atomic_set(&guc->outstanding_submission_g2h, 0);
 
 	enable_submission(guc);
+	intel_gt_unpark_heartbeats(guc_to_gt(guc));
 }
 
 /*
@@ -1859,6 +1862,11 @@ static int guc_resume(struct intel_engine_cs *engine)
 	return 0;
 }
 
+static bool guc_sched_engine_disabled(struct i915_sched_engine *sched_engine)
+{
+	return !sched_engine->tasklet.callback;
+}
+
 static void guc_set_default_submission(struct intel_engine_cs *engine)
 {
 	engine->submit_request = guc_submit_request;
@@ -2009,6 +2017,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
 			return -ENOMEM;
 
 		guc->sched_engine->schedule = i915_schedule;
+		guc->sched_engine->disabled = guc_sched_engine_disabled;
 		guc->sched_engine->private_data = guc;
 		tasklet_setup(&guc->sched_engine->tasklet,
 			      guc_submission_tasklet);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c
index 3a58a9130309..3fb009ea2cb2 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -440,6 +440,11 @@ void i915_sched_engine_free(struct kref *kref)
 	kfree(sched_engine);
 }
 
+static bool default_disabled(struct i915_sched_engine *sched_engine)
+{
+	return false;
+}
+
 struct i915_sched_engine *
 i915_sched_engine_create(unsigned int subclass)
 {
@@ -453,6 +458,7 @@ i915_sched_engine_create(unsigned int subclass)
 
 	sched_engine->queue = RB_ROOT_CACHED;
 	sched_engine->queue_priority_hint = INT_MIN;
+	sched_engine->disabled = default_disabled;
 
 	INIT_LIST_HEAD(&sched_engine->requests);
 	INIT_LIST_HEAD(&sched_engine->hold);
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 650ab8e0db9f..72105a53b0e1 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -98,4 +98,10 @@ void i915_request_show_with_schedule(struct drm_printer *m,
 				     const char *prefix,
 				     int indent);
 
+static inline bool
+i915_sched_engine_disabled(struct i915_sched_engine *sched_engine)
+{
+	return sched_engine->disabled(sched_engine);
+}
+
 #endif /* _I915_SCHEDULER_H_ */
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 5935c3152bdc..cfaf52e528d0 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -163,6 +163,11 @@ struct i915_sched_engine {
 	 */
 	void *private_data;
 
+	/**
+	 * @disabled: check if backend has disabled submission
+	 */
+	bool	(*disabled)(struct i915_sched_engine *sched_engine);
+
 	/**
 	 * @kick_backend: kick backend after a request's priority has changed
 	 */
-- 
2.28.0

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  parent reply	other threads:[~2021-06-24  6:49 UTC|newest]

Thread overview: 336+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24  7:04 [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 17:23   ` Michal Wajdeczko
2021-06-24 17:23     ` [Intel-gfx] " Michal Wajdeczko
2021-06-24  7:04 ` [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 11:58   ` Michal Wajdeczko
2021-06-25 11:58     ` Michal Wajdeczko
2021-06-24  7:04 ` [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 13:49   ` Michal Wajdeczko
2021-06-24 13:49     ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 15:41     ` Matthew Brost
2021-06-24 15:41       ` [Intel-gfx] " Matthew Brost
2021-06-25 12:03       ` Michal Wajdeczko
2021-06-25 12:03         ` [Intel-gfx] " Michal Wajdeczko
2021-06-24  7:04 ` [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 14:48   ` Michal Wajdeczko
2021-06-24 14:48     ` Michal Wajdeczko
2021-06-24 15:49     ` Matthew Brost
2021-06-24 15:49       ` Matthew Brost
2021-06-24 17:02       ` Michal Wajdeczko
2021-06-24 17:02         ` Michal Wajdeczko
2021-06-24 22:41         ` Matthew Brost
2021-06-24 22:41           ` Matthew Brost
2021-06-25 11:50           ` Michal Wajdeczko
2021-06-25 11:50             ` Michal Wajdeczko
2021-06-25 17:53             ` Matthew Brost
2021-06-25 17:53               ` Matthew Brost
2021-06-24 22:47         ` Matthew Brost
2021-06-24 22:47           ` Matthew Brost
2021-06-24  7:04 ` [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 17:37   ` Michal Wajdeczko
2021-06-24 17:37     ` Michal Wajdeczko
2021-06-24 23:01     ` Matthew Brost
2021-06-24 23:01       ` Matthew Brost
2021-06-24  7:04 ` [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 13:09   ` Michal Wajdeczko
2021-06-25 13:09     ` Michal Wajdeczko
2021-06-25 18:26     ` Matthew Brost
2021-06-25 18:26       ` Matthew Brost
2021-06-25 20:28     ` Matthew Brost
2021-06-25 20:28       ` Matthew Brost
2021-06-24  7:04 ` [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-29 21:11   ` John Harrison
2021-06-29 21:11     ` [Intel-gfx] " John Harrison
2021-06-30  0:30     ` Matthew Brost
2021-06-30  0:30       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 19:44   ` John Harrison
2021-06-25 19:44     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 13:17   ` Michal Wajdeczko
2021-06-25 13:17     ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 17:26     ` Matthew Brost
2021-06-25 17:26       ` [Intel-gfx] " Matthew Brost
2021-06-29 21:20       ` John Harrison
2021-06-29 21:20         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-29 22:04   ` John Harrison
2021-06-29 22:04     ` [Intel-gfx] " John Harrison
2021-06-30  0:41     ` Matthew Brost
2021-06-30  0:41       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-29 22:09   ` John Harrison
2021-06-29 22:09     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 13:25   ` Michal Wajdeczko
2021-06-25 13:25     ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 17:46     ` Matthew Brost
2021-06-25 17:46       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:39   ` John Harrison
2021-07-09 22:39     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:48   ` John Harrison
2021-07-09 22:48     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:53   ` John Harrison
2021-07-09 22:53     ` [Intel-gfx] " John Harrison
2021-07-10  3:00     ` Matthew Brost
2021-07-10  3:00       ` [Intel-gfx] " Matthew Brost
2021-07-12 17:57       ` John Harrison
2021-07-12 17:57         ` [Intel-gfx] " John Harrison
2021-07-12 18:11         ` Daniel Vetter
2021-07-12 18:11           ` Daniel Vetter
2021-06-24  7:04 ` [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:59   ` John Harrison
2021-07-09 22:59     ` [Intel-gfx] " John Harrison
2021-07-10  3:36     ` Matthew Brost
2021-07-10  3:36       ` [Intel-gfx] " Matthew Brost
2021-07-12 17:54       ` John Harrison
2021-07-12 17:54         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 23:03   ` John Harrison
2021-07-09 23:03     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-15  1:51   ` Daniele Ceraolo Spurio
2021-07-15  1:51     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-24  7:04 ` [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 23:53   ` John Harrison
2021-07-09 23:53     ` [Intel-gfx] " John Harrison
2021-07-15  0:07     ` Matthew Brost
2021-07-15  0:07       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-13 18:36   ` John Harrison
2021-07-13 18:36     ` [Intel-gfx] " John Harrison
2021-07-15  0:06     ` Matthew Brost
2021-07-15  0:06       ` [Intel-gfx] " Matthew Brost
2021-07-15  0:12       ` John Harrison
2021-07-15  0:12         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-10  0:16   ` John Harrison
2021-07-10  0:16     ` [Intel-gfx] " John Harrison
2021-07-10  3:55     ` Matthew Brost
2021-07-10  3:55       ` [Intel-gfx] " Matthew Brost
2021-07-17  4:09       ` Matthew Brost
2021-07-17  4:09         ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:05   ` John Harrison
2021-07-12 18:05     ` [Intel-gfx] " John Harrison
2021-07-12 20:59     ` Matthew Brost
2021-07-12 20:59       ` [Intel-gfx] " Matthew Brost
2021-07-12 21:37       ` John Harrison
2021-07-12 21:37         ` [Intel-gfx] " John Harrison
2021-07-13  8:51   ` Michal Wajdeczko
2021-07-13  8:51     ` [Intel-gfx] " Michal Wajdeczko
2021-07-14 23:56     ` Matthew Brost
2021-07-14 23:56       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:08   ` John Harrison
2021-07-12 18:08     ` [Intel-gfx] " John Harrison
2021-07-13  9:06   ` Tvrtko Ursulin
2021-07-13  9:06     ` Tvrtko Ursulin
2021-07-20  1:59     ` Matthew Brost
2021-07-20  1:59       ` Matthew Brost
2021-07-22 13:55       ` Tvrtko Ursulin
2021-07-22 13:55         ` Tvrtko Ursulin
2021-06-24  7:04 ` [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:10   ` John Harrison
2021-07-12 18:10     ` [Intel-gfx] " John Harrison
2021-07-12 21:47     ` Matthew Brost
2021-07-12 21:47       ` [Intel-gfx] " Matthew Brost
2021-07-12 21:51       ` John Harrison
2021-07-12 21:51         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-15  1:21   ` Daniele Ceraolo Spurio
2021-07-15  1:21     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-24  7:04 ` [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:11   ` John Harrison
2021-07-12 18:11     ` [Intel-gfx] " John Harrison
2021-07-12 20:06     ` Matthew Brost
2021-07-12 20:06       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-07-12 18:23     ` [Intel-gfx] " John Harrison
2021-07-12 20:05     ` Matthew Brost
2021-07-12 20:05       ` [Intel-gfx] " Matthew Brost
2021-07-12 21:36       ` Matthew Brost
2021-07-12 21:36         ` Matthew Brost
2021-07-12 21:48         ` John Harrison
2021-07-12 21:48           ` John Harrison
2021-06-24  7:04 ` [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-07-12 18:23     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 19:19   ` John Harrison
2021-07-12 19:19     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 19:58   ` John Harrison
2021-07-12 19:58     ` [Intel-gfx] " John Harrison
2021-07-15  0:53     ` Matthew Brost
2021-07-15  0:53       ` [Intel-gfx] " Matthew Brost
2021-07-15  9:36   ` Tvrtko Ursulin
2021-07-15  9:36     ` Tvrtko Ursulin
2021-07-26 22:48     ` Matthew Brost
2021-07-26 22:48       ` Matthew Brost
2021-07-27  8:56       ` Tvrtko Ursulin
2021-07-27  8:56         ` Tvrtko Ursulin
2021-07-27 18:30         ` Matthew Brost
2021-07-27 18:30           ` Matthew Brost
2021-06-24  7:05 ` Matthew Brost [this message]
2021-06-24  7:05   ` [Intel-gfx] [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-12 20:01   ` John Harrison
2021-07-12 20:01     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 20:11   ` John Harrison
2021-07-12 20:11     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 22:56   ` John Harrison
2021-07-12 22:56     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 22:58   ` John Harrison
2021-07-12 22:58     ` [Intel-gfx] " John Harrison
2021-07-15  0:32     ` Matthew Brost
2021-07-15  0:32       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 22:59   ` John Harrison
2021-07-12 22:59     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 23:00   ` John Harrison
2021-07-12 23:00     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24 15:55   ` Matthew Brost
2021-06-24 15:55     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24 16:19   ` Matthew Brost
2021-06-24 16:19     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 23:05   ` John Harrison
2021-07-12 23:05     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-15  0:43   ` Matthew Brost
2021-07-15  0:43     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-25  0:59   ` Matthew Brost
2021-06-25  0:59     ` Matthew Brost
2021-06-25 19:10     ` John Harrison
2021-06-25 19:10       ` John Harrison
2021-07-10 18:56       ` Matthew Brost
2021-07-10 18:56         ` Matthew Brost
2021-06-24  7:05 ` [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-25  1:10   ` Matthew Brost
2021-06-25  1:10     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24 16:34   ` Matthew Brost
2021-06-24 16:34     ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-30  8:22   ` Martin Peres
2021-06-30  8:22     ` [Intel-gfx] " Martin Peres
2021-06-30 18:00     ` Matthew Brost
2021-06-30 18:00       ` [Intel-gfx] " Matthew Brost
2021-07-01 18:24       ` Martin Peres
2021-07-01 18:24         ` [Intel-gfx] " Martin Peres
2021-07-02  8:13         ` Martin Peres
2021-07-02  8:13           ` [Intel-gfx] " Martin Peres
2021-07-02 13:06           ` Michal Wajdeczko
2021-07-02 13:06             ` [Intel-gfx] " Michal Wajdeczko
2021-07-02 13:12             ` Martin Peres
2021-07-02 13:12               ` [Intel-gfx] " Martin Peres
2021-07-02 14:08               ` Michal Wajdeczko
2021-07-02 14:08                 ` [Intel-gfx] " Michal Wajdeczko
2021-06-30 18:58     ` John Harrison
2021-06-30 18:58       ` [Intel-gfx] " John Harrison
2021-07-01  8:14       ` Pekka Paalanen
2021-07-01  8:14         ` [Intel-gfx] " Pekka Paalanen
2021-07-01 18:27         ` Martin Peres
2021-07-01 18:27           ` [Intel-gfx] " Martin Peres
2021-07-01 19:28           ` Daniel Vetter
2021-07-01 19:28             ` Daniel Vetter
2021-07-02  7:29             ` Pekka Paalanen
2021-07-02  7:29               ` Pekka Paalanen
2021-07-02  8:09               ` Martin Peres
2021-07-02  8:09                 ` Martin Peres
2021-07-02 15:07                 ` Michal Wajdeczko
2021-07-02 15:07                   ` Michal Wajdeczko
2021-07-03  8:21                   ` Martin Peres
2021-07-03  8:21                     ` Martin Peres
2021-07-07  0:57                     ` John Harrison
2021-07-07  0:57                       ` John Harrison
2021-07-07  7:47                       ` Pekka Paalanen
2021-07-07  7:47                         ` Pekka Paalanen
2021-07-07 10:11                       ` Michal Wajdeczko
2021-07-07 10:11                         ` Michal Wajdeczko
2021-07-15  0:49   ` Matthew Brost
2021-07-15  0:49     ` Matthew Brost
2021-06-24  7:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support Patchwork
2021-06-24  7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-24  7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22  9:35 ` [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22  9:35   ` [Intel-gfx] " Joonas Lahtinen
2021-10-22 16:42   ` Matthew Brost
2021-10-22 16:42     ` [Intel-gfx] " Matthew Brost
2021-10-25  9:37     ` Joonas Lahtinen
2021-10-25  9:37       ` [Intel-gfx] " Joonas Lahtinen
2021-10-25 15:15       ` Matthew Brost
2021-10-25 15:15         ` [Intel-gfx] " Matthew Brost
2021-10-26  8:59         ` Joonas Lahtinen
2021-10-26  8:59           ` [Intel-gfx] " Joonas Lahtinen
2021-10-26 15:43           ` Matthew Brost
2021-10-26 15:43             ` [Intel-gfx] " Matthew Brost
2021-10-26 15:51           ` Matthew Brost
2021-10-26 15:51             ` [Intel-gfx] " Matthew Brost
2021-10-27  9:21             ` Joonas Lahtinen
2021-10-27  9:21               ` [Intel-gfx] " Joonas Lahtinen
2021-10-25 17:06       ` John Harrison
2021-10-25 17:06         ` [Intel-gfx] " John Harrison

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