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From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org, daniele.ceraolospurio@intel.com,
	john.c.harrison@intel.com, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers
Date: Fri, 25 Jun 2021 14:03:39 +0200	[thread overview]
Message-ID: <5264ef27-efbd-1adf-b45c-602a59fb4d6d@intel.com> (raw)
In-Reply-To: <20210624154158.GA1629@sdutt-i7>



On 24.06.2021 17:41, Matthew Brost wrote:
> On Thu, Jun 24, 2021 at 03:49:55PM +0200, Michal Wajdeczko wrote:
>>
>>
>> On 24.06.2021 09:04, Matthew Brost wrote:
>>> With the introduction of non-blocking CTBs more than one CTB can be in
>>> flight at a time. Increasing the size of the CTBs should reduce how
>>> often software hits the case where no space is available in the CTB
>>> buffer.
>>>
>>> Cc: John Harrison <john.c.harrison@intel.com>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 11 ++++++++---
>>>  1 file changed, 8 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 07f080ddb9ae..a17215920e58 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -58,11 +58,16 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>>>   *      +--------+-----------------------------------------------+------+
>>>   *
>>>   * Size of each `CT Buffer`_ must be multiple of 4K.
>>> - * As we don't expect too many messages, for now use minimum sizes.
>>> + * We don't expect too many messages in flight at any time, unless we are
>>> + * using the GuC submission. In that case each request requires a minimum
>>> + * 2 dwords which gives us a maximum 256 queue'd requests. Hopefully this
>>> + * enough space to avoid backpressure on the driver. We increase the size
>>> + * of the receive buffer (relative to the send) to ensure a G2H response
>>> + * CTB has a landing spot.
>>>   */
>>>  #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
>>>  #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
>>> -#define CTB_G2H_BUFFER_SIZE	(SZ_4K)
>>> +#define CTB_G2H_BUFFER_SIZE	(4 * CTB_H2G_BUFFER_SIZE)
>>>  
>>>  struct ct_request {
>>>  	struct list_head link;
>>> @@ -641,7 +646,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>>>  	/* beware of buffer wrap case */
>>>  	if (unlikely(available < 0))
>>>  		available += size;
>>> -	CT_DEBUG(ct, "available %d (%u:%u)\n", available, head, tail);
>>> +	CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
>>
>> CTB size is already printed in intel_guc_ct_init() and is fixed so not
>> sure if repeating it on every ct_read has any benefit
>>
> 
> I'd say more debug the better and if CT_DEBUG is enabled the logs are
> very verbose so an extra value doesn't really hurt.

fair, but this doesn't mean we should add little/no value item, anyway
since DEBUG_GUC is if off by default, this is:

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

> 
> Matt
> 
>>>  	GEM_BUG_ON(available < 0);
>>>  
>>>  	header = cmds[head];
>>>

WARNING: multiple messages have this Message-ID (diff)
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers
Date: Fri, 25 Jun 2021 14:03:39 +0200	[thread overview]
Message-ID: <5264ef27-efbd-1adf-b45c-602a59fb4d6d@intel.com> (raw)
In-Reply-To: <20210624154158.GA1629@sdutt-i7>



On 24.06.2021 17:41, Matthew Brost wrote:
> On Thu, Jun 24, 2021 at 03:49:55PM +0200, Michal Wajdeczko wrote:
>>
>>
>> On 24.06.2021 09:04, Matthew Brost wrote:
>>> With the introduction of non-blocking CTBs more than one CTB can be in
>>> flight at a time. Increasing the size of the CTBs should reduce how
>>> often software hits the case where no space is available in the CTB
>>> buffer.
>>>
>>> Cc: John Harrison <john.c.harrison@intel.com>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 11 ++++++++---
>>>  1 file changed, 8 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> index 07f080ddb9ae..a17215920e58 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>>> @@ -58,11 +58,16 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct)
>>>   *      +--------+-----------------------------------------------+------+
>>>   *
>>>   * Size of each `CT Buffer`_ must be multiple of 4K.
>>> - * As we don't expect too many messages, for now use minimum sizes.
>>> + * We don't expect too many messages in flight at any time, unless we are
>>> + * using the GuC submission. In that case each request requires a minimum
>>> + * 2 dwords which gives us a maximum 256 queue'd requests. Hopefully this
>>> + * enough space to avoid backpressure on the driver. We increase the size
>>> + * of the receive buffer (relative to the send) to ensure a G2H response
>>> + * CTB has a landing spot.
>>>   */
>>>  #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
>>>  #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
>>> -#define CTB_G2H_BUFFER_SIZE	(SZ_4K)
>>> +#define CTB_G2H_BUFFER_SIZE	(4 * CTB_H2G_BUFFER_SIZE)
>>>  
>>>  struct ct_request {
>>>  	struct list_head link;
>>> @@ -641,7 +646,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg)
>>>  	/* beware of buffer wrap case */
>>>  	if (unlikely(available < 0))
>>>  		available += size;
>>> -	CT_DEBUG(ct, "available %d (%u:%u)\n", available, head, tail);
>>> +	CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size);
>>
>> CTB size is already printed in intel_guc_ct_init() and is fixed so not
>> sure if repeating it on every ct_read has any benefit
>>
> 
> I'd say more debug the better and if CT_DEBUG is enabled the logs are
> very verbose so an extra value doesn't really hurt.

fair, but this doesn't mean we should add little/no value item, anyway
since DEBUG_GUC is if off by default, this is:

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

> 
> Matt
> 
>>>  	GEM_BUG_ON(available < 0);
>>>  
>>>  	header = cmds[head];
>>>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2021-06-25 12:03 UTC|newest]

Thread overview: 336+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24  7:04 [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24  7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 17:23   ` Michal Wajdeczko
2021-06-24 17:23     ` [Intel-gfx] " Michal Wajdeczko
2021-06-24  7:04 ` [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 11:58   ` Michal Wajdeczko
2021-06-25 11:58     ` Michal Wajdeczko
2021-06-24  7:04 ` [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 13:49   ` Michal Wajdeczko
2021-06-24 13:49     ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 15:41     ` Matthew Brost
2021-06-24 15:41       ` [Intel-gfx] " Matthew Brost
2021-06-25 12:03       ` Michal Wajdeczko [this message]
2021-06-25 12:03         ` Michal Wajdeczko
2021-06-24  7:04 ` [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 14:48   ` Michal Wajdeczko
2021-06-24 14:48     ` Michal Wajdeczko
2021-06-24 15:49     ` Matthew Brost
2021-06-24 15:49       ` Matthew Brost
2021-06-24 17:02       ` Michal Wajdeczko
2021-06-24 17:02         ` Michal Wajdeczko
2021-06-24 22:41         ` Matthew Brost
2021-06-24 22:41           ` Matthew Brost
2021-06-25 11:50           ` Michal Wajdeczko
2021-06-25 11:50             ` Michal Wajdeczko
2021-06-25 17:53             ` Matthew Brost
2021-06-25 17:53               ` Matthew Brost
2021-06-24 22:47         ` Matthew Brost
2021-06-24 22:47           ` Matthew Brost
2021-06-24  7:04 ` [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24 17:37   ` Michal Wajdeczko
2021-06-24 17:37     ` Michal Wajdeczko
2021-06-24 23:01     ` Matthew Brost
2021-06-24 23:01       ` Matthew Brost
2021-06-24  7:04 ` [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 13:09   ` Michal Wajdeczko
2021-06-25 13:09     ` Michal Wajdeczko
2021-06-25 18:26     ` Matthew Brost
2021-06-25 18:26       ` Matthew Brost
2021-06-25 20:28     ` Matthew Brost
2021-06-25 20:28       ` Matthew Brost
2021-06-24  7:04 ` [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-29 21:11   ` John Harrison
2021-06-29 21:11     ` [Intel-gfx] " John Harrison
2021-06-30  0:30     ` Matthew Brost
2021-06-30  0:30       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 19:44   ` John Harrison
2021-06-25 19:44     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 13:17   ` Michal Wajdeczko
2021-06-25 13:17     ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 17:26     ` Matthew Brost
2021-06-25 17:26       ` [Intel-gfx] " Matthew Brost
2021-06-29 21:20       ` John Harrison
2021-06-29 21:20         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-29 22:04   ` John Harrison
2021-06-29 22:04     ` [Intel-gfx] " John Harrison
2021-06-30  0:41     ` Matthew Brost
2021-06-30  0:41       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-29 22:09   ` John Harrison
2021-06-29 22:09     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-06-25 13:25   ` Michal Wajdeczko
2021-06-25 13:25     ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 17:46     ` Matthew Brost
2021-06-25 17:46       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:39   ` John Harrison
2021-07-09 22:39     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:48   ` John Harrison
2021-07-09 22:48     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:53   ` John Harrison
2021-07-09 22:53     ` [Intel-gfx] " John Harrison
2021-07-10  3:00     ` Matthew Brost
2021-07-10  3:00       ` [Intel-gfx] " Matthew Brost
2021-07-12 17:57       ` John Harrison
2021-07-12 17:57         ` [Intel-gfx] " John Harrison
2021-07-12 18:11         ` Daniel Vetter
2021-07-12 18:11           ` Daniel Vetter
2021-06-24  7:04 ` [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 22:59   ` John Harrison
2021-07-09 22:59     ` [Intel-gfx] " John Harrison
2021-07-10  3:36     ` Matthew Brost
2021-07-10  3:36       ` [Intel-gfx] " Matthew Brost
2021-07-12 17:54       ` John Harrison
2021-07-12 17:54         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 23:03   ` John Harrison
2021-07-09 23:03     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-15  1:51   ` Daniele Ceraolo Spurio
2021-07-15  1:51     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-24  7:04 ` [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-09 23:53   ` John Harrison
2021-07-09 23:53     ` [Intel-gfx] " John Harrison
2021-07-15  0:07     ` Matthew Brost
2021-07-15  0:07       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-13 18:36   ` John Harrison
2021-07-13 18:36     ` [Intel-gfx] " John Harrison
2021-07-15  0:06     ` Matthew Brost
2021-07-15  0:06       ` [Intel-gfx] " Matthew Brost
2021-07-15  0:12       ` John Harrison
2021-07-15  0:12         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-10  0:16   ` John Harrison
2021-07-10  0:16     ` [Intel-gfx] " John Harrison
2021-07-10  3:55     ` Matthew Brost
2021-07-10  3:55       ` [Intel-gfx] " Matthew Brost
2021-07-17  4:09       ` Matthew Brost
2021-07-17  4:09         ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:05   ` John Harrison
2021-07-12 18:05     ` [Intel-gfx] " John Harrison
2021-07-12 20:59     ` Matthew Brost
2021-07-12 20:59       ` [Intel-gfx] " Matthew Brost
2021-07-12 21:37       ` John Harrison
2021-07-12 21:37         ` [Intel-gfx] " John Harrison
2021-07-13  8:51   ` Michal Wajdeczko
2021-07-13  8:51     ` [Intel-gfx] " Michal Wajdeczko
2021-07-14 23:56     ` Matthew Brost
2021-07-14 23:56       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:08   ` John Harrison
2021-07-12 18:08     ` [Intel-gfx] " John Harrison
2021-07-13  9:06   ` Tvrtko Ursulin
2021-07-13  9:06     ` Tvrtko Ursulin
2021-07-20  1:59     ` Matthew Brost
2021-07-20  1:59       ` Matthew Brost
2021-07-22 13:55       ` Tvrtko Ursulin
2021-07-22 13:55         ` Tvrtko Ursulin
2021-06-24  7:04 ` [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:10   ` John Harrison
2021-07-12 18:10     ` [Intel-gfx] " John Harrison
2021-07-12 21:47     ` Matthew Brost
2021-07-12 21:47       ` [Intel-gfx] " Matthew Brost
2021-07-12 21:51       ` John Harrison
2021-07-12 21:51         ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-15  1:21   ` Daniele Ceraolo Spurio
2021-07-15  1:21     ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-24  7:04 ` [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:11   ` John Harrison
2021-07-12 18:11     ` [Intel-gfx] " John Harrison
2021-07-12 20:06     ` Matthew Brost
2021-07-12 20:06       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:04 ` [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-07-12 18:23     ` [Intel-gfx] " John Harrison
2021-07-12 20:05     ` Matthew Brost
2021-07-12 20:05       ` [Intel-gfx] " Matthew Brost
2021-07-12 21:36       ` Matthew Brost
2021-07-12 21:36         ` Matthew Brost
2021-07-12 21:48         ` John Harrison
2021-07-12 21:48           ` John Harrison
2021-06-24  7:04 ` [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 18:23   ` John Harrison
2021-07-12 18:23     ` [Intel-gfx] " John Harrison
2021-06-24  7:04 ` [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-06-24  7:04   ` [Intel-gfx] " Matthew Brost
2021-07-12 19:19   ` John Harrison
2021-07-12 19:19     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 19:58   ` John Harrison
2021-07-12 19:58     ` [Intel-gfx] " John Harrison
2021-07-15  0:53     ` Matthew Brost
2021-07-15  0:53       ` [Intel-gfx] " Matthew Brost
2021-07-15  9:36   ` Tvrtko Ursulin
2021-07-15  9:36     ` Tvrtko Ursulin
2021-07-26 22:48     ` Matthew Brost
2021-07-26 22:48       ` Matthew Brost
2021-07-27  8:56       ` Tvrtko Ursulin
2021-07-27  8:56         ` Tvrtko Ursulin
2021-07-27 18:30         ` Matthew Brost
2021-07-27 18:30           ` Matthew Brost
2021-06-24  7:05 ` [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 20:01   ` John Harrison
2021-07-12 20:01     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 20:11   ` John Harrison
2021-07-12 20:11     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 22:56   ` John Harrison
2021-07-12 22:56     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 22:58   ` John Harrison
2021-07-12 22:58     ` [Intel-gfx] " John Harrison
2021-07-15  0:32     ` Matthew Brost
2021-07-15  0:32       ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 22:59   ` John Harrison
2021-07-12 22:59     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 23:00   ` John Harrison
2021-07-12 23:00     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24 15:55   ` Matthew Brost
2021-06-24 15:55     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24 16:19   ` Matthew Brost
2021-06-24 16:19     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-12 23:05   ` John Harrison
2021-07-12 23:05     ` [Intel-gfx] " John Harrison
2021-06-24  7:05 ` [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-07-15  0:43   ` Matthew Brost
2021-07-15  0:43     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-25  0:59   ` Matthew Brost
2021-06-25  0:59     ` Matthew Brost
2021-06-25 19:10     ` John Harrison
2021-06-25 19:10       ` John Harrison
2021-07-10 18:56       ` Matthew Brost
2021-07-10 18:56         ` Matthew Brost
2021-06-24  7:05 ` [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-25  1:10   ` Matthew Brost
2021-06-25  1:10     ` Matthew Brost
2021-06-24  7:05 ` [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24 16:34   ` Matthew Brost
2021-06-24 16:34     ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-24  7:05 ` [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-24  7:05   ` [Intel-gfx] " Matthew Brost
2021-06-30  8:22   ` Martin Peres
2021-06-30  8:22     ` [Intel-gfx] " Martin Peres
2021-06-30 18:00     ` Matthew Brost
2021-06-30 18:00       ` [Intel-gfx] " Matthew Brost
2021-07-01 18:24       ` Martin Peres
2021-07-01 18:24         ` [Intel-gfx] " Martin Peres
2021-07-02  8:13         ` Martin Peres
2021-07-02  8:13           ` [Intel-gfx] " Martin Peres
2021-07-02 13:06           ` Michal Wajdeczko
2021-07-02 13:06             ` [Intel-gfx] " Michal Wajdeczko
2021-07-02 13:12             ` Martin Peres
2021-07-02 13:12               ` [Intel-gfx] " Martin Peres
2021-07-02 14:08               ` Michal Wajdeczko
2021-07-02 14:08                 ` [Intel-gfx] " Michal Wajdeczko
2021-06-30 18:58     ` John Harrison
2021-06-30 18:58       ` [Intel-gfx] " John Harrison
2021-07-01  8:14       ` Pekka Paalanen
2021-07-01  8:14         ` [Intel-gfx] " Pekka Paalanen
2021-07-01 18:27         ` Martin Peres
2021-07-01 18:27           ` [Intel-gfx] " Martin Peres
2021-07-01 19:28           ` Daniel Vetter
2021-07-01 19:28             ` Daniel Vetter
2021-07-02  7:29             ` Pekka Paalanen
2021-07-02  7:29               ` Pekka Paalanen
2021-07-02  8:09               ` Martin Peres
2021-07-02  8:09                 ` Martin Peres
2021-07-02 15:07                 ` Michal Wajdeczko
2021-07-02 15:07                   ` Michal Wajdeczko
2021-07-03  8:21                   ` Martin Peres
2021-07-03  8:21                     ` Martin Peres
2021-07-07  0:57                     ` John Harrison
2021-07-07  0:57                       ` John Harrison
2021-07-07  7:47                       ` Pekka Paalanen
2021-07-07  7:47                         ` Pekka Paalanen
2021-07-07 10:11                       ` Michal Wajdeczko
2021-07-07 10:11                         ` Michal Wajdeczko
2021-07-15  0:49   ` Matthew Brost
2021-07-15  0:49     ` Matthew Brost
2021-06-24  7:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support Patchwork
2021-06-24  7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-24  7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22  9:35 ` [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22  9:35   ` [Intel-gfx] " Joonas Lahtinen
2021-10-22 16:42   ` Matthew Brost
2021-10-22 16:42     ` [Intel-gfx] " Matthew Brost
2021-10-25  9:37     ` Joonas Lahtinen
2021-10-25  9:37       ` [Intel-gfx] " Joonas Lahtinen
2021-10-25 15:15       ` Matthew Brost
2021-10-25 15:15         ` [Intel-gfx] " Matthew Brost
2021-10-26  8:59         ` Joonas Lahtinen
2021-10-26  8:59           ` [Intel-gfx] " Joonas Lahtinen
2021-10-26 15:43           ` Matthew Brost
2021-10-26 15:43             ` [Intel-gfx] " Matthew Brost
2021-10-26 15:51           ` Matthew Brost
2021-10-26 15:51             ` [Intel-gfx] " Matthew Brost
2021-10-27  9:21             ` Joonas Lahtinen
2021-10-27  9:21               ` [Intel-gfx] " Joonas Lahtinen
2021-10-25 17:06       ` John Harrison
2021-10-25 17:06         ` [Intel-gfx] " John Harrison

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