From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org, daniele.ceraolospurio@intel.com,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 25/47] drm/i915: Add intel_context tracing
Date: Mon, 12 Jul 2021 14:51:45 -0700 [thread overview]
Message-ID: <402382b2-79e5-8c2d-ea33-d0bff82163fc@intel.com> (raw)
In-Reply-To: <20210712214736.GA15781@DUT181-TGLU.fm.intel.com>
On 7/12/2021 14:47, Matthew Brost wrote:
> On Mon, Jul 12, 2021 at 11:10:40AM -0700, John Harrison wrote:
>> On 6/24/2021 00:04, Matthew Brost wrote:
>>> Add intel_context tracing. These trace points are particular helpful
>>> when debugging the GuC firmware and can be enabled via
>>> CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
>>>
>>> Cc: John Harrison <john.c.harrison@intel.com>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_context.c | 6 +
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++
>>> drivers/gpu/drm/i915/i915_trace.h | 148 +++++++++++++++++-
>>> 3 files changed, 166 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
>>> index 7f97753ab164..b24a1b7a3f88 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_context.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
>>> @@ -8,6 +8,7 @@
>>> #include "i915_drv.h"
>>> #include "i915_globals.h"
>>> +#include "i915_trace.h"
>>> #include "intel_context.h"
>>> #include "intel_engine.h"
>>> @@ -28,6 +29,7 @@ static void rcu_context_free(struct rcu_head *rcu)
>>> {
>>> struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
>>> + trace_intel_context_free(ce);
>>> kmem_cache_free(global.slab_ce, ce);
>>> }
>>> @@ -46,6 +48,7 @@ intel_context_create(struct intel_engine_cs *engine)
>>> return ERR_PTR(-ENOMEM);
>>> intel_context_init(ce, engine);
>>> + trace_intel_context_create(ce);
>>> return ce;
>>> }
>>> @@ -268,6 +271,8 @@ int __intel_context_do_pin_ww(struct intel_context *ce,
>>> GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
>>> + trace_intel_context_do_pin(ce);
>>> +
>>> err_unlock:
>>> mutex_unlock(&ce->pin_mutex);
>>> err_post_unpin:
>>> @@ -323,6 +328,7 @@ void __intel_context_do_unpin(struct intel_context *ce, int sub)
>>> */
>>> intel_context_get(ce);
>>> intel_context_active_release(ce);
>>> + trace_intel_context_do_unpin(ce);
>>> intel_context_put(ce);
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> index c2327eebc09c..d605af0d66e6 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> @@ -348,6 +348,7 @@ static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>>> err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
>>> if (!enabled && !err) {
>>> + trace_intel_context_sched_enable(ce);
>>> atomic_inc(&guc->outstanding_submission_g2h);
>>> set_context_enabled(ce);
>>> } else if (!enabled) {
>>> @@ -812,6 +813,8 @@ static int register_context(struct intel_context *ce)
>>> u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool) +
>>> ce->guc_id * sizeof(struct guc_lrc_desc);
>>> + trace_intel_context_register(ce);
>>> +
>>> return __guc_action_register_context(guc, ce->guc_id, offset);
>>> }
>>> @@ -831,6 +834,8 @@ static int deregister_context(struct intel_context *ce, u32 guc_id)
>>> {
>>> struct intel_guc *guc = ce_to_guc(ce);
>>> + trace_intel_context_deregister(ce);
>>> +
>>> return __guc_action_deregister_context(guc, guc_id);
>>> }
>>> @@ -905,6 +910,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce)
>>> * GuC before registering this context.
>>> */
>>> if (context_registered) {
>>> + trace_intel_context_steal_guc_id(ce);
>>> set_context_wait_for_deregister_to_register(ce);
>>> intel_context_get(ce);
>>> @@ -963,6 +969,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
>>> GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
>>> + trace_intel_context_sched_disable(ce);
>>> intel_context_get(ce);
>>> guc_submission_busy_loop(guc, action, ARRAY_SIZE(action),
>>> @@ -1119,6 +1126,9 @@ static void __guc_signal_context_fence(struct intel_context *ce)
>>> lockdep_assert_held(&ce->guc_state.lock);
>>> + if (!list_empty(&ce->guc_state.fences))
>>> + trace_intel_context_fence_release(ce);
>>> +
>>> list_for_each_entry(rq, &ce->guc_state.fences, guc_fence_link)
>>> i915_sw_fence_complete(&rq->submit);
>>> @@ -1529,6 +1539,8 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
>>> if (unlikely(!ce))
>>> return -EPROTO;
>>> + trace_intel_context_deregister_done(ce);
>>> +
>>> if (context_wait_for_deregister_to_register(ce)) {
>>> struct intel_runtime_pm *runtime_pm =
>>> &ce->engine->gt->i915->runtime_pm;
>>> @@ -1580,6 +1592,8 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
>>> return -EPROTO;
>>> }
>>> + trace_intel_context_sched_done(ce);
>>> +
>>> if (context_pending_enable(ce)) {
>>> clr_context_pending_enable(ce);
>>> } else if (context_pending_disable(ce)) {
>>> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
>>> index b02d04b6c8f6..97c2e83984ed 100644
>>> --- a/drivers/gpu/drm/i915/i915_trace.h
>>> +++ b/drivers/gpu/drm/i915/i915_trace.h
>>> @@ -818,8 +818,8 @@ DECLARE_EVENT_CLASS(i915_request,
>>> );
>>> DEFINE_EVENT(i915_request, i915_request_add,
>>> - TP_PROTO(struct i915_request *rq),
>>> - TP_ARGS(rq)
>>> + TP_PROTO(struct i915_request *rq),
>>> + TP_ARGS(rq)
>> Is this an intentional white space change?
>>
> Yea, probably should be in the previous patch though. Before this
> change the arguments were misaligned.
>
> Matt
Okay, one can never tell if the alignment is out for reals or just
because the email viewer and/or diff prefixes are playing silly buggers
with tab spacing. And yeah, would make more sense to bump the change
into the request trace point patch. With that done...
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
>
>>> );
>>> #if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
>>> @@ -905,6 +905,90 @@ TRACE_EVENT(i915_request_out,
>>> __entry->ctx, __entry->seqno, __entry->completed)
>>> );
>>> +DECLARE_EVENT_CLASS(intel_context,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce),
>>> +
>>> + TP_STRUCT__entry(
>>> + __field(u32, guc_id)
>>> + __field(int, pin_count)
>>> + __field(u32, sched_state)
>>> + __field(u32, guc_sched_state_no_lock)
>>> + ),
>>> +
>>> + TP_fast_assign(
>>> + __entry->guc_id = ce->guc_id;
>>> + __entry->pin_count = atomic_read(&ce->pin_count);
>>> + __entry->sched_state = ce->guc_state.sched_state;
>>> + __entry->guc_sched_state_no_lock =
>>> + atomic_read(&ce->guc_sched_state_no_lock);
>>> + ),
>>> +
>>> + TP_printk("guc_id=%d, pin_count=%d sched_state=0x%x,0x%x",
>>> + __entry->guc_id, __entry->pin_count, __entry->sched_state,
>>> + __entry->guc_sched_state_no_lock)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_register,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_deregister,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_deregister_done,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_sched_enable,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_sched_disable,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_sched_done,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_create,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_fence_release,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_free,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_steal_guc_id,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_do_pin,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_do_unpin,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> #else
>>> #if !defined(TRACE_HEADER_MULTI_READ)
>>> static inline void
>>> @@ -941,6 +1025,66 @@ static inline void
>>> trace_i915_request_out(struct i915_request *rq)
>>> {
>>> }
>>> +
>>> +static inline void
>>> +trace_intel_context_register(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_deregister(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_deregister_done(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_sched_enable(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_sched_disable(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_sched_done(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_create(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_fence_release(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_free(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_steal_guc_id(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_do_pin(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_do_unpin(struct intel_context *ce)
>>> +{
>>> +}
>>> #endif
>>> #endif
WARNING: multiple messages have this Message-ID (diff)
From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 25/47] drm/i915: Add intel_context tracing
Date: Mon, 12 Jul 2021 14:51:45 -0700 [thread overview]
Message-ID: <402382b2-79e5-8c2d-ea33-d0bff82163fc@intel.com> (raw)
In-Reply-To: <20210712214736.GA15781@DUT181-TGLU.fm.intel.com>
On 7/12/2021 14:47, Matthew Brost wrote:
> On Mon, Jul 12, 2021 at 11:10:40AM -0700, John Harrison wrote:
>> On 6/24/2021 00:04, Matthew Brost wrote:
>>> Add intel_context tracing. These trace points are particular helpful
>>> when debugging the GuC firmware and can be enabled via
>>> CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
>>>
>>> Cc: John Harrison <john.c.harrison@intel.com>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_context.c | 6 +
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 ++
>>> drivers/gpu/drm/i915/i915_trace.h | 148 +++++++++++++++++-
>>> 3 files changed, 166 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
>>> index 7f97753ab164..b24a1b7a3f88 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_context.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
>>> @@ -8,6 +8,7 @@
>>> #include "i915_drv.h"
>>> #include "i915_globals.h"
>>> +#include "i915_trace.h"
>>> #include "intel_context.h"
>>> #include "intel_engine.h"
>>> @@ -28,6 +29,7 @@ static void rcu_context_free(struct rcu_head *rcu)
>>> {
>>> struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
>>> + trace_intel_context_free(ce);
>>> kmem_cache_free(global.slab_ce, ce);
>>> }
>>> @@ -46,6 +48,7 @@ intel_context_create(struct intel_engine_cs *engine)
>>> return ERR_PTR(-ENOMEM);
>>> intel_context_init(ce, engine);
>>> + trace_intel_context_create(ce);
>>> return ce;
>>> }
>>> @@ -268,6 +271,8 @@ int __intel_context_do_pin_ww(struct intel_context *ce,
>>> GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
>>> + trace_intel_context_do_pin(ce);
>>> +
>>> err_unlock:
>>> mutex_unlock(&ce->pin_mutex);
>>> err_post_unpin:
>>> @@ -323,6 +328,7 @@ void __intel_context_do_unpin(struct intel_context *ce, int sub)
>>> */
>>> intel_context_get(ce);
>>> intel_context_active_release(ce);
>>> + trace_intel_context_do_unpin(ce);
>>> intel_context_put(ce);
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> index c2327eebc09c..d605af0d66e6 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> @@ -348,6 +348,7 @@ static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>>> err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
>>> if (!enabled && !err) {
>>> + trace_intel_context_sched_enable(ce);
>>> atomic_inc(&guc->outstanding_submission_g2h);
>>> set_context_enabled(ce);
>>> } else if (!enabled) {
>>> @@ -812,6 +813,8 @@ static int register_context(struct intel_context *ce)
>>> u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool) +
>>> ce->guc_id * sizeof(struct guc_lrc_desc);
>>> + trace_intel_context_register(ce);
>>> +
>>> return __guc_action_register_context(guc, ce->guc_id, offset);
>>> }
>>> @@ -831,6 +834,8 @@ static int deregister_context(struct intel_context *ce, u32 guc_id)
>>> {
>>> struct intel_guc *guc = ce_to_guc(ce);
>>> + trace_intel_context_deregister(ce);
>>> +
>>> return __guc_action_deregister_context(guc, guc_id);
>>> }
>>> @@ -905,6 +910,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce)
>>> * GuC before registering this context.
>>> */
>>> if (context_registered) {
>>> + trace_intel_context_steal_guc_id(ce);
>>> set_context_wait_for_deregister_to_register(ce);
>>> intel_context_get(ce);
>>> @@ -963,6 +969,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
>>> GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
>>> + trace_intel_context_sched_disable(ce);
>>> intel_context_get(ce);
>>> guc_submission_busy_loop(guc, action, ARRAY_SIZE(action),
>>> @@ -1119,6 +1126,9 @@ static void __guc_signal_context_fence(struct intel_context *ce)
>>> lockdep_assert_held(&ce->guc_state.lock);
>>> + if (!list_empty(&ce->guc_state.fences))
>>> + trace_intel_context_fence_release(ce);
>>> +
>>> list_for_each_entry(rq, &ce->guc_state.fences, guc_fence_link)
>>> i915_sw_fence_complete(&rq->submit);
>>> @@ -1529,6 +1539,8 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
>>> if (unlikely(!ce))
>>> return -EPROTO;
>>> + trace_intel_context_deregister_done(ce);
>>> +
>>> if (context_wait_for_deregister_to_register(ce)) {
>>> struct intel_runtime_pm *runtime_pm =
>>> &ce->engine->gt->i915->runtime_pm;
>>> @@ -1580,6 +1592,8 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
>>> return -EPROTO;
>>> }
>>> + trace_intel_context_sched_done(ce);
>>> +
>>> if (context_pending_enable(ce)) {
>>> clr_context_pending_enable(ce);
>>> } else if (context_pending_disable(ce)) {
>>> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
>>> index b02d04b6c8f6..97c2e83984ed 100644
>>> --- a/drivers/gpu/drm/i915/i915_trace.h
>>> +++ b/drivers/gpu/drm/i915/i915_trace.h
>>> @@ -818,8 +818,8 @@ DECLARE_EVENT_CLASS(i915_request,
>>> );
>>> DEFINE_EVENT(i915_request, i915_request_add,
>>> - TP_PROTO(struct i915_request *rq),
>>> - TP_ARGS(rq)
>>> + TP_PROTO(struct i915_request *rq),
>>> + TP_ARGS(rq)
>> Is this an intentional white space change?
>>
> Yea, probably should be in the previous patch though. Before this
> change the arguments were misaligned.
>
> Matt
Okay, one can never tell if the alignment is out for reals or just
because the email viewer and/or diff prefixes are playing silly buggers
with tab spacing. And yeah, would make more sense to bump the change
into the request trace point patch. With that done...
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
>
>>> );
>>> #if defined(CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS)
>>> @@ -905,6 +905,90 @@ TRACE_EVENT(i915_request_out,
>>> __entry->ctx, __entry->seqno, __entry->completed)
>>> );
>>> +DECLARE_EVENT_CLASS(intel_context,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce),
>>> +
>>> + TP_STRUCT__entry(
>>> + __field(u32, guc_id)
>>> + __field(int, pin_count)
>>> + __field(u32, sched_state)
>>> + __field(u32, guc_sched_state_no_lock)
>>> + ),
>>> +
>>> + TP_fast_assign(
>>> + __entry->guc_id = ce->guc_id;
>>> + __entry->pin_count = atomic_read(&ce->pin_count);
>>> + __entry->sched_state = ce->guc_state.sched_state;
>>> + __entry->guc_sched_state_no_lock =
>>> + atomic_read(&ce->guc_sched_state_no_lock);
>>> + ),
>>> +
>>> + TP_printk("guc_id=%d, pin_count=%d sched_state=0x%x,0x%x",
>>> + __entry->guc_id, __entry->pin_count, __entry->sched_state,
>>> + __entry->guc_sched_state_no_lock)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_register,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_deregister,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_deregister_done,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_sched_enable,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_sched_disable,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_sched_done,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_create,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_fence_release,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_free,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_steal_guc_id,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_do_pin,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> +DEFINE_EVENT(intel_context, intel_context_do_unpin,
>>> + TP_PROTO(struct intel_context *ce),
>>> + TP_ARGS(ce)
>>> +);
>>> +
>>> #else
>>> #if !defined(TRACE_HEADER_MULTI_READ)
>>> static inline void
>>> @@ -941,6 +1025,66 @@ static inline void
>>> trace_i915_request_out(struct i915_request *rq)
>>> {
>>> }
>>> +
>>> +static inline void
>>> +trace_intel_context_register(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_deregister(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_deregister_done(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_sched_enable(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_sched_disable(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_sched_done(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_create(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_fence_release(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_free(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_steal_guc_id(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_do_pin(struct intel_context *ce)
>>> +{
>>> +}
>>> +
>>> +static inline void
>>> +trace_intel_context_do_unpin(struct intel_context *ce)
>>> +{
>>> +}
>>> #endif
>>> #endif
_______________________________________________
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next prev parent reply other threads:[~2021-07-12 21:51 UTC|newest]
Thread overview: 336+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 7:04 [PATCH 00/47] GuC submission support Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 01/47] drm/i915/guc: Relax CTB response timeout Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24 17:23 ` Michal Wajdeczko
2021-06-24 17:23 ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 7:04 ` [PATCH 02/47] drm/i915/guc: Improve error message for unsolicited CT response Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-25 11:58 ` Michal Wajdeczko
2021-06-25 11:58 ` Michal Wajdeczko
2021-06-24 7:04 ` [PATCH 03/47] drm/i915/guc: Increase size of CTB buffers Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24 13:49 ` Michal Wajdeczko
2021-06-24 13:49 ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 15:41 ` Matthew Brost
2021-06-24 15:41 ` [Intel-gfx] " Matthew Brost
2021-06-25 12:03 ` Michal Wajdeczko
2021-06-25 12:03 ` [Intel-gfx] " Michal Wajdeczko
2021-06-24 7:04 ` [PATCH 04/47] drm/i915/guc: Add non blocking CTB send function Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24 14:48 ` Michal Wajdeczko
2021-06-24 14:48 ` Michal Wajdeczko
2021-06-24 15:49 ` Matthew Brost
2021-06-24 15:49 ` Matthew Brost
2021-06-24 17:02 ` Michal Wajdeczko
2021-06-24 17:02 ` Michal Wajdeczko
2021-06-24 22:41 ` Matthew Brost
2021-06-24 22:41 ` Matthew Brost
2021-06-25 11:50 ` Michal Wajdeczko
2021-06-25 11:50 ` Michal Wajdeczko
2021-06-25 17:53 ` Matthew Brost
2021-06-25 17:53 ` Matthew Brost
2021-06-24 22:47 ` Matthew Brost
2021-06-24 22:47 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 05/47] drm/i915/guc: Add stall timer to " Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24 17:37 ` Michal Wajdeczko
2021-06-24 17:37 ` Michal Wajdeczko
2021-06-24 23:01 ` Matthew Brost
2021-06-24 23:01 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 06/47] drm/i915/guc: Optimize CTB writes and reads Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-25 13:09 ` Michal Wajdeczko
2021-06-25 13:09 ` Michal Wajdeczko
2021-06-25 18:26 ` Matthew Brost
2021-06-25 18:26 ` Matthew Brost
2021-06-25 20:28 ` Matthew Brost
2021-06-25 20:28 ` Matthew Brost
2021-06-24 7:04 ` [PATCH 07/47] drm/i915/guc: Module load failure test for CT buffer creation Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 08/47] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-29 21:11 ` John Harrison
2021-06-29 21:11 ` [Intel-gfx] " John Harrison
2021-06-30 0:30 ` Matthew Brost
2021-06-30 0:30 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 09/47] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-25 19:44 ` John Harrison
2021-06-25 19:44 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 10/47] drm/i915/guc: Add lrc descriptor context lookup array Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-25 13:17 ` Michal Wajdeczko
2021-06-25 13:17 ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 17:26 ` Matthew Brost
2021-06-25 17:26 ` [Intel-gfx] " Matthew Brost
2021-06-29 21:20 ` John Harrison
2021-06-29 21:20 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 11/47] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-29 22:04 ` John Harrison
2021-06-29 22:04 ` [Intel-gfx] " John Harrison
2021-06-30 0:41 ` Matthew Brost
2021-06-30 0:41 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 12/47] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-29 22:09 ` John Harrison
2021-06-29 22:09 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 13/47] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-06-25 13:25 ` Michal Wajdeczko
2021-06-25 13:25 ` [Intel-gfx] " Michal Wajdeczko
2021-06-25 17:46 ` Matthew Brost
2021-06-25 17:46 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 14/47] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-09 22:39 ` John Harrison
2021-07-09 22:39 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 15/47] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-09 22:48 ` John Harrison
2021-07-09 22:48 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 16/47] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-09 22:53 ` John Harrison
2021-07-09 22:53 ` [Intel-gfx] " John Harrison
2021-07-10 3:00 ` Matthew Brost
2021-07-10 3:00 ` [Intel-gfx] " Matthew Brost
2021-07-12 17:57 ` John Harrison
2021-07-12 17:57 ` [Intel-gfx] " John Harrison
2021-07-12 18:11 ` Daniel Vetter
2021-07-12 18:11 ` Daniel Vetter
2021-06-24 7:04 ` [PATCH 17/47] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-09 22:59 ` John Harrison
2021-07-09 22:59 ` [Intel-gfx] " John Harrison
2021-07-10 3:36 ` Matthew Brost
2021-07-10 3:36 ` [Intel-gfx] " Matthew Brost
2021-07-12 17:54 ` John Harrison
2021-07-12 17:54 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 18/47] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-09 23:03 ` John Harrison
2021-07-09 23:03 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 19/47] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-15 1:51 ` Daniele Ceraolo Spurio
2021-07-15 1:51 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-24 7:04 ` [PATCH 20/47] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-09 23:53 ` John Harrison
2021-07-09 23:53 ` [Intel-gfx] " John Harrison
2021-07-15 0:07 ` Matthew Brost
2021-07-15 0:07 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 21/47] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-13 18:36 ` John Harrison
2021-07-13 18:36 ` [Intel-gfx] " John Harrison
2021-07-15 0:06 ` Matthew Brost
2021-07-15 0:06 ` [Intel-gfx] " Matthew Brost
2021-07-15 0:12 ` John Harrison
2021-07-15 0:12 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 22/47] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-10 0:16 ` John Harrison
2021-07-10 0:16 ` [Intel-gfx] " John Harrison
2021-07-10 3:55 ` Matthew Brost
2021-07-10 3:55 ` [Intel-gfx] " Matthew Brost
2021-07-17 4:09 ` Matthew Brost
2021-07-17 4:09 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 23/47] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 18:05 ` John Harrison
2021-07-12 18:05 ` [Intel-gfx] " John Harrison
2021-07-12 20:59 ` Matthew Brost
2021-07-12 20:59 ` [Intel-gfx] " Matthew Brost
2021-07-12 21:37 ` John Harrison
2021-07-12 21:37 ` [Intel-gfx] " John Harrison
2021-07-13 8:51 ` Michal Wajdeczko
2021-07-13 8:51 ` [Intel-gfx] " Michal Wajdeczko
2021-07-14 23:56 ` Matthew Brost
2021-07-14 23:56 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 24/47] drm/i915/guc: Add several request trace points Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 18:08 ` John Harrison
2021-07-12 18:08 ` [Intel-gfx] " John Harrison
2021-07-13 9:06 ` Tvrtko Ursulin
2021-07-13 9:06 ` Tvrtko Ursulin
2021-07-20 1:59 ` Matthew Brost
2021-07-20 1:59 ` Matthew Brost
2021-07-22 13:55 ` Tvrtko Ursulin
2021-07-22 13:55 ` Tvrtko Ursulin
2021-06-24 7:04 ` [PATCH 25/47] drm/i915: Add intel_context tracing Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 18:10 ` John Harrison
2021-07-12 18:10 ` [Intel-gfx] " John Harrison
2021-07-12 21:47 ` Matthew Brost
2021-07-12 21:47 ` [Intel-gfx] " Matthew Brost
2021-07-12 21:51 ` John Harrison [this message]
2021-07-12 21:51 ` John Harrison
2021-06-24 7:04 ` [PATCH 26/47] drm/i915/guc: GuC virtual engines Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-15 1:21 ` Daniele Ceraolo Spurio
2021-07-15 1:21 ` [Intel-gfx] " Daniele Ceraolo Spurio
2021-06-24 7:04 ` [PATCH 27/47] drm/i915: Track 'serial' counts for " Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 18:11 ` John Harrison
2021-07-12 18:11 ` [Intel-gfx] " John Harrison
2021-07-12 20:06 ` Matthew Brost
2021-07-12 20:06 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:04 ` [PATCH 28/47] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-07-12 18:23 ` [Intel-gfx] " John Harrison
2021-07-12 20:05 ` Matthew Brost
2021-07-12 20:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 21:36 ` Matthew Brost
2021-07-12 21:36 ` Matthew Brost
2021-07-12 21:48 ` John Harrison
2021-07-12 21:48 ` John Harrison
2021-06-24 7:04 ` [PATCH 29/47] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 18:23 ` John Harrison
2021-07-12 18:23 ` [Intel-gfx] " John Harrison
2021-06-24 7:04 ` [PATCH 30/47] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-06-24 7:04 ` [Intel-gfx] " Matthew Brost
2021-07-12 19:19 ` John Harrison
2021-07-12 19:19 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 31/47] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 19:58 ` John Harrison
2021-07-12 19:58 ` [Intel-gfx] " John Harrison
2021-07-15 0:53 ` Matthew Brost
2021-07-15 0:53 ` [Intel-gfx] " Matthew Brost
2021-07-15 9:36 ` Tvrtko Ursulin
2021-07-15 9:36 ` Tvrtko Ursulin
2021-07-26 22:48 ` Matthew Brost
2021-07-26 22:48 ` Matthew Brost
2021-07-27 8:56 ` Tvrtko Ursulin
2021-07-27 8:56 ` Tvrtko Ursulin
2021-07-27 18:30 ` Matthew Brost
2021-07-27 18:30 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 32/47] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 20:01 ` John Harrison
2021-07-12 20:01 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 33/47] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 20:11 ` John Harrison
2021-07-12 20:11 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 34/47] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 22:56 ` John Harrison
2021-07-12 22:56 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 35/47] drm/i915/guc: Handle context reset notification Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 22:58 ` John Harrison
2021-07-12 22:58 ` [Intel-gfx] " John Harrison
2021-07-15 0:32 ` Matthew Brost
2021-07-15 0:32 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 36/47] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 22:59 ` John Harrison
2021-07-12 22:59 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 37/47] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 23:00 ` John Harrison
2021-07-12 23:00 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 38/47] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 39/47] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-24 15:55 ` Matthew Brost
2021-06-24 15:55 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 40/47] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-24 16:19 ` Matthew Brost
2021-06-24 16:19 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 41/47] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-12 23:05 ` John Harrison
2021-07-12 23:05 ` [Intel-gfx] " John Harrison
2021-06-24 7:05 ` [PATCH 42/47] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-07-15 0:43 ` Matthew Brost
2021-07-15 0:43 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 43/47] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-25 0:59 ` Matthew Brost
2021-06-25 0:59 ` Matthew Brost
2021-06-25 19:10 ` John Harrison
2021-06-25 19:10 ` John Harrison
2021-07-10 18:56 ` Matthew Brost
2021-07-10 18:56 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 44/47] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-25 1:10 ` Matthew Brost
2021-06-25 1:10 ` Matthew Brost
2021-06-24 7:05 ` [PATCH 45/47] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-24 16:34 ` Matthew Brost
2021-06-24 16:34 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 46/47] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-24 7:05 ` [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-06-24 7:05 ` [Intel-gfx] " Matthew Brost
2021-06-30 8:22 ` Martin Peres
2021-06-30 8:22 ` [Intel-gfx] " Martin Peres
2021-06-30 18:00 ` Matthew Brost
2021-06-30 18:00 ` [Intel-gfx] " Matthew Brost
2021-07-01 18:24 ` Martin Peres
2021-07-01 18:24 ` [Intel-gfx] " Martin Peres
2021-07-02 8:13 ` Martin Peres
2021-07-02 8:13 ` [Intel-gfx] " Martin Peres
2021-07-02 13:06 ` Michal Wajdeczko
2021-07-02 13:06 ` [Intel-gfx] " Michal Wajdeczko
2021-07-02 13:12 ` Martin Peres
2021-07-02 13:12 ` [Intel-gfx] " Martin Peres
2021-07-02 14:08 ` Michal Wajdeczko
2021-07-02 14:08 ` [Intel-gfx] " Michal Wajdeczko
2021-06-30 18:58 ` John Harrison
2021-06-30 18:58 ` [Intel-gfx] " John Harrison
2021-07-01 8:14 ` Pekka Paalanen
2021-07-01 8:14 ` [Intel-gfx] " Pekka Paalanen
2021-07-01 18:27 ` Martin Peres
2021-07-01 18:27 ` [Intel-gfx] " Martin Peres
2021-07-01 19:28 ` Daniel Vetter
2021-07-01 19:28 ` Daniel Vetter
2021-07-02 7:29 ` Pekka Paalanen
2021-07-02 7:29 ` Pekka Paalanen
2021-07-02 8:09 ` Martin Peres
2021-07-02 8:09 ` Martin Peres
2021-07-02 15:07 ` Michal Wajdeczko
2021-07-02 15:07 ` Michal Wajdeczko
2021-07-03 8:21 ` Martin Peres
2021-07-03 8:21 ` Martin Peres
2021-07-07 0:57 ` John Harrison
2021-07-07 0:57 ` John Harrison
2021-07-07 7:47 ` Pekka Paalanen
2021-07-07 7:47 ` Pekka Paalanen
2021-07-07 10:11 ` Michal Wajdeczko
2021-07-07 10:11 ` Michal Wajdeczko
2021-07-15 0:49 ` Matthew Brost
2021-07-15 0:49 ` Matthew Brost
2021-06-24 7:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission support Patchwork
2021-06-24 7:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-24 7:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-07-12 19:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev2) Patchwork
2021-10-22 9:35 ` [PATCH 00/47] GuC submission support Joonas Lahtinen
2021-10-22 9:35 ` [Intel-gfx] " Joonas Lahtinen
2021-10-22 16:42 ` Matthew Brost
2021-10-22 16:42 ` [Intel-gfx] " Matthew Brost
2021-10-25 9:37 ` Joonas Lahtinen
2021-10-25 9:37 ` [Intel-gfx] " Joonas Lahtinen
2021-10-25 15:15 ` Matthew Brost
2021-10-25 15:15 ` [Intel-gfx] " Matthew Brost
2021-10-26 8:59 ` Joonas Lahtinen
2021-10-26 8:59 ` [Intel-gfx] " Joonas Lahtinen
2021-10-26 15:43 ` Matthew Brost
2021-10-26 15:43 ` [Intel-gfx] " Matthew Brost
2021-10-26 15:51 ` Matthew Brost
2021-10-26 15:51 ` [Intel-gfx] " Matthew Brost
2021-10-27 9:21 ` Joonas Lahtinen
2021-10-27 9:21 ` [Intel-gfx] " Joonas Lahtinen
2021-10-25 17:06 ` John Harrison
2021-10-25 17:06 ` [Intel-gfx] " John Harrison
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