From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 10/37] target/riscv: SIMD 8-bit Multiply Instructions Date: Thu, 24 Jun 2021 18:54:54 +0800 [thread overview] Message-ID: <20210624105521.3964-11-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> There are 6 instructions, including 8-bit signed or unsigned multiply, 8-bit signed or unsigned crossed multiply, Q7 signed or signed crossed saturating multiply. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvp.c.inc | 8 +++ target/riscv/packed_helper.c | 93 +++++++++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d13b84f165..4d0918b9a9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1225,3 +1225,10 @@ DEF_HELPER_3(umul16, i64, env, tl, tl) DEF_HELPER_3(umulx16, i64, env, tl, tl) DEF_HELPER_3(khm16, tl, env, tl, tl) DEF_HELPER_3(khmx16, tl, env, tl, tl) + +DEF_HELPER_3(smul8, i64, env, tl, tl) +DEF_HELPER_3(smulx8, i64, env, tl, tl) +DEF_HELPER_3(umul8, i64, env, tl, tl) +DEF_HELPER_3(umulx8, i64, env, tl, tl) +DEF_HELPER_3(khm8, tl, env, tl, tl) +DEF_HELPER_3(khmx8, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cbee995229..05c3e67477 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -828,3 +828,10 @@ umul16 1011000 ..... ..... 000 ..... 1110111 @r umulx16 1011001 ..... ..... 000 ..... 1110111 @r khm16 1000011 ..... ..... 000 ..... 1110111 @r khmx16 1001011 ..... ..... 000 ..... 1110111 @r + +smul8 1010100 ..... ..... 000 ..... 1110111 @r +smulx8 1010101 ..... ..... 000 ..... 1110111 @r +umul8 1011100 ..... ..... 000 ..... 1110111 @r +umulx8 1011101 ..... ..... 000 ..... 1110111 @r +khm8 1000111 ..... ..... 000 ..... 1110111 @r +khmx8 1001111 ..... ..... 000 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index b93ba63dd8..2188de8505 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -286,3 +286,11 @@ GEN_RVP_R_D64_OOL(umul16); GEN_RVP_R_D64_OOL(umulx16); GEN_RVP_R_OOL(khm16); GEN_RVP_R_OOL(khmx16); + +/* SIMD 8-bit Multiply Instructions */ +GEN_RVP_R_D64_OOL(smul8); +GEN_RVP_R_D64_OOL(smulx8); +GEN_RVP_R_D64_OOL(umul8); +GEN_RVP_R_D64_OOL(umulx8); +GEN_RVP_R_OOL(khm8); +GEN_RVP_R_OOL(khmx8); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 13fed2c4d1..56baefeb8e 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -827,3 +827,96 @@ static inline void do_khmx16(CPURISCVState *env, void *vd, void *va, } RVPR(khmx16, 2, 2); + +/* SIMD 8-bit Multiply Instructions */ +static inline void do_smul8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + int16_t *d = vd; + int8_t *a = va, *b = vb; + d[H2(0)] = (int16_t)a[H1(0)] * b[H1(0)]; + d[H2(1)] = (int16_t)a[H1(1)] * b[H1(1)]; + d[H2(2)] = (int16_t)a[H1(2)] * b[H1(2)]; + d[H2(3)] = (int16_t)a[H1(3)] * b[H1(3)]; +} + +RVPR64(smul8); + +static inline void do_smulx8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + int16_t *d = vd; + int8_t *a = va, *b = vb; + d[H2(0)] = (int16_t)a[H1(0)] * b[H1(1)]; + d[H2(1)] = (int16_t)a[H1(1)] * b[H1(0)]; + d[H2(2)] = (int16_t)a[H1(2)] * b[H1(3)]; + d[H2(3)] = (int16_t)a[H1(3)] * b[H1(2)]; +} + +RVPR64(smulx8); + +static inline void do_umul8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + uint16_t *d = vd; + uint8_t *a = va, *b = vb; + d[H2(0)] = (uint16_t)a[H1(0)] * b[H1(0)]; + d[H2(1)] = (uint16_t)a[H1(1)] * b[H1(1)]; + d[H2(2)] = (uint16_t)a[H1(2)] * b[H1(2)]; + d[H2(3)] = (uint16_t)a[H1(3)] * b[H1(3)]; +} + +RVPR64(umul8); + +static inline void do_umulx8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + uint16_t *d = vd; + uint8_t *a = va, *b = vb; + d[H2(0)] = (uint16_t)a[H1(0)] * b[H1(1)]; + d[H2(1)] = (uint16_t)a[H1(1)] * b[H1(0)]; + d[H2(2)] = (uint16_t)a[H1(2)] * b[H1(3)]; + d[H2(3)] = (uint16_t)a[H1(3)] * b[H1(2)]; +} + +RVPR64(umulx8); + +static inline void do_khm8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + + if (a[i] == INT8_MIN && b[i] == INT8_MIN) { + env->vxsat = 1; + d[i] = INT8_MAX; + } else { + d[i] = (int16_t)a[i] * b[i] >> 7; + } +} + +RVPR(khm8, 1, 1); + +static inline void do_khmx8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + /* + * t[x] = ra.B[x] s* rb.B[y]; + * rt.B[x] = SAT.Q7(t[x] s>> 7); + * + * (RV32: (x,y)=(3,2),(2,3), + * (1,0),(0,1), + * (RV64: (x,y)=(7,6),(6,7),(5,4),(4,5), + * (3,2),(2,3),(1,0),(0,1)) + */ + if (a[H1(i)] == INT8_MIN && b[H1(i + 1)] == INT8_MIN) { + env->vxsat = 1; + d[H1(i)] = INT8_MAX; + } else { + d[H1(i)] = (int16_t)a[H1(i)] * b[H1(i + 1)] >> 7; + } + if (a[H1(i + 1)] == INT8_MIN && b[H1(i)] == INT8_MIN) { + env->vxsat = 1; + d[H1(i + 1)] = INT8_MAX; + } else { + d[H1(i + 1)] = (int16_t)a[H1(i + 1)] * b[H1(i)] >> 7; + } +} + +RVPR(khmx8, 2, 1); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 10/37] target/riscv: SIMD 8-bit Multiply Instructions Date: Thu, 24 Jun 2021 18:54:54 +0800 [thread overview] Message-ID: <20210624105521.3964-11-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> There are 6 instructions, including 8-bit signed or unsigned multiply, 8-bit signed or unsigned crossed multiply, Q7 signed or signed crossed saturating multiply. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvp.c.inc | 8 +++ target/riscv/packed_helper.c | 93 +++++++++++++++++++++++++ 4 files changed, 115 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d13b84f165..4d0918b9a9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1225,3 +1225,10 @@ DEF_HELPER_3(umul16, i64, env, tl, tl) DEF_HELPER_3(umulx16, i64, env, tl, tl) DEF_HELPER_3(khm16, tl, env, tl, tl) DEF_HELPER_3(khmx16, tl, env, tl, tl) + +DEF_HELPER_3(smul8, i64, env, tl, tl) +DEF_HELPER_3(smulx8, i64, env, tl, tl) +DEF_HELPER_3(umul8, i64, env, tl, tl) +DEF_HELPER_3(umulx8, i64, env, tl, tl) +DEF_HELPER_3(khm8, tl, env, tl, tl) +DEF_HELPER_3(khmx8, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cbee995229..05c3e67477 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -828,3 +828,10 @@ umul16 1011000 ..... ..... 000 ..... 1110111 @r umulx16 1011001 ..... ..... 000 ..... 1110111 @r khm16 1000011 ..... ..... 000 ..... 1110111 @r khmx16 1001011 ..... ..... 000 ..... 1110111 @r + +smul8 1010100 ..... ..... 000 ..... 1110111 @r +smulx8 1010101 ..... ..... 000 ..... 1110111 @r +umul8 1011100 ..... ..... 000 ..... 1110111 @r +umulx8 1011101 ..... ..... 000 ..... 1110111 @r +khm8 1000111 ..... ..... 000 ..... 1110111 @r +khmx8 1001111 ..... ..... 000 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index b93ba63dd8..2188de8505 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -286,3 +286,11 @@ GEN_RVP_R_D64_OOL(umul16); GEN_RVP_R_D64_OOL(umulx16); GEN_RVP_R_OOL(khm16); GEN_RVP_R_OOL(khmx16); + +/* SIMD 8-bit Multiply Instructions */ +GEN_RVP_R_D64_OOL(smul8); +GEN_RVP_R_D64_OOL(smulx8); +GEN_RVP_R_D64_OOL(umul8); +GEN_RVP_R_D64_OOL(umulx8); +GEN_RVP_R_OOL(khm8); +GEN_RVP_R_OOL(khmx8); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 13fed2c4d1..56baefeb8e 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -827,3 +827,96 @@ static inline void do_khmx16(CPURISCVState *env, void *vd, void *va, } RVPR(khmx16, 2, 2); + +/* SIMD 8-bit Multiply Instructions */ +static inline void do_smul8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + int16_t *d = vd; + int8_t *a = va, *b = vb; + d[H2(0)] = (int16_t)a[H1(0)] * b[H1(0)]; + d[H2(1)] = (int16_t)a[H1(1)] * b[H1(1)]; + d[H2(2)] = (int16_t)a[H1(2)] * b[H1(2)]; + d[H2(3)] = (int16_t)a[H1(3)] * b[H1(3)]; +} + +RVPR64(smul8); + +static inline void do_smulx8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + int16_t *d = vd; + int8_t *a = va, *b = vb; + d[H2(0)] = (int16_t)a[H1(0)] * b[H1(1)]; + d[H2(1)] = (int16_t)a[H1(1)] * b[H1(0)]; + d[H2(2)] = (int16_t)a[H1(2)] * b[H1(3)]; + d[H2(3)] = (int16_t)a[H1(3)] * b[H1(2)]; +} + +RVPR64(smulx8); + +static inline void do_umul8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + uint16_t *d = vd; + uint8_t *a = va, *b = vb; + d[H2(0)] = (uint16_t)a[H1(0)] * b[H1(0)]; + d[H2(1)] = (uint16_t)a[H1(1)] * b[H1(1)]; + d[H2(2)] = (uint16_t)a[H1(2)] * b[H1(2)]; + d[H2(3)] = (uint16_t)a[H1(3)] * b[H1(3)]; +} + +RVPR64(umul8); + +static inline void do_umulx8(CPURISCVState *env, void *vd, void *va, void *vb) +{ + uint16_t *d = vd; + uint8_t *a = va, *b = vb; + d[H2(0)] = (uint16_t)a[H1(0)] * b[H1(1)]; + d[H2(1)] = (uint16_t)a[H1(1)] * b[H1(0)]; + d[H2(2)] = (uint16_t)a[H1(2)] * b[H1(3)]; + d[H2(3)] = (uint16_t)a[H1(3)] * b[H1(2)]; +} + +RVPR64(umulx8); + +static inline void do_khm8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + + if (a[i] == INT8_MIN && b[i] == INT8_MIN) { + env->vxsat = 1; + d[i] = INT8_MAX; + } else { + d[i] = (int16_t)a[i] * b[i] >> 7; + } +} + +RVPR(khm8, 1, 1); + +static inline void do_khmx8(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int8_t *d = vd, *a = va, *b = vb; + /* + * t[x] = ra.B[x] s* rb.B[y]; + * rt.B[x] = SAT.Q7(t[x] s>> 7); + * + * (RV32: (x,y)=(3,2),(2,3), + * (1,0),(0,1), + * (RV64: (x,y)=(7,6),(6,7),(5,4),(4,5), + * (3,2),(2,3),(1,0),(0,1)) + */ + if (a[H1(i)] == INT8_MIN && b[H1(i + 1)] == INT8_MIN) { + env->vxsat = 1; + d[H1(i)] = INT8_MAX; + } else { + d[H1(i)] = (int16_t)a[H1(i)] * b[H1(i + 1)] >> 7; + } + if (a[H1(i + 1)] == INT8_MIN && b[H1(i)] == INT8_MIN) { + env->vxsat = 1; + d[H1(i + 1)] = INT8_MAX; + } else { + d[H1(i + 1)] = (int16_t)a[H1(i + 1)] * b[H1(i)] >> 7; + } +} + +RVPR(khmx8, 2, 1); -- 2.17.1
next prev parent reply other threads:[~2021-06-24 11:21 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:02 ` Alistair Francis 2021-07-01 2:02 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:08 ` Alistair Francis 2021-07-01 2:08 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei [this message] 2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-24 11:55 ` no-reply 2021-07-01 1:30 ` Alistair Francis 2021-07-01 1:30 ` Alistair Francis 2021-07-01 3:06 ` LIU Zhiwei 2021-07-01 3:06 ` LIU Zhiwei
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