From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions Date: Thu, 24 Jun 2021 18:55:02 +0800 [thread overview] Message-ID: <20210624105521.3964-19-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> "16x16" with 64-bit Signed Addition(64 = 64 + 16x16). Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvp.c.inc | 51 +++++++++++++++++++++++++ target/riscv/packed_helper.c | 25 ++++++++++++ 4 files changed, 80 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5aac6ba578..a37b023c53 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1316,3 +1316,5 @@ DEF_HELPER_4(kmadrs, tl, env, tl, tl, tl) DEF_HELPER_4(kmaxds, tl, env, tl, tl, tl) DEF_HELPER_4(kmsda, tl, env, tl, tl, tl) DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl) + +DEF_HELPER_3(smal, i64, env, i64, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f590880750..233df941b4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -919,3 +919,5 @@ kmadrs 0110110 ..... ..... 001 ..... 1110111 @r kmaxds 0111110 ..... ..... 001 ..... 1110111 @r kmsda 0100110 ..... ..... 001 ..... 1110111 @r kmsxda 0100111 ..... ..... 001 ..... 1110111 @r + +smal 0101111 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 308fc223db..8b0728fc5a 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -451,3 +451,54 @@ GEN_RVP_R_ACC_OOL(kmadrs); GEN_RVP_R_ACC_OOL(kmaxds); GEN_RVP_R_ACC_OOL(kmsda); GEN_RVP_R_ACC_OOL(kmsxda); + +/* Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */ +static bool +r_d64_s64_ool(DisasContext *ctx, arg_r *a, + void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv)) +{ + TCGv src2; + TCGv_i64 src1, dst; + + if (!has_ext(ctx, RVP) || !ctx->ext_psfoperand) { + return false; + } + + src1 = tcg_temp_new_i64(); + src2 = tcg_temp_new(); + dst = tcg_temp_new_i64(); + + if (is_32bit(ctx)) { + TCGv t0, t1; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + gen_get_gpr(t1, a->rs1 + 1); + tcg_gen_concat_tl_i64(src1, t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } else { + TCGv t0; + t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_ext_tl_i64(src1, t0); + tcg_temp_free(t0); + } + + gen_get_gpr(src2, a->rs2); + fn(dst, cpu_env, src1, src2); + set_pair_regs(ctx, dst, a->rd); + + tcg_temp_free_i64(src1); + tcg_temp_free_i64(dst); + tcg_temp_free(src2); + return true; +} + +#define GEN_RVP_R_D64_S64_OOL(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r *a) \ +{ \ + return r_d64_s64_ool(s, a, gen_helper_##NAME); \ +} + +GEN_RVP_R_D64_S64_OOL(smal); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 88509fd118..1f9a5d620f 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1944,3 +1944,28 @@ static inline void do_kmsxda(CPURISCVState *env, void *vd, void *va, } RVPR_ACC(kmsxda, 1, 4); + +/* Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */ +static inline void do_smal(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int64_t *d = vd, *a = va; + int16_t *b = vb; + + if (i == 0) { + *d = *a; + } + + *d += b[H2(i)] * b[H2(i + 1)]; +} + +uint64_t helper_smal(CPURISCVState *env, uint64_t a, target_ulong b) +{ + int i; + int64_t result = 0; + + for (i = 0; i < sizeof(target_ulong) / 2; i += 2) { + do_smal(env, &result, &a, &b, i); + } + return result; +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions Date: Thu, 24 Jun 2021 18:55:02 +0800 [thread overview] Message-ID: <20210624105521.3964-19-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> "16x16" with 64-bit Signed Addition(64 = 64 + 16x16). Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvp.c.inc | 51 +++++++++++++++++++++++++ target/riscv/packed_helper.c | 25 ++++++++++++ 4 files changed, 80 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5aac6ba578..a37b023c53 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1316,3 +1316,5 @@ DEF_HELPER_4(kmadrs, tl, env, tl, tl, tl) DEF_HELPER_4(kmaxds, tl, env, tl, tl, tl) DEF_HELPER_4(kmsda, tl, env, tl, tl, tl) DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl) + +DEF_HELPER_3(smal, i64, env, i64, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f590880750..233df941b4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -919,3 +919,5 @@ kmadrs 0110110 ..... ..... 001 ..... 1110111 @r kmaxds 0111110 ..... ..... 001 ..... 1110111 @r kmsda 0100110 ..... ..... 001 ..... 1110111 @r kmsxda 0100111 ..... ..... 001 ..... 1110111 @r + +smal 0101111 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 308fc223db..8b0728fc5a 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -451,3 +451,54 @@ GEN_RVP_R_ACC_OOL(kmadrs); GEN_RVP_R_ACC_OOL(kmaxds); GEN_RVP_R_ACC_OOL(kmsda); GEN_RVP_R_ACC_OOL(kmsxda); + +/* Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */ +static bool +r_d64_s64_ool(DisasContext *ctx, arg_r *a, + void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv)) +{ + TCGv src2; + TCGv_i64 src1, dst; + + if (!has_ext(ctx, RVP) || !ctx->ext_psfoperand) { + return false; + } + + src1 = tcg_temp_new_i64(); + src2 = tcg_temp_new(); + dst = tcg_temp_new_i64(); + + if (is_32bit(ctx)) { + TCGv t0, t1; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + gen_get_gpr(t1, a->rs1 + 1); + tcg_gen_concat_tl_i64(src1, t0, t1); + tcg_temp_free(t0); + tcg_temp_free(t1); + } else { + TCGv t0; + t0 = tcg_temp_new(); + gen_get_gpr(t0, a->rs1); + tcg_gen_ext_tl_i64(src1, t0); + tcg_temp_free(t0); + } + + gen_get_gpr(src2, a->rs2); + fn(dst, cpu_env, src1, src2); + set_pair_regs(ctx, dst, a->rd); + + tcg_temp_free_i64(src1); + tcg_temp_free_i64(dst); + tcg_temp_free(src2); + return true; +} + +#define GEN_RVP_R_D64_S64_OOL(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r *a) \ +{ \ + return r_d64_s64_ool(s, a, gen_helper_##NAME); \ +} + +GEN_RVP_R_D64_S64_OOL(smal); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 88509fd118..1f9a5d620f 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1944,3 +1944,28 @@ static inline void do_kmsxda(CPURISCVState *env, void *vd, void *va, } RVPR_ACC(kmsxda, 1, 4); + +/* Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */ +static inline void do_smal(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int64_t *d = vd, *a = va; + int16_t *b = vb; + + if (i == 0) { + *d = *a; + } + + *d += b[H2(i)] * b[H2(i + 1)]; +} + +uint64_t helper_smal(CPURISCVState *env, uint64_t a, target_ulong b) +{ + int i; + int64_t result = 0; + + for (i = 0; i < sizeof(target_ulong) / 2; i += 2) { + do_smal(env, &result, &a, &b, i); + } + return result; +} -- 2.17.1
next prev parent reply other threads:[~2021-06-24 11:33 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:02 ` Alistair Francis 2021-07-01 2:02 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:08 ` Alistair Francis 2021-07-01 2:08 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei [this message] 2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-24 11:55 ` no-reply 2021-07-01 1:30 ` Alistair Francis 2021-07-01 1:30 ` Alistair Francis 2021-07-01 3:06 ` LIU Zhiwei 2021-07-01 3:06 ` LIU Zhiwei
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