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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com,
	Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 08/37] target/riscv: SIMD 8-bit Compare Instructions
Date: Thu, 24 Jun 2021 18:54:52 +0800	[thread overview]
Message-ID: <20210624105521.3964-9-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com>

There are 5 instructions here, including 8-bit compare
equal, signed less than, signed less than & equal,
unsigned less than, unsigned less than & equal.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  6 ++++
 target/riscv/insn32.decode              |  6 ++++
 target/riscv/insn_trans/trans_rvp.c.inc |  7 ++++
 target/riscv/packed_helper.c            | 46 +++++++++++++++++++++++++
 4 files changed, 65 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 830845761b..c424e45fe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1212,3 +1212,9 @@ DEF_HELPER_3(scmplt16, tl, env, tl, tl)
 DEF_HELPER_3(scmple16, tl, env, tl, tl)
 DEF_HELPER_3(ucmplt16, tl, env, tl, tl)
 DEF_HELPER_3(ucmple16, tl, env, tl, tl)
+
+DEF_HELPER_3(cmpeq8, tl, env, tl, tl)
+DEF_HELPER_3(scmplt8, tl, env, tl, tl)
+DEF_HELPER_3(scmple8, tl, env, tl, tl)
+DEF_HELPER_3(ucmplt8, tl, env, tl, tl)
+DEF_HELPER_3(ucmple8, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5031cebf1f..fdbf3798c7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -815,3 +815,9 @@ scmplt16   0000110  ..... ..... 000 ..... 1110111 @r
 scmple16   0001110  ..... ..... 000 ..... 1110111 @r
 ucmplt16   0010110  ..... ..... 000 ..... 1110111 @r
 ucmple16   0011110  ..... ..... 000 ..... 1110111 @r
+
+cmpeq8     0100111  ..... ..... 000 ..... 1110111 @r
+scmplt8    0000111  ..... ..... 000 ..... 1110111 @r
+scmple8    0001111  ..... ..... 000 ..... 1110111 @r
+ucmplt8    0010111  ..... ..... 000 ..... 1110111 @r
+ucmple8    0011111  ..... ..... 000 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 65199ffb5a..aa432701c8 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -210,3 +210,10 @@ GEN_RVP_R_OOL(scmplt16);
 GEN_RVP_R_OOL(scmple16);
 GEN_RVP_R_OOL(ucmplt16);
 GEN_RVP_R_OOL(ucmple16);
+
+/* SIMD 8-bit Compare Instructions */
+GEN_RVP_R_OOL(cmpeq8);
+GEN_RVP_R_OOL(scmplt8);
+GEN_RVP_R_OOL(scmple8);
+GEN_RVP_R_OOL(ucmplt8);
+GEN_RVP_R_OOL(ucmple8);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 30b916b5ad..ff86e015e4 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -677,3 +677,49 @@ static inline void do_ucmple16(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR(ucmple16, 1, 2);
+
+/* SIMD 8-bit Compare Instructions */
+static inline void do_cmpeq8(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] == b[i]) ? 0xff : 0x0;
+}
+
+RVPR(cmpeq8, 1, 1);
+
+static inline void do_scmplt8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    int8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] < b[i]) ? 0xff : 0x0;
+}
+
+RVPR(scmplt8, 1, 1);
+
+static inline void do_scmple8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    int8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] <= b[i]) ? 0xff : 0x0;
+}
+
+RVPR(scmple8, 1, 1);
+
+static inline void do_ucmplt8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    uint8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] < b[i]) ? 0xff : 0x0;
+}
+
+RVPR(ucmplt8, 1, 1);
+
+static inline void do_ucmple8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    uint8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] <= b[i]) ? 0xff : 0x0;
+}
+
+RVPR(ucmple8, 1, 1);
-- 
2.17.1



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 08/37] target/riscv: SIMD 8-bit Compare Instructions
Date: Thu, 24 Jun 2021 18:54:52 +0800	[thread overview]
Message-ID: <20210624105521.3964-9-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com>

There are 5 instructions here, including 8-bit compare
equal, signed less than, signed less than & equal,
unsigned less than, unsigned less than & equal.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  6 ++++
 target/riscv/insn32.decode              |  6 ++++
 target/riscv/insn_trans/trans_rvp.c.inc |  7 ++++
 target/riscv/packed_helper.c            | 46 +++++++++++++++++++++++++
 4 files changed, 65 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 830845761b..c424e45fe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1212,3 +1212,9 @@ DEF_HELPER_3(scmplt16, tl, env, tl, tl)
 DEF_HELPER_3(scmple16, tl, env, tl, tl)
 DEF_HELPER_3(ucmplt16, tl, env, tl, tl)
 DEF_HELPER_3(ucmple16, tl, env, tl, tl)
+
+DEF_HELPER_3(cmpeq8, tl, env, tl, tl)
+DEF_HELPER_3(scmplt8, tl, env, tl, tl)
+DEF_HELPER_3(scmple8, tl, env, tl, tl)
+DEF_HELPER_3(ucmplt8, tl, env, tl, tl)
+DEF_HELPER_3(ucmple8, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5031cebf1f..fdbf3798c7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -815,3 +815,9 @@ scmplt16   0000110  ..... ..... 000 ..... 1110111 @r
 scmple16   0001110  ..... ..... 000 ..... 1110111 @r
 ucmplt16   0010110  ..... ..... 000 ..... 1110111 @r
 ucmple16   0011110  ..... ..... 000 ..... 1110111 @r
+
+cmpeq8     0100111  ..... ..... 000 ..... 1110111 @r
+scmplt8    0000111  ..... ..... 000 ..... 1110111 @r
+scmple8    0001111  ..... ..... 000 ..... 1110111 @r
+ucmplt8    0010111  ..... ..... 000 ..... 1110111 @r
+ucmple8    0011111  ..... ..... 000 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index 65199ffb5a..aa432701c8 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -210,3 +210,10 @@ GEN_RVP_R_OOL(scmplt16);
 GEN_RVP_R_OOL(scmple16);
 GEN_RVP_R_OOL(ucmplt16);
 GEN_RVP_R_OOL(ucmple16);
+
+/* SIMD 8-bit Compare Instructions */
+GEN_RVP_R_OOL(cmpeq8);
+GEN_RVP_R_OOL(scmplt8);
+GEN_RVP_R_OOL(scmple8);
+GEN_RVP_R_OOL(ucmplt8);
+GEN_RVP_R_OOL(ucmple8);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 30b916b5ad..ff86e015e4 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -677,3 +677,49 @@ static inline void do_ucmple16(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR(ucmple16, 1, 2);
+
+/* SIMD 8-bit Compare Instructions */
+static inline void do_cmpeq8(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    uint8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] == b[i]) ? 0xff : 0x0;
+}
+
+RVPR(cmpeq8, 1, 1);
+
+static inline void do_scmplt8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    int8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] < b[i]) ? 0xff : 0x0;
+}
+
+RVPR(scmplt8, 1, 1);
+
+static inline void do_scmple8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    int8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] <= b[i]) ? 0xff : 0x0;
+}
+
+RVPR(scmple8, 1, 1);
+
+static inline void do_ucmplt8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    uint8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] < b[i]) ? 0xff : 0x0;
+}
+
+RVPR(ucmplt8, 1, 1);
+
+static inline void do_ucmple8(CPURISCVState *env, void *vd, void *va,
+                               void *vb, uint8_t i)
+{
+    uint8_t *d = vd, *a = va, *b = vb;
+    d[i] = (a[i] <= b[i]) ? 0xff : 0x0;
+}
+
+RVPR(ucmple8, 1, 1);
-- 
2.17.1



  parent reply	other threads:[~2021-06-24 11:14 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei
2021-06-24 10:54 ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-07-01  2:02   ` Alistair Francis
2021-07-01  2:02     ` Alistair Francis
2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-07-01  2:08   ` Alistair Francis
2021-07-01  2:08     ` Alistair Francis
2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` LIU Zhiwei [this message]
2021-06-24 10:54   ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-06-24 10:54   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-06-24 10:55   ` LIU Zhiwei
2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply
2021-06-24 11:55   ` no-reply
2021-07-01  1:30 ` Alistair Francis
2021-07-01  1:30   ` Alistair Francis
2021-07-01  3:06   ` LIU Zhiwei
2021-07-01  3:06     ` LIU Zhiwei

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