From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions Date: Thu, 24 Jun 2021 18:55:14 +0800 [thread overview] Message-ID: <20210624105521.3964-31-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> SIMD 32-bit absolute value, signed or unsigned maximum, minimum. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 6 +++ target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvp.c.inc | 15 +++++++ target/riscv/packed_helper.c | 55 +++++++++++++++++++++++++ 4 files changed, 82 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3b2a73db9a..d992859747 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1437,3 +1437,9 @@ DEF_HELPER_3(sll32, i64, env, i64, i64) DEF_HELPER_3(ksll32, i64, env, i64, i64) DEF_HELPER_3(kslra32, i64, env, i64, i64) DEF_HELPER_3(kslra32_u, i64, env, i64, i64) + +DEF_HELPER_3(smin32, i64, env, i64, i64) +DEF_HELPER_3(umin32, i64, env, i64, i64) +DEF_HELPER_3(smax32, i64, env, i64, i64) +DEF_HELPER_3(umax32, i64, env, i64, i64) +DEF_HELPER_2(kabs32, tl, env, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 80150c693a..ee5f855f28 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1060,3 +1060,9 @@ ksll32 0110010 ..... ..... 010 ..... 1110111 @r kslli32 1000010 ..... ..... 010 ..... 1110111 @sh5 kslra32 0101011 ..... ..... 010 ..... 1110111 @r kslra32_u 0110011 ..... ..... 010 ..... 1110111 @r + +smin32 1001000 ..... ..... 010 ..... 1110111 @r +umin32 1010000 ..... ..... 010 ..... 1110111 @r +smax32 1001001 ..... ..... 010 ..... 1110111 @r +umax32 1010001 ..... ..... 010 ..... 1110111 @r +kabs32 1010110 10010 ..... 000 ..... 1110111 @r2 diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 6cba14be84..77586e07e4 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1088,3 +1088,18 @@ GEN_RVP64_R_OOL(kslra32); GEN_RVP64_R_OOL(sra32_u); GEN_RVP64_R_OOL(srl32_u); GEN_RVP64_R_OOL(kslra32_u); + +/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */ +GEN_RVP64_R_OOL(smin32); +GEN_RVP64_R_OOL(umin32); +GEN_RVP64_R_OOL(smax32); +GEN_RVP64_R_OOL(umax32); + +#define GEN_RVP64_R2_OOL(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r2 *a) \ +{ \ + REQUIRE_64BIT(s); \ + return r2_ool(s, a, gen_helper_##NAME); \ +} + +GEN_RVP64_R2_OOL(kabs32); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 74d42e4c33..a808dae9d8 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3367,3 +3367,58 @@ static inline void do_kslra32_u(CPURISCVState *env, void *vd, void *va, } RVPR64_64_64(kslra32_u, 1, 4); + +/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */ +static inline void do_smin32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(smin32, 1, 4); + +static inline void do_umin32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(umin32, 1, 4); + +static inline void do_smax32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(smax32, 1, 4); + +static inline void do_umax32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(umax32, 1, 4); + +static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + + if (a[i] == INT32_MIN) { + d[i] = INT32_MAX; + env->vxsat = 0x1; + } else { + d[i] = abs(a[i]); + } +} + +RVPR2(kabs32, 1, 4); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions Date: Thu, 24 Jun 2021 18:55:14 +0800 [thread overview] Message-ID: <20210624105521.3964-31-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> SIMD 32-bit absolute value, signed or unsigned maximum, minimum. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/helper.h | 6 +++ target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvp.c.inc | 15 +++++++ target/riscv/packed_helper.c | 55 +++++++++++++++++++++++++ 4 files changed, 82 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3b2a73db9a..d992859747 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1437,3 +1437,9 @@ DEF_HELPER_3(sll32, i64, env, i64, i64) DEF_HELPER_3(ksll32, i64, env, i64, i64) DEF_HELPER_3(kslra32, i64, env, i64, i64) DEF_HELPER_3(kslra32_u, i64, env, i64, i64) + +DEF_HELPER_3(smin32, i64, env, i64, i64) +DEF_HELPER_3(umin32, i64, env, i64, i64) +DEF_HELPER_3(smax32, i64, env, i64, i64) +DEF_HELPER_3(umax32, i64, env, i64, i64) +DEF_HELPER_2(kabs32, tl, env, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 80150c693a..ee5f855f28 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1060,3 +1060,9 @@ ksll32 0110010 ..... ..... 010 ..... 1110111 @r kslli32 1000010 ..... ..... 010 ..... 1110111 @sh5 kslra32 0101011 ..... ..... 010 ..... 1110111 @r kslra32_u 0110011 ..... ..... 010 ..... 1110111 @r + +smin32 1001000 ..... ..... 010 ..... 1110111 @r +umin32 1010000 ..... ..... 010 ..... 1110111 @r +smax32 1001001 ..... ..... 010 ..... 1110111 @r +umax32 1010001 ..... ..... 010 ..... 1110111 @r +kabs32 1010110 10010 ..... 000 ..... 1110111 @r2 diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 6cba14be84..77586e07e4 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1088,3 +1088,18 @@ GEN_RVP64_R_OOL(kslra32); GEN_RVP64_R_OOL(sra32_u); GEN_RVP64_R_OOL(srl32_u); GEN_RVP64_R_OOL(kslra32_u); + +/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */ +GEN_RVP64_R_OOL(smin32); +GEN_RVP64_R_OOL(umin32); +GEN_RVP64_R_OOL(smax32); +GEN_RVP64_R_OOL(umax32); + +#define GEN_RVP64_R2_OOL(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_r2 *a) \ +{ \ + REQUIRE_64BIT(s); \ + return r2_ool(s, a, gen_helper_##NAME); \ +} + +GEN_RVP64_R2_OOL(kabs32); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 74d42e4c33..a808dae9d8 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3367,3 +3367,58 @@ static inline void do_kslra32_u(CPURISCVState *env, void *vd, void *va, } RVPR64_64_64(kslra32_u, 1, 4); + +/* (RV64 Only) SIMD 32-bit Miscellaneous Instructions */ +static inline void do_smin32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(smin32, 1, 4); + +static inline void do_umin32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] < b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(umin32, 1, 4); + +static inline void do_smax32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + int32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(smax32, 1, 4); + +static inline void do_umax32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + + d[i] = (a[i] > b[i]) ? a[i] : b[i]; +} + +RVPR64_64_64(umax32, 1, 4); + +static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i) +{ + int32_t *d = vd, *a = va; + + if (a[i] == INT32_MIN) { + d[i] = INT32_MAX; + env->vxsat = 0x1; + } else { + d[i] = abs(a[i]); + } +} + +RVPR2(kabs32, 1, 4); -- 2.17.1
next prev parent reply other threads:[~2021-06-24 11:34 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:02 ` Alistair Francis 2021-07-01 2:02 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:08 ` Alistair Francis 2021-07-01 2:08 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei [this message] 2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-24 11:55 ` no-reply 2021-07-01 1:30 ` Alistair Francis 2021-07-01 1:30 ` Alistair Francis 2021-07-01 3:06 ` LIU Zhiwei 2021-07-01 3:06 ` LIU Zhiwei
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210624105521.3964-31-zhiwei_liu@c-sky.com \ --to=zhiwei_liu@c-sky.com \ --cc=Alistair.Francis@wdc.com \ --cc=bin.meng@windriver.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.