From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions Date: Thu, 24 Jun 2021 18:54:58 +0800 [thread overview] Message-ID: <20210624105521.3964-15-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Concat 16-bit elements from source register to 32-bit element in destination register. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 9 +++++ target/riscv/packed_helper.c | 45 +++++++++++++++++++++++++ 4 files changed, 64 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9fd2a70f7d..9872f5efbd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1266,3 +1266,8 @@ DEF_HELPER_2(zunpkd820, tl, env, tl) DEF_HELPER_2(zunpkd830, tl, env, tl) DEF_HELPER_2(zunpkd831, tl, env, tl) DEF_HELPER_2(zunpkd832, tl, env, tl) + +DEF_HELPER_3(pkbb16, tl, env, tl, tl) +DEF_HELPER_3(pkbt16, tl, env, tl, tl) +DEF_HELPER_3(pktt16, tl, env, tl, tl) +DEF_HELPER_3(pktb16, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9b8ea0f9ab..0b6830c76e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -869,3 +869,8 @@ zunpkd820 1010110 01101 ..... 000 ..... 1110111 @r2 zunpkd830 1010110 01110 ..... 000 ..... 1110111 @r2 zunpkd831 1010110 01111 ..... 000 ..... 1110111 @r2 zunpkd832 1010110 10111 ..... 000 ..... 1110111 @r2 + +pkbb16 0000111 ..... ..... 001 ..... 1110111 @r +pkbt16 0001111 ..... ..... 001 ..... 1110111 @r +pktt16 0010111 ..... ..... 001 ..... 1110111 @r +pktb16 0011111 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 5af2c7c2cc..b5bd8b1406 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -360,3 +360,12 @@ GEN_RVP_R2_OOL(zunpkd820); GEN_RVP_R2_OOL(zunpkd830); GEN_RVP_R2_OOL(zunpkd831); GEN_RVP_R2_OOL(zunpkd832); + +/* + *** Partial-SIMD Data Processing Instruction + */ +/* 16-bit Packing Instructions */ +GEN_RVP_R_OOL(pkbb16); +GEN_RVP_R_OOL(pkbt16); +GEN_RVP_R_OOL(pktt16); +GEN_RVP_R_OOL(pktb16); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 8226dbd079..f6cea654b2 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1314,3 +1314,48 @@ do_zunpkd832(CPURISCVState *env, void *vd, void *va, uint8_t i) } RVPR2(zunpkd832, 4, 1); + +/* + *** Partial-SIMD Data Processing Instructions + */ + +/* 16-bit Packing Instructions */ +static inline void do_pkbb16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i)]; + d[H2(i)] = b[H2(i)]; +} + +RVPR(pkbb16, 2, 2); + +static inline void do_pkbt16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i)]; + d[H2(i)] = b[H2(i + 1)]; +} + +RVPR(pkbt16, 2, 2); + +static inline void do_pktt16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i + 1)]; + d[H2(i)] = b[H2(i + 1)]; +} + +RVPR(pktt16, 2, 2); + +static inline void do_pktb16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i + 1)]; + d[H2(i)] = b[H2(i)]; +} + +RVPR(pktb16, 2, 2); -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions Date: Thu, 24 Jun 2021 18:54:58 +0800 [thread overview] Message-ID: <20210624105521.3964-15-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Concat 16-bit elements from source register to 32-bit element in destination register. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 9 +++++ target/riscv/packed_helper.c | 45 +++++++++++++++++++++++++ 4 files changed, 64 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9fd2a70f7d..9872f5efbd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1266,3 +1266,8 @@ DEF_HELPER_2(zunpkd820, tl, env, tl) DEF_HELPER_2(zunpkd830, tl, env, tl) DEF_HELPER_2(zunpkd831, tl, env, tl) DEF_HELPER_2(zunpkd832, tl, env, tl) + +DEF_HELPER_3(pkbb16, tl, env, tl, tl) +DEF_HELPER_3(pkbt16, tl, env, tl, tl) +DEF_HELPER_3(pktt16, tl, env, tl, tl) +DEF_HELPER_3(pktb16, tl, env, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9b8ea0f9ab..0b6830c76e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -869,3 +869,8 @@ zunpkd820 1010110 01101 ..... 000 ..... 1110111 @r2 zunpkd830 1010110 01110 ..... 000 ..... 1110111 @r2 zunpkd831 1010110 01111 ..... 000 ..... 1110111 @r2 zunpkd832 1010110 10111 ..... 000 ..... 1110111 @r2 + +pkbb16 0000111 ..... ..... 001 ..... 1110111 @r +pkbt16 0001111 ..... ..... 001 ..... 1110111 @r +pktt16 0010111 ..... ..... 001 ..... 1110111 @r +pktb16 0011111 ..... ..... 001 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 5af2c7c2cc..b5bd8b1406 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -360,3 +360,12 @@ GEN_RVP_R2_OOL(zunpkd820); GEN_RVP_R2_OOL(zunpkd830); GEN_RVP_R2_OOL(zunpkd831); GEN_RVP_R2_OOL(zunpkd832); + +/* + *** Partial-SIMD Data Processing Instruction + */ +/* 16-bit Packing Instructions */ +GEN_RVP_R_OOL(pkbb16); +GEN_RVP_R_OOL(pkbt16); +GEN_RVP_R_OOL(pktt16); +GEN_RVP_R_OOL(pktb16); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 8226dbd079..f6cea654b2 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -1314,3 +1314,48 @@ do_zunpkd832(CPURISCVState *env, void *vd, void *va, uint8_t i) } RVPR2(zunpkd832, 4, 1); + +/* + *** Partial-SIMD Data Processing Instructions + */ + +/* 16-bit Packing Instructions */ +static inline void do_pkbb16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i)]; + d[H2(i)] = b[H2(i)]; +} + +RVPR(pkbb16, 2, 2); + +static inline void do_pkbt16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i)]; + d[H2(i)] = b[H2(i + 1)]; +} + +RVPR(pkbt16, 2, 2); + +static inline void do_pktt16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i + 1)]; + d[H2(i)] = b[H2(i + 1)]; +} + +RVPR(pktt16, 2, 2); + +static inline void do_pktb16(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint16_t *d = vd, *a = va, *b = vb; + d[H2(i + 1)] = a[H2(i + 1)]; + d[H2(i)] = b[H2(i)]; +} + +RVPR(pktb16, 2, 2); -- 2.17.1
next prev parent reply other threads:[~2021-06-24 11:27 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 10:54 [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 01/37] target/riscv: implementation-defined constant parameters LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 02/37] target/riscv: Make the vector helper functions public LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:02 ` Alistair Francis 2021-07-01 2:02 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-07-01 2:08 ` Alistair Francis 2021-07-01 2:08 ` Alistair Francis 2021-06-24 10:54 ` [PATCH v3 06/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 08/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 10/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 12/37] target/riscv: SIMD 8-bit " LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei [this message] 2021-06-24 10:54 ` [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions LIU Zhiwei 2021-06-24 10:54 ` [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei 2021-06-24 10:54 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 16/37] target/riscv: Signed MSW 32x16 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 18/37] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 21/37] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 22/37] target/riscv: 32-bit Multiply " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 23/37] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 25/37] target/riscv: Non-SIMD Q31 " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 26/37] target/riscv: 32-bit Computation Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 27/37] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 32/37] target/riscv: RV64 Only 32-bit " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 34/37] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 36/37] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 10:55 ` [PATCH v3 37/37] target/riscv: configure and turn on packed extension from command line LIU Zhiwei 2021-06-24 10:55 ` LIU Zhiwei 2021-06-24 11:55 ` [PATCH v3 00/37] target/riscv: support packed extension v0.9.4 no-reply 2021-06-24 11:55 ` no-reply 2021-07-01 1:30 ` Alistair Francis 2021-07-01 1:30 ` Alistair Francis 2021-07-01 3:06 ` LIU Zhiwei 2021-07-01 3:06 ` LIU Zhiwei
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