[PATCH v3 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions

From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com,
	Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions
Date: Thu, 24 Jun 2021 18:55:16 +0800	[thread overview]
Message-ID: <20210624105521.3964-33-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com>

Multiply the straight or crossed 32-bit elements of two registers.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/helper.h                   |  3 +++
 target/riscv/insn32.decode              |  3 +++
 target/riscv/insn_trans/trans_rvp.c.inc |  4 ++++
 target/riscv/packed_helper.c            | 21 +++++++++++++++++++++
 4 files changed, 31 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5edaf389e4..0fa48955d8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1453,3 +1453,6 @@ DEF_HELPER_3(kdmtt16, i64, env, i64, i64)
 DEF_HELPER_4(kdmabb16, tl, env, tl, tl, tl)
 DEF_HELPER_4(kdmabt16, tl, env, tl, tl, tl)
 DEF_HELPER_4(kdmatt16, tl, env, tl, tl, tl)
+
+DEF_HELPER_3(smbt32, i64, env, i64, i64)
+DEF_HELPER_3(smtt32, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a7b5643d5f..d06075c062 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1076,3 +1076,6 @@ kdmtt16    1111101  ..... ..... 001 ..... 1110111 @r
 kdmabb16   1101100  ..... ..... 001 ..... 1110111 @r
 kdmabt16   1110100  ..... ..... 001 ..... 1110111 @r
 kdmatt16   1111100  ..... ..... 001 ..... 1110111 @r
+
+smbt32     0001100  ..... ..... 010 ..... 1110111 @r
+smtt32     0010100  ..... ..... 010 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index aa97161697..a88ce7a5c4 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1122,3 +1122,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a)    \
 GEN_RVP64_R_ACC_OOL(kdmabb16);
 GEN_RVP64_R_ACC_OOL(kdmabt16);
 GEN_RVP64_R_ACC_OOL(kdmatt16);
+
+/* (RV64 Only) 32-bit Multiply Instructions */
+GEN_RVP64_R_OOL(smbt32);
+GEN_RVP64_R_OOL(smtt32);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 32e0af2ef6..eb086b775f 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3561,3 +3561,24 @@ static inline void do_kdmatt16(CPURISCVState *env, void *vd, void *va,
 }
 
 RVPR_ACC(kdmatt16, 2, 2);
+
+/* (RV64 Only) 32-bit Multiply Instructions */
+static inline void do_smbt32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    int64_t *d = vd;
+    int32_t *a = va, *b = vb;
+    *d = (int64_t)a[H4(2 * i)] * b[H4(2 * i + 1)];
+}
+
+RVPR64_64_64(smbt32, 1, 8);
+
+static inline void do_smtt32(CPURISCVState *env, void *vd, void *va,
+                             void *vb, uint8_t i)
+{
+    int64_t *d = vd;
+    int32_t *a = va, *b = vb;
+    *d = (int64_t)a[H4(2 * i + 1)] * b[H4(2 * i + 1)];
+}
+
+RVPR64_64_64(smtt32, 1, 8);
-- 
2.17.1


