* [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-15 2:22 ` Sinan Akman
2021-07-08 2:51 ` Tom Rini
2021-05-15 1:34 ` [PATCH 03/27] arm: Remove integratorap* boards Tom Rini
` (25 subsequent siblings)
26 siblings, 2 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
Drop the MPC837XERDB_SLAVE configuration.
Cc: Sinan Akman <sinan@writeme.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
configs/MPC837XERDB_SLAVE_defconfig | 140 ----------------------------
1 file changed, 140 deletions(-)
delete mode 100644 configs/MPC837XERDB_SLAVE_defconfig
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
deleted file mode 100644
index fa27cd07bb56..000000000000
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ /dev/null
@@ -1,140 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC837XERDB=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_LDP_PIN_MUX_STATE_0=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM_LOWER"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="SDRAM_UPPER"
-CONFIG_BAT1_BASE=0x10000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="IMMR"
-CONFIG_BAT2_BASE=0xE0000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="L2_SWITCH"
-CONFIG_BAT3_BASE=0xF0000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_INHIBITED=y
-CONFIG_BAT3_ICACHE_GUARDED=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now
2021-05-15 1:34 ` [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now Tom Rini
@ 2021-05-15 2:22 ` Sinan Akman
2021-07-08 2:51 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Sinan Akman @ 2021-05-15 2:22 UTC (permalink / raw)
To: u-boot
? Hi Tom
On 2021-05-14 9:34 p.m., Tom Rini wrote:
> Drop the MPC837XERDB_SLAVE configuration.
>
> Cc: Sinan Akman <sinan@writeme.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
?? Acked-by: Sinan Akman <sinan@writeme.com>
?? Thanks
?? -- sinan
> ---
> configs/MPC837XERDB_SLAVE_defconfig | 140 ----------------------------
> 1 file changed, 140 deletions(-)
> delete mode 100644 configs/MPC837XERDB_SLAVE_defconfig
>
> diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
> deleted file mode 100644
> index fa27cd07bb56..000000000000
> --- a/configs/MPC837XERDB_SLAVE_defconfig
> +++ /dev/null
> @@ -1,140 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFE000000
> -CONFIG_ENV_SIZE=0x4000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_SYS_CLK_FREQ=66666667
> -CONFIG_MPC83xx=y
> -CONFIG_TARGET_MPC837XERDB=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_5_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_RGMII=y
> -CONFIG_TSEC2_MODE_RGMII=y
> -CONFIG_LDP_PIN_MUX_STATE_0=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM_LOWER"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT1=y
> -CONFIG_BAT1_NAME="SDRAM_UPPER"
> -CONFIG_BAT1_BASE=0x10000000
> -CONFIG_BAT1_LENGTH_256_MBYTES=y
> -CONFIG_BAT1_ACCESS_RW=y
> -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_USER_MODE_VALID=y
> -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT2=y
> -CONFIG_BAT2_NAME="IMMR"
> -CONFIG_BAT2_BASE=0xE0000000
> -CONFIG_BAT2_LENGTH_8_MBYTES=y
> -CONFIG_BAT2_ACCESS_RW=y
> -CONFIG_BAT2_ICACHE_INHIBITED=y
> -CONFIG_BAT2_ICACHE_GUARDED=y
> -CONFIG_BAT2_DCACHE_INHIBITED=y
> -CONFIG_BAT2_DCACHE_GUARDED=y
> -CONFIG_BAT2_USER_MODE_VALID=y
> -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT3=y
> -CONFIG_BAT3_NAME="L2_SWITCH"
> -CONFIG_BAT3_BASE=0xF0000000
> -CONFIG_BAT3_ACCESS_RW=y
> -CONFIG_BAT3_ICACHE_INHIBITED=y
> -CONFIG_BAT3_ICACHE_GUARDED=y
> -CONFIG_BAT3_DCACHE_INHIBITED=y
> -CONFIG_BAT3_DCACHE_GUARDED=y
> -CONFIG_BAT3_USER_MODE_VALID=y
> -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFE000000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_LBLAW1=y
> -CONFIG_LBLAW1_BASE=0xE0600000
> -CONFIG_LBLAW1_NAME="NAND"
> -CONFIG_LBLAW1_LENGTH_32_KBYTES=y
> -CONFIG_LBLAW2=y
> -CONFIG_LBLAW2_BASE=0xF0000000
> -CONFIG_LBLAW2_NAME="VSC7385"
> -CONFIG_LBLAW2_LENGTH_128_KBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFE000000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_SCY_9=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_EHTR_1_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_ELBC_BR1_OR1=y
> -CONFIG_BR1_OR1_NAME="NAND"
> -CONFIG_BR1_OR1_BASE=0xE0600000
> -CONFIG_BR1_ERRORCHECKING_BOTH=y
> -CONFIG_BR1_MACHINE_FCM=y
> -CONFIG_OR1_SCY_1=y
> -CONFIG_OR1_CSCT_8_CYCLE=y
> -CONFIG_OR1_CST_ONE_CLOCK=y
> -CONFIG_OR1_CHT_TWO_CLOCK=y
> -CONFIG_OR1_TRLX_RELAXED=y
> -CONFIG_OR1_EHTR_8_CYCLE=y
> -CONFIG_ELBC_BR2_OR2=y
> -CONFIG_BR2_OR2_NAME="VSC7385"
> -CONFIG_BR2_OR2_BASE=0xF0000000
> -CONFIG_OR2_AM_128_KBYTES=y
> -CONFIG_OR2_SCY_15=y
> -CONFIG_OR2_CSNT_EARLIER=y
> -CONFIG_OR2_XACS_EXTENDED=y
> -CONFIG_OR2_SETA_EXTERNAL=y
> -CONFIG_OR2_TRLX_RELAXED=y
> -CONFIG_OR2_EHTR_8_CYCLE=y
> -CONFIG_OR2_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_ACR_PIPE_DEP_4=y
> -CONFIG_ACR_RPTCNT_4=y
> -CONFIG_SPCR_TSECEP_3=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_8=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE"
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_PCI=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_DATE=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFE080000
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_STORAGE=y
> -CONFIG_OF_LIBFDT=y
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now
2021-05-15 1:34 ` [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now Tom Rini
2021-05-15 2:22 ` Sinan Akman
@ 2021-07-08 2:51 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:51 UTC (permalink / raw)
To: u-boot; +Cc: Sinan Akman
[-- Attachment #1: Type: text/plain, Size: 246 bytes --]
On Fri, May 14, 2021 at 09:34:07PM -0400, Tom Rini wrote:
> Drop the MPC837XERDB_SLAVE configuration.
>
> Cc: Sinan Akman <sinan@writeme.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 03/27] arm: Remove integratorap* boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
2021-05-15 1:34 ` [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-15 12:27 ` Linus Walleij
2021-05-15 1:34 ` [PATCH 04/27] m68k: Remove M5485 boards Tom Rini
` (24 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
I haven't fully streamlined things for integatorcp-only, in case you
wish to do the DM_PCI migration instead. Thanks!
---
arch/arm/mach-integrator/Kconfig | 4 -
board/armltd/integrator/MAINTAINERS | 5 -
board/armltd/integrator/Makefile | 1 -
board/armltd/integrator/integrator.c | 1 -
board/armltd/integrator/pci.c | 462 ------------------------
board/armltd/integrator/pci_v3.h | 187 ----------
configs/integratorap_cm720t_defconfig | 31 --
configs/integratorap_cm920t_defconfig | 31 --
configs/integratorap_cm926ejs_defconfig | 31 --
configs/integratorap_cm946es_defconfig | 31 --
include/configs/integratorap.h | 48 ---
11 files changed, 832 deletions(-)
delete mode 100644 board/armltd/integrator/pci.c
delete mode 100644 board/armltd/integrator/pci_v3.h
delete mode 100644 configs/integratorap_cm720t_defconfig
delete mode 100644 configs/integratorap_cm920t_defconfig
delete mode 100644 configs/integratorap_cm926ejs_defconfig
delete mode 100644 configs/integratorap_cm946es_defconfig
delete mode 100644 include/configs/integratorap.h
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index d506ee5b39cd..c1d41e182156 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -5,9 +5,6 @@ choice
prompt "Integrator platform select"
optional
-config ARCH_INTEGRATOR_AP
- bool "Support Integrator/AP platform"
-
config ARCH_INTEGRATOR_CP
bool "Support Integrator/CP platform"
select ARCH_CINTEGRATOR
@@ -50,7 +47,6 @@ config SYS_VENDOR
default "armltd"
config SYS_CONFIG_NAME
- default "integratorap" if ARCH_INTEGRATOR_AP
default "integratorcp" if ARCH_INTEGRATOR_CP
config SYS_MALLOC_F_LEN
diff --git a/board/armltd/integrator/MAINTAINERS b/board/armltd/integrator/MAINTAINERS
index 8af765eaebc8..577fce08a731 100644
--- a/board/armltd/integrator/MAINTAINERS
+++ b/board/armltd/integrator/MAINTAINERS
@@ -4,11 +4,6 @@ S: Maintained
F: board/armltd/integrator/
F: include/configs/integratorcp.h
F: configs/integratorcp_cm1136_defconfig
-F: include/configs/integratorap.h
-F: configs/integratorap_cm720t_defconfig
-F: configs/integratorap_cm920t_defconfig
F: configs/integratorcp_cm920t_defconfig
-F: configs/integratorap_cm926ejs_defconfig
F: configs/integratorcp_cm926ejs_defconfig
-F: configs/integratorap_cm946es_defconfig
F: configs/integratorcp_cm946es_defconfig
diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile
index 8c906e3f072b..107e59bf0fa2 100644
--- a/board/armltd/integrator/Makefile
+++ b/board/armltd/integrator/Makefile
@@ -10,5 +10,4 @@
obj-y := lowlevel_init.o
obj-y += integrator.o
-obj-$(CONFIG_PCI) += pci.o
obj-y += timer.o
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index 3e864e8e7a5c..388795809dfd 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -181,7 +181,6 @@ int board_eth_init(struct bd_info *bis)
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
- rc += pci_eth_init(bis);
return rc;
}
#endif
diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c
deleted file mode 100644
index 28efc33f1f42..000000000000
--- a/board/armltd/integrator/pci.c
+++ /dev/null
@@ -1,462 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * (C) Copyright 2011
- * Linaro
- * Linus Walleij <linus.walleij@linaro.org>
- */
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <linux/bug.h>
-#include <linux/delay.h>
-#include "integrator-sc.h"
-#include "pci_v3.h"
-
-#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
-#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
-
-/*
- * These are in the physical addresses on the CPU side, i.e.
- * where we read and write stuff - you don't want to try to
- * move these around
- */
-#define PHYS_PCI_MEM_BASE 0x40000000
-#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
-#define PHYS_PCI_CONFIG_BASE 0x61000000
-#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
-#define SZ_256M 0x10000000
-
-/*
- * These are in the PCI BUS address space
- * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
- * we follow the example of the kernel, because that is the address
- * range that devices actually use - what would they be doing at
- * 0x40000000?
- */
-#define PCI_BUS_NONMEM_START 0x00000000
-#define PCI_BUS_NONMEM_SIZE SZ_256M
-
-#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
-#define PCI_BUS_PREMEM_SIZE SZ_256M
-
-#if PCI_BUS_NONMEM_START & 0x000fffff
-#error PCI_BUS_NONMEM_START must be megabyte aligned
-#endif
-#if PCI_BUS_PREMEM_START & 0x000fffff
-#error PCI_BUS_PREMEM_START must be megabyte aligned
-#endif
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
-#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
-static struct pci_config_table pci_integrator_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif /* CONFIG_PCI_PNP */
-
-/* V3 access routines */
-#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
-#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
-
-#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
-#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
-
-#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
-#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
-
-static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
-{
- unsigned int address, mapaddress;
- unsigned int busnr = PCI_BUS(bdf);
- unsigned int devfn = PCI_FUNC(bdf);
-
- /*
- * Trap out illegal values
- */
- if (offset > 255)
- BUG();
- if (busnr > 255)
- BUG();
- if (devfn > 255)
- BUG();
-
- if (busnr == 0) {
- /*
- * Linux calls the thing U-Boot calls "DEV" "SLOT"
- * instead, but it's the same 5 bits
- */
- int slot = PCI_DEV(bdf);
-
- /*
- * local bus segment so need a type 0 config cycle
- *
- * build the PCI configuration "address" with one-hot in
- * A31-A11
- *
- * mapaddress:
- * 3:1 = config cycle (101)
- * 0 = PCI A1 & A0 are 0 (0)
- */
- address = PCI_FUNC(bdf) << 8;
- mapaddress = V3_LB_MAP_TYPE_CONFIG;
-
- if (slot > 12)
- /*
- * high order bits are handled by the MAP register
- */
- mapaddress |= 1 << (slot - 5);
- else
- /*
- * low order bits handled directly in the address
- */
- address |= 1 << (slot + 11);
- } else {
- /*
- * not the local bus segment so need a type 1 config cycle
- *
- * address:
- * 23:16 = bus number
- * 15:11 = slot number (7:3 of devfn)
- * 10:8 = func number (2:0 of devfn)
- *
- * mapaddress:
- * 3:1 = config cycle (101)
- * 0 = PCI A1 & A0 from host bus (1)
- */
- mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
- address = (busnr << 16) | (devfn << 8);
- }
-
- /*
- * Set up base0 to see all 512Mbytes of memory space (not
- * prefetchable), this frees up base1 for re-use by
- * configuration memory
- */
- v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
- V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
-
- /*
- * Set up base1/map1 to point into configuration space.
- */
- v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
- V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP1, mapaddress);
-
- return PHYS_PCI_CONFIG_BASE + address + offset;
-}
-
-static void v3_close_config_window(void)
-{
- /*
- * Reassign base1 for use by prefetchable PCI memory
- */
- v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
- V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
- V3_LB_MAP_TYPE_MEM_MULTIPLE);
-
- /*
- * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
- */
- v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
-}
-
-static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
- int offset, unsigned char *val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- *val = __raw_readb(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_read__word(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned short *val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- *val = __raw_readw(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_read_dword(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned int *val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- *val = __raw_readl(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_write_byte(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned char val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- __raw_writeb((u8)val, addr);
- __raw_readb(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_write_word(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned short val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- __raw_writew((u8)val, addr);
- __raw_readw(addr);
- v3_close_config_window();
- return 0;
-}
-
-static int pci_integrator_write_dword(struct pci_controller *hose,
- pci_dev_t bdf, int offset,
- unsigned int val)
-{
- unsigned long addr;
-
- addr = v3_open_config_window(bdf, offset);
- __raw_writel((u8)val, addr);
- __raw_readl(addr);
- v3_close_config_window();
- return 0;
-}
-
-struct pci_controller integrator_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_integrator_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- struct pci_controller *hose = &integrator_hose;
- u16 val;
-
- /* setting this register will take the V3 out of reset */
- __raw_writel(SC_PCI_PCIEN, SC_PCI);
-
- /* Wait for 230 ms (from spec) before accessing any V3 registers */
- mdelay(230);
-
- /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
- v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
-
- /* Wait for the mailbox to settle */
- do {
- v3_writeb(V3_MAIL_DATA, 0xAA);
- v3_writeb(V3_MAIL_DATA + 4, 0x55);
- } while (v3_readb(V3_MAIL_DATA) != 0xAA ||
- v3_readb(V3_MAIL_DATA + 4) != 0x55);
-
- /* Make sure that V3 register access is not locked, if it is, unlock it */
- if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
- v3_writew(V3_SYSTEM, 0xA05F);
-
- /*
- * Ensure that the slave accesses from PCI are disabled while we
- * setup memory windows
- */
- val = v3_readw(V3_PCI_CMD);
- val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
- v3_writew(V3_PCI_CMD, val);
-
- /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
- val = v3_readw(V3_SYSTEM);
- val &= ~V3_SYSTEM_M_RST_OUT;
- v3_writew(V3_SYSTEM, val);
-
- /* Make all accesses from PCI space retry until we're ready for them */
- val = v3_readw(V3_PCI_CFG);
- val |= V3_PCI_CFG_M_RETRY_EN;
- v3_writew(V3_PCI_CFG, val);
-
- /*
- * Set up any V3 PCI Configuration Registers that we absolutely have to.
- * LB_CFG controls Local Bus protocol.
- * Enable LocalBus byte strobes for READ accesses too.
- * set bit 7 BE_IMODE and bit 6 BE_OMODE
- */
- val = v3_readw(V3_LB_CFG);
- val |= 0x0C0;
- v3_writew(V3_LB_CFG, val);
-
- /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
- val = v3_readw(V3_PCI_CMD);
- val |= V3_COMMAND_M_MASTER_EN;
- v3_writew(V3_PCI_CMD, val);
-
- /*
- * PCI_MAP0 controls where the PCI to CPU memory window is on
- * Local Bus
- */
- v3_writel(V3_PCI_MAP0,
- (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
- V3_PCI_MAP_M_REG_EN |
- V3_PCI_MAP_M_ENABLE));
-
- /* PCI_BASE0 is the PCI address of the start of the window */
- v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
-
- /* PCI_MAP1 is LOCAL address of the start of the window */
- v3_writel(V3_PCI_MAP1,
- (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
- V3_PCI_MAP_M_REG_EN |
- V3_PCI_MAP_M_ENABLE));
-
- /* PCI_BASE1 is the PCI address of the start of the window */
- v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
-
- /*
- * Set up memory the windows from local bus memory into PCI
- * configuration, I/O and Memory regions.
- * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
- */
- v3_writew(V3_LB_BASE2,
- v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP2, 0);
-
- /* PCI Configuration, use LB_BASE1/LB_MAP1. */
-
- /*
- * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
- * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
- */
- v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP0,
- v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
-
- /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
- v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
- V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
- V3_LB_BASE_ENABLE);
- v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
- V3_LB_MAP_TYPE_MEM_MULTIPLE);
-
- /* Dump PCI to local address space mappings */
- debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
- debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
- debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
- debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
- debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
- debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
- debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
-
- /*
- * Allow accesses to PCI Configuration space and set up A1, A0 for
- * type 1 config cycles
- */
- val = v3_readw(V3_PCI_CFG);
- val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
- val |= V3_PCI_CFG_M_AD_LOW0;
- v3_writew(V3_PCI_CFG, val);
-
- /* now we can allow incoming PCI MEMORY accesses */
- val = v3_readw(V3_PCI_CMD);
- val |= V3_COMMAND_M_MEM_EN;
- v3_writew(V3_PCI_CMD, val);
-
- /*
- * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
- * now initialise.
- */
- val = v3_readw(V3_SYSTEM);
- val |= V3_SYSTEM_M_RST_OUT;
- v3_writew(V3_SYSTEM, val);
-
- /* Lock the V3 system register so that no one else can play with it */
- val = v3_readw(V3_SYSTEM);
- val |= V3_SYSTEM_M_LOCK;
- v3_writew(V3_SYSTEM, val);
-
- /*
- * Configure and register the PCI hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space, window 0 256 MB non-prefetchable */
- pci_set_region(hose->regions + 0,
- PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
- SZ_256M,
- PCI_REGION_MEM);
-
- /* System memory space, window 1 256 MB prefetchable */
- pci_set_region(hose->regions + 1,
- PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
- SZ_256M,
- PCI_REGION_MEM |
- PCI_REGION_PREFETCH);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 2,
- 0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
- PCI_REGION_IO);
-
- /* PCI Memory - config space */
- pci_set_region(hose->regions + 3,
- 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
- PCI_REGION_MEM);
- /* PCI V3 regs */
- pci_set_region(hose->regions + 4,
- 0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
- PCI_REGION_MEM);
-
- hose->region_count = 5;
-
- pci_set_ops(hose,
- pci_integrator_read_byte,
- pci_integrator_read__word,
- pci_integrator_read_dword,
- pci_integrator_write_byte,
- pci_integrator_write_word,
- pci_integrator_write_dword);
-
- pci_register_hose(hose);
-
- pciauto_config_init(hose);
- pciauto_config_device(hose, 0);
-
- hose->last_busno = pci_hose_scan(hose);
-}
diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h
deleted file mode 100644
index 8d09e6966db2..000000000000
--- a/board/armltd/integrator/pci_v3.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * arch/arm/include/asm/hardware/pci_v3.h
- *
- * Internal header file PCI V3 chip
- *
- * Copyright (C) ARM Limited
- * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- */
-#ifndef ASM_ARM_HARDWARE_PCI_V3_H
-#define ASM_ARM_HARDWARE_PCI_V3_H
-
-/* -------------------------------------------------------------------------------
- * V3 Local Bus to PCI Bridge definitions
- * -------------------------------------------------------------------------------
- * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
- * All V3 register names are prefaced by V3_ to avoid clashing with any other
- * PCI definitions. Their names match the user's manual.
- *
- * I'm assuming that I20 is disabled.
- *
- */
-#define V3_PCI_VENDOR 0x00000000
-#define V3_PCI_DEVICE 0x00000002
-#define V3_PCI_CMD 0x00000004
-#define V3_PCI_STAT 0x00000006
-#define V3_PCI_CC_REV 0x00000008
-#define V3_PCI_HDR_CFG 0x0000000C
-#define V3_PCI_IO_BASE 0x00000010
-#define V3_PCI_BASE0 0x00000014
-#define V3_PCI_BASE1 0x00000018
-#define V3_PCI_SUB_VENDOR 0x0000002C
-#define V3_PCI_SUB_ID 0x0000002E
-#define V3_PCI_ROM 0x00000030
-#define V3_PCI_BPARAM 0x0000003C
-#define V3_PCI_MAP0 0x00000040
-#define V3_PCI_MAP1 0x00000044
-#define V3_PCI_INT_STAT 0x00000048
-#define V3_PCI_INT_CFG 0x0000004C
-#define V3_LB_BASE0 0x00000054
-#define V3_LB_BASE1 0x00000058
-#define V3_LB_MAP0 0x0000005E
-#define V3_LB_MAP1 0x00000062
-#define V3_LB_BASE2 0x00000064
-#define V3_LB_MAP2 0x00000066
-#define V3_LB_SIZE 0x00000068
-#define V3_LB_IO_BASE 0x0000006E
-#define V3_FIFO_CFG 0x00000070
-#define V3_FIFO_PRIORITY 0x00000072
-#define V3_FIFO_STAT 0x00000074
-#define V3_LB_ISTAT 0x00000076
-#define V3_LB_IMASK 0x00000077
-#define V3_SYSTEM 0x00000078
-#define V3_LB_CFG 0x0000007A
-#define V3_PCI_CFG 0x0000007C
-#define V3_DMA_PCI_ADR0 0x00000080
-#define V3_DMA_PCI_ADR1 0x00000090
-#define V3_DMA_LOCAL_ADR0 0x00000084
-#define V3_DMA_LOCAL_ADR1 0x00000094
-#define V3_DMA_LENGTH0 0x00000088
-#define V3_DMA_LENGTH1 0x00000098
-#define V3_DMA_CSR0 0x0000008B
-#define V3_DMA_CSR1 0x0000009B
-#define V3_DMA_CTLB_ADR0 0x0000008C
-#define V3_DMA_CTLB_ADR1 0x0000009C
-#define V3_DMA_DELAY 0x000000E0
-#define V3_MAIL_DATA 0x000000C0
-#define V3_PCI_MAIL_IEWR 0x000000D0
-#define V3_PCI_MAIL_IERD 0x000000D2
-#define V3_LB_MAIL_IEWR 0x000000D4
-#define V3_LB_MAIL_IERD 0x000000D6
-#define V3_MAIL_WR_STAT 0x000000D8
-#define V3_MAIL_RD_STAT 0x000000DA
-#define V3_QBA_MAP 0x000000DC
-
-/* PCI COMMAND REGISTER bits
- */
-#define V3_COMMAND_M_FBB_EN (1 << 9)
-#define V3_COMMAND_M_SERR_EN (1 << 8)
-#define V3_COMMAND_M_PAR_EN (1 << 6)
-#define V3_COMMAND_M_MASTER_EN (1 << 2)
-#define V3_COMMAND_M_MEM_EN (1 << 1)
-#define V3_COMMAND_M_IO_EN (1 << 0)
-
-/* SYSTEM REGISTER bits
- */
-#define V3_SYSTEM_M_RST_OUT (1 << 15)
-#define V3_SYSTEM_M_LOCK (1 << 14)
-
-/* PCI_CFG bits
- */
-#define V3_PCI_CFG_M_I2O_EN (1 << 15)
-#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
-#define V3_PCI_CFG_M_IO_DIS (1 << 13)
-#define V3_PCI_CFG_M_EN3V (1 << 12)
-#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
-
-/* PCI_BASE register bits (PCI -> Local Bus)
- */
-#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
-#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
-#define V3_PCI_BASE_M_PREFETCH (1 << 3)
-#define V3_PCI_BASE_M_TYPE (3 << 1)
-#define V3_PCI_BASE_M_IO (1 << 0)
-
-/* PCI MAP register bits (PCI -> Local bus)
- */
-#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
-#define V3_PCI_MAP_M_SWAP (3 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
-#define V3_PCI_MAP_M_REG_EN (1 << 1)
-#define V3_PCI_MAP_M_ENABLE (1 << 0)
-
-#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4)
-#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4)
-
-/*
- * LB_BASE0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_BASE_ADR_BASE 0xfff00000
-#define V3_LB_BASE_SWAP (3 << 8)
-#define V3_LB_BASE_ADR_SIZE (15 << 4)
-#define V3_LB_BASE_PREFETCH (1 << 3)
-#define V3_LB_BASE_ENABLE (1 << 0)
-
-#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
-#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
-#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
-#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
-#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
-#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
-#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
-#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
-#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
-#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
-#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
-#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
-
-#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
-
-/*
- * LB_MAP0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_MAP_MAP_ADR 0xfff0
-#define V3_LB_MAP_TYPE (7 << 1)
-#define V3_LB_MAP_AD_LOW_EN (1 << 0)
-
-#define V3_LB_MAP_TYPE_IACK (0 << 1)
-#define V3_LB_MAP_TYPE_IO (1 << 1)
-#define V3_LB_MAP_TYPE_MEM (3 << 1)
-#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
-#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
-
-/* PCI MAP register bits (PCI -> Local bus) */
-#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
-
-/*
- * LB_BASE2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_BASE2_ADR_BASE 0xff00
-#define V3_LB_BASE2_SWAP (3 << 6)
-#define V3_LB_BASE2_ENABLE (1 << 0)
-
-#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
-
-/*
- * LB_MAP2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_MAP2_MAP_ADR 0xff00
-
-#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
-
-#endif
diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig
deleted file mode 100644
index 5d28135a8220..000000000000
--- a/configs/integratorap_cm720t_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_INTEGRATOR=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_ARCH_INTEGRATOR_AP=y
-CONFIG_CM720T=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x8000
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
-CONFIG_BAUDRATE=38400
-CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig
deleted file mode 100644
index 0e914e91ebed..000000000000
--- a/configs/integratorap_cm920t_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_INTEGRATOR=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_ARCH_INTEGRATOR_AP=y
-CONFIG_CM920T=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x8000
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
-CONFIG_BAUDRATE=38400
-CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig
deleted file mode 100644
index d28bc0f976cf..000000000000
--- a/configs/integratorap_cm926ejs_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_INTEGRATOR=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_ARCH_INTEGRATOR_AP=y
-CONFIG_CM926EJ_S=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x8000
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
-CONFIG_BAUDRATE=38400
-CONFIG_OF_LIBFDT=y
diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig
deleted file mode 100644
index ae44f01ff50d..000000000000
--- a/configs/integratorap_cm946es_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_INTEGRATOR=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_ARCH_INTEGRATOR_AP=y
-CONFIG_CM946ES=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x8000
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAM0 console=tty"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="Integrator-AP # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ARMFLASH=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_EEPRO100=y
-CONFIG_TULIP=y
-CONFIG_PCI=y
-CONFIG_BAUDRATE=38400
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
deleted file mode 100644
index 2f8ac20a76ea..000000000000
--- a/include/configs/integratorap.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Texas Instruments.
- * Kshitij Gupta <kshitij@ti.com>
- * Configuation settings for the TI OMAP Innovator board.
- *
- * (C) Copyright 2004
- * ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- * Configuration for Integrator AP board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include "integrator-common.h"
-
-/* Integrator/AP-specific configuration */
-#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_BOOTCOMMAND ""
-
-/* Flash settings */
-#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-/*-----------------------------------------------------------------------
- * PCI definitions
- */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. integratorcp_CM926EJ-S_config
- */
-#include "armcoremodule.h"
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 03/27] arm: Remove integratorap* boards
2021-05-15 1:34 ` [PATCH 03/27] arm: Remove integratorap* boards Tom Rini
@ 2021-05-15 12:27 ` Linus Walleij
0 siblings, 0 replies; 71+ messages in thread
From: Linus Walleij @ 2021-05-15 12:27 UTC (permalink / raw)
To: u-boot
On Sat, May 15, 2021 at 3:34 AM Tom Rini <trini@konsulko.com> wrote:
> These boards have not been converted to CONFIG_DM_PCI by the deadline.
> Remove them.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> I haven't fully streamlined things for integatorcp-only, in case you
> wish to do the DM_PCI migration instead. Thanks!
Sorry for missing this!
We never used PCI to boot (weird but true, we boot from serial).
I will send a patch to remove PCI support instead.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 04/27] m68k: Remove M5485 boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
2021-05-15 1:34 ` [PATCH 02/27] ppc: Drop MPC837XERDB_SLAVE for now Tom Rini
2021-05-15 1:34 ` [PATCH 03/27] arm: Remove integratorap* boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 05/27] m68k: Remove M5475x boards Tom Rini
` (23 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is all of the CONFIG_M548x platforms as well,
remove that code.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/m68k/Kconfig | 9 -
arch/m68k/dts/M5485AFE.dts | 25 ---
arch/m68k/dts/M5485BFE.dts | 25 ---
arch/m68k/dts/M5485CFE.dts | 25 ---
arch/m68k/dts/M5485DFE.dts | 25 ---
arch/m68k/dts/M5485EFE.dts | 25 ---
arch/m68k/dts/M5485FFE.dts | 25 ---
arch/m68k/dts/M5485GFE.dts | 25 ---
arch/m68k/dts/M5485HFE.dts | 25 ---
arch/m68k/dts/Makefile | 8 -
arch/m68k/include/asm/coldfire/intctrl.h | 2 +-
arch/m68k/include/asm/immap.h | 47 -----
board/freescale/m548xevb/Kconfig | 15 --
board/freescale/m548xevb/MAINTAINERS | 13 --
board/freescale/m548xevb/Makefile | 6 -
board/freescale/m548xevb/m548xevb.c | 108 -----------
configs/M5485AFE_defconfig | 32 ----
configs/M5485BFE_defconfig | 32 ----
configs/M5485CFE_defconfig | 32 ----
configs/M5485DFE_defconfig | 32 ----
configs/M5485EFE_defconfig | 32 ----
configs/M5485FFE_defconfig | 32 ----
configs/M5485GFE_defconfig | 32 ----
configs/M5485HFE_defconfig | 32 ----
include/configs/M5485EVB.h | 228 -----------------------
25 files changed, 1 insertion(+), 891 deletions(-)
delete mode 100644 arch/m68k/dts/M5485AFE.dts
delete mode 100644 arch/m68k/dts/M5485BFE.dts
delete mode 100644 arch/m68k/dts/M5485CFE.dts
delete mode 100644 arch/m68k/dts/M5485DFE.dts
delete mode 100644 arch/m68k/dts/M5485EFE.dts
delete mode 100644 arch/m68k/dts/M5485FFE.dts
delete mode 100644 arch/m68k/dts/M5485GFE.dts
delete mode 100644 arch/m68k/dts/M5485HFE.dts
delete mode 100644 board/freescale/m548xevb/Kconfig
delete mode 100644 board/freescale/m548xevb/MAINTAINERS
delete mode 100644 board/freescale/m548xevb/Makefile
delete mode 100644 board/freescale/m548xevb/m548xevb.c
delete mode 100644 configs/M5485AFE_defconfig
delete mode 100644 configs/M5485BFE_defconfig
delete mode 100644 configs/M5485CFE_defconfig
delete mode 100644 configs/M5485DFE_defconfig
delete mode 100644 configs/M5485EFE_defconfig
delete mode 100644 configs/M5485FFE_defconfig
delete mode 100644 configs/M5485GFE_defconfig
delete mode 100644 configs/M5485HFE_defconfig
delete mode 100644 include/configs/M5485EVB.h
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index fef108105b50..f7f6d08be3f5 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -141,10 +141,6 @@ config M547x
bool
select MCF547x_8x
-config M548x
- bool
- select MCF547x_8x
-
choice
prompt "Target select"
optional
@@ -221,10 +217,6 @@ config TARGET_M5475EVB
bool "Support M5475EVB"
select M547x
-config TARGET_M5485EVB
- bool "Support M5485EVB"
- select M548x
-
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
@@ -253,7 +245,6 @@ source "board/freescale/m54418twr/Kconfig"
source "board/freescale/m54451evb/Kconfig"
source "board/freescale/m54455evb/Kconfig"
source "board/freescale/m547xevb/Kconfig"
-source "board/freescale/m548xevb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
diff --git a/arch/m68k/dts/M5485AFE.dts b/arch/m68k/dts/M5485AFE.dts
deleted file mode 100644
index b1f5bf0f561d..000000000000
--- a/arch/m68k/dts/M5485AFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485AFE";
- compatible = "fsl,M5485AFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485BFE.dts b/arch/m68k/dts/M5485BFE.dts
deleted file mode 100644
index 10b8f5b20157..000000000000
--- a/arch/m68k/dts/M5485BFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485BFE";
- compatible = "fsl,M5485BFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485CFE.dts b/arch/m68k/dts/M5485CFE.dts
deleted file mode 100644
index a1ae64f65ca0..000000000000
--- a/arch/m68k/dts/M5485CFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485CFE";
- compatible = "fsl,M5485CFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485DFE.dts b/arch/m68k/dts/M5485DFE.dts
deleted file mode 100644
index 9b38d451fc0e..000000000000
--- a/arch/m68k/dts/M5485DFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485DFE";
- compatible = "fsl,M5485DFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485EFE.dts b/arch/m68k/dts/M5485EFE.dts
deleted file mode 100644
index a1ac3f5a489f..000000000000
--- a/arch/m68k/dts/M5485EFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485EFE";
- compatible = "fsl,M5485EFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485FFE.dts b/arch/m68k/dts/M5485FFE.dts
deleted file mode 100644
index 7f22de49f48a..000000000000
--- a/arch/m68k/dts/M5485FFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485FFE";
- compatible = "fsl,M5485FFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485GFE.dts b/arch/m68k/dts/M5485GFE.dts
deleted file mode 100644
index 3430aa72795c..000000000000
--- a/arch/m68k/dts/M5485GFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485GFE";
- compatible = "fsl,M5485GFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5485HFE.dts b/arch/m68k/dts/M5485HFE.dts
deleted file mode 100644
index 57c98f1ef79e..000000000000
--- a/arch/m68k/dts/M5485HFE.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5485HFE";
- compatible = "fsl,M5485HFE";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
index e059f23ccd3f..0a356b8e3728 100644
--- a/arch/m68k/dts/Makefile
+++ b/arch/m68k/dts/Makefile
@@ -39,14 +39,6 @@ dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
M5475EFE.dtb \
M5475FFE.dtb \
M5475GFE.dtb
-dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \
- M5485BFE.dtb \
- M5485CFE.dtb \
- M5485DFE.dtb \
- M5485EFE.dtb \
- M5485FFE.dtb \
- M5485GFE.dtb \
- M5485HFE.dtb
targets += $(dtb-y)
diff --git a/arch/m68k/include/asm/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h
index 7b42e65bc82f..f7f0f07d30f0 100644
--- a/arch/m68k/include/asm/coldfire/intctrl.h
+++ b/arch/m68k/include/asm/coldfire/intctrl.h
@@ -11,7 +11,7 @@
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
- defined(CONFIG_M547x) || defined(CONFIG_M548x)
+ defined(CONFIG_M547x)
# define CONFIG_SYS_CF_INTC_REG1
#endif
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 9e84fb9d260c..cabdb0f1a5e0 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -412,51 +412,4 @@
#endif
#endif /* CONFIG_M547x */
-#ifdef CONFIG_M548x
-#include <asm/immap_547x_8x.h>
-#include <asm/m547x_8x.h>
-
-#ifdef CONFIG_FSLDMAFEC
-#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
-#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-
-#define FEC0_RX_TASK 0
-#define FEC0_TX_TASK 1
-#define FEC0_RX_PRIORITY 6
-#define FEC0_TX_PRIORITY 7
-#define FEC0_RX_INIT 16
-#define FEC0_TX_INIT 17
-#define FEC1_RX_TASK 2
-#define FEC1_TX_TASK 3
-#define FEC1_RX_PRIORITY 6
-#define FEC1_TX_PRIORITY 7
-#define FEC1_RX_INIT 30
-#define FEC1_TX_INIT 31
-#endif
-
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
-
-/* Timer */
-#ifdef CONFIG_SLTTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
-#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
-#endif
-
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
-
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
-#endif
-#endif /* CONFIG_M548x */
-
#endif /* __IMMAP_H */
diff --git a/board/freescale/m548xevb/Kconfig b/board/freescale/m548xevb/Kconfig
deleted file mode 100644
index da924e3ce98f..000000000000
--- a/board/freescale/m548xevb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M5485EVB
-
-config SYS_CPU
- default "mcf547x_8x"
-
-config SYS_BOARD
- default "m548xevb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M5485EVB"
-
-endif
diff --git a/board/freescale/m548xevb/MAINTAINERS b/board/freescale/m548xevb/MAINTAINERS
deleted file mode 100644
index 4e642e69d516..000000000000
--- a/board/freescale/m548xevb/MAINTAINERS
+++ /dev/null
@@ -1,13 +0,0 @@
-M548XEVB BOARD
-M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S: Maintained
-F: board/freescale/m548xevb/
-F: include/configs/M5485EVB.h
-F: configs/M5485AFE_defconfig
-F: configs/M5485BFE_defconfig
-F: configs/M5485CFE_defconfig
-F: configs/M5485DFE_defconfig
-F: configs/M5485EFE_defconfig
-F: configs/M5485FFE_defconfig
-F: configs/M5485GFE_defconfig
-F: configs/M5485HFE_defconfig
diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile
deleted file mode 100644
index 05bfaa337113..000000000000
--- a/board/freescale/m548xevb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y = m548xevb.o
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
deleted file mode 100644
index b62355a7ae7b..000000000000
--- a/board/freescale/m548xevb/m548xevb.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Board: ");
- puts("Freescale FireEngine 5485 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- siu_t *siu = (siu_t *) (MMAP_SIU);
- sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
- u32 dramsize, i;
-#ifdef CONFIG_SYS_DRAMSZ1
- u32 temp;
-#endif
-
- out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
-
- dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
- out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
-
-#ifdef CONFIG_SYS_DRAMSZ1
- temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
- for (i = 0x13; i < 0x20; i++) {
- if (temp == (1 << i))
- break;
- }
- i--;
- dramsize += temp;
- out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
-#endif
-
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
-
- /* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
-
- udelay(500);
-
- /* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
-
- out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
-
- udelay(100);
-
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-extern void pci_mcf547x_8x_init(struct pci_controller *hose);
-
-void pci_init_board(void)
-{
- pci_mcf547x_8x_init(&hose);
-}
-#endif /* CONFIG_PCI */
diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig
deleted file mode 100644
index 548deaf90279..000000000000
--- a/configs/M5485AFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485AFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig
deleted file mode 100644
index 0d72da3b364e..000000000000
--- a/configs/M5485BFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485BFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig
deleted file mode 100644
index 68908e2f431d..000000000000
--- a/configs/M5485CFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485CFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig
deleted file mode 100644
index 25872009536c..000000000000
--- a/configs/M5485DFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485DFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig
deleted file mode 100644
index a43b40223805..000000000000
--- a/configs/M5485EFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485EFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig
deleted file mode 100644
index 335ad0e1e730..000000000000
--- a/configs/M5485FFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485FFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig
deleted file mode 100644
index 2665be9fb56a..000000000000
--- a/configs/M5485GFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485GFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig
deleted file mode 100644
index a0536bfae110..000000000000
--- a/configs/M5485HFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5485EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5485HFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
deleted file mode 100644
index cd8dd67043f0..000000000000
--- a/include/configs/M5485EVB.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF5485 FireEngine board.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5485EVB_H
-#define _M5485EVB_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#undef CONFIG_HW_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
-
-#define CONFIG_SLTTMR
-
-#ifdef CONFIG_FSLDMAFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_HAS_ETH1
-# define CONFIG_SYS_DMA_USE_INTSRAM 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 32
-# define CONFIG_SYS_TX_ETH_BUFFER 48
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-#endif
-
-#ifdef CONFIG_CMD_USB
-# define CONFIG_USB_OHCI_NEW
-/*# define CONFIG_PCI_OHCI*/
-# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
-# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
-# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-#endif
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* PCI */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_SYS_PCI_IO_BUS 0x71000000
-#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
-#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
-#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
-#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
-#endif
-
-#define CONFIG_UDP_CHECKSUM
-
-#define CONFIG_HOSTNAME "M548xEVB"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "loadaddr=10000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off bank 1;" \
- "era ff800000 ff83ffff;" \
- "cp.b ${loadaddr} ff800000 ${filesize};"\
- "save\0" \
- ""
-
-#define CONFIG_PRAM 512 /* 512 KB */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
-
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
-#define CONFIG_SYS_INTSRAMSZ 0x8000
-
-/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
-#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_CFG1 0x73711630
-#define CONFIG_SYS_SDRAM_CFG2 0x46770000
-#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x018D0000
-#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
-#ifdef CONFIG_SYS_DRAMSZ1
-# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
-#else
-# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-#ifdef CONFIG_SYS_NOR1SZ
-# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
-#else
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
-#endif
-#endif
-
-/* Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
- CF_CACR_IDCM)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
- CF_CACR_IEC | CF_CACR_ICINVA)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Chipselect bank definitions
- */
-/*
- * CS0 - NOR Flash 1, 2, 4, or 8MB
- * CS1 - NOR Flash
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-#define CONFIG_SYS_CS0_BASE 0xFF800000
-#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
-#define CONFIG_SYS_CS0_CTRL 0x00101980
-
-#ifdef CONFIG_SYS_NOR1SZ
-#define CONFIG_SYS_CS1_BASE 0xE0000000
-#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CONFIG_SYS_CS1_CTRL 0x00101D80
-#endif
-
-#endif /* _M5485EVB_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 05/27] m68k: Remove M5475x boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (2 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 04/27] m68k: Remove M5485 boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 06/27] mips: Remove malta boards Tom Rini
` (22 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is the last of the mcf547x_8x family of boards,
remove that support as well.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/m68k/Kconfig | 15 -
arch/m68k/Makefile | 2 -
arch/m68k/cpu/mcf547x_8x/Makefile | 9 -
arch/m68k/cpu/mcf547x_8x/cpu.c | 153 ---------
arch/m68k/cpu/mcf547x_8x/cpu_init.c | 150 ---------
arch/m68k/cpu/mcf547x_8x/interrupts.c | 35 ---
arch/m68k/cpu/mcf547x_8x/pci.c | 154 ---------
arch/m68k/cpu/mcf547x_8x/slicetimer.c | 95 ------
arch/m68k/cpu/mcf547x_8x/speed.c | 33 --
arch/m68k/cpu/mcf547x_8x/start.S | 264 ----------------
arch/m68k/dts/M5475AFE.dts | 21 --
arch/m68k/dts/M5475BFE.dts | 21 --
arch/m68k/dts/M5475CFE.dts | 21 --
arch/m68k/dts/M5475DFE.dts | 21 --
arch/m68k/dts/M5475EFE.dts | 21 --
arch/m68k/dts/M5475FFE.dts | 21 --
arch/m68k/dts/M5475GFE.dts | 21 --
arch/m68k/dts/Makefile | 7 -
arch/m68k/include/asm/cache.h | 2 +-
arch/m68k/include/asm/coldfire/dspi.h | 6 -
arch/m68k/include/asm/coldfire/eport.h | 13 -
arch/m68k/include/asm/fec.h | 5 -
arch/m68k/include/asm/immap_547x_8x.h | 258 ---------------
arch/m68k/include/asm/m547x_8x.h | 417 -------------------------
arch/m68k/lib/cache.c | 2 +-
board/freescale/m547xevb/Kconfig | 15 -
board/freescale/m547xevb/MAINTAINERS | 12 -
board/freescale/m547xevb/Makefile | 6 -
board/freescale/m547xevb/README | 271 ----------------
board/freescale/m547xevb/m547xevb.c | 108 -------
configs/M5475AFE_defconfig | 32 --
configs/M5475BFE_defconfig | 32 --
configs/M5475CFE_defconfig | 32 --
configs/M5475DFE_defconfig | 32 --
configs/M5475EFE_defconfig | 32 --
configs/M5475FFE_defconfig | 32 --
configs/M5475GFE_defconfig | 32 --
doc/arch/m68k.rst | 2 +-
drivers/net/mcfmii.c | 4 -
env/Kconfig | 2 +-
include/configs/M5475EVB.h | 241 --------------
include/fsl_dspi.h | 6 -
42 files changed, 4 insertions(+), 2654 deletions(-)
delete mode 100644 arch/m68k/cpu/mcf547x_8x/Makefile
delete mode 100644 arch/m68k/cpu/mcf547x_8x/cpu.c
delete mode 100644 arch/m68k/cpu/mcf547x_8x/cpu_init.c
delete mode 100644 arch/m68k/cpu/mcf547x_8x/interrupts.c
delete mode 100644 arch/m68k/cpu/mcf547x_8x/pci.c
delete mode 100644 arch/m68k/cpu/mcf547x_8x/slicetimer.c
delete mode 100644 arch/m68k/cpu/mcf547x_8x/speed.c
delete mode 100644 arch/m68k/cpu/mcf547x_8x/start.S
delete mode 100644 arch/m68k/dts/M5475AFE.dts
delete mode 100644 arch/m68k/dts/M5475BFE.dts
delete mode 100644 arch/m68k/dts/M5475CFE.dts
delete mode 100644 arch/m68k/dts/M5475DFE.dts
delete mode 100644 arch/m68k/dts/M5475EFE.dts
delete mode 100644 arch/m68k/dts/M5475FFE.dts
delete mode 100644 arch/m68k/dts/M5475GFE.dts
delete mode 100644 arch/m68k/include/asm/immap_547x_8x.h
delete mode 100644 arch/m68k/include/asm/m547x_8x.h
delete mode 100644 board/freescale/m547xevb/Kconfig
delete mode 100644 board/freescale/m547xevb/MAINTAINERS
delete mode 100644 board/freescale/m547xevb/Makefile
delete mode 100644 board/freescale/m547xevb/README
delete mode 100644 board/freescale/m547xevb/m547xevb.c
delete mode 100644 configs/M5475AFE_defconfig
delete mode 100644 configs/M5475BFE_defconfig
delete mode 100644 configs/M5475CFE_defconfig
delete mode 100644 configs/M5475DFE_defconfig
delete mode 100644 configs/M5475EFE_defconfig
delete mode 100644 configs/M5475FFE_defconfig
delete mode 100644 configs/M5475GFE_defconfig
delete mode 100644 include/configs/M5475EVB.h
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index f7f6d08be3f5..cf45d789d63d 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -65,12 +65,6 @@ config MCF5227x
select DM_SERIAL
bool
-config MCF547x_8x
- select OF_CONTROL
- select DM
- select DM_SERIAL
- bool
-
# processor type
config M5208
bool
@@ -137,10 +131,6 @@ config M52277
bool
select MCF5227x
-config M547x
- bool
- select MCF547x_8x
-
choice
prompt "Target select"
optional
@@ -213,10 +203,6 @@ config TARGET_M54455EVB
bool "Support M54455EVB"
select M54455
-config TARGET_M5475EVB
- bool "Support M5475EVB"
- select M547x
-
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
@@ -244,7 +230,6 @@ source "board/freescale/m5373evb/Kconfig"
source "board/freescale/m54418twr/Kconfig"
source "board/freescale/m54451evb/Kconfig"
source "board/freescale/m54455evb/Kconfig"
-source "board/freescale/m547xevb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 7f23ff45887a..86b36e1a40e7 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -19,14 +19,12 @@ cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC
cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC
-cpuflags-$(CONFIG_MCF547x_8x) := -mcpu=5485 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
ldflags-$(CONFIG_MCF5441x) := --got=single
ldflags-$(CONFIG_MCF5445x) := --got=single
-ldflags-$(CONFIG_MCF547x_8x) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
diff --git a/arch/m68k/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile
deleted file mode 100644
index 0db3386aa850..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-# ccflags-y += -DET_DEBUG
-
-extra-y = start.o
-obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c
deleted file mode 100644
index c1361e705799..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/cpu.c
+++ /dev/null
@@ -1,153 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <vsprintf.h>
-#include <watchdog.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-
-#include <asm/immap.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
-
- out_be16(&gptmr->pre, 10);
- out_be16(&gptmr->cnt, 1);
-
- /* enable watchdog, set timeout to 0 and wait */
- out_8(&gptmr->mode, GPT_TMS_SGPIO);
- out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
-
- /* we don't return! */
- return 1;
-};
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- siu_t *siu = (siu_t *) MMAP_SIU;
- u16 id = 0;
-
- puts("CPU: ");
-
- switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
- case 0x0C:
- id = 5485;
- break;
- case 0x0D:
- id = 5484;
- break;
- case 0x0E:
- id = 5483;
- break;
- case 0x0F:
- id = 5482;
- break;
- case 0x10:
- id = 5481;
- break;
- case 0x11:
- id = 5480;
- break;
- case 0x12:
- id = 5475;
- break;
- case 0x13:
- id = 5474;
- break;
- case 0x14:
- id = 5473;
- break;
- case 0x15:
- id = 5472;
- break;
- case 0x16:
- id = 5471;
- break;
- case 0x17:
- id = 5470;
- break;
- }
-
- if (id) {
- char buf1[32], buf2[32];
-
- printf("Freescale MCF%d\n", id);
- printf(" CPU CLK %s MHz BUS CLK %s MHz\n",
- strmhz(buf1, gd->cpu_clk),
- strmhz(buf2, gd->bus_clk));
- }
-
- return 0;
-};
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#if defined(CONFIG_HW_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void hw_watchdog_reset(void)
-{
- gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
-
- out_8(&gptmr->ocpw, 0xa5);
-}
-
-int watchdog_disable(void)
-{
- gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
-
- /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- out_8(&gptmr->mode, 0);
- out_8(&gptmr->ctrl, 0);
-
- puts("WATCHDOG:disabled\n");
-
- return (0);
-}
-
-int watchdog_init(void)
-{
- gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
-
- out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
- out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
-
- out_8(&gptmr->mode, GPT_TMS_SGPIO);
- out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
- puts("WATCHDOG:enabled\n");
-
- return (0);
-}
-#endif /* CONFIG_HW_WATCHDOG */
-
-#if defined(CONFIG_FSLDMAFEC) || defined(CONFIG_MCFFEC)
-/* Default initializations for MCFFEC controllers. To override,
- * create a board-specific function called:
- * int board_eth_init(struct bd_info *bis)
- */
-
-int cpu_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FSLDMAFEC)
- mcdmafec_initialize(bis);
-#endif
-#if defined(CONFIG_MCFFEC)
- mcffec_initialize(bis);
-#endif
- return 0;
-}
-#endif
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c
deleted file mode 100644
index 8e42b6314123..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c
+++ /dev/null
@@ -1,150 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#include <common.h>
-#include <MCD_dma.h>
-#include <cpu_func.h>
-#include <init.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_CMD_NET)
-#include <config.h>
-#include <net.h>
-#include <asm/fec.h>
-#include <asm/fsl_mcdmafec.h>
-#endif
-
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
-
- out_be32(&xlbarb->adrto, 0x2000);
- out_be32(&xlbarb->datto, 0x2500);
- out_be32(&xlbarb->busto, 0x3000);
-
- out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
-
- /* Master Priority Enable */
- out_be32(&xlbarb->prien, 0xff);
- out_be32(&xlbarb->pri, 0);
-
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
- out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
- out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
- out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
-#endif
-
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
- out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
- out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
- out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
-#endif
-
-#ifdef CONFIG_SYS_I2C_FSL
- out_be16(&gpio->par_feci2cirq,
- GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
-#endif
-
- icache_enable();
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
- MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
- MCD_RELOC_TASKS);
-#endif
- return (0);
-}
-
-void uart_port_conf(int port)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
-
- /* Setup Ports: */
- switch (port) {
- case 0:
- out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
- break;
- case 1:
- out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
- break;
- case 2:
- out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
- break;
- case 3:
- out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
- break;
- }
-
- clrbits_8(pscsicr, 0x07);
-}
-
-#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(fec_info_t *info, int setclear)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- u32 fec0_base;
-
- if (fec_get_base_addr(0, &fec0_base))
- return -1;
-
- if (setclear) {
- if (info->iobase == fec0_base)
- setbits_be16(&gpio->par_feci2cirq, 0xf000);
- else
- setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
- } else {
- if (info->iobase == fec0_base)
- clrbits_be16(&gpio->par_feci2cirq, 0xf000);
- else
- clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
- }
- return 0;
-}
-#endif
diff --git a/arch/m68k/cpu/mcf547x_8x/interrupts.c b/arch/m68k/cpu/mcf547x_8x/interrupts.c
deleted file mode 100644
index 703090ddc258..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/interrupts.c
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-/* CPU specific interrupt routine */
-#include <common.h>
-#include <irq_func.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-
-int interrupt_init(void)
-{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-
- /* Make sure all interrupts are disabled */
- setbits_be32(&intp->imrh0, 0xffffffff);
- setbits_be32(&intp->imrl0, 0xffffffff);
-
- enable_interrupts();
-
- return 0;
-}
-
-#if defined(CONFIG_SLTTMR)
-void dtimer_intr_setup(void)
-{
- int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-
- out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
- clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
-}
-#endif
diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c
deleted file mode 100644
index 74ba68124f1a..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/pci.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-/*
- * PCI Configuration space access support
- */
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/immap.h>
-#include <linux/delay.h>
-
-#if defined(CONFIG_PCI)
-/* System RAM mapped over PCI */
-#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
-
-#define cfg_read(val, addr, type, op) *val = op((type)(addr));
-#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
-
-#define PCI_OP(rw, size, type, op, mask) \
-int pci_##rw##_cfg_##size(struct pci_controller *hose, \
- pci_dev_t dev, int offset, type val) \
-{ \
- u32 addr = 0; \
- u16 cfg_type = 0; \
- addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
- out_be32(hose->cfg_addr, addr); \
- cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
- __asm__ __volatile__("nop"); \
- __asm__ __volatile__("nop"); \
- out_be32(hose->cfg_addr, addr & 0x7fffffff); \
- return 0; \
-}
-
-PCI_OP(read, byte, u8 *, in_8, 3)
-PCI_OP(read, word, u16 *, in_le16, 2)
-PCI_OP(write, byte, u8, out_8, 3)
-PCI_OP(write, word, u16, out_le16, 2)
-PCI_OP(write, dword, u32, out_le32, 0)
-
-int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
- int offset, u32 * val)
-{
- u32 addr;
- u32 tmpv;
- u32 mask = 2; /* word access */
- /* Read lower 16 bits */
- addr = ((offset & 0xfc) | (dev) | 0x80000000);
- out_be32(hose->cfg_addr, addr);
- *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
- __asm__ __volatile__("nop");
- out_be32(hose->cfg_addr, addr & 0x7fffffff);
-
- /* Read upper 16 bits */
- offset += 2;
- addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
- out_be32(hose->cfg_addr, addr);
- tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
- __asm__ __volatile__("nop");
- out_be32(hose->cfg_addr, addr & 0x7fffffff);
-
- /* combine results into dword value */
- *val = (tmpv << 16) | *val;
-
- return 0;
-}
-
-void pci_mcf547x_8x_init(struct pci_controller *hose)
-{
- pci_t *pci = (pci_t *) MMAP_PCI;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- /* Port configuration */
- out_be16(&gpio->par_pcibg,
- GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
- GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
- GPIO_PAR_PCIBG_PCIBG4(3));
- out_be16(&gpio->par_pcibr,
- GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
- GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
- GPIO_PAR_PCIBR_PCIBR4(3));
-
- /* Assert reset bit */
- setbits_be32(&pci->gscr, PCI_GSCR_PR);
-
- out_be32(&pci->tcr1, PCI_TCR1_P);
-
- /* Initiator windows */
- out_be32(&pci->iw0btar,
- CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
- out_be32(&pci->iw1btar,
- CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
- out_be32(&pci->iw2btar,
- CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
-
- out_be32(&pci->iwcr,
- PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
- PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
-
- out_be32(&pci->icr, 0);
-
- /* Enable bus master and mem access */
- out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
-
- /* Cache line size and master latency */
- out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
- out_be32(&pci->cr2, 0);
-
-#ifdef CONFIG_SYS_PCI_BAR0
- out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
- out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
-#endif
-#ifdef CONFIG_SYS_PCI_BAR1
- out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
- out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
-#endif
-
- /* Deassert reset bit */
- clrbits_be32(&pci->gscr, PCI_GSCR_PR);
- udelay(1000);
-
- /* Enable PCI bus master support */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
- CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
-
- pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
- CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
-
- pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
- CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 3;
-
- hose->cfg_addr = &(pci->car);
- hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
-
- pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
- pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
- pci_write_cfg_dword);
-
- /* Hose scan */
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
-#endif /* CONFIG_PCI */
diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c
deleted file mode 100644
index dc076fc6e814..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <irq_func.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/timer.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static ulong timestamp;
-
-#if defined(CONFIG_SLTTMR)
-#ifndef CONFIG_SYS_UDELAY_BASE
-# error "uDelay base not defined!"
-#endif
-
-#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
-# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
-#endif
-extern void dtimer_intr_setup(void);
-
-void __udelay(unsigned long usec)
-{
- slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
- u32 now, freq;
-
- /* 1 us period */
- freq = CONFIG_SYS_TIMER_PRESCALER;
-
- /* Disable */
- out_be32(&timerp->cr, 0);
- out_be32(&timerp->tcnt, usec * freq);
- out_be32(&timerp->cr, SLT_CR_TEN);
-
- now = in_be32(&timerp->cnt);
- while (now != 0)
- now = in_be32(&timerp->cnt);
-
- setbits_be32(&timerp->sr, SLT_SR_ST);
- out_be32(&timerp->cr, 0);
-}
-
-void dtimer_interrupt(void *not_used)
-{
- slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
-
- /* check for timer interrupt asserted */
- if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
- setbits_be32(&timerp->sr, SLT_SR_ST);
- timestamp++;
- return;
- }
-}
-
-int timer_init(void)
-{
- slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
-
- timestamp = 0;
-
- /* disable timer */
- out_be32(&timerp->cr, 0);
- out_be32(&timerp->tcnt, 0);
- /* clear status */
- out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
-
- /* initialize and enable timer interrupt */
- irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
-
- /* Interrupt every ms */
- out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
-
- dtimer_intr_setup();
-
- /* set a period of 1us, set timer mode to restart and
- enable timer and interrupt */
- out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
- return 0;
-}
-
-ulong get_timer(ulong base)
-{
- return (timestamp - base);
-}
-
-#endif /* CONFIG_SLTTMR */
diff --git a/arch/m68k/cpu/mcf547x_8x/speed.c b/arch/m68k/cpu/mcf547x_8x/speed.c
deleted file mode 100644
index bbcf601f38fb..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/speed.c
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-
-#include <asm/immap.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
-{
- gd->bus_clk = CONFIG_SYS_CLK;
- gd->cpu_clk = (gd->bus_clk * 2);
-
-#ifdef CONFIG_SYS_I2C_FSL
- gd->arch.i2c1_clk = gd->bus_clk;
-#endif
-
- return (0);
-}
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
deleted file mode 100644
index b70842b2b83d..000000000000
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ /dev/null
@@ -1,264 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include "version.h"
-#include <asm/cache.h>
-
-#define _START _start
-#define _FAULT _fault
-
-#define SAVE_ALL \
- move.w #0x2700,%sr; /* disable intrs */ \
- subl #60,%sp; /* space for 15 regs */ \
- moveml %d0-%d7/%a0-%a6,%sp@;
-
-#define RESTORE_ALL \
- moveml %sp@,%d0-%d7/%a0-%a6; \
- addl #60,%sp; /* space for 15 regs */ \
- rte;
-
-.text
-
-/*
- * Vector table. This is used for initial platform startup.
- * These vectors are to catch any un-intended traps.
- */
-_vectors:
-INITSP: .long 0x00000000 /* Initial SP */
-INITPC: .long _START /* Initial PC */
-
-vector02_0F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-/* Reserved */
-vector10_17:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector18_1F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-/* TRAP #0 - #15 */
-vector20_2F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-/* Reserved */
-vector30_3F:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector64_127:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector128_191:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-vector192_255:
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-.text
-
-.globl _start
-_start:
- nop
- nop
- move.w #0x2700,%sr /* Mask off Interrupt */
-
- /* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
- movec %d0, %VBR
-
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
- movec %d0, %RAMBAR0
-
- move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
- movec %d0, %RAMBAR1
-
- move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
- move.c %d0, %MBAR
-
- /* invalidate and disable cache */
- move.l #0x01040100, %d0 /* Invalidate cache cmd */
- movec %d0, %CACR /* Invalidate cache */
- move.l #0, %d0
- movec %d0, %ACR0
- movec %d0, %ACR1
- movec %d0, %ACR2
- movec %d0, %ACR3
-
- /* initialize general use internal ram */
- move.l #0, %d0
- move.l #(ICACHE_STATUS), %a1 /* icache */
- move.l #(DCACHE_STATUS), %a2 /* icache */
- move.l %d0, (%a1)
- move.l %d0, (%a2)
-
- /* put relocation table address to a5 */
- move.l #__got_start, %a5
-
- /* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
-
- /*
- * if configured, malloc_f arena will be reserved first,
- * then (and always) gd struct space will be reserved
- */
- move.l %sp, -(%sp)
- move.l #board_init_f_alloc_reserve, %a1
- jsr (%a1)
-
- /* update stack and frame-pointers */
- move.l %d0, %sp
- move.l %sp, %fp
-
- /* initialize reserved area */
- move.l %d0, -(%sp)
- move.l #board_init_f_init_reserve, %a1
- jsr (%a1)
-
- /* run low-level CPU init code (from flash) */
- jbsr cpu_init_f
-
- /* run low-level board init code (from flash) */
- clr.l %sp at -
- jbsr board_init_f
-
- /* board_init_f() does not return */
-
-/******************************************************************************/
-
-/*
- * void relocate_code(addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
-.globl relocate_code
-relocate_code:
- link.w %a6,#0
- move.l 8(%a6), %sp /* set new stack pointer */
-
- move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
- move.l 16(%a6), %a0 /* Save copy of Destination Address */
-
- move.l #CONFIG_SYS_MONITOR_BASE, %a1
- move.l #__init_end, %a2
- move.l %a0, %a3
-
- /* copy the code to RAM */
-1:
- move.l (%a1)+, (%a3)+
- cmp.l %a1,%a2
- bgt.s 1b
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- move.l %a0, %a1
- add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
- jmp (%a1)
-
-in_ram:
-
-clear_bss:
- /*
- * Now clear BSS segment
- */
- move.l %a0, %a1
- add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a0, %d1
- add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
-6:
- clr.l (%a1)+
- cmp.l %a1,%d1
- bgt.s 6b
-
- /*
- * fix got table in RAM
- */
- move.l %a0, %a1
- add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
- move.l %a1,%a5 /* fix got pointer register a5 */
-
- move.l %a0, %a2
- add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
- move.l (%a1),%d1
- sub.l #_start,%d1
- add.l %a0,%d1
- move.l %d1,(%a1)+
- cmp.l %a2, %a1
- bne 7b
-
- /* calculate relative jump to board_init_r in ram */
- move.l %a0, %a1
- add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
-
- /* set parameters for board_init_r */
- move.l %a0,-(%sp) /* dest_addr */
- move.l %d0,-(%sp) /* gd */
- jsr (%a1)
-
-/******************************************************************************/
-
-/* exception code */
-.globl _fault
-_fault:
- bra _fault
-
-.globl _exc_handler
-_exc_handler:
- SAVE_ALL
- movel %sp,%sp at -
- bsr exc_handler
- addql #4,%sp
- RESTORE_ALL
-
-.globl _int_handler
-_int_handler:
- SAVE_ALL
- movel %sp,%sp at -
- bsr int_handler
- addql #4,%sp
- RESTORE_ALL
-
-/******************************************************************************/
-
-.globl version_string
-version_string:
-.ascii U_BOOT_VERSION_STRING, "\0"
-.align 4
diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts
deleted file mode 100644
index 7895b520cf72..000000000000
--- a/arch/m68k/dts/M5475AFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475AFE";
- compatible = "fsl,M5475AFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts
deleted file mode 100644
index ffbc2d6a063e..000000000000
--- a/arch/m68k/dts/M5475BFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475BFE";
- compatible = "fsl,M5475BFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts
deleted file mode 100644
index f1033f7efbbf..000000000000
--- a/arch/m68k/dts/M5475CFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475CFE";
- compatible = "fsl,M5475CFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts
deleted file mode 100644
index 69a8faba83ba..000000000000
--- a/arch/m68k/dts/M5475DFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475DFE";
- compatible = "fsl,M5475DFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts
deleted file mode 100644
index 3c898958c8fa..000000000000
--- a/arch/m68k/dts/M5475EFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475EFE";
- compatible = "fsl,M5475EFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts
deleted file mode 100644
index bb3c21588f54..000000000000
--- a/arch/m68k/dts/M5475FFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475FFE";
- compatible = "fsl,M5475FFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts
deleted file mode 100644
index 75080fa7371e..000000000000
--- a/arch/m68k/dts/M5475GFE.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf54xx.dtsi"
-
-/ {
- model = "Freescale M5475GFE";
- compatible = "fsl,M5475GFE";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
index 0a356b8e3728..47260a101d8a 100644
--- a/arch/m68k/dts/Makefile
+++ b/arch/m68k/dts/Makefile
@@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
M54455EVB_i66.dtb
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
-dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \
- M5475BFE.dtb \
- M5475CFE.dtb \
- M5475DFE.dtb \
- M5475EFE.dtb \
- M5475FFE.dtb \
- M5475GFE.dtb
targets += $(dtb-y)
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index a1eeabc2af93..fabec0ae92e3 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -19,7 +19,7 @@
#define CONFIG_CF_V3
#endif
-#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
+#if defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h
index ddd8f3380542..7848dbdff490 100644
--- a/arch/m68k/include/asm/coldfire/dspi.h
+++ b/arch/m68k/include/asm/coldfire/dspi.h
@@ -20,14 +20,8 @@ typedef struct dspi {
u32 tfr; /* 0x34 - PUSHR */
u16 resv1; /* 0x38 */
u16 rfr; /* 0x3A - POPR */
-#ifdef CONFIG_MCF547x_8x
- u32 tfdr[4]; /* 0x3C */
- u8 resv2[0x30]; /* 0x40 */
- u32 rfdr[4]; /* 0x7C */
-#else
u32 tfdr[16]; /* 0x3C */
u32 rfdr[16]; /* 0x7C */
-#endif
} dspi_t;
/* Module configuration */
diff --git a/arch/m68k/include/asm/coldfire/eport.h b/arch/m68k/include/asm/coldfire/eport.h
index 0e64bef5ed62..eb5c66636129 100644
--- a/arch/m68k/include/asm/coldfire/eport.h
+++ b/arch/m68k/include/asm/coldfire/eport.h
@@ -11,18 +11,6 @@
/* Edge Port Module (EPORT) */
typedef struct eport {
-#ifdef CONFIG_MCF547x_8x
- u16 par; /* 0x00 */
- u16 res0; /* 0x02 */
- u8 ddr; /* 0x04 */
- u8 ier; /* 0x05 */
- u16 res1; /* 0x06 */
- u8 dr; /* 0x08 */
- u8 pdr; /* 0x09 */
- u16 res2; /* 0x0A */
- u8 fr; /* 0x0C */
- u8 res3[3]; /* 0x0D */
-#else
u16 par; /* 0x00 Pin Assignment */
u8 ddr; /* 0x02 Data Direction */
u8 ier; /* 0x03 Interrupt Enable */
@@ -30,7 +18,6 @@ typedef struct eport {
u8 pdr; /* 0x05 Pin Data */
u8 fr; /* 0x06 Flag */
u8 res0;
-#endif
} eport_t;
/* EPPAR */
diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h
index cdb8119d3ea9..759c8cfc43de 100644
--- a/arch/m68k/include/asm/fec.h
+++ b/arch/m68k/include/asm/fec.h
@@ -337,13 +337,8 @@ typedef struct fec {
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
-#ifdef CONFIG_MCF547x_8x
-typedef struct fec_info_dma fec_info_t;
-#define FEC_T fecdma_t
-#else
typedef struct fec_info_s fec_info_t;
#define FEC_T fec_t
-#endif
int fecpin_setclear(fec_info_t *info, int setclear);
int mii_discover_phy(fec_info_t *info);
diff --git a/arch/m68k/include/asm/immap_547x_8x.h b/arch/m68k/include/asm/immap_547x_8x.h
deleted file mode 100644
index 5e1345684de0..000000000000
--- a/arch/m68k/include/asm/immap_547x_8x.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF547x_8x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#ifndef __IMMAP_547x_8x__
-#define __IMMAP_547x_8x__
-
-#define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100)
-#define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700)
-#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800)
-#define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900)
-#define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00)
-#define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00)
-#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00)
-#define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00)
-#define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00)
-#define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800)
-#define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900)
-#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00)
-#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000)
-#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800)
-#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000)
-#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800)
-#define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000)
-#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000)
-#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00)
-#define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000)
-
-#include <asm/coldfire/dspi.h>
-#include <asm/coldfire/eport.h>
-#include <asm/coldfire/flexbus.h>
-#include <asm/coldfire/flexcan.h>
-#include <asm/coldfire/intctrl.h>
-
-typedef struct siu {
- u32 mbar; /* 0x00 */
- u32 drv; /* 0x04 */
- u32 rsvd1[2]; /* 0x08 - 0x1F */
- u32 sbcr; /* 0x10 */
- u32 rsvd2[3]; /* 0x14 - 0x1F */
- u32 cs0cfg; /* 0x20 */
- u32 cs1cfg; /* 0x24 */
- u32 cs2cfg; /* 0x28 */
- u32 cs3cfg; /* 0x2C */
- u32 rsvd3[2]; /* 0x30 - 0x37 */
- u32 secsacr; /* 0x38 */
- u32 rsvd4[2]; /* 0x3C - 0x43 */
- u32 rsr; /* 0x44 */
- u32 rsvd5[2]; /* 0x48 - 0x4F */
- u32 jtagid; /* 0x50 */
-} siu_t;
-
-typedef struct sdram {
- u32 mode; /* 0x00 */
- u32 ctrl; /* 0x04 */
- u32 cfg1; /* 0x08 */
- u32 cfg2; /* 0x0c */
-} sdram_t;
-
-typedef struct xlb_arb {
- u32 cfg; /* 0x240 */
- u32 ver; /* 0x244 */
- u32 sr; /* 0x248 */
- u32 imr; /* 0x24c */
- u32 adrcap; /* 0x250 */
- u32 sigcap; /* 0x254 */
- u32 adrto; /* 0x258 */
- u32 datto; /* 0x25c */
- u32 busto; /* 0x260 */
- u32 prien; /* 0x264 */
- u32 pri; /* 0x268 */
-} xlbarb_t;
-
-typedef struct gptmr {
- u8 ocpw;
- u8 octict;
- u8 ctrl;
- u8 mode;
-
- u16 pre; /* Prescale */
- u16 cnt;
-
- u16 pwmwidth;
- u8 pwmop; /* Output Polarity */
- u8 pwmld; /* Immediate Update */
-
- u16 cap; /* Capture internal counter */
- u8 ovfpin; /* Ovf and Pin */
- u8 intr; /* Interrupts */
-} gptmr_t;
-
-typedef struct canex_ctrl {
- can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
-} canex_t;
-
-
-typedef struct slt {
- u32 tcnt; /* 0x00 */
- u32 cr; /* 0x04 */
- u32 cnt; /* 0x08 */
- u32 sr; /* 0x0C */
-} slt_t;
-
-typedef struct gpio {
- /* Port Output Data Registers */
- u8 podr_fbctl; /*0x00 */
- u8 podr_fbcs; /*0x01 */
- u8 podr_dma; /*0x02 */
- u8 rsvd1; /*0x03 */
- u8 podr_fec0h; /*0x04 */
- u8 podr_fec0l; /*0x05 */
- u8 podr_fec1h; /*0x06 */
- u8 podr_fec1l; /*0x07 */
- u8 podr_feci2c; /*0x08 */
- u8 podr_pcibg; /*0x09 */
- u8 podr_pcibr; /*0x0A */
- u8 rsvd2; /*0x0B */
- u8 podr_psc3psc2; /*0x0C */
- u8 podr_psc1psc0; /*0x0D */
- u8 podr_dspi; /*0x0E */
- u8 rsvd3; /*0x0F */
-
- /* Port Data Direction Registers */
- u8 pddr_fbctl; /*0x10 */
- u8 pddr_fbcs; /*0x11 */
- u8 pddr_dma; /*0x12 */
- u8 rsvd4; /*0x13 */
- u8 pddr_fec0h; /*0x14 */
- u8 pddr_fec0l; /*0x15 */
- u8 pddr_fec1h; /*0x16 */
- u8 pddr_fec1l; /*0x17 */
- u8 pddr_feci2c; /*0x18 */
- u8 pddr_pcibg; /*0x19 */
- u8 pddr_pcibr; /*0x1A */
- u8 rsvd5; /*0x1B */
- u8 pddr_psc3psc2; /*0x1C */
- u8 pddr_psc1psc0; /*0x1D */
- u8 pddr_dspi; /*0x1E */
- u8 rsvd6; /*0x1F */
-
- /* Port Pin Data/Set Data Registers */
- u8 ppdsdr_fbctl; /*0x20 */
- u8 ppdsdr_fbcs; /*0x21 */
- u8 ppdsdr_dma; /*0x22 */
- u8 rsvd7; /*0x23 */
- u8 ppdsdr_fec0h; /*0x24 */
- u8 ppdsdr_fec0l; /*0x25 */
- u8 ppdsdr_fec1h; /*0x26 */
- u8 ppdsdr_fec1l; /*0x27 */
- u8 ppdsdr_feci2c; /*0x28 */
- u8 ppdsdr_pcibg; /*0x29 */
- u8 ppdsdr_pcibr; /*0x2A */
- u8 rsvd8; /*0x2B */
- u8 ppdsdr_psc3psc2; /*0x2C */
- u8 ppdsdr_psc1psc0; /*0x2D */
- u8 ppdsdr_dspi; /*0x2E */
- u8 rsvd9; /*0x2F */
-
- /* Port Clear Output Data Registers */
- u8 pclrr_fbctl; /*0x30 */
- u8 pclrr_fbcs; /*0x31 */
- u8 pclrr_dma; /*0x32 */
- u8 rsvd10; /*0x33 */
- u8 pclrr_fec0h; /*0x34 */
- u8 pclrr_fec0l; /*0x35 */
- u8 pclrr_fec1h; /*0x36 */
- u8 pclrr_fec1l; /*0x37 */
- u8 pclrr_feci2c; /*0x38 */
- u8 pclrr_pcibg; /*0x39 */
- u8 pclrr_pcibr; /*0x3A */
- u8 rsvd11; /*0x3B */
- u8 pclrr_psc3psc2; /*0x3C */
- u8 pclrr_psc1psc0; /*0x3D */
- u8 pclrr_dspi; /*0x3E */
- u8 rsvd12; /*0x3F */
-
- /* Pin Assignment Registers */
- u16 par_fbctl; /*0x40 */
- u8 par_fbcs; /*0x42 */
- u8 par_dma; /*0x43 */
- u16 par_feci2cirq; /*0x44 */
- u16 rsvd13; /*0x46 */
- u16 par_pcibg; /*0x48 */
- u16 par_pcibr; /*0x4A */
- u8 par_psc3; /*0x4C */
- u8 par_psc2; /*0x4D */
- u8 par_psc1; /*0x4E */
- u8 par_psc0; /*0x4F */
- u16 par_dspi; /*0x50 */
- u8 par_timer; /*0x52 */
- u8 rsvd14; /*0x53 */
-} gpio_t;
-
-typedef struct pci {
- u32 idr; /* 0x00 Device Id / Vendor Id */
- u32 scr; /* 0x04 Status / command */
- u32 ccrir; /* 0x08 Class Code / Revision Id */
- u32 cr1; /* 0x0c Configuration 1 */
- u32 bar0; /* 0x10 Base address register 0 */
- u32 bar1; /* 0x14 Base address register 1 */
- u32 bar2; /* 0x18 NA */
- u32 bar3; /* 0x1c NA */
- u32 bar4; /* 0x20 NA */
- u32 bar5; /* 0x24 NA */
- u32 ccpr; /* 0x28 Cardbus CIS Pointer */
- u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
- u32 erbar; /* 0x30 Expansion ROM Base Address */
- u32 cpr; /* 0x34 Capabilities Pointer */
- u32 rsvd1; /* 0x38 */
- u32 cr2; /* 0x3c Configuration 2 */
- u32 rsvd2[8]; /* 0x40 - 0x5f */
-
- /* General control / status registers */
- u32 gscr; /* 0x60 Global Status / Control */
- u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
- u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
- u32 tcr1; /* 0x6c Target Control 1 Register */
- u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
- u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
- u32 iw2btar; /* 0x78 NA */
- u32 rsvd3; /* 0x7c */
- u32 iwcr; /* 0x80 Initiator Window Configuration */
- u32 icr; /* 0x84 Initiator Control */
- u32 isr; /* 0x88 Initiator Status */
- u32 tcr2; /* 0x8c NA */
- u32 tbatr0; /* 0x90 NA */
- u32 tbatr1; /* 0x94 NA */
- u32 tbatr2; /* 0x98 NA */
- u32 tbatr3; /* 0x9c NA */
- u32 tbatr4; /* 0xa0 NA */
- u32 tbatr5; /* 0xa4 NA */
- u32 intr; /* 0xa8 NA */
- u32 rsvd4[19]; /* 0xac - 0xf7 */
- u32 car; /* 0xf8 Configuration Address */
-} pci_t;
-
-typedef struct pci_arbiter {
- /* Pci Arbiter Registers */
- union {
- u32 acr; /* Arbiter Control */
- u32 asr; /* Arbiter Status */
- };
-} pciarb_t;
-#endif /* __IMMAP_547x_8x__ */
diff --git a/arch/m68k/include/asm/m547x_8x.h b/arch/m68k/include/asm/m547x_8x.h
deleted file mode 100644
index 30f12004b76b..000000000000
--- a/arch/m68k/include/asm/m547x_8x.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#ifndef mcf547x_8x_h
-#define mcf547x_8x_h
-
-/*********************************************************************
-* XLB Arbiter (XLB)
-*********************************************************************/
-/* Bit definitions and macros for XARB_CFG */
-#define XARB_CFG_AT (0x00000002)
-#define XARB_CFG_DT (0x00000004)
-#define XARB_CFG_BA (0x00000008)
-#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
-#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
-#define XARB_CFG_PLDIS (0x80000000)
-
-/* Bit definitions and macros for XARB_SR */
-#define XARB_SR_AT (0x00000001)
-#define XARB_SR_DT (0x00000002)
-#define XARB_SR_BA (0x00000004)
-#define XARB_SR_TTM (0x00000008)
-#define XARB_SR_ECW (0x00000010)
-#define XARB_SR_TTR (0x00000020)
-#define XARB_SR_TTA (0x00000040)
-#define XARB_SR_MM (0x00000080)
-#define XARB_SR_SEA (0x00000100)
-
-/* Bit definitions and macros for XARB_IMR */
-#define XARB_IMR_ATE (0x00000001)
-#define XARB_IMR_DTE (0x00000002)
-#define XARB_IMR_BAE (0x00000004)
-#define XARB_IMR_TTME (0x00000008)
-#define XARB_IMR_ECWE (0x00000010)
-#define XARB_IMR_TTRE (0x00000020)
-#define XARB_IMR_TTAE (0x00000040)
-#define XARB_IMR_MME (0x00000080)
-#define XARB_IMR_SEAE (0x00000100)
-
-/* Bit definitions and macros for XARB_SIGCAP */
-#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
-#define XARB_SIGCAP_TBST (0x00000020)
-#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
-
-/* Bit definitions and macros for XARB_PRIEN */
-#define XARB_PRIEN_M0 (0x00000001)
-#define XARB_PRIEN_M2 (0x00000004)
-#define XARB_PRIEN_M3 (0x00000008)
-
-/* Bit definitions and macros for XARB_PRI */
-#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
-#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
-#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
-
-/*********************************************************************
-* General Purpose I/O (GPIO)
-*********************************************************************/
-/* Bit definitions and macros for GPIO_PAR_FBCTL */
-#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
-#define GPIO_PAR_FBCTL_TA (0x0004)
-#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
-#define GPIO_PAR_FBCTL_OE (0x0040)
-#define GPIO_PAR_FBCTL_BWE0 (0x0100)
-#define GPIO_PAR_FBCTL_BWE1 (0x0400)
-#define GPIO_PAR_FBCTL_BWE2 (0x1000)
-#define GPIO_PAR_FBCTL_BWE3 (0x4000)
-#define GPIO_PAR_FBCTL_TS_GPIO (0)
-#define GPIO_PAR_FBCTL_TS_TBST (2)
-#define GPIO_PAR_FBCTL_TS_TS (3)
-#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
-#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
-#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
-
-/* Bit definitions and macros for GPIO_PAR_FBCS */
-#define GPIO_PAR_FBCS_CS1 (0x02)
-#define GPIO_PAR_FBCS_CS2 (0x04)
-#define GPIO_PAR_FBCS_CS3 (0x08)
-#define GPIO_PAR_FBCS_CS4 (0x10)
-#define GPIO_PAR_FBCS_CS5 (0x20)
-
-/* Bit definitions and macros for GPIO_PAR_DMA */
-#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
-#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
-#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
-#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
-#define GPIO_PAR_DMA_DACKx_GPIO (0)
-#define GPIO_PAR_DMA_DACKx_TOUT (2)
-#define GPIO_PAR_DMA_DACKx_DACK (3)
-#define GPIO_PAR_DMA_DREQx_GPIO (0)
-#define GPIO_PAR_DMA_DREQx_TIN (2)
-#define GPIO_PAR_DMA_DREQx_DREQ (3)
-
-/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
-#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
-#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
-#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
-#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
-#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
-#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
-#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
-#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
-#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
-#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
-#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
-#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
-#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
-#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
-#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
-#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
-
-/* Bit definitions and macros for GPIO_PAR_PCIBG */
-#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
-#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
-#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
-
-/* Bit definitions and macros for GPIO_PAR_PCIBR */
-#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
-#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
-#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
-
-/* Bit definitions and macros for GPIO_PAR_PSC3 */
-#define GPIO_PAR_PSC3_TXD3 (0x04)
-#define GPIO_PAR_PSC3_RXD3 (0x08)
-#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
-#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
-#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
-#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
-#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
-#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
-#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
-#define GPIO_PAR_PSC3_RTS3_RTS (0x30)
-#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
-
-/* Bit definitions and macros for GPIO_PAR_PSC2 */
-#define GPIO_PAR_PSC2_TXD2 (0x04)
-#define GPIO_PAR_PSC2_RXD2 (0x08)
-#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
-#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
-#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
-#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
-#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
-#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
-#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
-#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
-#define GPIO_PAR_PSC2_RTS2_RTS (0x30)
-
-/* Bit definitions and macros for GPIO_PAR_PSC1 */
-#define GPIO_PAR_PSC1_TXD1 (0x04)
-#define GPIO_PAR_PSC1_RXD1 (0x08)
-#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
-#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
-#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
-#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
-#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
-#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
-#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
-#define GPIO_PAR_PSC1_RTS1_RTS (0x30)
-
-/* Bit definitions and macros for GPIO_PAR_PSC0 */
-#define GPIO_PAR_PSC0_TXD0 (0x04)
-#define GPIO_PAR_PSC0_RXD0 (0x08)
-#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
-#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
-#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
-#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
-#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
-#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
-#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
-#define GPIO_PAR_PSC0_RTS0_RTS (0x30)
-
-/* Bit definitions and macros for GPIO_PAR_DSPI */
-#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
-#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
-#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
-#define GPIO_PAR_DSPI_CS5 (0x1000)
-#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
-#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
-#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
-#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
-#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
-#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
-#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
-#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
-#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
-#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
-#define GPIO_PAR_DSPI_CS0_RTS (0x0080)
-#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
-#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
-#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
-#define GPIO_PAR_DSPI_SCK_CTS (0x0020)
-#define GPIO_PAR_DSPI_SCK_SCK (0x0030)
-#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
-#define GPIO_PAR_DSPI_SIN_RXD (0x0008)
-#define GPIO_PAR_DSPI_SIN_SIN (0x000C)
-#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
-#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
-#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
-
-/* Bit definitions and macros for GPIO_PAR_TIMER */
-#define GPIO_PAR_TIMER_TOUT2 (0x01)
-#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
-#define GPIO_PAR_TIMER_TOUT3 (0x08)
-#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
-#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
-#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
-#define GPIO_PAR_TIMER_TIN3_TIN (0x30)
-#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
-#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
-#define GPIO_PAR_TIMER_TIN2_TIN (0x06)
-
-/*********************************************************************
-* Slice Timer (SLT)
-*********************************************************************/
-#define SLT_CR_RUN (0x04000000)
-#define SLT_CR_IEN (0x02000000)
-#define SLT_CR_TEN (0x01000000)
-
-#define SLT_SR_BE (0x02000000)
-#define SLT_SR_ST (0x01000000)
-
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
-#define INT0_LO_RSVD0 (0)
-#define INT0_LO_EPORT1 (1)
-#define INT0_LO_EPORT2 (2)
-#define INT0_LO_EPORT3 (3)
-#define INT0_LO_EPORT4 (4)
-#define INT0_LO_EPORT5 (5)
-#define INT0_LO_EPORT6 (6)
-#define INT0_LO_EPORT7 (7)
-#define INT0_LO_EP0ISR (15)
-#define INT0_LO_EP1ISR (16)
-#define INT0_LO_EP2ISR (17)
-#define INT0_LO_EP3ISR (18)
-#define INT0_LO_EP4ISR (19)
-#define INT0_LO_EP5ISR (20)
-#define INT0_LO_EP6ISR (21)
-#define INT0_LO_USBISR (22)
-#define INT0_LO_USBAISR (23)
-#define INT0_LO_USB (24)
-#define INT1_LO_DSPI_RFOF_TFUF (25)
-#define INT1_LO_DSPI_RFOF (26)
-#define INT1_LO_DSPI_RFDF (27)
-#define INT1_LO_DSPI_TFUF (28)
-#define INT1_LO_DSPI_TCF (29)
-#define INT1_LO_DSPI_TFFF (30)
-#define INT1_LO_DSPI_EOQF (31)
-
-#define INT0_HI_UART3 (32)
-#define INT0_HI_UART2 (33)
-#define INT0_HI_UART1 (34)
-#define INT0_HI_UART0 (35)
-#define INT0_HI_COMMTIM_TC (36)
-#define INT0_HI_SEC (37)
-#define INT0_HI_FEC1 (38)
-#define INT0_HI_FEC0 (39)
-#define INT0_HI_I2C (40)
-#define INT0_HI_PCIARB (41)
-#define INT0_HI_CBPCI (42)
-#define INT0_HI_XLBPCI (43)
-#define INT0_HI_XLBARB (47)
-#define INT0_HI_DMA (48)
-#define INT0_HI_CAN0_ERROR (49)
-#define INT0_HI_CAN0_BUSOFF (50)
-#define INT0_HI_CAN0_MBOR (51)
-#define INT0_HI_SLT1 (53)
-#define INT0_HI_SLT0 (54)
-#define INT0_HI_CAN1_ERROR (55)
-#define INT0_HI_CAN1_BUSOFF (56)
-#define INT0_HI_CAN1_MBOR (57)
-#define INT0_HI_GPT3 (59)
-#define INT0_HI_GPT2 (60)
-#define INT0_HI_GPT1 (61)
-#define INT0_HI_GPT0 (62)
-
-/*********************************************************************
-* General Purpose Timers (GPTMR)
-*********************************************************************/
-/* Enable and Mode Select */
-#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
-#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
-#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
-#define GPT_CTRL_CE 0x10 /* Counter Enable */
-#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
-#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
-#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
-#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
-#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
-#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
-#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
-#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
-
-#define GPT_PWM_WIDTH(x) (x & 0xffff)
-
-/* Status */
-#define GPT_STA_CAPTURE(x) (x & 0xffff)
-
-#define GPT_OVFPIN_OVF(x) (x & 0x70)
-#define GPT_OVFPIN_PIN 0x01
-
-#define GPT_INT_TEXP 0x08
-#define GPT_INT_PWMP 0x04
-#define GPT_INT_COMP 0x02
-#define GPT_INT_CAPT 0x01
-
-/*********************************************************************
-* PCI
-*********************************************************************/
-
-/* Bit definitions and macros for SCR */
-#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
-#define PCI_SCR_SE (0x40000000) /* System error signalled */
-#define PCI_SCR_MA (0x20000000) /* Master aboart received */
-#define PCI_SCR_TR (0x10000000) /* Target abort received */
-#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
-#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
-#define PCI_SCR_DP (0x01000000) /* Master data parity err */
-#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
-#define PCI_SCR_R (0x00400000) /* Reserved */
-#define PCI_SCR_66M (0x00200000) /* 66Mhz */
-#define PCI_SCR_C (0x00100000) /* Capabilities list */
-#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
-#define PCI_SCR_S (0x00000100) /* SERR enable */
-#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
-#define PCI_SCR_PER (0x00000040) /* Parity error response */
-#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
-#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
-#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
-#define PCI_SCR_B (0x00000004) /* Bus master enable */
-#define PCI_SCR_M (0x00000002) /* Memory access control */
-#define PCI_SCR_IO (0x00000001) /* I/O access control */
-
-#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
-#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
-#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
-#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
-
-#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
-#define PCI_BAR_BAR1(x) (x & 0xC0000000)
-#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
-#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
-#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
-
-#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
-#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
-#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
-#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
-
-#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
-#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
-#define PCI_GSCR_SE (0x10000000) /* SERR detected */
-#define PCI_GSCR_ER (0x08000000) /* Error response detected */
-#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
-#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
-#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
-#define PCI_GSCR_PR (0x00000001) /* PCI reset */
-
-#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
-#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
-#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
-#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
-
-#define PCI_TCR1_B5E (0x00002000) /* */
-#define PCI_TCR1_B4E (0x00001000) /* */
-#define PCI_TCR1_B3E (0x00000800) /* */
-#define PCI_TCR1_B2E (0x00000400) /* */
-#define PCI_TCR1_B1E (0x00000200) /* */
-#define PCI_TCR1_B0E (0x00000100) /* */
-#define PCI_TCR1_CR (0x00000001) /* */
-
-#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
-#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
-#define PCI_TBATR_EN (0x00000001) /* Enable */
-
-#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
-#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
-#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
-#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
-#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
-#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
-#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
-#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
-#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
-
-#define PCI_ICR_REE (0x04000000) /* Retry error enable */
-#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
-#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
-#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
-
-#define PCIARB_ACR_DS (0x80000000)
-#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
-#define PCIARB_ARC_INTMINTEN (0x00010000)
-#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
-#define PCIARB_ARC_INTMPRI (0x00000001)
-
-#endif /* mcf547x_8x_h */
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index 68f2eef584b7..aa2b93e0e0fb 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -80,7 +80,7 @@ void icache_invalid(void)
}
/*
- * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
+ * data cache only for ColdFire V4 such as MCF5445x
* the dcache will be dummy in ColdFire V2 and V3
*/
void dcache_enable(void)
diff --git a/board/freescale/m547xevb/Kconfig b/board/freescale/m547xevb/Kconfig
deleted file mode 100644
index 8cfe20ab8dd4..000000000000
--- a/board/freescale/m547xevb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M5475EVB
-
-config SYS_CPU
- default "mcf547x_8x"
-
-config SYS_BOARD
- default "m547xevb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M5475EVB"
-
-endif
diff --git a/board/freescale/m547xevb/MAINTAINERS b/board/freescale/m547xevb/MAINTAINERS
deleted file mode 100644
index 0d821eb011f1..000000000000
--- a/board/freescale/m547xevb/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-M547XEVB BOARD
-M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S: Maintained
-F: board/freescale/m547xevb/
-F: include/configs/M5475EVB.h
-F: configs/M5475AFE_defconfig
-F: configs/M5475BFE_defconfig
-F: configs/M5475CFE_defconfig
-F: configs/M5475DFE_defconfig
-F: configs/M5475EFE_defconfig
-F: configs/M5475FFE_defconfig
-F: configs/M5475GFE_defconfig
diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile
deleted file mode 100644
index 29fe9dad775f..000000000000
--- a/board/freescale/m547xevb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y = m547xevb.o
diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README
deleted file mode 100644
index 6b4fbe5c25d3..000000000000
--- a/board/freescale/m547xevb/README
+++ /dev/null
@@ -1,271 +0,0 @@
-Freescale MCF5475EVB ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew at freescale.com)
-Created Jan 08, 2008
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
-- board/freescale/m547xevb/mii.c MII init
-- board/freescale/m547xevb/Makefile Makefile
-- board/freescale/m547xevb/config.mk config make
-- board/freescale/m547xevb/u-boot.lds Linker description
-
-- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
-- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock
-- arch/m68k/cpu/mcf547x_8x/Makefile Makefile
-- arch/m68k/cpu/mcf547x_8x/config.mk config make
-- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code
-
-- board/freescale/m547xevb/README This readme file
-
-- drivers/dma/MCD_dmaApi.c DMA API functions
-- drivers/dma/MCD_tasks.c DMA Tasks
-- drivers/dma/MCD_tasksInit.c DMA Tasks Init
-- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver
-- drivers/serial/mcfuart.c ColdFire common UART driver
-
-- include/MCD_dma.h DMA header file
-- include/MCD_progCheck.h DMA header file
-- include/MCD_tasksInit.h DMA header file
-- include/asm-m68k/bitops.h Bit operation function export
-- include/asm-m68k/byteorder.h Byte order functions
-- include/asm-m68k/errno.h Error Number definition
-- include/asm-m68k/fec.h FEC structure and definition
-- include/asm-m68k/fsl_i2c.h I2C structure and definition
-- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition
-- include/asm-m68k/global_data.h Global data structure
-- include/asm-m68k/immap.h ColdFire specific header file and driver macros
-- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file
-- include/asm-m68k/io.h io functions
-- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file
-- include/asm-m68k/posix_types.h Posix
-- include/asm-m68k/processor.h header file
-- include/asm-m68k/ptrace.h Exception structure
-- include/asm-m68k/rtc.h Realtime clock header file
-- include/asm-m68k/string.h String function export
-- include/asm-m68k/timer.h Timer structure and definition
-- include/asm-m68k/types.h Data types definition
-- include/asm-m68k/uart.h Uart structure and definition
-- include/asm-m68k/u-boot.h U-Boot structure
-
-- include/configs/M5475EVB.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts Coldfire common interrupt functions
-- arch/m68k/lib/m68k_linux.c
-- arch/m68k/lib/traps.c Exception init code
-
-1 MCF547x specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in thie coldfire family
-
-1.2 Configuration settings for M5475EVB Development Board
-CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs
-CONFIG_M547x -- define for all Freescale MCF547x CPUs
-CONFIG_M5475 -- define for M5475EVB board
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_FSLDMAFEC -- define to use common dma FEC driver
-CONFIG_MII -- enable to use MII driver
-CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
-CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
-CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
-CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
-CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
-CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
-CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
-MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot
-
-CONFIG_CMD_USB -- enable USB commands
-CONFIG_USB_OHCI_NEW -- enable USB OHCI driver
-CONFIG_USB_STORAGE -- enable USB Storage device
-CONFIG_DOS_PARTITION -- enable DOS read/write
-
-CONFIG_SLTTMR -- define to use SLT timer
-
-CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED -- define for I2C speed
-CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_PCI -- define for PCI support
-CONFIG_PCI_PNP -- define for Plug n play support
-CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge
-CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
-CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
-CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
-CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
-CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
-CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
-CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
-CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
-CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- Flash: 0xFF800000-0xFFFFFFFF (8MB)
- DDR: 0x00000000-0x3FFFFFFF (1024MB)
- SRAM: 0xF2000000-0xF2000FFF (4KB)
- PCI: 0x70000000-0x8FFFFFFF (512MB)
- IP: 0xF0000000-0xFFFFFFFF (256MB)
-
-3. COMPILATION
-==============
-3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
- version) from codesourcery.com was used. Download it from:
- http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-3.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot-1.x.x
- make distclean
- make M5475AFE_config, or - boot 2MB, RAM 64MB
- make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB
- make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB
- make M5475DFE_config, or - boot 2MB, USB, RAM 64MB
- make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB
- make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB
- make M5475GFE_config, or - boot 2MB, RAM 64MB
- make
-
-5. SCREEN DUMP
-==============
-5.1
-
-U-Boot 1.3.1 (Jan 8 2008 - 12:47:44)
-
-CPU: Freescale MCF5475
- CPU CLK 266 Mhz BUS CLK 133 Mhz
-Board: Freescale FireEngine 5475 EVB
-I2C: ready
-DRAM: 64 MB
-FLASH: 18 MB
-In: serial
-Out: serial
-Err: serial
-Net: FEC0, FEC1
--> pri
-bootdelay=1
-baudrate=115200
-ethaddr=00:e0:0c:bc:e5:60
-eth1addr=00:e0:0c:bc:e5:61
-ipaddr=192.162.1.2
-serverip=192.162.1.1
-gatewayip=192.162.1.1
-netmask=255.255.255.0
-hostname=M547xEVB
-netdev=eth0
-loadaddr=10000
-u-boot=u-boot.bin
-load=tftp ${loadaddr) ${u-boot}
-upd=run load; run prog
-prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
-stdin=serial
-stdout=serial
-stderr=serial
-ethact=FEC0
-mem=65024k
-
-Environment size: 433/8188 bytes
--> bdin
-memstart = 0x00000000
-memsize = 0x04000000
-flashstart = 0xFF800000
-flashsize = 0x01200000
-flashoffset = 0x00000000
-sramstart = 0xF2000000
-sramsize = 0x00001000
-mbar = 0xF0000000
-busfreq = 133.333 MHz
-pcifreq = 0 MHz
-ethaddr = 00:E0:0C:BC:E5:60
-eth1addr = 00:E0:0C:BC:E5:61
-ip_addr = 192.162.1.2
-baudrate = 115200 bps
--> ?
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-dcache - enable or disable data cache
-echo - echo args to console
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-go - start application at address 'addr'
-help - print online help
-i2c - I2C sub-system
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-imls - list all images found in flash
-itest - return true/false on integer compare
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loady - load binary file over serial line (ymodem mode)
-loop - infinite loop on address range
-md - memory display
-mii - MII utility commands
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nfs - boot image via network using NFS protocol
-nm - memory modify (constant address)
-pci - list and access PCI Configuration Space
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-tftpboot- boot image via network using TFTP protocol
-usb - USB sub-system
-usbboot - boot from USB device
-version - print monitor version
--> usb start
-(Re)start USB...
-USB: OHCI pci controller (1131, 1561) found @(0:17:0)
-OHCI regs address 0x80000000
-scanning bus for devices... 2 USB Device(s) found
- scanning bus for storage devices... 1 Storage Device(s) found
-->
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
deleted file mode 100644
index 1568f455e927..000000000000
--- a/board/freescale/m547xevb/m547xevb.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Board: ");
- puts("Freescale FireEngine 5475 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- siu_t *siu = (siu_t *) (MMAP_SIU);
- sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
- u32 dramsize, i;
-#ifdef CONFIG_SYS_DRAMSZ1
- u32 temp;
-#endif
-
- out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
-
- dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
- out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
-
-#ifdef CONFIG_SYS_DRAMSZ1
- temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
- for (i = 0x13; i < 0x20; i++) {
- if (temp == (1 << i))
- break;
- }
- i--;
- dramsize += temp;
- out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
-#endif
-
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
-
- /* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
-
- udelay(500);
-
- /* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
-
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
-
- out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
-
- udelay(100);
-
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-extern void pci_mcf547x_8x_init(struct pci_controller *hose);
-
-void pci_init_board(void)
-{
- pci_mcf547x_8x_init(&hose);
-}
-#endif /* CONFIG_PCI */
diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig
deleted file mode 100644
index a919bf720bba..000000000000
--- a/configs/M5475AFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475AFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig
deleted file mode 100644
index b9f4904134a4..000000000000
--- a/configs/M5475BFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475BFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig
deleted file mode 100644
index ae5853572633..000000000000
--- a/configs/M5475CFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475CFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig
deleted file mode 100644
index a9d085f3707a..000000000000
--- a/configs/M5475DFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475DFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig
deleted file mode 100644
index 38d31ace0120..000000000000
--- a/configs/M5475EFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475EFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig
deleted file mode 100644
index 0a620c39f1a1..000000000000
--- a/configs/M5475FFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475FFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig
deleted file mode 100644
index 05b0ba7af8cd..000000000000
--- a/configs/M5475GFE_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_TARGET_M5475EVB=y
-CONFIG_DEFAULT_DEVICE_TREE="M5475GFE"
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64"
-CONFIG_BOOTDELAY=1
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FSLDMAFEC=y
-CONFIG_MII=y
-CONFIG_PCI=y
-CONFIG_PHY=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 44e1a5dfa384..698e288c4487 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -72,7 +72,7 @@ A bash script similar to the one below may be used:
export CROSS_COMPILE=/opt/toolchains/m68k/gcc-4.9.0-nolibc/bin/m68k-linux-
- board=M5475DFE
+ board=M5249EVB
make distclean
make ${board}_defconfig
diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 0987266c96ef..ca06b35316d3 100644
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -11,11 +11,7 @@
#include <asm/global_data.h>
#include <linux/delay.h>
-#ifdef CONFIG_MCF547x_8x
-#include <asm/fsl_mcdmafec.h>
-#else
#include <asm/fec.h>
-#endif
#include <asm/immap.h>
#include <linux/mii.h>
diff --git a/env/Kconfig b/env/Kconfig
index 1411f9e815ec..ea0ee1e8bafa 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -82,7 +82,7 @@ config ENV_IS_IN_FLASH
depends on !CHAIN_OF_TRUST
default y if ARCH_CINTEGRATOR
default y if ARCH_INTEGRATOR_CP
- default y if M548x || M547x || M5282 || MCF547x_8x
+ default y if M548x || M547x || M5282
default y if MCF532x || MCF52x2
default y if MPC86xx || MPC83xx
default y if ARCH_MPC8572 || ARCH_MPC8548 || ARCH_MPC8641
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
deleted file mode 100644
index 406830c98d56..000000000000
--- a/include/configs/M5475EVB.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF5475 board.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew at freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5475EVB_H
-#define _M5475EVB_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#undef CONFIG_HW_WATCHDOG
-#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
-
-#define CONFIG_SLTTMR
-
-#ifdef CONFIG_FSLDMAFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_HAS_ETH1
-# define CONFIG_SYS_DMA_USE_INTSRAM 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 32
-# define CONFIG_SYS_TX_ETH_BUFFER 48
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-#endif
-
-#ifdef CONFIG_CMD_USB
-# define CONFIG_USB_OHCI_NEW
-
-# define CONFIG_PCI_OHCI
-
-# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-# undef CONFIG_SYS_USB_OHCI_CPU_INIT
-# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
-# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-#endif
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* PCI */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
-
-#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_SYS_PCI_IO_BUS 0x71000000
-#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
-#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
-#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
-#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
-#endif
-
-#define CONFIG_UDP_CHECKSUM
-
-#ifdef CONFIG_MCFFEC
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-#endif /* FEC_ENET */
-
-#define CONFIG_HOSTNAME "M547xEVB"
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "loadaddr=10000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off bank 1;" \
- "era ff800000 ff83ffff;" \
- "cp.b ${loadaddr} ff800000 ${filesize};"\
- "save\0" \
- ""
-
-#define CONFIG_PRAM 512 /* 512 KB */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00010000
-
-#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
-#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
-
-#define CONFIG_SYS_MBAR 0xF0000000
-#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
-#define CONFIG_SYS_INTSRAMSZ 0x8000
-
-/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
-#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_CFG1 0x73711630
-#define CONFIG_SYS_SDRAM_CFG2 0x46770000
-#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x018D0000
-#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
-#ifdef CONFIG_SYS_DRAMSZ1
-# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
-#else
-# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-#ifdef CONFIG_SYS_NOR1SZ
-# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
-#else
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
-#endif
-#endif
-
-/* Configuration for environment
- * Environment is not embedded in u-boot but@offset 0x40000 on the flash.
- * First time runing may have env crc error warning if there is
- * no correct environment on the flash.
- */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
- CF_CACR_IDCM)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
- CF_CACR_IEC | CF_CACR_ICINVA)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Chipselect bank definitions
- */
-/*
- * CS0 - NOR Flash 1, 2, 4, or 8MB
- * CS1 - NOR Flash
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-#define CONFIG_SYS_CS0_BASE 0xFF800000
-#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
-#define CONFIG_SYS_CS0_CTRL 0x00101980
-
-#ifdef CONFIG_SYS_NOR1SZ
-#define CONFIG_SYS_CS1_BASE 0xE0000000
-#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CONFIG_SYS_CS1_CTRL 0x00101D80
-#endif
-
-#endif /* _M5475EVB_H */
diff --git a/include/fsl_dspi.h b/include/fsl_dspi.h
index 4fec83549e1f..ebe1803e4665 100644
--- a/include/fsl_dspi.h
+++ b/include/fsl_dspi.h
@@ -21,14 +21,8 @@ struct dspi {
u32 irsr; /* 0x30 */
u32 tfr; /* 0x34 - PUSHR */
u32 rfr; /* 0x38 - POPR */
-#ifdef CONFIG_MCF547x_8x
- u32 tfdr[4]; /* 0x3C */
- u8 resv2[0x30]; /* 0x40 */
- u32 rfdr[4]; /* 0x7C */
-#else
u32 tfdr[16]; /* 0x3C */
u32 rfdr[16]; /* 0x7C */
-#endif
};
/* Module configuration */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 06/27] mips: Remove malta boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (3 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 05/27] m68k: Remove M5475x boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-17 23:32 ` Daniel Schwierzeck
2021-05-15 1:34 ` [PATCH 07/27] ppc: Remove sbc8349 board Tom Rini
` (21 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.
Cc: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
As I hope these boards will get converted quickly I've not removed all
of the other references to Malta and the associated PCI host controller
drivers.
---
arch/mips/Kconfig | 1 -
board/imgtec/malta/Kconfig | 16 --
board/imgtec/malta/MAINTAINERS | 9 -
board/imgtec/malta/Makefile | 8 -
board/imgtec/malta/flash-malta-boot.tcl | 38 ----
board/imgtec/malta/lowlevel_init.S | 231 -----------------------
board/imgtec/malta/malta.c | 233 ------------------------
board/imgtec/malta/superio.c | 62 -------
board/imgtec/malta/superio.h | 14 --
configs/malta64_defconfig | 33 ----
configs/malta64el_defconfig | 35 ----
configs/malta_defconfig | 32 ----
configs/maltael_defconfig | 34 ----
include/configs/malta.h | 81 --------
14 files changed, 827 deletions(-)
delete mode 100644 board/imgtec/malta/Kconfig
delete mode 100644 board/imgtec/malta/MAINTAINERS
delete mode 100644 board/imgtec/malta/Makefile
delete mode 100644 board/imgtec/malta/flash-malta-boot.tcl
delete mode 100644 board/imgtec/malta/lowlevel_init.S
delete mode 100644 board/imgtec/malta/malta.c
delete mode 100644 board/imgtec/malta/superio.c
delete mode 100644 board/imgtec/malta/superio.h
delete mode 100644 configs/malta64_defconfig
delete mode 100644 configs/malta64el_defconfig
delete mode 100644 configs/malta_defconfig
delete mode 100644 configs/maltael_defconfig
delete mode 100644 include/configs/malta.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 77f563e98ed2..dc13c8c6ce6a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -172,7 +172,6 @@ config TARGET_XILFPGA
endchoice
source "board/imgtec/boston/Kconfig"
-source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
deleted file mode 100644
index 98eb4d16c717..000000000000
--- a/board/imgtec/malta/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_MALTA
-
-config SYS_BOARD
- default "malta"
-
-config SYS_VENDOR
- default "imgtec"
-
-config SYS_CONFIG_NAME
- default "malta"
-
-config SYS_TEXT_BASE
- default 0xbe000000 if 32BIT
- default 0xffffffffbe000000 if 64BIT
-
-endif
diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS
deleted file mode 100644
index b1cf297f4fac..000000000000
--- a/board/imgtec/malta/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MALTA BOARD
-M: Paul Burton <paul.burton@mips.com>
-S: Maintained
-F: board/imgtec/malta/
-F: include/configs/malta.h
-F: configs/malta64_defconfig
-F: configs/malta64el_defconfig
-F: configs/malta_defconfig
-F: configs/maltael_defconfig
diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile
deleted file mode 100644
index d0d84010fc76..000000000000
--- a/board/imgtec/malta/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y = malta.o
-obj-y += lowlevel_init.o
-obj-y += superio.o
diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl
deleted file mode 100644
index 972002a8e911..000000000000
--- a/board/imgtec/malta/flash-malta-boot.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2013 Imagination Technologies
-#
-# Programs a MIPS Malta boot flash with a flat binary image.
-
-proc flash-boot { binfile } {
- puts "flash monitor binary $binfile"
- config Coherent on
- config CoherencyDuringLoad on
-
- if {[endian]=="big"} {
- puts "CPU in BE mode"
- flash device sharp_16x32_be;
- } else {
- puts "CPU in LE mode"
- flash device sharp_16x32;
- }
-
- flash clear all;
- flash set 0xBE000000..0xBE0FFFFF
- flash erase sector 0xbe000000;
- flash erase sector 0xbe020000;
- flash erase sector 0xbe040000;
- flash erase sector 0xbe060000;
- flash erase sector 0xbe080000;
- flash erase sector 0xbe0a0000;
- flash erase sector 0xbe0c0000;
- flash erase sector 0xbe0e0000;
- puts "finished erasing boot flash";
-
- puts "programming flash, please be patient"
- load bin 0xbe000000 $binfile size4
-
- flash clear all
- config CoherencyDuringLoad off
- puts "finished programming boot flash";
-}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
deleted file mode 100644
index ecb4424fd92a..000000000000
--- a/board/imgtec/malta/lowlevel_init.S
+++ /dev/null
@@ -1,231 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#include <config.h>
-#include <gt64120.h>
-#include <msc01.h>
-#include <pci.h>
-
-#include <asm/addrspace.h>
-#include <asm/asm.h>
-#include <asm/regdef.h>
-#include <asm/malta.h>
-#include <asm/mipsregs.h>
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CPU_TO_GT32(_x) ((_x))
-#else
-#define CPU_TO_GT32(_x) ( \
- (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
- (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
-#endif
-
- .text
- .set noreorder
-
- .globl lowlevel_init
-lowlevel_init:
- /* detect the core card */
- PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
- lw t0, 0(t0)
- srl t0, t0, MALTA_REVISION_CORID_SHF
- andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
- MALTA_REVISION_CORID_SHF)
-
- /* core cards using the gt64120 system controller */
- li t1, MALTA_REVISION_CORID_CORE_LV
- beq t0, t1, _gt64120
-
- /* core cards using the MSC01 system controller */
- li t1, MALTA_REVISION_CORID_CORE_FPGA6
- beq t0, t1, _msc01
- nop
-
- /* unknown system controller */
- b .
- nop
-
- /*
- * Load BAR registers of GT64120 as done by YAMON
- *
- * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
- * to the barebox mailing list.
- * The subject of the original patch:
- * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
- * URL:
- * http://www.mail-archive.com/barebox at lists.infradead.org/msg06128.html
- *
- * based on write_bootloader() in qemu.git/hw/mips_malta.c
- * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
- */
-_gt64120:
- /* move GT64120 registers from 0x14000000 to 0x1be00000 */
- PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
- li t0, CPU_TO_GT32(0xdf000000)
- sw t0, GT_ISD_OFS(t1)
-
- /* setup MEM-to-PCI0 mapping */
- PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
-
- /* setup PCI0 io window to 0x18000000-0x181fffff */
- li t0, CPU_TO_GT32(0xc0000000)
- sw t0, GT_PCI0IOLD_OFS(t1)
- li t0, CPU_TO_GT32(0x40000000)
- sw t0, GT_PCI0IOHD_OFS(t1)
-
- /* setup PCI0 mem windows */
- li t0, CPU_TO_GT32(0x80000000)
- sw t0, GT_PCI0M0LD_OFS(t1)
- li t0, CPU_TO_GT32(0x3f000000)
- sw t0, GT_PCI0M0HD_OFS(t1)
-
- li t0, CPU_TO_GT32(0xc1000000)
- sw t0, GT_PCI0M1LD_OFS(t1)
- li t0, CPU_TO_GT32(0x5e000000)
- sw t0, GT_PCI0M1HD_OFS(t1)
-
- jr ra
- nop
-
- /*
- *
- */
-_msc01:
- /* setup peripheral bus controller clock divide */
- PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
- li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
- sw t1, MSC01_PBC_CLKCFG_OFS(t0)
-
- /* tweak peripheral bus controller timings */
- li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
- (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
- sw t1, MSC01_PBC_CS0TIM_OFS(t0)
- li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
- (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
- (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
- (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
- sw t1, MSC01_PBC_CS0RW_OFS(t0)
- lw t1, MSC01_PBC_CS0CFG_OFS(t0)
- li t2, MSC01_PBC_CS0CFG_DTYP_MSK
- and t1, t2
- ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
- (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
- (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
- sw t1, MSC01_PBC_CS0CFG_OFS(t0)
-
- /* setup basic address decode */
- PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
- li t1, 0x0
- li t2, -CONFIG_SYS_MEM_SIZE
- sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
- sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
- sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
- sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
-
- /* initialise IP1 - unused */
- li t1, MALTA_MSC01_IP1_BASE
- li t2, -MALTA_MSC01_IP1_SIZE
- sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
- sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
- sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
- sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
-
- /* initialise IP2 - PCI */
- li t1, MALTA_MSC01_IP2_BASE1
- li t2, -MALTA_MSC01_IP2_SIZE1
- sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
- sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
- li t1, MALTA_MSC01_IP2_BASE2
- li t2, -MALTA_MSC01_IP2_SIZE2
- sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
- sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
-
- /* initialise IP3 - peripheral bus controller */
- li t1, MALTA_MSC01_IP3_BASE
- li t2, -MALTA_MSC01_IP3_SIZE
- sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
- sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
- sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
- sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
-
- /* setup PCI memory */
- PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
- li t1, MALTA_MSC01_PCIMEM_BASE
- li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
- li t3, MALTA_MSC01_PCIMEM_MAP
- sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
- sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
- sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
-
- /* setup PCI I/O */
- li t1, MALTA_MSC01_PCIIO_BASE
- li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
- li t3, MALTA_MSC01_PCIIO_MAP
- sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
- sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
- sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
-
- /* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_MEM_SIZE
- sw t1, MSC01_PCI_BAR0_OFS(t0)
-
- /* setup PCI to SysCon/CPU translation */
- sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
- sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
-
- /* setup PCI vendor & device IDs */
- li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
- (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
- sw t1, MSC01_PCI_HEAD0_OFS(t0)
-
- /* setup PCI subsystem vendor & device IDs */
- sw t1, MSC01_PCI_HEAD11_OFS(t0)
-
- /* setup PCI class, revision */
- li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
- (0x1 << MSC01_PCI_HEAD2_REV_SHF)
- sw t1, MSC01_PCI_HEAD2_OFS(t0)
-
- /* ensure a sane setup */
- sw zero, MSC01_PCI_HEAD3_OFS(t0)
- sw zero, MSC01_PCI_HEAD4_OFS(t0)
- sw zero, MSC01_PCI_HEAD5_OFS(t0)
- sw zero, MSC01_PCI_HEAD6_OFS(t0)
- sw zero, MSC01_PCI_HEAD7_OFS(t0)
- sw zero, MSC01_PCI_HEAD8_OFS(t0)
- sw zero, MSC01_PCI_HEAD9_OFS(t0)
- sw zero, MSC01_PCI_HEAD10_OFS(t0)
- sw zero, MSC01_PCI_HEAD12_OFS(t0)
- sw zero, MSC01_PCI_HEAD13_OFS(t0)
- sw zero, MSC01_PCI_HEAD14_OFS(t0)
- sw zero, MSC01_PCI_HEAD15_OFS(t0)
-
- /* setup PCI command register */
- li t1, (PCI_COMMAND_FAST_BACK | \
- PCI_COMMAND_SERR | \
- PCI_COMMAND_PARITY | \
- PCI_COMMAND_MASTER | \
- PCI_COMMAND_MEMORY)
- sw t1, MSC01_PCI_HEAD1_OFS(t0)
-
- /* setup PCI byte swapping */
-#ifdef CONFIG_SYS_BIG_ENDIAN
- li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
- (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
- sw t1, MSC01_PCI_SWAP_OFS(t0)
-#else
- sw zero, MSC01_PCI_SWAP_OFS(t0)
-#endif
-
- /* enable PCI host configuration cycles */
- lw t1, MSC01_PCI_CFG_OFS(t0)
- li t2, MSC01_PCI_CFG_RA_MSK | \
- MSC01_PCI_CFG_G_MSK | \
- MSC01_PCI_CFG_EN_MSK
- or t1, t1, t2
- sw t1, MSC01_PCI_CFG_OFS(t0)
-
- jr ra
- nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
deleted file mode 100644
index c04f727961de..000000000000
--- a/board/imgtec/malta/malta.c
+++ /dev/null
@@ -1,233 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2013 Imagination Technologies
- */
-
-#include <common.h>
-#include <ide.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <pci.h>
-#include <pci_gt64120.h>
-#include <pci_msc01.h>
-#include <rtc.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/malta.h>
-
-#include "superio.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum core_card {
- CORE_UNKNOWN,
- CORE_LV,
- CORE_FPGA6,
-};
-
-enum sys_con {
- SYSCON_UNKNOWN,
- SYSCON_GT64120,
- SYSCON_MSC01,
-};
-
-static void malta_lcd_puts(const char *str)
-{
- int i;
- void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
-
- /* print up to 8 characters of the string */
- for (i = 0; i < min((int)strlen(str), 8); i++) {
- __raw_writel(str[i], reg);
- reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
- }
-
- /* fill the rest of the display with spaces */
- for (; i < 8; i++) {
- __raw_writel(' ', reg);
- reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
- }
-}
-
-static enum core_card malta_core_card(void)
-{
- u32 corid, rev;
- const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
-
- rev = __raw_readl(reg);
- corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
-
- switch (corid) {
- case MALTA_REVISION_CORID_CORE_LV:
- return CORE_LV;
-
- case MALTA_REVISION_CORID_CORE_FPGA6:
- return CORE_FPGA6;
-
- default:
- return CORE_UNKNOWN;
- }
-}
-
-static enum sys_con malta_sys_con(void)
-{
- switch (malta_core_card()) {
- case CORE_LV:
- return SYSCON_GT64120;
-
- case CORE_FPGA6:
- return SYSCON_MSC01;
-
- default:
- return SYSCON_UNKNOWN;
- }
-}
-
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_MEM_SIZE;
-
- return 0;
-}
-
-int checkboard(void)
-{
- enum core_card core;
-
- malta_lcd_puts("U-Boot");
- puts("Board: MIPS Malta");
-
- core = malta_core_card();
- switch (core) {
- case CORE_LV:
- puts(" CoreLV");
- break;
-
- case CORE_FPGA6:
- puts(" CoreFPGA6");
- break;
-
- default:
- puts(" CoreUnknown");
- }
-
- putc('\n');
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
-void _machine_restart(void)
-{
- void __iomem *reset_base;
-
- reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
- __raw_writel(GORESET, reset_base);
- mdelay(1000);
-}
-
-int board_early_init_f(void)
-{
- ulong io_base;
-
- /* choose correct PCI I/O base */
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
- break;
-
- case SYSCON_MSC01:
- io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
- break;
-
- default:
- return -1;
- }
-
- set_io_port_base(io_base);
-
- /* setup FDC37M817 super I/O controller */
- malta_superio_init();
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- rtc_reset();
-
- return 0;
-}
-
-void pci_init_board(void)
-{
- pci_dev_t bdf;
- u32 val32;
- u8 val8;
-
- switch (malta_sys_con()) {
- case SYSCON_GT64120:
- gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- 0x10000000, 0x10000000, 128 * 1024 * 1024,
- 0x00000000, 0x00000000, 0x20000);
- break;
-
- default:
- case SYSCON_MSC01:
- msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- MALTA_MSC01_PCIMEM_MAP,
- CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
- MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
- 0x00000000, MALTA_MSC01_PCIIO_SIZE);
- break;
- }
-
- bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82371AB_0, 0);
- if (bdf == -1)
- panic("Failed to find PIIX4 PCI bridge\n");
-
- /* setup PCI interrupt routing */
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
-
- /* mux SERIRQ onto SERIRQ pin */
- pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
- val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
-
- /* enable SERIRQ - Linux currently depends upon this */
- pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
- val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
- pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
-
- bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
- PCI_DEVICE_ID_INTEL_82371AB, 0);
- if (bdf == -1)
- panic("Failed to find PIIX4 IDE controller\n");
-
- /* enable bus master & IO access */
- val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_dword(bdf, PCI_COMMAND, val32);
-
- /* set latency */
- pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
-
- /* enable IDE/ATA */
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
- PCI_CFG_PIIX4_IDETIM_IDE);
- pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
- PCI_CFG_PIIX4_IDETIM_IDE);
-}
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
deleted file mode 100644
index aba11e25be31..000000000000
--- a/board/imgtec/malta/superio.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@mips.com>
- *
- * Setup code for the FDC37M817 super I/O controller
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define SIO_CONF_PORT 0x3f0
-#define SIO_DATA_PORT 0x3f1
-
-enum sio_conf_key {
- SIOCONF_DEVNUM = 0x07,
- SIOCONF_ACTIVATE = 0x30,
- SIOCONF_ENTER_SETUP = 0x55,
- SIOCONF_BASE_HIGH = 0x60,
- SIOCONF_BASE_LOW = 0x61,
- SIOCONF_PRIMARY_INT = 0x70,
- SIOCONF_EXIT_SETUP = 0xaa,
- SIOCONF_MODE = 0xf0,
-};
-
-static struct {
- u8 key;
- u8 data;
-} sio_config[] = {
- /* tty0 */
- { SIOCONF_DEVNUM, 0x04 },
- { SIOCONF_BASE_HIGH, 0x03 },
- { SIOCONF_BASE_LOW, 0xf8 },
- { SIOCONF_MODE, 0x02 },
- { SIOCONF_PRIMARY_INT, 0x04 },
- { SIOCONF_ACTIVATE, 0x01 },
-
- /* tty1 */
- { SIOCONF_DEVNUM, 0x05 },
- { SIOCONF_BASE_HIGH, 0x02 },
- { SIOCONF_BASE_LOW, 0xf8 },
- { SIOCONF_MODE, 0x02 },
- { SIOCONF_PRIMARY_INT, 0x03 },
- { SIOCONF_ACTIVATE, 0x01 },
-};
-
-void malta_superio_init(void)
-{
- unsigned i;
-
- /* enter config state */
- outb(SIOCONF_ENTER_SETUP, SIO_CONF_PORT);
-
- /* configure peripherals */
- for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
- outb(sio_config[i].key, SIO_CONF_PORT);
- outb(sio_config[i].data, SIO_DATA_PORT);
- }
-
- /* exit config state */
- outb(SIOCONF_EXIT_SETUP, SIO_CONF_PORT);
-}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
deleted file mode 100644
index 11e9cef978e8..000000000000
--- a/board/imgtec/malta/superio.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@mips.com>
- *
- * Setup code for the FDC37M817 super I/O controller
- */
-
-#ifndef __BOARD_MALTA_SUPERIO_H__
-#define __BOARD_MALTA_SUPERIO_H__
-
-void malta_superio_init(void);
-
-#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
deleted file mode 100644
index 878dc6ee05bc..000000000000
--- a/configs/malta64_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_CPU_MIPS64_R2=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="malta # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
deleted file mode 100644
index 7dfe67355ff8..000000000000
--- a/configs/malta64el_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_BUILD_TARGET="u-boot-swap.bin"
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS64_R2=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="maltael # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
deleted file mode 100644
index 304f2198baaf..000000000000
--- a/configs/malta_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="malta # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
deleted file mode 100644
index 7436e4e94390..000000000000
--- a/configs/maltael_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBE000000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_MALTA=y
-CONFIG_BUILD_TARGET="u-boot-swap.bin"
-CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
-CONFIG_SYS_LITTLE_ENDIAN=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="maltael # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBE3E0000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PCNET=y
-CONFIG_PCI=y
-CONFIG_RTC_MC146818=y
-CONFIG_SYS_NS16550=y
diff --git a/include/configs/malta.h b/include/configs/malta.h
deleted file mode 100644
index 9602773ff91f..000000000000
--- a/include/configs/malta.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#ifndef _MALTA_CONFIG_H
-#define _MALTA_CONFIG_H
-
-/*
- * System configuration
- */
-#define CONFIG_MALTA
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-#define CONFIG_PCI_GT64120
-#define CONFIG_PCI_MSC01
-
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-
-/*
- * CPU Configuration
- */
-#define CONFIG_SYS_MHZ 250 /* arbitrary value */
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#ifdef CONFIG_64BIT
-# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
-#else
-# define CONFIG_SYS_SDRAM_BASE 0x80000000
-#endif
-#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
-
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
-#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
-#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
-
-/*
- * Serial driver
- */
-#define CONFIG_SYS_NS16550_PORT_MAPPED
-
-/*
- * Flash configuration
- */
-#ifdef CONFIG_64BIT
-# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
-#else
-# define CONFIG_SYS_FLASH_BASE 0xbe000000
-#endif
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-/*
- * Environment
- */
-
-/*
- * IDE/ATA
- */
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/*
- * Commands
- */
-
-#endif /* _MALTA_CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 06/27] mips: Remove malta boards
2021-05-15 1:34 ` [PATCH 06/27] mips: Remove malta boards Tom Rini
@ 2021-05-17 23:32 ` Daniel Schwierzeck
2021-05-18 1:36 ` Tom Rini
0 siblings, 1 reply; 71+ messages in thread
From: Daniel Schwierzeck @ 2021-05-17 23:32 UTC (permalink / raw)
To: u-boot
Hi Tom,
Am Freitag, den 14.05.2021, 21:34 -0400 schrieb Tom Rini:
> These boards have not been converted to CONFIG_DM_PCI by the
> deadline.
> Remove them.
>
> Cc: Paul Burton <paul.burton@mips.com>
> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> As I hope these boards will get converted quickly I've not removed
> all
> of the other references to Malta and the associated PCI host
> controller
> drivers.
it is not trivial to convert Malta and Paul is not involved with any
MIPS anymore since 2019. I have this on my todo list for over one year
but didn't find time ;)
But Malta is rather important because it is the reference board for
MIPS Qemu. It's also important for U-Boot CI due to build coverage for
LE/BE and 32/64 bit and Qemu tests. The qemu_mips board also used for
CI is deprecated and I definitely won't convert that. In fact I already
sent patches to remove it with this release.
Anyway I started to convert things and made good progress. But I need
some more days to finish and test. When do you plan to apply the
removal patch series?
--
- Daniel
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 06/27] mips: Remove malta boards
2021-05-17 23:32 ` Daniel Schwierzeck
@ 2021-05-18 1:36 ` Tom Rini
0 siblings, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-18 1:36 UTC (permalink / raw)
To: u-boot
On Tue, May 18, 2021 at 01:32:17AM +0200, Daniel Schwierzeck wrote:
> Hi Tom,
>
> Am Freitag, den 14.05.2021, 21:34 -0400 schrieb Tom Rini:
> > These boards have not been converted to CONFIG_DM_PCI by the
> > deadline.
> > Remove them.
> >
> > Cc: Paul Burton <paul.burton@mips.com>
> > Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
> > Signed-off-by: Tom Rini <trini@konsulko.com>
> > ---
> > As I hope these boards will get converted quickly I've not removed
> > all
> > of the other references to Malta and the associated PCI host
> > controller
> > drivers.
>
> it is not trivial to convert Malta and Paul is not involved with any
> MIPS anymore since 2019. I have this on my todo list for over one year
> but didn't find time ;)
Ah, ok.
> But Malta is rather important because it is the reference board for
> MIPS Qemu. It's also important for U-Boot CI due to build coverage for
> LE/BE and 32/64 bit and Qemu tests. The qemu_mips board also used for
> CI is deprecated and I definitely won't convert that. In fact I already
> sent patches to remove it with this release.
>
> Anyway I started to convert things and made good progress. But I need
> some more days to finish and test. When do you plan to apply the
> removal patch series?
The DM_PCI deadline was v2019.07, so after the v2021.07 release. Based
on how DM_MMC went for this release, I expect it will be closer to
v2021.10-rc2 timeframe before I do the final remove and enforce.
--
Tom
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^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 07/27] ppc: Remove sbc8349 board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (4 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 06/27] mips: Remove malta boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-15 19:16 ` Paul Gortmaker
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 08/27] ppc: Remove many T104x boards Tom Rini
` (20 subsequent siblings)
26 siblings, 2 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
board/sbc8349/Kconfig | 9 -
board/sbc8349/MAINTAINERS | 8 -
board/sbc8349/Makefile | 6 -
board/sbc8349/README | 127 ------------
board/sbc8349/pci.c | 70 -------
board/sbc8349/sbc8349.c | 243 -----------------------
configs/sbc8349_PCI_33_defconfig | 123 ------------
configs/sbc8349_PCI_66_defconfig | 123 ------------
configs/sbc8349_defconfig | 101 ----------
include/configs/sbc8349.h | 322 -------------------------------
11 files changed, 1137 deletions(-)
delete mode 100644 board/sbc8349/Kconfig
delete mode 100644 board/sbc8349/MAINTAINERS
delete mode 100644 board/sbc8349/Makefile
delete mode 100644 board/sbc8349/README
delete mode 100644 board/sbc8349/pci.c
delete mode 100644 board/sbc8349/sbc8349.c
delete mode 100644 configs/sbc8349_PCI_33_defconfig
delete mode 100644 configs/sbc8349_PCI_66_defconfig
delete mode 100644 configs/sbc8349_defconfig
delete mode 100644 include/configs/sbc8349.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index ff85834c460c..e0bdfc4b9716 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -12,10 +12,6 @@ config TARGET_MPC8308_P1M
bool "Support mpc8308_p1m"
select ARCH_MPC8308
-config TARGET_SBC8349
- bool "Support sbc8349"
- select ARCH_MPC8349
-
config TARGET_VE8313
bool "Support ve8313"
select ARCH_MPC8313
@@ -312,7 +308,6 @@ source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
source "board/mpc8308_p1m/Kconfig"
-source "board/sbc8349/Kconfig"
source "board/tqc/tqm834x/Kconfig"
source "board/ve8313/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig
deleted file mode 100644
index 129d6b92ec57..000000000000
--- a/board/sbc8349/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC8349
-
-config SYS_BOARD
- default "sbc8349"
-
-config SYS_CONFIG_NAME
- default "sbc8349"
-
-endif
diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS
deleted file mode 100644
index af95c1dd0d23..000000000000
--- a/board/sbc8349/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-SBC8349 BOARD
-M: Paul Gortmaker <paul.gortmaker@windriver.com>
-S: Maintained
-F: board/sbc8349/
-F: include/configs/sbc8349.h
-F: configs/sbc8349_defconfig
-F: configs/sbc8349_PCI_33_defconfig
-F: configs/sbc8349_PCI_66_defconfig
diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
deleted file mode 100644
index c469174085d9..000000000000
--- a/board/sbc8349/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2006 Wind River Systems, Inc.
-
-obj-y += sbc8349.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/sbc8349/README b/board/sbc8349/README
deleted file mode 100644
index 3c142e040762..000000000000
--- a/board/sbc8349/README
+++ /dev/null
@@ -1,127 +0,0 @@
-
-
- U-Boot for Wind River SBC834x Boards
- ====================================
-
-
-The Wind River SBC834x board is a 6U form factor (not CPCI) reference
-design that uses the MPC8347E or MPC8349E processor. U-Boot support
-for this board is heavily based on the existing U-Boot support for
-Freescale MPC8349 reference boards.
-
-Support has been primarily tested on the SBC8349 version of the board,
-although earlier versions were also tested on the SBC8347. The primary
-difference in the two is the level of PCI functionality.
-
- http://www.windriver.com/products/OCD/SBC8347E_49E/
-
-
-Flash Details:
-==============
-
-The flash type is intel 28F640Jx (4096x16) [one device]. Base address
-is 0xFF80_0000 which is also where the Hardware Reset Configuration
-Word (HRCW) is stored. Caution should be used to not reset the
-board without having a valid HRCW in place (i.e. erased flash) as
-then a Wind River ICE will be required to restore the HRCW and flash
-image.
-
-
-Restoring a corrupted or missing flash image:
-=============================================
-
-Note that U-Boot versions up to and including 2009.06 had essentially
-two copies of U-Boot in flash; one at the very beginning, which set
-the HRCW, and one at the very end, which was the image that was run.
-As of this point in time, the two have been combined into just one
-at the beginning of flash, which provides both the HRCW, and the image
-that is executed. This frees up the remainder of flash for other uses.
-Use of the U-Boot command "fli" will indicate what parts are in use.
-Details for storing U-Boot to flash using a Wind River ICE can be found
-on page 19 of the board manual (request ERG-00328-001). The following
-is a summary of that information:
-
- - Connect ICE and establish connection to it from WorkBench/OCD.
- - Ensure you have background mode (BKM) in the OCD terminal window.
- - Select the appropriate flash type (listed above)
- - Prepare a U-Boot image by using the Wind River Convert utility;
- by using "Convert and Add file" on the ELF file from your build.
- Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
- trying to preserve your old environment settings and user flash).
- - Set the start address of the erase/flash process to FF80_0000
- - Set the target RAM required to 64kB.
- - Select sectors for erasing (see note on environment below)
- - Select Erase and Reprogram.
-
-Note that some versions of the register files used with Workbench
-would zero some TSEC registers, which inhibits ethernet operation
-by U-Boot when this register file is played to the target. Using
-"INN" in the OCD terminal window instead of "IN" before the "GO"
-will not play the register file, and allow U-Boot to use the TSEC
-interface while executed from the ICE "GO" command.
-
-Alternatively, you can locate the register file which will be named
-WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
-beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to
-use all the remaining register file content.
-
-If you wish to preserve your prior U-Boot environment settings,
-then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
-The size for converting (and erasing) must be at least as large
-as u-boot.bin.
-
-
-Updating U-Boot with U-Boot:
-============================
-
-This procedure is very similar to other boards that have U-Boot installed.
-Assuming that the network has been configured, and that the new u-boot.bin
-has been copied to the TFTP server, the commands are:
-
- tftp 200000 u-boot.bin
- protect off all
- erase ff800000 ff83ffff
- cp.b 200000 ff800000 40000
- protect on all
-
-You may wish to do a "md ff800000 20" operation as a prefix and postfix
-to the above steps to inspect/compare the HRCW before/after as an extra
-safety check before resetting the board upon completion of the reflash.
-
-PCI:
-====
-
-There are three configuration choices:
- sbc8349_config
- sbc8349_PCI_33_config
- sbc8349_PCI_66_config
-
-The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
-will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
-and linux in order to have functional PCI under linux. The only
-reason for choosing to not enable PCI would be if you had a very
-early (rev 1.0) CPU with possible PCI issues.
-
-The second enables PCI support and builds for a 33MHz clock rate. Note
-that if a 33MHz 32bit card is inserted in the slot, then the whole board
-will clock down to a 33MHz base clock instead of the default 66MHz. This
-will change the baud clocks and mess up your serial console output if you
-were previously running at 66MHz. If you want to use a 33MHz PCI card,
-then you should build a U-Boot with sbc8349_PCI_33_config and store this
-to flash prior to powering down the board and inserting the 33MHz PCI
-card.
-
-The third option builds PCI support in, and leaves the clocking at the
-default 66MHz. This has been tested with an intel PCI-X e1000 card.
-This is also the appropriate choice for people with a recent (non 1.0)
-CPU who currently have the PCI slot physically empty, but intend to
-possibly add a PCI-X card at a later date.
-
- => pci
- Scanning PCI devices on bus 0
- BusDevFun VendorId DeviceId Device Class Sub-Class
- _____________________________________________________________
- 00.00.00 0x1957 0x0080 Processor 0x20
- 00.11.00 0x8086 0x1026 Network controller 0x00
- =>
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
deleted file mode 100644
index 26c4f24e4f8b..000000000000
--- a/board/sbc8349/pci.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * pci.c -- WindRiver SBC8349 PCI board support.
- * Copyright (c) 2006 Wind River Systems, Inc.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * Based on MPC8349 PCI support but w/o PIB related code.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: PCI2 is not supported. There is only one
- * physical PCI slot on the board.
- *
- */
-void
-pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci1_regions };
-
- /* Enable all 8 PCI_CLK_OUTPUTS */
- clk->occr = 0xff000000;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- udelay(2000);
-
- mpc83xx_pci_init(1, reg);
-}
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
deleted file mode 100644
index b440a0b17e97..000000000000
--- a/board/sbc8349/sbc8349.c
+++ /dev/null
@@ -1,243 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * sbc8349.c -- WindRiver SBC8349 board support.
- * Copyright (c) 2006-2007 Wind River Systems, Inc.
- *
- * Paul Gortmaker <paul.gortmaker@windriver.com>
- * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/bitops.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int fixed_sdram(void);
-void sdram_init(void);
-
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
-void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f (void)
-{
- return 0;
-}
-#endif
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- sdram_init();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE;
- u32 ddr_size = msize << 20; /* DDR size in bytes */
- u32 ddr_size_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currently any ddr size other than 256 is not supported
-#endif
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-
- /* currently we use only one CS, so disable the other banks */
- im->ddr.cs_config[0] = 0;
- im->ddr.cs_config[1] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
- im->ddr.sdram_cfg =
- SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
- | SDRAM_CFG_2T_EN
-#endif
- | SDRAM_CFG_SDRAM_TYPE_DDR1;
-#if defined (CONFIG_DDR_32BIT)
- /* for 32-bit mode burst length is 8 */
- im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- udelay(200);
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- return msize;
-}
-#endif/*!CONFIG_SYS_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
- puts("Board: Wind River SBC834x\n");
- return 0;
-}
-
-/*
- * if board is fitted with SDRAM
- */
-#if defined(CONFIG_SYS_BR2_PRELIM) \
- && defined(CONFIG_SYS_OR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void sdram_init(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &immap->im_lbc;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
- LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
- LSDMR_WRC3 | LSDMR_CL3;
-
- puts("\n SDRAM on Local Bus: ");
- print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers, already done in cpu_init.c
- */
-
- /* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = 0x00000000;
- /* LB refresh timer prescal, 266MHz/32 */
- lbc->mrtpr = 0x20000000;
- /* LB sdram refresh timer, about 6us */
- lbc->lsrt = 0x32000000;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
- /* 0x40636733; normal operation */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
-
- /* 0x68636733; precharge all the banks */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x48636733; auto refresh */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync");
- /*1 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*2 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*3 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*4 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*5 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*6 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*7 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*8 times*/
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x58636733; mode register write operation */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x40636733; normal operation */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-}
-#else
-void sdram_init(void)
-{
- puts(" SDRAM on Local Bus: Disabled in config\n");
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
deleted file mode 100644
index e428933b41e5..000000000000
--- a/configs/sbc8349_PCI_33_defconfig
+++ /dev/null
@@ -1,123 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=33000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_SBC8349=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_8_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_64BIT_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFF800000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI_33M"
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_ENV_ADDR_REDUND=0xFF860000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
deleted file mode 100644
index 4774cd9836fe..000000000000
--- a/configs/sbc8349_PCI_66_defconfig
+++ /dev/null
@@ -1,123 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_SBC8349=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_64BIT_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFF800000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI_66M"
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_ENV_ADDR_REDUND=0xFF860000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
deleted file mode 100644
index b69e66b61e1b..000000000000
--- a/configs/sbc8349_defconfig
+++ /dev/null
@@ -1,101 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFF800000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_SBC8349=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFF800000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFF840000
-CONFIG_ENV_ADDR_REDUND=0xFF860000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
deleted file mode 100644
index 929579efe133..000000000000
--- a/include/configs/sbc8349.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * WindRiver SBC8349 U-Boot configuration file.
- * Copyright (c) 2006, 2007 Wind River Systems, Inc.
- *
- * Paul Gortmaker <paul.gortmaker@windriver.com>
- * Based on the MPC8349EMDS config.
- */
-
-/*
- * sbc8349 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
-#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-#define CONFIG_DDR_2T_TIMING
-
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
-
-#else
-/*
- * Manually set up DDR parameters
- * NB: manual DDR setup untested on sbc834x
- */
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
-#define CONFIG_SYS_DDR_TIMING_1 0x36332321
-#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
-#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
-
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
- /* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000023
-#else
-/* the default burst length is 4 - for 64-bit data path */
- /* DLL,normal,seq,4/2.5, 4 burst len */
-#define CONFIG_SYS_DDR_MODE 0x00000022
-#endif
-#endif
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
- /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
- /* Size of used area in RAM*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0xFIXME
-#endif
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_PHY_BCM5421S 1
-#define TSEC1_PHY_ADDR 0x19
-#define TSEC2_PHY_ADDR 0x1a
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "SBC8349"
-#define CONFIG_ROOTPATH "/tftpboot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=sbc8349\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
- "update=protect off ff800000 ff83ffff; " \
- "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=sbc8349.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 07/27] ppc: Remove sbc8349 board
2021-05-15 1:34 ` [PATCH 07/27] ppc: Remove sbc8349 board Tom Rini
@ 2021-05-15 19:16 ` Paul Gortmaker
2021-07-08 2:52 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Paul Gortmaker @ 2021-05-15 19:16 UTC (permalink / raw)
To: u-boot
[[PATCH 07/27] ppc: Remove sbc8349 board] On 14/05/2021 (Fri 21:34) Tom Rini wrote:
> This board has not been converted to CONFIG_DM_MMC by the deadline.
> Remove it.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Ack - this was removed in the linux-kernel already.
Thanks,
Paul.
--
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
> board/sbc8349/Kconfig | 9 -
> board/sbc8349/MAINTAINERS | 8 -
> board/sbc8349/Makefile | 6 -
> board/sbc8349/README | 127 ------------
> board/sbc8349/pci.c | 70 -------
> board/sbc8349/sbc8349.c | 243 -----------------------
> configs/sbc8349_PCI_33_defconfig | 123 ------------
> configs/sbc8349_PCI_66_defconfig | 123 ------------
> configs/sbc8349_defconfig | 101 ----------
> include/configs/sbc8349.h | 322 -------------------------------
> 11 files changed, 1137 deletions(-)
> delete mode 100644 board/sbc8349/Kconfig
> delete mode 100644 board/sbc8349/MAINTAINERS
> delete mode 100644 board/sbc8349/Makefile
> delete mode 100644 board/sbc8349/README
> delete mode 100644 board/sbc8349/pci.c
> delete mode 100644 board/sbc8349/sbc8349.c
> delete mode 100644 configs/sbc8349_PCI_33_defconfig
> delete mode 100644 configs/sbc8349_PCI_66_defconfig
> delete mode 100644 configs/sbc8349_defconfig
> delete mode 100644 include/configs/sbc8349.h
>
> diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
> index ff85834c460c..e0bdfc4b9716 100644
> --- a/arch/powerpc/cpu/mpc83xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc83xx/Kconfig
> @@ -12,10 +12,6 @@ config TARGET_MPC8308_P1M
> bool "Support mpc8308_p1m"
> select ARCH_MPC8308
>
> -config TARGET_SBC8349
> - bool "Support sbc8349"
> - select ARCH_MPC8349
> -
> config TARGET_VE8313
> bool "Support ve8313"
> select ARCH_MPC8313
> @@ -312,7 +308,6 @@ source "board/freescale/mpc837xerdb/Kconfig"
> source "board/ids/ids8313/Kconfig"
> source "board/keymile/Kconfig"
> source "board/mpc8308_p1m/Kconfig"
> -source "board/sbc8349/Kconfig"
> source "board/tqc/tqm834x/Kconfig"
> source "board/ve8313/Kconfig"
> source "board/gdsys/mpc8308/Kconfig"
> diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig
> deleted file mode 100644
> index 129d6b92ec57..000000000000
> --- a/board/sbc8349/Kconfig
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -if TARGET_SBC8349
> -
> -config SYS_BOARD
> - default "sbc8349"
> -
> -config SYS_CONFIG_NAME
> - default "sbc8349"
> -
> -endif
> diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS
> deleted file mode 100644
> index af95c1dd0d23..000000000000
> --- a/board/sbc8349/MAINTAINERS
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -SBC8349 BOARD
> -M: Paul Gortmaker <paul.gortmaker@windriver.com>
> -S: Maintained
> -F: board/sbc8349/
> -F: include/configs/sbc8349.h
> -F: configs/sbc8349_defconfig
> -F: configs/sbc8349_PCI_33_defconfig
> -F: configs/sbc8349_PCI_66_defconfig
> diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
> deleted file mode 100644
> index c469174085d9..000000000000
> --- a/board/sbc8349/Makefile
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (c) 2006 Wind River Systems, Inc.
> -
> -obj-y += sbc8349.o
> -obj-$(CONFIG_PCI) += pci.o
> diff --git a/board/sbc8349/README b/board/sbc8349/README
> deleted file mode 100644
> index 3c142e040762..000000000000
> --- a/board/sbc8349/README
> +++ /dev/null
> @@ -1,127 +0,0 @@
> -
> -
> - U-Boot for Wind River SBC834x Boards
> - ====================================
> -
> -
> -The Wind River SBC834x board is a 6U form factor (not CPCI) reference
> -design that uses the MPC8347E or MPC8349E processor. U-Boot support
> -for this board is heavily based on the existing U-Boot support for
> -Freescale MPC8349 reference boards.
> -
> -Support has been primarily tested on the SBC8349 version of the board,
> -although earlier versions were also tested on the SBC8347. The primary
> -difference in the two is the level of PCI functionality.
> -
> - http://www.windriver.com/products/OCD/SBC8347E_49E/
> -
> -
> -Flash Details:
> -==============
> -
> -The flash type is intel 28F640Jx (4096x16) [one device]. Base address
> -is 0xFF80_0000 which is also where the Hardware Reset Configuration
> -Word (HRCW) is stored. Caution should be used to not reset the
> -board without having a valid HRCW in place (i.e. erased flash) as
> -then a Wind River ICE will be required to restore the HRCW and flash
> -image.
> -
> -
> -Restoring a corrupted or missing flash image:
> -=============================================
> -
> -Note that U-Boot versions up to and including 2009.06 had essentially
> -two copies of U-Boot in flash; one at the very beginning, which set
> -the HRCW, and one at the very end, which was the image that was run.
> -As of this point in time, the two have been combined into just one
> -at the beginning of flash, which provides both the HRCW, and the image
> -that is executed. This frees up the remainder of flash for other uses.
> -Use of the U-Boot command "fli" will indicate what parts are in use.
> -Details for storing U-Boot to flash using a Wind River ICE can be found
> -on page 19 of the board manual (request ERG-00328-001). The following
> -is a summary of that information:
> -
> - - Connect ICE and establish connection to it from WorkBench/OCD.
> - - Ensure you have background mode (BKM) in the OCD terminal window.
> - - Select the appropriate flash type (listed above)
> - - Prepare a U-Boot image by using the Wind River Convert utility;
> - by using "Convert and Add file" on the ELF file from your build.
> - Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
> - trying to preserve your old environment settings and user flash).
> - - Set the start address of the erase/flash process to FF80_0000
> - - Set the target RAM required to 64kB.
> - - Select sectors for erasing (see note on environment below)
> - - Select Erase and Reprogram.
> -
> -Note that some versions of the register files used with Workbench
> -would zero some TSEC registers, which inhibits ethernet operation
> -by U-Boot when this register file is played to the target. Using
> -"INN" in the OCD terminal window instead of "IN" before the "GO"
> -will not play the register file, and allow U-Boot to use the TSEC
> -interface while executed from the ICE "GO" command.
> -
> -Alternatively, you can locate the register file which will be named
> -WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
> -beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to
> -use all the remaining register file content.
> -
> -If you wish to preserve your prior U-Boot environment settings,
> -then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
> -The size for converting (and erasing) must be at least as large
> -as u-boot.bin.
> -
> -
> -Updating U-Boot with U-Boot:
> -============================
> -
> -This procedure is very similar to other boards that have U-Boot installed.
> -Assuming that the network has been configured, and that the new u-boot.bin
> -has been copied to the TFTP server, the commands are:
> -
> - tftp 200000 u-boot.bin
> - protect off all
> - erase ff800000 ff83ffff
> - cp.b 200000 ff800000 40000
> - protect on all
> -
> -You may wish to do a "md ff800000 20" operation as a prefix and postfix
> -to the above steps to inspect/compare the HRCW before/after as an extra
> -safety check before resetting the board upon completion of the reflash.
> -
> -PCI:
> -====
> -
> -There are three configuration choices:
> - sbc8349_config
> - sbc8349_PCI_33_config
> - sbc8349_PCI_66_config
> -
> -The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
> -will be left empty (M66EN high), and so the board will operate with
> -a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
> -and linux in order to have functional PCI under linux. The only
> -reason for choosing to not enable PCI would be if you had a very
> -early (rev 1.0) CPU with possible PCI issues.
> -
> -The second enables PCI support and builds for a 33MHz clock rate. Note
> -that if a 33MHz 32bit card is inserted in the slot, then the whole board
> -will clock down to a 33MHz base clock instead of the default 66MHz. This
> -will change the baud clocks and mess up your serial console output if you
> -were previously running at 66MHz. If you want to use a 33MHz PCI card,
> -then you should build a U-Boot with sbc8349_PCI_33_config and store this
> -to flash prior to powering down the board and inserting the 33MHz PCI
> -card.
> -
> -The third option builds PCI support in, and leaves the clocking at the
> -default 66MHz. This has been tested with an intel PCI-X e1000 card.
> -This is also the appropriate choice for people with a recent (non 1.0)
> -CPU who currently have the PCI slot physically empty, but intend to
> -possibly add a PCI-X card at a later date.
> -
> - => pci
> - Scanning PCI devices on bus 0
> - BusDevFun VendorId DeviceId Device Class Sub-Class
> - _____________________________________________________________
> - 00.00.00 0x1957 0x0080 Processor 0x20
> - 00.11.00 0x8086 0x1026 Network controller 0x00
> - =>
> diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
> deleted file mode 100644
> index 26c4f24e4f8b..000000000000
> --- a/board/sbc8349/pci.c
> +++ /dev/null
> @@ -1,70 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * pci.c -- WindRiver SBC8349 PCI board support.
> - * Copyright (c) 2006 Wind River Systems, Inc.
> - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
> - *
> - * Based on MPC8349 PCI support but w/o PIB related code.
> - */
> -
> -#include <init.h>
> -#include <asm/mmu.h>
> -#include <asm/io.h>
> -#include <common.h>
> -#include <mpc83xx.h>
> -#include <pci.h>
> -#include <i2c.h>
> -#include <asm/fsl_i2c.h>
> -#include <linux/delay.h>
> -
> -static struct pci_region pci1_regions[] = {
> - {
> - bus_start: CONFIG_SYS_PCI1_MEM_BASE,
> - phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
> - size: CONFIG_SYS_PCI1_MEM_SIZE,
> - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_IO_BASE,
> - phys_start: CONFIG_SYS_PCI1_IO_PHYS,
> - size: CONFIG_SYS_PCI1_IO_SIZE,
> - flags: PCI_REGION_IO
> - },
> - {
> - bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
> - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
> - size: CONFIG_SYS_PCI1_MMIO_SIZE,
> - flags: PCI_REGION_MEM
> - },
> -};
> -
> -/*
> - * pci_init_board()
> - *
> - * NOTICE: PCI2 is not supported. There is only one
> - * physical PCI slot on the board.
> - *
> - */
> -void
> -pci_init_board(void)
> -{
> - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
> - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
> - volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
> - struct pci_region *reg[] = { pci1_regions };
> -
> - /* Enable all 8 PCI_CLK_OUTPUTS */
> - clk->occr = 0xff000000;
> - udelay(2000);
> -
> - /* Configure PCI Local Access Windows */
> - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
> - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
> -
> - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
> - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
> -
> - udelay(2000);
> -
> - mpc83xx_pci_init(1, reg);
> -}
> diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
> deleted file mode 100644
> index b440a0b17e97..000000000000
> --- a/board/sbc8349/sbc8349.c
> +++ /dev/null
> @@ -1,243 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * sbc8349.c -- WindRiver SBC8349 board support.
> - * Copyright (c) 2006-2007 Wind River Systems, Inc.
> - *
> - * Paul Gortmaker <paul.gortmaker@windriver.com>
> - * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
> - */
> -
> -#include <common.h>
> -#include <fdt_support.h>
> -#include <init.h>
> -#include <ioports.h>
> -#include <mpc83xx.h>
> -#include <asm/bitops.h>
> -#include <asm/global_data.h>
> -#include <asm/mpc8349_pci.h>
> -#include <i2c.h>
> -#include <spd_sdram.h>
> -#include <miiphy.h>
> -#if defined(CONFIG_OF_LIBFDT)
> -#include <linux/libfdt.h>
> -#endif
> -#include <linux/delay.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int fixed_sdram(void);
> -void sdram_init(void);
> -
> -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
> -void ddr_enable_ecc(unsigned int dram_size);
> -#endif
> -
> -#ifdef CONFIG_BOARD_EARLY_INIT_F
> -int board_early_init_f (void)
> -{
> - return 0;
> -}
> -#endif
> -
> -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
> -
> -int dram_init(void)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = 0;
> -
> - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
> - return -1;
> -
> - /* DDR SDRAM - Main SODIMM */
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
> -#if defined(CONFIG_SPD_EEPROM)
> - msize = spd_sdram();
> -#else
> - msize = fixed_sdram();
> -#endif
> - /*
> - * Initialize SDRAM if it is on local bus.
> - */
> - sdram_init();
> -
> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> - /*
> - * Initialize and enable DDR ECC.
> - */
> - ddr_enable_ecc(msize * 1024 * 1024);
> -#endif
> - /* set total bus SDRAM size(bytes) -- DDR */
> - gd->ram_size = msize * 1024 * 1024;
> -
> - return 0;
> -}
> -
> -#if !defined(CONFIG_SPD_EEPROM)
> -/*************************************************************************
> - * fixed sdram init -- doesn't use serial presence detect.
> - ************************************************************************/
> -int fixed_sdram(void)
> -{
> - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> - u32 msize = CONFIG_SYS_DDR_SIZE;
> - u32 ddr_size = msize << 20; /* DDR size in bytes */
> - u32 ddr_size_log2 = __ilog2(msize);
> -
> - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
> - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
> -
> -#if (CONFIG_SYS_DDR_SIZE != 256)
> -#warning Currently any ddr size other than 256 is not supported
> -#endif
> -
> -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
> -#warning Chip select bounds is only configurable in 16MB increments
> -#endif
> - im->ddr.csbnds[2].csbnds =
> - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
> - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
> - CSBNDS_EA_SHIFT) & CSBNDS_EA);
> - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
> -
> - /* currently we use only one CS, so disable the other banks */
> - im->ddr.cs_config[0] = 0;
> - im->ddr.cs_config[1] = 0;
> - im->ddr.cs_config[3] = 0;
> -
> - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> -
> - im->ddr.sdram_cfg =
> - SDRAM_CFG_SREN
> -#if defined(CONFIG_DDR_2T_TIMING)
> - | SDRAM_CFG_2T_EN
> -#endif
> - | SDRAM_CFG_SDRAM_TYPE_DDR1;
> -#if defined (CONFIG_DDR_32BIT)
> - /* for 32-bit mode burst length is 8 */
> - im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
> -#endif
> - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
> -
> - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - udelay(200);
> -
> - /* enable DDR controller */
> - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
> - return msize;
> -}
> -#endif/*!CONFIG_SYS_SPD_EEPROM*/
> -
> -
> -int checkboard (void)
> -{
> - puts("Board: Wind River SBC834x\n");
> - return 0;
> -}
> -
> -/*
> - * if board is fitted with SDRAM
> - */
> -#if defined(CONFIG_SYS_BR2_PRELIM) \
> - && defined(CONFIG_SYS_OR2_PRELIM) \
> - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
> - && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
> -/*
> - * Initialize SDRAM memory on the Local Bus.
> - */
> -
> -void sdram_init(void)
> -{
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile fsl_lbc_t *lbc = &immap->im_lbc;
> - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
> - const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
> - LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
> - LSDMR_WRC3 | LSDMR_CL3;
> -
> - puts("\n SDRAM on Local Bus: ");
> - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
> -
> - /*
> - * Setup SDRAM Base and Option Registers, already done in cpu_init.c
> - */
> -
> - /* setup mtrpt, lsrt and lbcr for LB bus */
> - lbc->lbcr = 0x00000000;
> - /* LB refresh timer prescal, 266MHz/32 */
> - lbc->mrtpr = 0x20000000;
> - /* LB sdram refresh timer, about 6us */
> - lbc->lsrt = 0x32000000;
> - asm("sync");
> -
> - /*
> - * Configure the SDRAM controller Machine Mode Register.
> - */
> - /* 0x40636733; normal operation */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
> -
> - /* 0x68636733; precharge all the banks */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x48636733; auto refresh */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
> - asm("sync");
> - /*1 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*2 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*3 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*4 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*5 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*6 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*7 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> - /*8 times*/
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x58636733; mode register write operation */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -
> - /* 0x40636733; normal operation */
> - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
> - asm("sync");
> - *sdram_addr = 0xff;
> - udelay(100);
> -}
> -#else
> -void sdram_init(void)
> -{
> - puts(" SDRAM on Local Bus: Disabled in config\n");
> -}
> -#endif
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, struct bd_info *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -#ifdef CONFIG_PCI
> - ft_pci_setup(blob, bd);
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
> deleted file mode 100644
> index e428933b41e5..000000000000
> --- a/configs/sbc8349_PCI_33_defconfig
> +++ /dev/null
> @@ -1,123 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFF800000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_SYS_CLK_FREQ=33000000
> -CONFIG_MPC83xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8349=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_8_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_PCI_HOST_MODE_ENABLE=y
> -CONFIG_PCI_64BIT_MODE_ENABLE=y
> -CONFIG_PCI_INT_ARBITER1_ENABLE=y
> -CONFIG_BOOT_MEMORY_SPACE_LOW=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_GMII=y
> -CONFIG_TSEC2_MODE_GMII=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT1=y
> -CONFIG_BAT1_NAME="PCI1_MEM"
> -CONFIG_BAT1_BASE=0x80000000
> -CONFIG_BAT1_LENGTH_256_MBYTES=y
> -CONFIG_BAT1_ACCESS_RW=y
> -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_USER_MODE_VALID=y
> -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT2=y
> -CONFIG_BAT2_NAME="PCI1_MMIO"
> -CONFIG_BAT2_BASE=0x90000000
> -CONFIG_BAT2_LENGTH_256_MBYTES=y
> -CONFIG_BAT2_ACCESS_RW=y
> -CONFIG_BAT2_ICACHE_INHIBITED=y
> -CONFIG_BAT2_ICACHE_GUARDED=y
> -CONFIG_BAT2_DCACHE_INHIBITED=y
> -CONFIG_BAT2_DCACHE_GUARDED=y
> -CONFIG_BAT2_USER_MODE_VALID=y
> -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT5=y
> -CONFIG_BAT5_NAME="IMMR_PCIIO"
> -CONFIG_BAT5_BASE=0xE0000000
> -CONFIG_BAT5_LENGTH_256_MBYTES=y
> -CONFIG_BAT5_ACCESS_RW=y
> -CONFIG_BAT5_ICACHE_INHIBITED=y
> -CONFIG_BAT5_ICACHE_GUARDED=y
> -CONFIG_BAT5_DCACHE_INHIBITED=y
> -CONFIG_BAT5_DCACHE_GUARDED=y
> -CONFIG_BAT5_USER_MODE_VALID=y
> -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT6=y
> -CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
> -CONFIG_BAT6_BASE=0xF0000000
> -CONFIG_BAT6_LENGTH_256_MBYTES=y
> -CONFIG_BAT6_ACCESS_RW=y
> -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_ICACHE_GUARDED=y
> -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_DCACHE_GUARDED=y
> -CONFIG_BAT6_USER_MODE_VALID=y
> -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFF800000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFF800000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_XAM_SET=y
> -CONFIG_OR0_SCY_15=y
> -CONFIG_OR0_CSNT_EARLIER=y
> -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_TRLX_RELAXED=y
> -CONFIG_OR0_EHTR_8_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_4=y
> -CONFIG_PCI_64BIT=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="PCI_33M"
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> -CONFIG_ENV_ADDR=0xFF840000
> -CONFIG_ENV_ADDR_REDUND=0xFF860000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
> deleted file mode 100644
> index 4774cd9836fe..000000000000
> --- a/configs/sbc8349_PCI_66_defconfig
> +++ /dev/null
> @@ -1,123 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFF800000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_SYS_CLK_FREQ=66000000
> -CONFIG_MPC83xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8349=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_4_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_PCI_HOST_MODE_ENABLE=y
> -CONFIG_PCI_64BIT_MODE_ENABLE=y
> -CONFIG_PCI_INT_ARBITER1_ENABLE=y
> -CONFIG_BOOT_MEMORY_SPACE_LOW=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_GMII=y
> -CONFIG_TSEC2_MODE_GMII=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT1=y
> -CONFIG_BAT1_NAME="PCI1_MEM"
> -CONFIG_BAT1_BASE=0x80000000
> -CONFIG_BAT1_LENGTH_256_MBYTES=y
> -CONFIG_BAT1_ACCESS_RW=y
> -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT1_USER_MODE_VALID=y
> -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT2=y
> -CONFIG_BAT2_NAME="PCI1_MMIO"
> -CONFIG_BAT2_BASE=0x90000000
> -CONFIG_BAT2_LENGTH_256_MBYTES=y
> -CONFIG_BAT2_ACCESS_RW=y
> -CONFIG_BAT2_ICACHE_INHIBITED=y
> -CONFIG_BAT2_ICACHE_GUARDED=y
> -CONFIG_BAT2_DCACHE_INHIBITED=y
> -CONFIG_BAT2_DCACHE_GUARDED=y
> -CONFIG_BAT2_USER_MODE_VALID=y
> -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT5=y
> -CONFIG_BAT5_NAME="IMMR_PCIIO"
> -CONFIG_BAT5_BASE=0xE0000000
> -CONFIG_BAT5_LENGTH_256_MBYTES=y
> -CONFIG_BAT5_ACCESS_RW=y
> -CONFIG_BAT5_ICACHE_INHIBITED=y
> -CONFIG_BAT5_ICACHE_GUARDED=y
> -CONFIG_BAT5_DCACHE_INHIBITED=y
> -CONFIG_BAT5_DCACHE_GUARDED=y
> -CONFIG_BAT5_USER_MODE_VALID=y
> -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT6=y
> -CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
> -CONFIG_BAT6_BASE=0xF0000000
> -CONFIG_BAT6_LENGTH_256_MBYTES=y
> -CONFIG_BAT6_ACCESS_RW=y
> -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_ICACHE_GUARDED=y
> -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_DCACHE_GUARDED=y
> -CONFIG_BAT6_USER_MODE_VALID=y
> -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFF800000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFF800000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_XAM_SET=y
> -CONFIG_OR0_SCY_15=y
> -CONFIG_OR0_CSNT_EARLIER=y
> -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_TRLX_RELAXED=y
> -CONFIG_OR0_EHTR_8_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_4=y
> -CONFIG_PCI_64BIT=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="PCI_66M"
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> -CONFIG_ENV_ADDR=0xFF840000
> -CONFIG_ENV_ADDR_REDUND=0xFF860000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
> deleted file mode 100644
> index b69e66b61e1b..000000000000
> --- a/configs/sbc8349_defconfig
> +++ /dev/null
> @@ -1,101 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFF800000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_SYS_CLK_FREQ=66000000
> -CONFIG_MPC83xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8349=y
> -CONFIG_DDR_MC_CLOCK_MODE_1_1=y
> -CONFIG_SYSTEM_PLL_FACTOR_4_1=y
> -CONFIG_CORE_PLL_RATIO_2_1=y
> -CONFIG_PCI_HOST_MODE_ENABLE=y
> -CONFIG_PCI_INT_ARBITER1_ENABLE=y
> -CONFIG_PCI_INT_ARBITER2_ENABLE=y
> -CONFIG_BOOT_MEMORY_SPACE_LOW=y
> -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
> -CONFIG_TSEC1_MODE_GMII=y
> -CONFIG_TSEC2_MODE_GMII=y
> -CONFIG_BAT0=y
> -CONFIG_BAT0_NAME="SDRAM"
> -CONFIG_BAT0_BASE=0x00000000
> -CONFIG_BAT0_LENGTH_256_MBYTES=y
> -CONFIG_BAT0_ACCESS_RW=y
> -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT0_USER_MODE_VALID=y
> -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT5=y
> -CONFIG_BAT5_NAME="IMMR_PCIIO"
> -CONFIG_BAT5_BASE=0xE0000000
> -CONFIG_BAT5_LENGTH_256_MBYTES=y
> -CONFIG_BAT5_ACCESS_RW=y
> -CONFIG_BAT5_ICACHE_INHIBITED=y
> -CONFIG_BAT5_ICACHE_GUARDED=y
> -CONFIG_BAT5_DCACHE_INHIBITED=y
> -CONFIG_BAT5_DCACHE_GUARDED=y
> -CONFIG_BAT5_USER_MODE_VALID=y
> -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
> -CONFIG_BAT6=y
> -CONFIG_BAT6_NAME="LBC_INITRAM_FLASH"
> -CONFIG_BAT6_BASE=0xF0000000
> -CONFIG_BAT6_LENGTH_256_MBYTES=y
> -CONFIG_BAT6_ACCESS_RW=y
> -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_ICACHE_GUARDED=y
> -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
> -CONFIG_BAT6_DCACHE_GUARDED=y
> -CONFIG_BAT6_USER_MODE_VALID=y
> -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
> -CONFIG_LBLAW0=y
> -CONFIG_LBLAW0_BASE=0xFF800000
> -CONFIG_LBLAW0_NAME="FLASH"
> -CONFIG_LBLAW0_LENGTH_8_MBYTES=y
> -CONFIG_ELBC_BR0_OR0=y
> -CONFIG_BR0_OR0_NAME="FLASH"
> -CONFIG_BR0_OR0_BASE=0xFF800000
> -CONFIG_BR0_PORTSIZE_16BIT=y
> -CONFIG_OR0_AM_8_MBYTES=y
> -CONFIG_OR0_XAM_SET=y
> -CONFIG_OR0_SCY_15=y
> -CONFIG_OR0_CSNT_EARLIER=y
> -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
> -CONFIG_OR0_XACS_EXTENDED=y
> -CONFIG_OR0_TRLX_RELAXED=y
> -CONFIG_OR0_EHTR_8_CYCLE=y
> -CONFIG_OR0_EAD_EXTRA=y
> -CONFIG_HID0_FINAL_EMCP=y
> -CONFIG_HID0_FINAL_ICE=y
> -CONFIG_HID2_HBE=y
> -CONFIG_LCRR_DBYP_PLL_BYPASSED=y
> -CONFIG_LCRR_CLKDIV_4=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=6
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
> -CONFIG_ENV_ADDR=0xFF840000
> -CONFIG_ENV_ADDR_REDUND=0xFF860000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -# CONFIG_PCI is not set
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
> deleted file mode 100644
> index 929579efe133..000000000000
> --- a/include/configs/sbc8349.h
> +++ /dev/null
> @@ -1,322 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * WindRiver SBC8349 U-Boot configuration file.
> - * Copyright (c) 2006, 2007 Wind River Systems, Inc.
> - *
> - * Paul Gortmaker <paul.gortmaker@windriver.com>
> - * Based on the MPC8349EMDS config.
> - */
> -
> -/*
> - * sbc8349 board configuration file.
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/*
> - * High Level Configuration Options
> - */
> -#define CONFIG_E300 1 /* E300 Family */
> -
> -/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
> -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
> -
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -
> -/*
> - * DDR Setup
> - */
> -#undef CONFIG_DDR_ECC /* only for ECC DDR module */
> -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
> -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
> -#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
> -
> -/*
> - * 32-bit data path mode.
> - *
> - * Please note that using this mode for devices with the real density of 64-bit
> - * effectively reduces the amount of available memory due to the effect of
> - * wrapping around while translating address to row/columns, for example in the
> - * 256MB module the upper 128MB get aliased with contents of the lower
> - * 128MB); normally this define should be used for devices with real 32-bit
> - * data path.
> - */
> -#undef CONFIG_DDR_32BIT
> -
> -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
> -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
> - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
> -#define CONFIG_DDR_2T_TIMING
> -
> -#if defined(CONFIG_SPD_EEPROM)
> -/*
> - * Determine DDR configuration from I2C interface.
> - */
> -#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
> -
> -#else
> -/*
> - * Manually set up DDR parameters
> - * NB: manual DDR setup untested on sbc834x
> - */
> -#define CONFIG_SYS_DDR_SIZE 256 /* MB */
> -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
> - | CSCONFIG_ROW_BIT_13 \
> - | CSCONFIG_COL_BIT_10)
> -#define CONFIG_SYS_DDR_TIMING_1 0x36332321
> -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
> -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
> -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
> -
> -#if defined(CONFIG_DDR_32BIT)
> -/* set burst length to 8 for 32-bit data path */
> - /* DLL,normal,seq,4/2.5, 8 burst len */
> -#define CONFIG_SYS_DDR_MODE 0x00000023
> -#else
> -/* the default burst length is 4 - for 64-bit data path */
> - /* DLL,normal,seq,4/2.5, 4 burst len */
> -#define CONFIG_SYS_DDR_MODE 0x00000022
> -#endif
> -#endif
> -
> -/*
> - * SDRAM on the Local Bus
> - */
> -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
> -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
> -
> -/*
> - * FLASH on the Local Bus
> - */
> -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
> -#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
> -
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
> -#define CONFIG_SYS_RAMBOOT
> -#else
> -#undef CONFIG_SYS_RAMBOOT
> -#endif
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> - /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
> - /* Size of used area in RAM*/
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET \
> - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
> -
> -#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
> -
> -/*
> - * Serial Port
> - */
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
> -
> -/* I2C */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_FSL_I2C2_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
> -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
> -
> -/* TSEC */
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
> -#define CONFIG_SYS_TSEC2_OFFSET 0x25000
> -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
> -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
> -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
> -
> -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
> -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
> -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
> -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
> -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
> -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
> -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
> -
> -#if defined(CONFIG_PCI)
> -
> -
> -#if !defined(CONFIG_PCI_PNP)
> - #define PCI_ENET0_IOADDR 0xFIXME
> - #define PCI_ENET0_MEMADDR 0xFIXME
> - #define PCI_IDSEL_NUMBER 0xFIXME
> -#endif
> -
> -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
> -
> -#endif /* CONFIG_PCI */
> -
> -/*
> - * TSEC configuration
> - */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "TSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "TSEC1"
> -#define CONFIG_PHY_BCM5421S 1
> -#define TSEC1_PHY_ADDR 0x19
> -#define TSEC2_PHY_ADDR 0x1a
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -
> -/* Options are: TSEC[0-1] */
> -#define CONFIG_ETHPRIME "TSEC0"
> -
> -#endif /* CONFIG_TSEC_ENET */
> -
> -/*
> - * Environment
> - */
> -#ifndef CONFIG_SYS_RAMBOOT
> -/* Address and size of Redundant Environment Sector */
> -#endif
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 256 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> - /* Initial Memory map for Linux*/
> -#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
> -
> -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
> -
> -/* System IO Config */
> -#define CONFIG_SYS_SICRH 0
> -#define CONFIG_SYS_SICRL SICRL_LDP_A
> -
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#endif
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_HOSTNAME "SBC8349"
> -#define CONFIG_ROOTPATH "/tftpboot/rootfs"
> -#define CONFIG_BOOTFILE "uImage"
> -
> - /* default location for tftp and bootm */
> -#define CONFIG_LOADADDR 800000
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "hostname=sbc8349\0" \
> - "nfsargs=setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=${serverip}:${rootpath}\0" \
> - "ramargs=setenv bootargs root=/dev/ram rw\0" \
> - "addip=setenv bootargs ${bootargs} " \
> - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> - ":${hostname}:${netdev}:off panic=1\0" \
> - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
> - "flash_nfs=run nfsargs addip addtty;" \
> - "bootm ${kernel_addr}\0" \
> - "flash_self=run ramargs addip addtty;" \
> - "bootm ${kernel_addr} ${ramdisk_addr}\0" \
> - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
> - "bootm\0" \
> - "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
> - "update=protect off ff800000 ff83ffff; " \
> - "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
> - "upd=run load update\0" \
> - "fdtaddr=780000\0" \
> - "fdtfile=sbc8349.dtb\0" \
> - ""
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
> - "$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#define CONFIG_BOOTCOMMAND "run flash_self"
> -
> -#endif /* __CONFIG_H */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 07/27] ppc: Remove sbc8349 board
2021-05-15 1:34 ` [PATCH 07/27] ppc: Remove sbc8349 board Tom Rini
2021-05-15 19:16 ` Paul Gortmaker
@ 2021-07-08 2:52 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:52 UTC (permalink / raw)
To: u-boot; +Cc: Paul Gortmaker
[-- Attachment #1: Type: text/plain, Size: 300 bytes --]
On Fri, May 14, 2021 at 09:34:12PM -0400, Tom Rini wrote:
> This board has not been converted to CONFIG_DM_MMC by the deadline.
> Remove it.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 08/27] ppc: Remove many T104x boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (5 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 07/27] ppc: Remove sbc8349 board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 09/27] ppc: Remove mpc8308_p1m board Tom Rini
` (19 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or
in some cases CONFIG_DM itself by the deadline. Remove them.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 16 -----
arch/powerpc/include/asm/fsl_secure_boot.h | 2 -
configs/T1040D4RDB_NAND_defconfig | 78 ---------------------
configs/T1040D4RDB_SDCARD_defconfig | 75 --------------------
configs/T1040D4RDB_SPIFLASH_defconfig | 77 ---------------------
configs/T1040D4RDB_defconfig | 62 -----------------
configs/T1040RDB_NAND_defconfig | 79 ----------------------
configs/T1040RDB_SDCARD_defconfig | 76 ---------------------
configs/T1040RDB_SPIFLASH_defconfig | 78 ---------------------
configs/T1040RDB_defconfig | 63 -----------------
configs/T1042D4RDB_SECURE_BOOT_defconfig | 66 ------------------
configs/T1042RDB_PI_NAND_defconfig | 79 ----------------------
configs/T1042RDB_PI_SDCARD_defconfig | 76 ---------------------
configs/T1042RDB_PI_SPIFLASH_defconfig | 78 ---------------------
configs/T1042RDB_PI_defconfig | 63 -----------------
configs/T1042RDB_defconfig | 62 -----------------
16 files changed, 1030 deletions(-)
delete mode 100644 configs/T1040D4RDB_NAND_defconfig
delete mode 100644 configs/T1040D4RDB_SDCARD_defconfig
delete mode 100644 configs/T1040D4RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1040D4RDB_defconfig
delete mode 100644 configs/T1040RDB_NAND_defconfig
delete mode 100644 configs/T1040RDB_SDCARD_defconfig
delete mode 100644 configs/T1040RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1040RDB_defconfig
delete mode 100644 configs/T1042D4RDB_SECURE_BOOT_defconfig
delete mode 100644 configs/T1042RDB_PI_NAND_defconfig
delete mode 100644 configs/T1042RDB_PI_SDCARD_defconfig
delete mode 100644 configs/T1042RDB_PI_SPIFLASH_defconfig
delete mode 100644 configs/T1042RDB_PI_defconfig
delete mode 100644 configs/T1042RDB_defconfig
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 206ee76a50b8..676aaf1d2ca6 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -147,22 +147,6 @@ config TARGET_T1024RDB
imply CMD_EEPROM
imply PANIC_HANG
-config TARGET_T1040RDB
- bool "Support T1040RDB"
- select ARCH_T1040
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
-config TARGET_T1040D4RDB
- bool "Support T1040D4RDB"
- select ARCH_T1040
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
config TARGET_T1042RDB
bool "Support T1042RDB"
select ARCH_T1042
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 6499e10ef4fb..53bfb8f64af7 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -25,8 +25,6 @@
defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
- defined(CONFIG_TARGET_T1040RDB) || \
- defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042RDB) || \
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
deleted file mode 100644
index fadf07b49d83..000000000000
--- a/configs/T1040D4RDB_NAND_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
deleted file mode 100644
index a56018e5b507..000000000000
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
deleted file mode 100644
index ed3a7bfa1d8a..000000000000
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
deleted file mode 100644
index d1c646ccd03b..000000000000
--- a/configs/T1040D4RDB_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
deleted file mode 100644
index 2aeae95e7733..000000000000
--- a/configs/T1040RDB_NAND_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
deleted file mode 100644
index 0a29e097c2f9..000000000000
--- a/configs/T1040RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
deleted file mode 100644
index f162019ab3e7..000000000000
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
deleted file mode 100644
index 119ad36ea9c7..000000000000
--- a/configs/T1040RDB_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index b36b36a46d05..000000000000
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042D4RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
deleted file mode 100644
index 209078f11b43..000000000000
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x180000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
deleted file mode 100644
index bf1da4087b33..000000000000
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
deleted file mode 100644
index 3f4dd96b48f6..000000000000
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
deleted file mode 100644
index 60fbb80bb88e..000000000000
--- a/configs/T1042RDB_PI_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
deleted file mode 100644
index 33bc8cba2ddc..000000000000
--- a/configs/T1042RDB_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 09/27] ppc: Remove mpc8308_p1m board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (6 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 08/27] ppc: Remove many T104x boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 10/27] ppc: Remove ve8313 board Tom Rini
` (18 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Cc: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
board/mpc8308_p1m/Kconfig | 9 -
board/mpc8308_p1m/MAINTAINERS | 6 -
board/mpc8308_p1m/Makefile | 8 -
board/mpc8308_p1m/mpc8308_p1m.c | 92 ---------
board/mpc8308_p1m/sdram.c | 80 --------
configs/mpc8308_p1m_defconfig | 133 -------------
include/configs/mpc8308_p1m.h | 307 -------------------------------
8 files changed, 640 deletions(-)
delete mode 100644 board/mpc8308_p1m/Kconfig
delete mode 100644 board/mpc8308_p1m/MAINTAINERS
delete mode 100644 board/mpc8308_p1m/Makefile
delete mode 100644 board/mpc8308_p1m/mpc8308_p1m.c
delete mode 100644 board/mpc8308_p1m/sdram.c
delete mode 100644 configs/mpc8308_p1m_defconfig
delete mode 100644 include/configs/mpc8308_p1m.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index e0bdfc4b9716..23f7a60a44c0 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -8,10 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_MPC8308_P1M
- bool "Support mpc8308_p1m"
- select ARCH_MPC8308
-
config TARGET_VE8313
bool "Support ve8313"
select ARCH_MPC8313
@@ -307,7 +303,6 @@ source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
-source "board/mpc8308_p1m/Kconfig"
source "board/tqc/tqm834x/Kconfig"
source "board/ve8313/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
diff --git a/board/mpc8308_p1m/Kconfig b/board/mpc8308_p1m/Kconfig
deleted file mode 100644
index b7e39dafbc62..000000000000
--- a/board/mpc8308_p1m/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MPC8308_P1M
-
-config SYS_BOARD
- default "mpc8308_p1m"
-
-config SYS_CONFIG_NAME
- default "mpc8308_p1m"
-
-endif
diff --git a/board/mpc8308_p1m/MAINTAINERS b/board/mpc8308_p1m/MAINTAINERS
deleted file mode 100644
index 80d8de7711f2..000000000000
--- a/board/mpc8308_p1m/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8308_P1M BOARD
-M: Ilya Yanok <yanok@emcraft.com>
-S: Maintained
-F: board/mpc8308_p1m/
-F: include/configs/mpc8308_p1m.h
-F: configs/mpc8308_p1m_defconfig
diff --git a/board/mpc8308_p1m/Makefile b/board/mpc8308_p1m/Makefile
deleted file mode 100644
index 4ec3b0cda92b..000000000000
--- a/board/mpc8308_p1m/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-# (C) Copyright 2010
-# Ilya Yanok, Emcraft Systems, yanok at emcraft.com
-
-obj-y := mpc8308_p1m.o sdram.o
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
deleted file mode 100644
index 87607bd48983..000000000000
--- a/board/mpc8308_p1m/mpc8308_p1m.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-int checkboard(void)
-{
- printf("Board: MPC8308 P1M\n");
-
- return 0;
-}
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- sysconf83xx_t *sysconf = &immr->sysconf;
- law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
- fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(1, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
- return 0;
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
- int rv, num_if = 0;
-
- /* Initialize TSECs first */
- rv = cpu_eth_init(bis);
- if (rv >= 0)
- num_if += rv;
- else
- printf("ERROR: failed to initialize TSECs.\n");
-
- rv = pci_eth_init(bis);
- if (rv >= 0)
- num_if += rv;
- else
- printf("ERROR: failed to initialize PCI Ethernet.\n");
-
- return num_if;
-}
diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
deleted file mode 100644
index 62a2d8a53afa..000000000000
--- a/board/mpc8308_p1m/sdram.c
+++ /dev/null
@@ -1,80 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- * This files is mostly identical to the original from
- * board/freescale/mpc8308rdb/sdram.c
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <asm/global_data.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
- u32 msize_log2 = __ilog2(msize);
-
- out_be32(&im->sysconf.ddrlaw[0].bar,
- CONFIG_SYS_SDRAM_BASE & 0xfffff000);
- out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
- out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
- out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
- /* Currently we use only one CS, so disable the other bank. */
- out_be32(&im->ddr.cs_config[1], 0);
-
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
- out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
- out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
- out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
- out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
-
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
- sync();
-
- /* enable DDR controller */
- setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
- sync();
-
- return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
-}
-
-int dram_init(void)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize;
-
- if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM */
- msize = fixed_sdram();
-
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize;
-
- return 0;
-}
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
deleted file mode 100644
index 75966ed3b400..000000000000
--- a/configs/mpc8308_p1m_defconfig
+++ /dev/null
@@ -1,133 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFC000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=33333333
-CONFIG_MPC83xx=y
-CONFIG_TARGET_MPC8308_P1M=y
-CONFIG_SYSTEM_PLL_VCO_DIV_2=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_3_1=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_128_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMRBAR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_8_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="FLASH"
-CONFIG_BAT2_BASE=0xFC000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="STACKINDCACHE"
-CONFIG_BAT3_BASE=0xE6000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFC000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_64_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xFBFF0000
-CONFIG_LBLAW1_NAME="SJA1000"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xFBFF8000
-CONFIG_LBLAW2_NAME="CPLD"
-CONFIG_LBLAW2_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFC000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_64_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_4=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="SJA1000"
-CONFIG_BR1_OR1_BASE=0xFBFF0000
-CONFIG_OR1_SCY_5=y
-CONFIG_OR1_EHTR_1_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="CPLD"
-CONFIG_BR2_OR2_BASE=0xFBFF8000
-CONFIG_OR2_SCY_4=y
-CONFIG_OR2_EHTR_1_CYCLE=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_SICR_ESDHC_A_GPIO=y
-CONFIG_SICR_ESDHC_B_GPIO=y
-CONFIG_SICR_ESDHC_C_GTM=y
-CONFIG_SICR_GPIO_A_TSEC2=y
-CONFIG_SICR_GPIO_B_TSEC2=y
-CONFIG_SICR_IEEE1588_A_GPIO=y
-CONFIG_SICR_GTM_GPIO=y
-CONFIG_SICR_GPIOSEL_IEEE1588=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=5
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFC060000
-CONFIG_ENV_ADDR_REDUND=0xFC080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
deleted file mode 100644
index 489200996c11..000000000000
--- a/include/configs/mpc8308_p1m.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
- * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok at emcraft.com
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-
-/*
- * On-board devices
- *
- * TSECs
- */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-
-#define CONFIG_SYS_GPIO1_PRELIM
-/* GPIO Default input/output settings */
-#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00
-/*
- * Default GPIO values:
- * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
- */
-#define CONFIG_SYS_GPIO1_DAT 0x08008C00
-
-/*
- * SERDES
- */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1 0xe3000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_LOZ \
- | DDRCDR_NZ_LOZ \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of two chips HY5PS12621BFP-C4 from HYNIX
- */
-
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (6 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (4 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-
-/*
- * Memory test
- */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024)
-/* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
-
-/*
- * SJA1000 CAN controller on Local Bus
- */
-#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
-
-
-/*
- * CPLD on Local Bus
- */
-#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
-
-
-/*
- * Serial Port
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
-
-/* enable PCIE clock */
-#define CONFIG_SYS_SCCR_PCIEXP1CM 1
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
-
-/*
- * TSEC
- */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define TSEC1_PHY_ADDR 1
-#define TSEC2_PHY_ADDR 2
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS 0
-#define TSEC2_FLAGS 0
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME "eTSEC0"
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs}" \
- " console=${consoledev},${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addmisc=setenv bootargs ${bootargs}\0" \
- "kernel_addr=FC0A0000\0" \
- "fdt_addr=FC2A0000\0" \
- "ramdisk_addr=FC2C0000\0" \
- "u-boot=mpc8308_p1m/u-boot.bin\0" \
- "kernel_addr_r=1000000\0" \
- "fdt_addr_r=C00000\0" \
- "hostname=mpc8308_p1m\0" \
- "bootfile=mpc8308_p1m/uImage\0" \
- "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \
- "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
- "flash_self=run ramargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
- "tftp ${fdt_addr_r} ${fdtfile};" \
- "run nfsargs addip addtty addmtd addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "bootcmd=run flash_self\0" \
- "load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
- " +${filesize};cp.b ${fileaddr} " \
- __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
- "upd=run load update\0" \
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 10/27] ppc: Remove ve8313 board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (7 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 09/27] ppc: Remove mpc8308_p1m board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-15 4:34 ` Heiko Schocher
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 11/27] ppc: Remove MPC8313ERDB boards Tom Rini
` (17 subsequent siblings)
26 siblings, 2 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
board/ve8313/Kconfig | 9 --
board/ve8313/MAINTAINERS | 6 -
board/ve8313/Makefile | 6 -
board/ve8313/ve8313.c | 209 -------------------------
configs/ve8313_defconfig | 160 -------------------
include/configs/ve8313.h | 260 -------------------------------
7 files changed, 655 deletions(-)
delete mode 100644 board/ve8313/Kconfig
delete mode 100644 board/ve8313/MAINTAINERS
delete mode 100644 board/ve8313/Makefile
delete mode 100644 board/ve8313/ve8313.c
delete mode 100644 configs/ve8313_defconfig
delete mode 100644 include/configs/ve8313.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 23f7a60a44c0..0d24574ecc4d 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -8,10 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_VE8313
- bool "Support ve8313"
- select ARCH_MPC8313
-
config TARGET_VME8349
bool "Support vme8349"
select ARCH_MPC8349
@@ -304,7 +300,6 @@ source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
source "board/tqc/tqm834x/Kconfig"
-source "board/ve8313/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
endmenu
diff --git a/board/ve8313/Kconfig b/board/ve8313/Kconfig
deleted file mode 100644
index a63744b1546e..000000000000
--- a/board/ve8313/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_VE8313
-
-config SYS_BOARD
- default "ve8313"
-
-config SYS_CONFIG_NAME
- default "ve8313"
-
-endif
diff --git a/board/ve8313/MAINTAINERS b/board/ve8313/MAINTAINERS
deleted file mode 100644
index e3ca3325fcea..000000000000
--- a/board/ve8313/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VE8313 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/ve8313/
-F: include/configs/ve8313.h
-F: configs/ve8313_defconfig
diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile
deleted file mode 100644
index d656bd93ab1d..000000000000
--- a/board/ve8313/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := ve8313.o
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
deleted file mode 100644
index 78d401e955eb..000000000000
--- a/board/ve8313/ve8313.c
+++ /dev/null
@@ -1,209 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <scottwood@freescale.com>
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <ns16550.h>
-#include <nand.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void disable_addr_trans (void);
-extern void enable_addr_trans (void);
-
-int checkboard(void)
-{
- puts("Board: ve8313\n");
- return 0;
-}
-
-static long fixed_sdram(void)
-{
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize_log2 = __ilog2(msize);
-
- out_be32(&im->sysconf.ddrlaw[0].bar,
- (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
- out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
- out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
-
- /*
- * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
- * or the DDR2 controller may fail to initialize correctly.
- */
- __udelay(50000);
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- out_be32(&im->ddr.csbnds[0].csbnds,
- ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
- CSBNDS_EA));
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
-
- /* Currently we use only one CS, so disable the other bank. */
- out_be32(&im->ddr.cs_config[1], 0);
-
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
- out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
-
- out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
- out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
- out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
-
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
- sync();
-
- /* enable DDR controller */
- setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
-
- /* now check the real size */
- disable_addr_trans ();
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
- enable_addr_trans ();
-#endif
-
- return msize;
-}
-
-int dram_init(void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &im->im_lbc;
- u32 msize;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- msize = fixed_sdram();
-
- /* Local Bus setup lbcr and mrtpr */
- out_be32(&lbc->lbcr, 0x00040000);
- out_be32(&lbc->mrtpr, 0x20000000);
- sync();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize;
-
- return 0;
-}
-
-#define VE8313_WDT_EN 0x00020000
-#define VE8313_WDT_TRIG 0x00040000
-
-int board_early_init_f (void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
-
-#if defined(CONFIG_HW_WATCHDOG)
- /* enable WDT */
- clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
-#else
- /* disable WDT */
- setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
-#endif
- /* set WDT pins as output */
- setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
-
- return 0;
-}
-
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
- unsigned long reg;
-
- reg = in_be32(&gpio->dat);
- if (reg & VE8313_WDT_TRIG)
- clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
- else
- setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
-}
-#endif
-
-
-#if defined(CONFIG_PCI)
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- setbits_be32(&clk->occr, 0xe0000000);
-
- /*
- * Configure PCI Local Access Windows
- */
- out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
- out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
- out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
-
- mpc83xx_pci_init(1, reg);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
deleted file mode 100644
index ed98cd1936ac..000000000000
--- a/configs/ve8313_defconfig
+++ /dev/null
@@ -1,160 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=32000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_VE8313=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_25_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_LALE_TIMING_EARLIER=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO_BCSR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="INITRAM_FLASH"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="FPGA_SRAM_NAND"
-CONFIG_BAT7_BASE=0x60000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_NAND_LBLAWBAR_PRELIM_1=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0x61000000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_32_MBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0x61000000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_BCTLD_NOT_ASSERTED=y
-CONFIG_OR1_SCY_2=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_RST_ONE_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="NVRAM"
-CONFIG_BR2_OR2_BASE=0x60000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_3=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="SRAM"
-CONFIG_BR3_OR3_BASE=0x62000000
-CONFIG_BR3_PORTSIZE_16BIT=y
-CONFIG_OR3_AM_32_MBYTES=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_EADC_3=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE060000
-CONFIG_ENV_ADDR_REDUND=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
deleted file mode 100644
index 91249f2eb482..000000000000
--- a/include/configs/ve8313.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- */
-/*
- * ve8313 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-
-#define CONFIG_PCI_INDIRECT_BRIDGE 1
-
-/*
- * On-board devices
- *
- */
-
-/*
- * Device configurations
- */
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-
-/*
- * Manually set up DDR parameters, as this board does not
- * have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_AP \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ALL \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80840102 */
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (3 << TIMING_CFG0_RRT_SHIFT) \
- | (2 << TIMING_CFG0_WWT_SHIFT) \
- | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x0e720802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (6 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x26256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x029028c7 */
-#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03202000 */
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
- /* 0x73000002 */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-/*
- * NAND settings
- */
-#define CONFIG_SYS_NAND_BASE 0x61000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-
-
-
-/* Still needed for spl_minimal.c */
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-
-
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-#endif
-
-/*
- * TSEC
- */
-
-#define CONFIG_TSEC1
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC1"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x01
-#define TSEC1_FLAGS 0
-#define TSEC1_PHYIDX 0
-#endif
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Environment
- */
-/* Address and size of Redundant Environment Sector */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (0x01000000 | \
- SICRH_ETSEC2_B | \
- SICRH_ETSEC2_C | \
- SICRH_ETSEC2_D | \
- SICRH_ETSEC2_E | \
- SICRH_ETSEC2_F | \
- SICRH_ETSEC2_G | \
- SICRH_TSOBI1 | \
- SICRH_TSOBI2)
- /* 0x010fff03 */
-#define CONFIG_SYS_SICRL (SICRL_LBC | \
- SICRL_SPI_A | \
- SICRL_SPI_B | \
- SICRL_SPI_C | \
- SICRL_SPI_D | \
- SICRL_ETSEC2_A)
- /* 0x33fc0003) */
-
-#define CONFIG_NETDEV eth0
-
-#define CONFIG_HOSTNAME "ve8313"
-#define CONFIG_UBOOTPATH ve8313/u-boot.bin
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" __stringify(CONFIG_NETDEV) "\0" \
- "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
- "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "u-boot_addr_r=100000\0" \
- "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
- " +${filesize};" \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize};" \
- "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 10/27] ppc: Remove ve8313 board
2021-05-15 1:34 ` [PATCH 10/27] ppc: Remove ve8313 board Tom Rini
@ 2021-05-15 4:34 ` Heiko Schocher
2021-07-08 2:52 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Heiko Schocher @ 2021-05-15 4:34 UTC (permalink / raw)
To: u-boot
Hello Tom,
On 15.05.21 03:34, Tom Rini wrote:
> This board has not been converted to CONFIG_DM_PCI by the deadline.
> Remove it.
>
> Cc: Heiko Schocher <hs@denx.de>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
> board/ve8313/Kconfig | 9 --
> board/ve8313/MAINTAINERS | 6 -
> board/ve8313/Makefile | 6 -
> board/ve8313/ve8313.c | 209 -------------------------
> configs/ve8313_defconfig | 160 -------------------
> include/configs/ve8313.h | 260 -------------------------------
> 7 files changed, 655 deletions(-)
> delete mode 100644 board/ve8313/Kconfig
> delete mode 100644 board/ve8313/MAINTAINERS
> delete mode 100644 board/ve8313/Makefile
> delete mode 100644 board/ve8313/ve8313.c
> delete mode 100644 configs/ve8313_defconfig
> delete mode 100644 include/configs/ve8313.h
Thanks!
Acked-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 10/27] ppc: Remove ve8313 board
2021-05-15 1:34 ` [PATCH 10/27] ppc: Remove ve8313 board Tom Rini
2021-05-15 4:34 ` Heiko Schocher
@ 2021-07-08 2:52 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:52 UTC (permalink / raw)
To: u-boot; +Cc: Heiko Schocher
[-- Attachment #1: Type: text/plain, Size: 323 bytes --]
On Fri, May 14, 2021 at 09:34:15PM -0400, Tom Rini wrote:
> This board has not been converted to CONFIG_DM_PCI by the deadline.
> Remove it.
>
> Cc: Heiko Schocher <hs@denx.de>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Acked-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 11/27] ppc: Remove MPC8313ERDB boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (8 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 10/27] ppc: Remove ve8313 board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 12/27] ppc: Remove caddy2 / vme8349 boards Tom Rini
` (16 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 13 -
board/freescale/mpc8313erdb/Kconfig | 25 --
board/freescale/mpc8313erdb/MAINTAINERS | 9 -
board/freescale/mpc8313erdb/Makefile | 6 -
board/freescale/mpc8313erdb/README | 111 ------
board/freescale/mpc8313erdb/mpc8313erdb.c | 160 ---------
board/freescale/mpc8313erdb/sdram.c | 129 -------
configs/MPC8313ERDB_33_defconfig | 169 ----------
configs/MPC8313ERDB_66_defconfig | 168 ----------
configs/MPC8313ERDB_NAND_33_defconfig | 178 ----------
configs/MPC8313ERDB_NAND_66_defconfig | 177 ----------
include/configs/MPC8313ERDB_NAND.h | 392 ----------------------
include/configs/MPC8313ERDB_NOR.h | 361 --------------------
13 files changed, 1898 deletions(-)
delete mode 100644 board/freescale/mpc8313erdb/Kconfig
delete mode 100644 board/freescale/mpc8313erdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8313erdb/Makefile
delete mode 100644 board/freescale/mpc8313erdb/README
delete mode 100644 board/freescale/mpc8313erdb/mpc8313erdb.c
delete mode 100644 board/freescale/mpc8313erdb/sdram.c
delete mode 100644 configs/MPC8313ERDB_33_defconfig
delete mode 100644 configs/MPC8313ERDB_66_defconfig
delete mode 100644 configs/MPC8313ERDB_NAND_33_defconfig
delete mode 100644 configs/MPC8313ERDB_NAND_66_defconfig
delete mode 100644 include/configs/MPC8313ERDB_NAND.h
delete mode 100644 include/configs/MPC8313ERDB_NOR.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 0d24574ecc4d..e4c6f5d40b26 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -16,18 +16,6 @@ config TARGET_CADDY2
bool "Support caddy2"
select ARCH_MPC8349
-config TARGET_MPC8313ERDB_NOR
- bool "Support MPC8313ERDB_NOR"
- select ARCH_MPC8313
- select BOARD_EARLY_INIT_F
- select SUPPORT_SPL
-
-config TARGET_MPC8313ERDB_NAND
- bool "Support MPC8313ERDB_NAND"
- select ARCH_MPC8313
- select BOARD_EARLY_INIT_F
- select SUPPORT_SPL
-
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
select ARCH_MPC8315
@@ -291,7 +279,6 @@ config FSL_ELBC
bool
source "board/esd/vme8349/Kconfig"
-source "board/freescale/mpc8313erdb/Kconfig"
source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
deleted file mode 100644
index b6332a1368bf..000000000000
--- a/board/freescale/mpc8313erdb/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_MPC8313ERDB_NOR
-
-config SYS_BOARD
- default "mpc8313erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8313ERDB_NOR"
-
-endif
-
-if TARGET_MPC8313ERDB_NAND
-
-config SYS_BOARD
- default "mpc8313erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8313ERDB_NAND"
-
-endif
diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
deleted file mode 100644
index 807fb0b6e9eb..000000000000
--- a/board/freescale/mpc8313erdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MPC8313ERDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/mpc8313erdb/
-F: include/configs/MPC8313ERDB.h
-F: configs/MPC8313ERDB_33_defconfig
-F: configs/MPC8313ERDB_66_defconfig
-F: configs/MPC8313ERDB_NAND_33_defconfig
-F: configs/MPC8313ERDB_NAND_66_defconfig
diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
deleted file mode 100644
index af600ccdbb5f..000000000000
--- a/board/freescale/mpc8313erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := mpc8313erdb.o sdram.o
diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
deleted file mode 100644
index 697cee4c42ee..000000000000
--- a/board/freescale/mpc8313erdb/README
+++ /dev/null
@@ -1,111 +0,0 @@
-Freescale MPC8313ERDB Board
------------------------------------------
-
-1. Board Switches and Jumpers
-
- S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
- To boot the image at 0xFE000000 in NOR flash, use these DIP
- switch settings for S3 S4:
-
- +------+ +------+
- | | | **** |
- | **** | | |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- To boot the image at the beginning of NAND flash, use these
- DIP switch settings for S3 S4:
-
- +------+ +------+
- | * | | *** |
- | *** | | * |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x07ff_ffff DDR 128M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xe200_0000 0xe20f_ffff PCI IO 16M
- 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
- 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K
- 0xfa00_0000 0xfa00_7fff Board Status/ 32K
- LED Control (CS3)
- 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
-
- When booting from NAND, NAND flash is CS0 and NOR flash
- is CS1.
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8313ERDB.h
-
- CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC831x MPC831x specific
- CONFIG_MPC8313ERDB MPC8313ERDB board specific
-
-4. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make MPC8313ERDB_XXX_config
- (where XXX is:
- 33 - 33 MHz oscillator, boot from NOR flash
- 66 - 66 MHz oscillator, boot from NOR flash
- NAND_33 - 33 MHz oscillator, boot from NAND flash
- NAND_66 - 66 MHz oscillator, boot from NAND flash)
- make
-
-5. Downloading and Flashing Images
-
-5.1 Reflash U-Boot Image using U-Boot
-
- NOR flash:
-
- =>run tftpflash
-
- You may want to try
- =>tftpboot $loadaddr $uboot
- first, to make sure that the TFTP load will succeed before it
- goes ahead and wipes out your current firmware. And of course,
- have an alternate means of programming the flash available
- if the new U-Boot doesn't boot.
-
- NAND flash:
-
- =>tftpboot $loadaddr <filename>
- =>nand erase 0 0x80000
- =>nand write $loadaddr 0 0x80000
-
- ...where 0x80000 is the filesize rounded up to
- the next 0x20000 increment.
-
-5.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, rootpath (if using NFS root),
- fdtfile, and bootfile).
-
- Then, do one of the following, depending on whether you
- want an NFS root or a ramdisk root:
-
- =>run nfsboot
- or
- =>run ramboot
-
-6 Notes
-
- The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
deleted file mode 100644
index 3bf5cff1e100..000000000000
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Author: Scott Wood <scottwood@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <fdt_support.h>
-#include <init.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <pci.h>
-#include <mpc83xx.h>
-#include <vsc7385.h>
-#include <ns16550.h>
-#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
-#include <asm/gpio.h>
-#endif
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- gd->flags |= GD_FLG_SILENT;
-#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
- mpc83xx_gpio_init_f();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
- mpc83xx_gpio_init_r();
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8313ERDB\n");
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-static struct pci_region pci_regions[] = {
- {
- .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
- .size = CONFIG_SYS_PCI1_MEM_SIZE,
- .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
- .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
- .size = CONFIG_SYS_PCI1_MMIO_SIZE,
- .flags = PCI_REGION_MEM
- },
- {
- .bus_start = CONFIG_SYS_PCI1_IO_BASE,
- .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
- .size = CONFIG_SYS_PCI1_IO_SIZE,
- .flags = PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- *
- * If a VSC7385 microcode image is present, then upload it.
-*/
-int misc_init_r(void)
-{
- int rc = 0;
-
-#ifdef CONFIG_VSC7385_IMAGE
- if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
- CONFIG_VSC7385_IMAGE_SIZE)) {
- puts("Failure uploading VSC7385 microcode.\n");
- rc = 1;
- }
-#endif
-
- return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
-#else /* CONFIG_SPL_BUILD */
-void board_init_f(ulong bootflag)
-{
- board_early_init_f();
- ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
- puts("NAND boot... ");
- timer_init();
- dram_init();
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (gd->flags & GD_FLG_SILENT)
- return;
-
- if (c == '\n')
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
deleted file mode 100644
index f146ae5d43c4..000000000000
--- a/board/freescale/mpc8313erdb/sdram.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- *
- * Authors: Nick.Spence at freescale.com
- * Wilson.Lo at freescale.com
- * scottwood at freescale.com
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
-static void resume_from_sleep(void)
-{
- u32 magic = *(u32 *)0;
-
- typedef void (*func_t)(void);
- func_t resume = *(func_t *)4;
-
- if (magic == 0xf5153ae5)
- resume();
-
- gd->flags &= ~GD_FLG_SILENT;
- puts("\nResume from sleep failed: bad magic word\n");
-}
-#endif
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-static long fixed_sdram(void)
-{
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
- /*
- * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
- * or the DDR2 controller may fail to initialize correctly.
- */
- __udelay(50000);
-
-#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
- CSBNDS_EA);
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
- /* Currently we use only one CS, so disable the other bank. */
- im->ddr.cs_config[1] = 0;
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
- else
-#endif
- im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
-
- im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- sync();
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-#endif
-
- return msize;
-}
-
-int dram_init(void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &im->im_lbc;
- u32 msize;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -ENXIO;
-
- /* DDR SDRAM - Main SODIMM */
- msize = fixed_sdram();
-
- /* Local Bus setup lbcr and mrtpr */
- lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
- /* LB refresh timer prescal, 266MHz/32 */
- lbc->mrtpr = 0x20000000;
- sync();
-
-#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- resume_from_sleep();
-#endif
-
- /* return total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize;
-
- return 0;
-}
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
deleted file mode 100644
index 07b7c54b7ffe..000000000000
--- a/configs/MPC8313ERDB_33_defconfig
+++ /dev/null
@@ -1,169 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=33333333
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8313ERDB_NOR=y
-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2800000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xFA000000
-CONFIG_LBLAW3_NAME="BCSR"
-CONFIG_LBLAW3_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE2800000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m at 1m(kernel),-(fs)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
deleted file mode 100644
index 3d8d3219b427..000000000000
--- a/configs/MPC8313ERDB_66_defconfig
+++ /dev/null
@@ -1,168 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8313ERDB_NOR=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2800000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xFA000000
-CONFIG_LBLAW3_NAME="BCSR"
-CONFIG_LBLAW3_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_9=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_EHTR_1_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE2800000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m at 1m(kernel),-(fs)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
deleted file mode 100644
index 2fe304f179e1..000000000000
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x80000
-CONFIG_SPL_TEXT_BASE=0xFFF00000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x90000
-CONFIG_SYS_CLK_FREQ=33333333
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8313ERDB_NAND=y
-CONFIG_SYSTEM_PLL_FACTOR_5_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_NAND_LBLAWBAR_PRELIM_1=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2800000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xFA000000
-CONFIG_LBLAW3_NAME="BCSR"
-CONFIG_LBLAW3_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="NAND"
-CONFIG_BR0_OR0_BASE=0xE2800000
-CONFIG_BR0_ERRORCHECKING_BOTH=y
-CONFIG_BR0_MACHINE_FCM=y
-CONFIG_OR0_SCY_1=y
-CONFIG_OR0_CSCT_8_CYCLE=y
-CONFIG_OR0_CST_ONE_CLOCK=y
-CONFIG_OR0_CHT_TWO_CLOCK=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FLASH"
-CONFIG_BR1_OR1_BASE=0xFE000000
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_8_MBYTES=y
-CONFIG_OR1_SCY_9=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_EHTR_1_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m at 1m(kernel),-(fs)"
-CONFIG_ENV_OVERWRITE=y
-# CONFIG_ENV_IS_IN_FLASH is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
deleted file mode 100644
index 28b973c424be..000000000000
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ /dev/null
@@ -1,177 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00100000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x80000
-CONFIG_SPL_TEXT_BASE=0xFFF00000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x90000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8313ERDB_NAND=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO_BASE"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="STACK_IN_DCACHE"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_NAND_LBLAWBAR_PRELIM_1=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_16_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE2800000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xF0000000
-CONFIG_LBLAW2_NAME="VSC7385"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xFA000000
-CONFIG_LBLAW3_NAME="BCSR"
-CONFIG_LBLAW3_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR_OR_NAND_PRELIM_0=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="NAND"
-CONFIG_BR0_OR0_BASE=0xE2800000
-CONFIG_BR0_ERRORCHECKING_BOTH=y
-CONFIG_BR0_MACHINE_FCM=y
-CONFIG_OR0_SCY_1=y
-CONFIG_OR0_CSCT_8_CYCLE=y
-CONFIG_OR0_CST_ONE_CLOCK=y
-CONFIG_OR0_CHT_TWO_CLOCK=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FLASH"
-CONFIG_BR1_OR1_BASE=0xFE000000
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_8_MBYTES=y
-CONFIG_OR1_SCY_9=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_EHTR_1_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="VSC7385"
-CONFIG_BR2_OR2_BASE=0xF0000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_SETA_EXTERNAL=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="BCSR"
-CONFIG_BR3_OR3_BASE=0xFA000000
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m at 1m(kernel),-(fs)"
-CONFIG_ENV_OVERWRITE=y
-# CONFIG_ENV_IS_IN_FLASH is not set
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
deleted file mode 100644
index 2db0c6fd7867..000000000000
--- a/include/configs/MPC8313ERDB_NAND.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
- */
-/*
- * mpc8313epb board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-
-#define CONFIG_SPL_INIT_MINIMAL
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SPL_MAX_SIZE (4 * 1024)
-#define CONFIG_SPL_PAD_TO 0x4000
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-/*
- * On-board devices
- *
- * TSEC1 is VSC switch
- * TSEC2 is SoC TSEC
- */
-#define CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-
-#if !defined(CONFIG_SPL_BUILD)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
-/* Early revs of this board will lock up hard when attempting
- * to access the PMC registers, unless a JTAG debugger is
- * connected, or some resistor modifications are made.
- */
-#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC1
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-
-/*
- * Manually set up DDR parameters, as this board does not
- * seem to have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (10 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x05100500 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32 \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#endif
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0632 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
- !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/* drivers/mtd/nand/raw/nand.c */
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-#endif
-
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
-/* Still needed for spl_minimal.c */
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
-
-/* local bus write LED / read status buffer (BCSR) mapping */
-#define CONFIG_SYS_BCSR_ADDR 0xFA000000
-#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
- /* map@0xFA000000 on LCS3 */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
- /* VSC7385 Base address on LCS2 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-
-
-#endif
-
-#define CONFIG_MPC83XX_GPIO 1
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1c
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
- /* Enable Internal USB Phy and GPIO on LCD Connector */
-#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME "mpc8313erdb"
-#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
deleted file mode 100644
index c223ea5613c5..000000000000
--- a/include/configs/MPC8313ERDB_NOR.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
- */
-/*
- * mpc8313epb board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#include <linux/stringify.h>
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-/*
- * On-board devices
- *
- * TSEC1 is VSC switch
- * TSEC2 is SoC TSEC
- */
-#define CONFIG_VSC7385_ENET
-#define CONFIG_TSEC2
-
-/* Early revs of this board will lock up hard when attempting
- * to access the PMC registers, unless a JTAG debugger is
- * connected, or some resistor modifications are made.
- */
-#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
-
-/*
- * Device configurations
- */
-
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
-#define CONFIG_TSEC1
-
-/* The flash address and size of the VSC7385 firmware image */
-#define CONFIG_VSC7385_IMAGE 0xFE7FE000
-#define CONFIG_VSC7385_IMAGE_SIZE 8192
-
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-
-/*
- * Manually set up DDR parameters, as this board does not
- * seem to have the SPD connected to I2C.
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (10 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3835a322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (5 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x129048c6 */ /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x05100500 */
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32 \
- | SDRAM_CFG_2T_EN)
- /* 0x43088000 */
-#else
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#endif
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-/* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0632 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480632 */
-#define CONFIG_SYS_DDR_MODE_2 0x8000C000
-
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /*0x02000000*/
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
- !defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/* drivers/mtd/nand/nand.c */
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
-
-/* Still needed for spl_minimal.c */
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-
-/* local bus write LED / read status buffer (BCSR) mapping */
-#define CONFIG_SYS_BCSR_ADDR 0xFA000000
-#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
- /* map@0xFA000000 on LCS3 */
-/* Vitesse 7385 */
-
-#ifdef CONFIG_VSC7385_ENET
-
- /* VSC7385 Base address on LCS2 */
-#define CONFIG_SYS_VSC7385_BASE 0xF0000000
-#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
-
-
-#endif
-
-#define CONFIG_MPC83XX_GPIO 1
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1c
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#if !defined(CONFIG_SYS_RAMBOOT)
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
- /* Enable Internal USB Phy and GPIO on LCD Connector */
-#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME "mpc8313erdb"
-#define CONFIG_ROOTPATH "/nfs/root/path"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc8313erdb.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 12/27] ppc: Remove caddy2 / vme8349 boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (9 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 11/27] ppc: Remove MPC8313ERDB boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 13/27] ppc: Remove sbc8548 boards Tom Rini
` (15 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 9 -
board/esd/vme8349/Kconfig | 25 ---
board/esd/vme8349/MAINTAINERS | 7 -
board/esd/vme8349/Makefile | 9 -
board/esd/vme8349/caddy.c | 178 -----------------
board/esd/vme8349/caddy.h | 59 ------
board/esd/vme8349/pci.c | 118 ------------
board/esd/vme8349/vme8349.c | 213 ---------------------
board/esd/vme8349/vme8349pin.h | 18 --
configs/caddy2_defconfig | 123 ------------
configs/vme8349_defconfig | 134 -------------
drivers/pci/pci_auto.c | 3 +-
include/configs/caddy2.h | 315 -------------------------------
include/configs/vme8349.h | 315 -------------------------------
14 files changed, 1 insertion(+), 1525 deletions(-)
delete mode 100644 board/esd/vme8349/Kconfig
delete mode 100644 board/esd/vme8349/MAINTAINERS
delete mode 100644 board/esd/vme8349/Makefile
delete mode 100644 board/esd/vme8349/caddy.c
delete mode 100644 board/esd/vme8349/caddy.h
delete mode 100644 board/esd/vme8349/pci.c
delete mode 100644 board/esd/vme8349/vme8349.c
delete mode 100644 board/esd/vme8349/vme8349pin.h
delete mode 100644 configs/caddy2_defconfig
delete mode 100644 configs/vme8349_defconfig
delete mode 100644 include/configs/caddy2.h
delete mode 100644 include/configs/vme8349.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index e4c6f5d40b26..e751daac6e2d 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -8,14 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_VME8349
- bool "Support vme8349"
- select ARCH_MPC8349
-
-config TARGET_CADDY2
- bool "Support caddy2"
- select ARCH_MPC8349
-
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
select ARCH_MPC8315
@@ -278,7 +270,6 @@ endmenu
config FSL_ELBC
bool
-source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig
deleted file mode 100644
index ef2af40f7e80..000000000000
--- a/board/esd/vme8349/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_VME8349
-
-config SYS_BOARD
- default "vme8349"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "vme8349"
-
-endif
-
-if TARGET_CADDY2
-
-config SYS_BOARD
- default "vme8349"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "caddy2"
-
-endif
diff --git a/board/esd/vme8349/MAINTAINERS b/board/esd/vme8349/MAINTAINERS
deleted file mode 100644
index a88ba13c303d..000000000000
--- a/board/esd/vme8349/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-VME8349 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/vme8349/
-F: include/configs/vme8349.h
-F: configs/caddy2_defconfig
-F: configs/vme8349_defconfig
diff --git a/board/esd/vme8349/Makefile b/board/esd/vme8349/Makefile
deleted file mode 100644
index 850c16ba638c..000000000000
--- a/board/esd/vme8349/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright (c) 2009 esd gmbh hannover germany.
-
-obj-y += vme8349.o caddy.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/esd/vme8349/caddy.c b/board/esd/vme8349/caddy.c
deleted file mode 100644
index ba91f4b3c843..000000000000
--- a/board/esd/vme8349/caddy.c
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-
-#include "caddy.h"
-
-static struct caddy_interface *caddy_interface;
-
-void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
-{
- struct caddy_answer *answer;
- uint32_t ptr;
-
- answer = &caddy_interface->answer[caddy_interface->answer_in];
- memset((void *)answer, 0, sizeof(struct caddy_answer));
- answer->answer = cmd->cmd;
- answer->issue = cmd->issue;
- answer->status = status;
- memcpy(answer->par, result, 5 * sizeof(result[0]));
- ptr = caddy_interface->answer_in + 1;
- ptr = ptr & (ANSWER_SIZE - 1);
- if (ptr != caddy_interface->answer_out)
- caddy_interface->answer_in = ptr;
-}
-
-int do_caddy(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned long base_addr;
- uint32_t ptr;
- struct caddy_cmd *caddy_cmd;
- uint32_t result[5];
- uint16_t data16;
- uint8_t data8;
- uint32_t status;
- pci_dev_t dev;
- void *pci_ptr;
-
- if (argc < 2) {
- puts("Missing parameter\n");
- return 1;
- }
-
- base_addr = simple_strtoul(argv[1], NULL, 16);
- caddy_interface = (struct caddy_interface *) base_addr;
-
- memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
- memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
-
- while (ctrlc() == 0) {
- if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
- memset(result, 0, 5 * sizeof(result[0]));
- status = 0;
- caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
- pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
- (caddy_cmd->addr & 0x001fffff);
-
- switch (caddy_cmd->cmd) {
- case CADDY_CMD_IO_READ_8:
- result[0] = in_8(pci_ptr);
- break;
-
- case CADDY_CMD_IO_READ_16:
- result[0] = in_be16(pci_ptr);
- break;
-
- case CADDY_CMD_IO_READ_32:
- result[0] = in_be32(pci_ptr);
- break;
-
- case CADDY_CMD_IO_WRITE_8:
- data8 = caddy_cmd->par[0] & 0x000000ff;
- out_8(pci_ptr, data8);
- break;
-
- case CADDY_CMD_IO_WRITE_16:
- data16 = caddy_cmd->par[0] & 0x0000ffff;
- out_be16(pci_ptr, data16);
- break;
-
- case CADDY_CMD_IO_WRITE_32:
- out_be32(pci_ptr, caddy_cmd->par[0]);
- break;
-
- case CADDY_CMD_CONFIG_READ_8:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_read_config_byte(dev,
- caddy_cmd->addr,
- &data8);
- result[0] = data8;
- break;
-
- case CADDY_CMD_CONFIG_READ_16:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_read_config_word(dev,
- caddy_cmd->addr,
- &data16);
- result[0] = data16;
- break;
-
- case CADDY_CMD_CONFIG_READ_32:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_read_config_dword(dev,
- caddy_cmd->addr,
- &result[0]);
- break;
-
- case CADDY_CMD_CONFIG_WRITE_8:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- data8 = caddy_cmd->par[3] & 0x000000ff;
- status = pci_write_config_byte(dev,
- caddy_cmd->addr,
- data8);
- break;
-
- case CADDY_CMD_CONFIG_WRITE_16:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- data16 = caddy_cmd->par[3] & 0x0000ffff;
- status = pci_write_config_word(dev,
- caddy_cmd->addr,
- data16);
- break;
-
- case CADDY_CMD_CONFIG_WRITE_32:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_write_config_dword(dev,
- caddy_cmd->addr,
- caddy_cmd->par[3]);
- break;
-
- default:
- status = 0xffffffff;
- break;
- }
-
- generate_answer(caddy_cmd, status, &result[0]);
-
- ptr = caddy_interface->cmd_out + 1;
- ptr = ptr & (CMD_SIZE - 1);
- caddy_interface->cmd_out = ptr;
- }
-
- caddy_interface->heartbeat++;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- caddy, 2, 0, do_caddy,
- "Start Caddy server.",
- "Start Caddy server with Data structure a given addr\n"
- );
diff --git a/board/esd/vme8349/caddy.h b/board/esd/vme8349/caddy.h
deleted file mode 100644
index 8e3033ba20ee..000000000000
--- a/board/esd/vme8349/caddy.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#ifndef __CADDY_H__
-#define __CADDY_H__
-
-#define CMD_SIZE 1024
-#define ANSWER_SIZE 1024
-#define CADDY_MAGIC "esd vme8349 V1.0"
-
-enum caddy_cmds {
- CADDY_CMD_IO_READ_8,
- CADDY_CMD_IO_READ_16,
- CADDY_CMD_IO_READ_32,
- CADDY_CMD_IO_WRITE_8,
- CADDY_CMD_IO_WRITE_16,
- CADDY_CMD_IO_WRITE_32,
- CADDY_CMD_CONFIG_READ_8,
- CADDY_CMD_CONFIG_READ_16,
- CADDY_CMD_CONFIG_READ_32,
- CADDY_CMD_CONFIG_WRITE_8,
- CADDY_CMD_CONFIG_WRITE_16,
- CADDY_CMD_CONFIG_WRITE_32,
-};
-
-struct caddy_cmd {
- uint32_t cmd;
- uint32_t issue;
- uint32_t addr;
- uint32_t par[5];
-};
-
-struct caddy_answer {
- uint32_t answer;
- uint32_t issue;
- uint32_t status;
- uint32_t par[5];
-};
-
-struct caddy_interface {
- uint8_t magic[16];
- uint32_t cmd_in;
- uint32_t cmd_out;
- uint32_t heartbeat;
- uint32_t reserved1;
- struct caddy_cmd cmd[CMD_SIZE];
- uint32_t answer_in;
- uint32_t answer_out;
- uint32_t reserved2;
- uint32_t reserved3;
- struct caddy_answer answer[CMD_SIZE];
-};
-
-#endif /* of __CADDY_H__ */
diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c
deleted file mode 100644
index bf51d39b67c8..000000000000
--- a/board/esd/vme8349/pci.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * pci.c -- esd VME8349 PCI board support.
- * Copyright (c) 2006 Wind River Systems, Inc.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * Based on MPC8349 PCI support but w/o PIB related code.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-#include "vme8349pin.h"
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: PCI2 is not supported. There is only one
- * physical PCI slot on the board.
- *
- */
-void
-pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci1_regions };
- u8 reg8;
- int monarch = 0;
-
- i2c_set_bus_num(1);
- /* Read the PCI_M66EN jumper setting */
- if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
- (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
- if (reg8 & 0x40) {
- clk->occr = 0xff000000; /* 66 MHz PCI */
- printf("PCI: 66MHz\n");
- } else {
- clk->occr = 0xffff0003; /* 33 MHz PCI */
- printf("PCI: 33MHz\n");
- }
- if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
- monarch = 1;
- } else {
- clk->occr = 0xffff0003; /* 33 MHz PCI */
- printf("PCI: 33MHz (I2C read failed)\n");
- }
- udelay(2000);
-
- /*
- * Assert/deassert VME reset
- */
- clrsetbits_be32(&immr->gpio[1].dat,
- GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
- GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
- setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
- GPIO2_TSI_POWERUP_RESET_N |
- GPIO2_VME_RESET_N |
- GPIO2_L_RESET_EN_N);
- clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
- udelay(200);
- setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
- udelay(200);
- setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
- udelay(600000);
- clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- udelay(2000);
-
- if (monarch == 0) {
- mpc83xx_pci_init(1, reg);
- } else {
- /*
- * Release PCI RST Output signal
- */
- out_be32(&immr->pci_ctrl[0].gcr, 0);
- udelay(2000);
- out_be32(&immr->pci_ctrl[0].gcr, 1);
- }
-}
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
deleted file mode 100644
index d388fc6d4901..000000000000
--- a/board/esd/vme8349/vme8349.c
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * vme8349.c -- esd VME8349 board support
- *
- * Copyright (c) 2008-2009 esd gmbh.
- *
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <spd.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void ddr_enable_ecc(unsigned int dram_size);
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -ENXIO;
-
- /* DDR SDRAM - Main memory */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
- msize = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
- /* Now check memory size (after ECC is initialized) */
- msize = get_ram_size(0, msize);
-
- /* return total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-int checkboard(void)
-{
-#ifdef CONFIG_TARGET_CADDY2
- puts("Board: esd VME-CADDY/2\n");
-#else
- puts("Board: esd VME-CPU/8349\n");
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_TARGET_CADDY2
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
-
-int misc_init_r()
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
-
- return 0;
-}
-
-/*
- * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
- * and VME-CADDY/2) have different SDRAM configurations.
- */
-#ifdef CONFIG_TARGET_CADDY2
-#define SMALL_RAM 0xff
-#define LARGE_RAM 0x00
-#else
-#define SMALL_RAM 0x00
-#define LARGE_RAM 0xff
-#endif
-
-#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
-
-static spd_eeprom_t default_spd_eeprom = {
- SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
- SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
- SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
- SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
- SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
- SPD_VAL(0x00, 0x00), /* 05 */
- SPD_VAL(0x40, 0x40), /* 06 */
- SPD_VAL(0x00, 0x00), /* 07 */
- SPD_VAL(0x05, 0x05), /* 08 */
- SPD_VAL(0x30, 0x30), /* 09 */
- SPD_VAL(0x45, 0x45), /* 10 */
- SPD_VAL(0x02, 0x02), /* 11 ecc used */
- SPD_VAL(0x82, 0x82), /* 12 */
- SPD_VAL(0x10, 0x10), /* 13 */
- SPD_VAL(0x08, 0x08), /* 14 */
- SPD_VAL(0x00, 0x00), /* 15 */
- SPD_VAL(0x0c, 0x0c), /* 16 */
- SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
- SPD_VAL(0x38, 0x38), /* 18 */
- SPD_VAL(0x00, 0x00), /* 19 */
- SPD_VAL(0x02, 0x02), /* 20 */
- SPD_VAL(0x00, 0x00), /* 21 */
- SPD_VAL(0x03, 0x03), /* 22 */
- SPD_VAL(0x3d, 0x3d), /* 23 */
- SPD_VAL(0x45, 0x45), /* 24 */
- SPD_VAL(0x50, 0x50), /* 25 */
- SPD_VAL(0x45, 0x45), /* 26 */
- SPD_VAL(0x3c, 0x3c), /* 27 */
- SPD_VAL(0x28, 0x28), /* 28 */
- SPD_VAL(0x3c, 0x3c), /* 29 */
- SPD_VAL(0x2d, 0x2d), /* 30 */
- SPD_VAL(0x20, 0x80), /* 31 */
- SPD_VAL(0x20, 0x20), /* 32 */
- SPD_VAL(0x27, 0x27), /* 33 */
- SPD_VAL(0x10, 0x10), /* 34 */
- SPD_VAL(0x17, 0x17), /* 35 */
- SPD_VAL(0x3c, 0x3c), /* 36 */
- SPD_VAL(0x1e, 0x1e), /* 37 */
- SPD_VAL(0x1e, 0x1e), /* 38 */
- SPD_VAL(0x00, 0x00), /* 39 */
- SPD_VAL(0x00, 0x06), /* 40 */
- SPD_VAL(0x37, 0x37), /* 41 */
- SPD_VAL(0x4b, 0x7f), /* 42 */
- SPD_VAL(0x80, 0x80), /* 43 */
- SPD_VAL(0x18, 0x18), /* 44 */
- SPD_VAL(0x22, 0x22), /* 45 */
- SPD_VAL(0x00, 0x00), /* 46 */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
- SPD_VAL(0x10, 0x10), /* 62 */
- SPD_VAL(0x7e, 0x1d), /* 63 */
- { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
- SPD_VAL(0x00, 0x00), /* 72 */
-#ifdef CONFIG_TARGET_CADDY2
- { "vme-caddy/2 ram " }
-#else
- { "vme-cpu/2 ram " }
-#endif
-};
-
-int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int old_bus = i2c_get_bus_num();
- unsigned int l, sum;
- int valid = 0;
-
- i2c_set_bus_num(0);
-
- if (i2c_read(chip, addr, alen, buffer, len) == 0)
- if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
- sum = 0;
- for (l = 0; l < 63; l++)
- sum = (sum + buffer[l]) & 0xff;
- if (sum == buffer[63])
- valid = 1;
- else
- printf("Invalid checksum in EEPROM %02x %02x\n",
- sum, buffer[63]);
- }
-
- if (valid == 0) {
- memcpy(buffer, (void *)&default_spd_eeprom, len);
- sum = 0;
- for (l = 0; l < 63; l++)
- sum = (sum + buffer[l]) & 0xff;
- if (sum != buffer[63])
- printf("Invalid checksum in FLASH %02x %02x\n",
- sum, buffer[63]);
- buffer[63] = sum;
- }
-
- i2c_set_bus_num(old_bus);
-
- return 0;
-}
diff --git a/board/esd/vme8349/vme8349pin.h b/board/esd/vme8349/vme8349pin.h
deleted file mode 100644
index 9ae9c7becae7..000000000000
--- a/board/esd/vme8349/vme8349pin.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#ifndef __VME8349PIN_H__
-#define __VME8349PIN_H__
-
-#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
-#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
-#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
-#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
-#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
-
-#endif /* of ifndef __VME8349PIN_H__ */
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
deleted file mode 100644
index cf24b3348647..000000000000
--- a/configs/caddy2_defconfig
+++ /dev/null
@@ -1,123 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_CADDY2=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="UNKNOWN"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFFC00000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_4_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF0000000
-CONFIG_LBLAW1_NAME="WINDOW1"
-CONFIG_LBLAW1_LENGTH_256_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFFC00000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_4_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="WINDOW1"
-CONFIG_BR1_OR1_BASE=0xF0000000
-CONFIG_BR1_PORTSIZE_32BIT=y
-CONFIG_OR1_AM_256_KBYTES=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_TSI148=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFFFC0000
-CONFIG_ENV_ADDR_REDUND=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_E1000=y
-CONFIG_RTC_RX8025=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
deleted file mode 100644
index 286b5837d3c6..000000000000
--- a/configs/vme8349_defconfig
+++ /dev/null
@@ -1,134 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_VME8349=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_64BIT_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="UNKNOWN"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xF8000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_128_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF0000000
-CONFIG_LBLAW1_NAME="WINDOW1"
-CONFIG_LBLAW1_LENGTH_256_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF8000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_128_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="WINDOW1"
-CONFIG_BR1_OR1_BASE=0xF0000000
-CONFIG_BR1_PORTSIZE_32BIT=y
-CONFIG_OR1_AM_256_KBYTES=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_TSI148=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFFFC0000
-CONFIG_ENV_ADDR_REDUND=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_RTC_RX8025=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 05663c72b4b8..b128a05dd380 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -348,8 +348,7 @@ int dm_pciauto_config_device(struct udevice *dev)
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
- !defined(CONFIG_TARGET_CADDY2)
+#if defined(CONFIG_ARCH_MPC834X)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
deleted file mode 100644
index 78891fefd2df..000000000000
--- a/include/configs/caddy2.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * esd vme8349 U-Boot configuration file
- * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
- *
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * reinhard.arlt at esd-electronics.de
- * Based on the MPC8349EMDS config.
- */
-
-/*
- * vme8349 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_READ_SPD vme8349_read_spd
-#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-#define CONFIG_DDR_2T_TIMING
-#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
-
-
-#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-
-#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
-
-#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0xFIXME
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII /* MII PHY management */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_PHY_M88E1111
-#define TSEC1_PHY_ADDR 0x08
-#define TSEC2_PHY_ADDR 0x10
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_SYS_RTC_BUS_NUM 0x01
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-
-/* Pass Ethernet MAC to VxWorks */
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0x00100000
-#define CONFIG_SYS_GPIO1_DAT 0x00100000
-
-#define CONFIG_SYS_GPIO2_PRELIM
-#define CONFIG_SYS_GPIO2_DIR 0x78900000
-#define CONFIG_SYS_GPIO2_DAT 0x70100000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "VME8349"
-#define CONFIG_ROOTPATH "/tftpboot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=vme8349\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
- "update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=vme8349.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#ifndef __ASSEMBLY__
-int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len);
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
deleted file mode 100644
index 20fcce187055..000000000000
--- a/include/configs/vme8349.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * esd vme8349 U-Boot configuration file
- * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
- *
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * reinhard.arlt@esd-electronics.de
- * Based on the MPC8349EMDS config.
- */
-
-/*
- * vme8349 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_READ_SPD vme8349_read_spd
-#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-#define CONFIG_DDR_2T_TIMING
-#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-
-
-#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-
-#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
-
-#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0xFIXME
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII /* MII PHY management */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_PHY_M88E1111
-#define TSEC1_PHY_ADDR 0x08
-#define TSEC2_PHY_ADDR 0x10
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_SYS_RTC_BUS_NUM 0x01
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-
-/* Pass Ethernet MAC to VxWorks */
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0x00100000
-#define CONFIG_SYS_GPIO1_DAT 0x00100000
-
-#define CONFIG_SYS_GPIO2_PRELIM
-#define CONFIG_SYS_GPIO2_DIR 0x78900000
-#define CONFIG_SYS_GPIO2_DAT 0x70100000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "VME8349"
-#define CONFIG_ROOTPATH "/tftpboot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=vme8349\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
- "update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=vme8349.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#ifndef __ASSEMBLY__
-int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len);
-#endif
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 13/27] ppc: Remove sbc8548 boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (10 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 12/27] ppc: Remove caddy2 / vme8349 boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-15 19:18 ` Paul Gortmaker
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 14/27] ppc: Remove TQM834x board Tom Rini
` (14 subsequent siblings)
26 siblings, 2 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline and are
also missing conversion to CONFIG_DM. Remove them.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 5 -
board/sbc8548/Kconfig | 9 -
board/sbc8548/MAINTAINERS | 10 -
board/sbc8548/Makefile | 12 -
board/sbc8548/README | 269 -------------
board/sbc8548/ddr.c | 132 -------
board/sbc8548/law.c | 54 ---
board/sbc8548/sbc8548.c | 315 ---------------
board/sbc8548/tlb.c | 121 ------
configs/sbc8548_PCI_33_PCIE_defconfig | 42 --
configs/sbc8548_PCI_33_defconfig | 42 --
configs/sbc8548_PCI_66_PCIE_defconfig | 42 --
configs/sbc8548_PCI_66_defconfig | 42 --
configs/sbc8548_defconfig | 41 --
include/configs/sbc8548.h | 540 --------------------------
15 files changed, 1676 deletions(-)
delete mode 100644 board/sbc8548/Kconfig
delete mode 100644 board/sbc8548/MAINTAINERS
delete mode 100644 board/sbc8548/Makefile
delete mode 100644 board/sbc8548/README
delete mode 100644 board/sbc8548/ddr.c
delete mode 100644 board/sbc8548/law.c
delete mode 100644 board/sbc8548/sbc8548.c
delete mode 100644 board/sbc8548/tlb.c
delete mode 100644 configs/sbc8548_PCI_33_PCIE_defconfig
delete mode 100644 configs/sbc8548_PCI_33_defconfig
delete mode 100644 configs/sbc8548_PCI_66_PCIE_defconfig
delete mode 100644 configs/sbc8548_PCI_66_defconfig
delete mode 100644 configs/sbc8548_defconfig
delete mode 100644 include/configs/sbc8548.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 676aaf1d2ca6..22cfa4dc3499 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -16,10 +16,6 @@ choice
prompt "Target select"
optional
-config TARGET_SBC8548
- bool "Support sbc8548"
- select ARCH_MPC8548
-
config TARGET_SOCRATES
bool "Support socrates"
select ARCH_MPC8544
@@ -1303,7 +1299,6 @@ source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
-source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
source "board/xes/xpedite520x/Kconfig"
source "board/xes/xpedite537x/Kconfig"
diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig
deleted file mode 100644
index 626cbdf2ab27..000000000000
--- a/board/sbc8548/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC8548
-
-config SYS_BOARD
- default "sbc8548"
-
-config SYS_CONFIG_NAME
- default "sbc8548"
-
-endif
diff --git a/board/sbc8548/MAINTAINERS b/board/sbc8548/MAINTAINERS
deleted file mode 100644
index ba1f2475eabf..000000000000
--- a/board/sbc8548/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-SBC8548 BOARD
-M: Paul Gortmaker <paul.gortmaker@windriver.com>
-S: Maintained
-F: board/sbc8548/
-F: include/configs/sbc8548.h
-F: configs/sbc8548_defconfig
-F: configs/sbc8548_PCI_33_defconfig
-F: configs/sbc8548_PCI_33_PCIE_defconfig
-F: configs/sbc8548_PCI_66_defconfig
-F: configs/sbc8548_PCI_66_PCIE_defconfig
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
deleted file mode 100644
index 83d208cf1fe9..000000000000
--- a/board/sbc8548/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2004-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8548 board
-
-obj-y += sbc8548.o
-obj-y += law.o
-obj-y += tlb.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8548/README b/board/sbc8548/README
deleted file mode 100644
index 0def245bd9ce..000000000000
--- a/board/sbc8548/README
+++ /dev/null
@@ -1,269 +0,0 @@
-Intro:
-======
-
-The SBC8548 is a stand alone single board computer with a 1GHz
-MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
-memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
-and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
-ethernet connections.
-
-U-Boot Configuration:
-=====================
-
-The following possible U-Boot configuration targets are available:
-
- 1) sbc8548_config
- 2) sbc8548_PCI_33_config
- 3) sbc8548_PCI_66_config
- 4) sbc8548_PCI_33_PCIE_config
- 5) sbc8548_PCI_66_PCIE_config
-
-Generally speaking, most people should choose to use #5. Details
-of each choice are listed below.
-
-Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
-will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
-and linux in order to have functional PCI under linux.
-
-The second enables PCI support and builds for a 33MHz clock rate. Note
-that if a 33MHz 32bit card is inserted in the slot, then the whole board
-will clock down to a 33MHz base clock instead of the default 66MHz. This
-will change the baud clocks and mess up your serial console output if you
-were previously running at 66MHz. If you want to use a 33MHz PCI card,
-then you should build a U-Boot with a _PCI_33_ config and store this
-to flash prior to powering down the board and inserting the 33MHz PCI
-card. [The above discussion assumes that the SW2[1-4] has not been changed
-to reflect a different CCB:SYSCLK ratio]
-
-The third option builds PCI support in, and leaves the clocking at the
-default 66MHz. Options four and five are just repeats of option two
-and three, but with PCI-e support enabled as well.
-
-PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
-is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
-a 33MHz PCI configuration is currently untested.)
-
- => pci 0
- Scanning PCI devices on bus 0
- BusDevFun VendorId DeviceId Device Class Sub-Class
- _____________________________________________________________
- 00.00.00 0x1057 0x0012 Processor 0x20
- 00.01.00 0x8086 0x1026 Network controller 0x00
- => pci 1
- Scanning PCI devices on bus 1
- BusDevFun VendorId DeviceId Device Class Sub-Class
- _____________________________________________________________
- 01.00.00 0x1957 0x0012 Processor 0x20
- => pci 2
- Scanning PCI devices on bus 2
- BusDevFun VendorId DeviceId Device Class Sub-Class
- _____________________________________________________________
- 02.00.00 0x1148 0x9e00 Network controller 0x00
- =>
-
-Memory Size and using SPD:
-==========================
-
-The default configuration uses hard coded memory configuration settings
-for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
-EEPROM data to read what memory is installed.
-
-There is a hardware errata, which causes the older local bus SDRAM
-SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
-that the SPD data can not be read reliably. You can test if your
-board has the errata fix by running "i2c probe". If you see 0x53
-as a valid device, it has been fixed. If you only see 0x50, 0x51
-then your board does not have the fix.
-
-You can also visually inspect the board to see if this hardware
-fix has been applied:
-
- 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
- the back of the PCB behind the DDR SDRAM SODIMM connector.
- 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
- to R313 pin 2. Pin 2 for each resistor is the end of the
- resistor closest to the CPU.
-
-Boards without the mod will have R314 and R313 in parallel, like "||".
-After the mod, they will be touching and form an "L" shape.
-
-If you want to upgrade to larger RAM size, you can simply enable
- #define CONFIG_SPD_EEPROM
- #define CONFIG_DDR_SPD
-in include/configs/sbc8548.h file. (The lines are already there
-but listed as #undef).
-
-If you did the i2c test, and your board does not have the errata
-fix, then you will have to physically remove the LBC 128MB DIMM
-from the board's socket to resolve the above i2c address overlap
-issue and allow SPD autodetection of RAM to work.
-
-
-Updating U-Boot with U-Boot:
-============================
-
-Note that versions of U-Boot up to and including 2009.08 had U-Boot stored
-at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
-0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
-update U-Boot with U-Boot and it uses the old address, you will render
-your board inoperable, and you will require JTAG recovery.
-
-The following steps list how to update with the current address:
-
- tftp u-boot.bin
- md 200000 10
- protect off all
- erase fffa0000 ffffffff
- cp.b 200000 fffa0000 60000
- md fffa0000 10
- protect on all
-
-The "md" steps in the above are just a precautionary step that allow
-you to confirm the U-Boot version that was downloaded, and then confirm
-that it was copied to flash.
-
-The above assumes that you are using the default board settings which
-have U-Boot in the 8MB flash, tied to /CS0.
-
-If you are running the default 8MB /CS0 settings but want to store an
-image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
-(as a backup, etc) then the steps will become:
-
- tftp u-boot.bin
- md 200000 10
- protect off all
- era eff00000 efffffff
- cp.b 200000 eff00000 100000
- md eff00000 10
- protect on all
-
-Finally, if you are running the alternate 64MB /CS0 settings and want
-to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT
-enabled) the steps will become:
-
- tftp u-boot.bin
- md 200000 10
- protect off all
- era fff00000 ffffffff
- cp.b 200000 fff00000 100000
- md fff00000 10
- protect on all
-
-
-Hardware Reference:
-===================
-
-The following contains some summary information on hardware settings
-that are relevant to U-Boot, based on the board manual. For the
-most up to date and complete details of the board, please request the
-reference manual ERG-00327-001.pdf from www.windriver.com
-
-Boot flash:
- intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
-
-Sodimm flash:
- intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
- Note that this address reflects the default setting for
- the JTAG debugging tools, but since the alignment is
- rather inconvenient, U-Boot puts it at 0xec00_0000.
-
-
- Jumpers:
-
-Jumper Name ON OFF
-----------------------------------------------------------------
-JP12 CS0/CS6 swap see note[*] see note[*]
-
-JP13 SODIMM flash write OK writes disabled
- write prot.
-
-JP14 HRESET/TRST joined isolated
-
-JP15 PWR ON when AC pwr use S1 for on/off
-
-JP16 Demo LEDs lit not lit
-
-JP19 PCI mode PCI PCI-X
-
-
-[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
-onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
-is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
-SODIMM flash and /CS6 is for the boot flash. Note that in this
-alternate setting, you also need to switch SW2.8 to ON.
-See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
-and boot U-Boot from the 64MB SODIMM
-
-
- Switches:
-
-The defaults are marked with a *
-
-Name Desc. ON OFF
-------------------------------------------------------------------
-S1 Pwr toggle n/a n/a
-
-SW2.1 CFG_SYS_PLL0 1 0*
-SW2.2 CFG_SYS_PLL1 1* 0
-SW2.3 CFG_SYS_PLL2 1* 0
-SW2.4 CFG_SYS_PLL3 1 0*
-SW2.5 CFG_CORE_PLL0 1* 0
-SW2.6 CFG_CORE_PLL1 1 0*
-SW2.7 CFG_CORE_PLL2 1* 0
-SW2.8 CFG_ROM_LOC1 1 0*
-
-SW3.1 CFG_HOST_AGT0 1* 0
-SW3.2 CFG_HOST_AGT1 1* 0
-SW3.3 CFG_HOST_AGT2 1* 0
-SW3.4 CFG_IO_PORTS0 1* 0
-SW3.5 CFG_IO_PORTS0 1 0*
-SW3.6 CFG_IO_PORTS0 1 0*
-
-SerDes CLK(MHz) SW5.1 SW5.2
-----------------------------------------------
-25 0 0
-100* 1 0
-125 0 1
-200 1 1
-
-SerDes CLK spread SW5.3 SW5.4
-----------------------------------------------
-+/- 0.25% 0 0
--0.50% 1 0
--0.75% 0 1
-No Spread* 1 1
-
-SW4 settings are readable from the EPLD and are currently not used for
-any hardware settings (i.e. user configuration switches).
-
- LEDs:
-
-Name Desc. ON OFF
-------------------------------------------------------------------
-D13 PCI/PCI-X PCI-X PCI
-D14 3.3V PWR 3.3V no power
-D15 SYSCLK 66MHz 33MHz
-
-
- Default Memory Map:
-
-start end CS<n> width Desc.
-----------------------------------------------------------------------
-0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
-f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
-f800_0000 f8b0_1fff CS5 - EPLD
-fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
-ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
-
-[*] fb80 represents the default programmed by WR JTAG register files,
- but U-Boot places the flash at either ec00 or fc00 based on JP12.
-
-The EPLD on CS5 demuxes the following devices at the following offsets:
-
-offset size width device
---------------------------------------------------------
-0 1fff 8 7 segment display LED
-10_0000 1fff 4 user switches
-30_0000 1fff 4 HW Rev. register
-b0_0000 1fff 8 8kB EEPROM
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
deleted file mode 100644
index 61bc77c418a9..000000000000
--- a/board/sbc8548/ddr.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <linux/delay.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
-
-#ifdef CONFIG_SPD_EEPROM
-/*
- * Workaround for hardware errata. An i2c address conflict
- * existed on earlier boards; the workaround moved the DDR
- * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
- * if that fails, then fall back to reading at 0x51.
- */
-void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
-{
- int ret;
-
-#ifdef ALT_SPD_EEPROM_ADDRESS
- if (i2c_address == SPD_EEPROM_ADDRESS) {
- ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
- sizeof(generic_spd_eeprom_t));
- if (ret == 0)
- return; /* Good data at 0x53 */
- memset(spd, 0, sizeof(generic_spd_eeprom_t));
- }
-#endif
- ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
- sizeof(generic_spd_eeprom_t));
- if (ret) {
- printf("DDR: failed to read SPD from addr %u\n", i2c_address);
- memset(spd, 0, sizeof(generic_spd_eeprom_t));
- }
-}
-
-#else
-/*
- * fixed_sdram init -- doesn't use serial presence detect.
- * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
- */
-phys_size_t fixed_sdram(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-
- out_be32(&ddr->cs0_bnds, 0x0000007f);
- out_be32(&ddr->cs1_bnds, 0x008000ff);
- out_be32(&ddr->cs2_bnds, 0x00000000);
- out_be32(&ddr->cs3_bnds, 0x00000000);
-
- out_be32(&ddr->cs0_config, 0x80010101);
- out_be32(&ddr->cs1_config, 0x80010101);
- out_be32(&ddr->cs2_config, 0x00000000);
- out_be32(&ddr->cs3_config, 0x00000000);
-
- out_be32(&ddr->timing_cfg_3, 0x00000000);
- out_be32(&ddr->timing_cfg_0, 0x00220802);
- out_be32(&ddr->timing_cfg_1, 0x38377322);
- out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
-
- out_be32(&ddr->sdram_cfg, 0x4300C000);
- out_be32(&ddr->sdram_cfg_2, 0x24401000);
-
- out_be32(&ddr->sdram_mode, 0x23C00542);
- out_be32(&ddr->sdram_mode_2, 0x00000000);
-
- out_be32(&ddr->sdram_interval, 0x05080100);
- out_be32(&ddr->sdram_md_cntl, 0x00000000);
- out_be32(&ddr->sdram_data_init, 0x00000000);
- out_be32(&ddr->sdram_clk_cntl, 0x03800000);
- asm("sync;isync;msync");
- udelay(500);
-
- #ifdef CONFIG_DDR_ECC
- /* Enable ECC checking */
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
- #else
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
- #endif
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
deleted file mode 100644
index 97271ea6f66b..000000000000
--- a/board/sbc8548/law.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x0fff_ffff DDR 256M
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
- * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
- * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * If swapped CS0/CS6 via JP12+SW2.8:
- * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
- * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_ALT_BOOT
- SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
-#else
- SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-#endif
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
-#endif
-#ifdef CONFIG_SYS_LBC_SDRAM_BASE
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#else
- /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
deleted file mode 100644
index bd4b528d03f7..000000000000
--- a/board/sbc8548/sbc8548.c
+++ /dev/null
@@ -1,315 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
- *
- * Copyright 2007 Embedded Specialties, Inc.
- *
- * Copyright 2004, 2007 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <spd_sdram.h>
-#include <netdev.h>
-#include <tsec.h>
-#include <miiphy.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-void local_bus_init(void);
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
- volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
-
- printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
- in_8(rev) >> 4);
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
- out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
-
- lbc_mhz = sysinfo.freq_localbus / 1000000;
- clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
-
- debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
-
- out_be32(&gur->lbiuiplldcr1, 0x00078080);
- if (clkdiv == 16) {
- out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
- } else if (clkdiv == 8) {
- out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
- } else if (clkdiv == 4) {
- out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
- }
-
- /*
- * Local Bus Clock > 83.3 MHz. According to timing
- * specifications set LCRR[EADC] to 2 delay cycles.
- */
- if (lbc_mhz > 83) {
- lcrr &= ~LCRR_EADC;
- lcrr |= LCRR_EADC_2;
- }
-
- /*
- * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
- * disable PLL bypass for Local Bus Clock > 83 MHz.
- */
- if (lbc_mhz >= 66)
- lcrr &= (~LCRR_DBYP); /* DLL Enabled */
-
- else
- lcrr |= LCRR_DBYP; /* DLL Bypass */
-
- out_be32(&lbc->lcrr, lcrr);
- asm("sync;isync;msync");
-
- /*
- * According to MPC8548ERMAD Rev.1.3 read back LCRR
- * and terminate with isync
- */
- lcrr = in_be32(&lbc->lcrr);
- asm ("isync;");
-
- /* let DLL stabilize */
- udelay(500);
-
- out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
- out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
-
- uint idx;
- const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
-
- puts(" SDRAM: ");
-
- print_size(size, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
- set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
- set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
-
- out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
- asm("msync");
-
- out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
- out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
- asm("msync");
-
- /*
- * Issue PRECHARGE ALL command.
- */
- out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- *sdram_addr2 = 0xff;
- ppcDcbf((unsigned long) sdram_addr2);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- *sdram_addr2 = 0xff;
- ppcDcbf((unsigned long) sdram_addr2);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- *sdram_addr2 = 0xff;
- ppcDcbf((unsigned long) sdram_addr2);
- udelay(100);
-
- /*
- * Issue RFEN command.
- */
- out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- *sdram_addr2 = 0xff;
- ppcDcbf((unsigned long) sdram_addr2);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int
-testdram(void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("Testing DRAM from 0x%08x to 0x%08x\n",
- CONFIG_SYS_MEMTEST_START,
- CONFIG_SYS_MEMTEST_END);
-
- printf("DRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("DRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("DRAM test passed.\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI1 */
-
-#ifdef CONFIG_PCI
-void
-pci_init_board(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int first_free_busno = 0;
-
-#ifdef CONFIG_PCI1
- struct fsl_pci_info pci_info;
- u32 devdisr = in_be32(&gur->devdisr);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 porpllsr = in_be32(&gur->porpllsr);
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
- uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
- uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
-
- printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33000000) ? "33" :
- (pci_speed == 66000000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_arb ? "arbiter" : "external-arbiter");
-
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
-
- fsl_pcie_init_board(first_free_busno);
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
- tsec_standard_init(bis);
- pci_eth_init(bis);
- return 0; /* otherwise cpu_eth_init gets run */
-}
-
-int last_stage_init(void)
-{
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_FSL_PCI_INIT
- FT_FSL_PCI_SETUP;
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
deleted file mode 100644
index 8ad01d10e49b..000000000000
--- a/board/sbc8548/tlb.c
+++ /dev/null
@@ -1,121 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /*
- * TLB 0: 64M Non-cacheable, guarded
- * 0xfc000000 56M unused
- * 0xff800000 8M boot FLASH
- * .... or ....
- * 0xfc000000 64M user flash
- *
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 512M PCI1 MEM
- * 0xa0000000 512M PCIe MEM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
-
- /*
- * TLB 2: 64M Non-cacheable, guarded
- * 0xe0000000 1M CCSRBAR
- * 0xe2000000 8M PCI1 IO
- * 0xe2800000 8M PCIe IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
-#ifdef CONFIG_SYS_LBC_SDRAM_BASE
- /*
- * TLB 3: 64M Cacheable, non-guarded
- * 0xf0000000 64M LBC SDRAM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 3, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 4: 64M Cacheable, non-guarded
- * 0xf4000000 64M LBC SDRAM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
- CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-#endif
-
- /*
- * TLB 5: 16M Cacheable, non-guarded
- * 0xf8000000 1M 7-segment LED display
- * 0xf8100000 1M User switches
- * 0xf8300000 1M Board revision
- * 0xf8b00000 1M EEPROM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_16M, 1),
-
-#ifndef CONFIG_SYS_ALT_BOOT
- /*
- * TLB 6: 64M Non-cacheable, guarded
- * 0xec000000 64M 64MB user FLASH
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-#else
- /*
- * TLB 6: 4M Non-cacheable, guarded
- * 0xef800000 4M 1st 1/2 8MB soldered FLASH
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_4M, 1),
-
- /*
- * TLB 7: 4M Non-cacheable, guarded
- * 0xefc00000 4M 2nd half 8MB soldered FLASH
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
- CONFIG_SYS_ALT_FLASH + 0x400000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
deleted file mode 100644
index 3157ed92f396..000000000000
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFFA0000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_SBC8548=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
-CONFIG_BOOTDELAY=10
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
deleted file mode 100644
index ac4dbd04215b..000000000000
--- a/configs/sbc8548_PCI_33_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFFA0000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_SBC8548=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="33"
-CONFIG_BOOTDELAY=10
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
deleted file mode 100644
index b7cd900e5d8e..000000000000
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFFA0000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_SBC8548=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
-CONFIG_BOOTDELAY=10
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
deleted file mode 100644
index eb3c56b47b07..000000000000
--- a/configs/sbc8548_PCI_66_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFFA0000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_SBC8548=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="66"
-CONFIG_BOOTDELAY=10
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
deleted file mode 100644
index 6e38d9257969..000000000000
--- a/configs/sbc8548_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFFA0000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_SBC8548=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
deleted file mode 100644
index 6e26d456ab74..000000000000
--- a/include/configs/sbc8548.h
+++ /dev/null
@@ -1,540 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007,2009 Wind River Systems <www.windriver.com>
- * Copyright 2007 Embedded Specialties, Inc.
- * Copyright 2004, 2007 Freescale Semiconductor.
- */
-
-/*
- * sbc8548 board configuration file
- * Please refer to board/sbc8548/README for more info.
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI1
-#endif
-
-#ifdef CONFIG_66
-#define CONFIG_SYS_CLK_DIV 1
-#endif
-
-#ifdef CONFIG_33
-#define CONFIG_SYS_CLK_DIV 2
-#endif
-
-#ifdef CONFIG_PCIE
-#define CONFIG_PCIE1
-#endif
-
-/*
- * High Level Configuration Options
- */
-
-/*
- * If you want to boot from the SODIMM flash, instead of the soldered
- * on flash, set this, and change JP12, SW2:8 accordingly.
- */
-#undef CONFIG_SYS_ALT_BOOT
-
-#undef CONFIG_RIO
-
-#ifdef CONFIG_PCI
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#endif
-
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
-/*
- * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
- */
-#ifndef CONFIG_SYS_CLK_DIV
-#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
-#endif
-#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-/*
- * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
- * to collide, meaning you couldn't reliably read either. So
- * physically remove the LBC PC100 SDRAM module from the board
- * before enabling the two SPD options below, or check that you
- * have the hardware fix on your board via "i2c probe" and looking
- * for a device at 0x53.
- */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/*
- * The hardware fix for the I2C address collision puts the DDR
- * SPD at 0x53, but if we are running on an older board w/o the
- * fix, it will still be at 0x51. We check 0x53 1st.
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
-
-/*
- * Make sure required options are set
- */
-#ifndef CONFIG_SPD_EEPROM
- #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
- #define CONFIG_SYS_DDR_CONTROL 0xc300c000
-#endif
-
-/*
- * FLASH on the Local Bus
- * Two banks, one 8MB the other 64MB, using the CFI driver.
- * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
- * CS0 the 8MB boot flash, and CS6 the 64MB flash.
- *
- * Default:
- * ec00_0000 efff_ffff 64MB SODIMM
- * ff80_0000 ffff_ffff 8MB soldered flash
- *
- * Alternate:
- * ef80_0000 efff_ffff 8MB soldered flash
- * fc00_0000 ffff_ffff 64MB SODIMM
- *
- * BR0_8M:
- * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
- * Port Size = 8 bits = BRx[19:20] = 01
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
- *
- * BR0_64M:
- * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
- * Port Size = 32 bits = BRx[19:20] = 11
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
- * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
- */
-#define CONFIG_SYS_BR0_8M 0xff800801
-#define CONFIG_SYS_BR0_64M 0xfc001801
-
-/*
- * BR6_8M:
- * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
- * Port Size = 8 bits = BRx[19:20] = 01
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
-
- * BR6_64M:
- * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
- * Port Size = 32 bits = BRx[19:20] = 11
- *
- * 0 4 8 12 16 20 24 28
- * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
- * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
- */
-#define CONFIG_SYS_BR6_8M 0xef800801
-#define CONFIG_SYS_BR6_64M 0xec001801
-
-/*
- * OR0_8M:
- * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
- * XAM = OR0[17:18] = 11
- * CSNT = OR0[20] = 1
- * ACS = half cycle delay = OR0[21:22] = 11
- * SCY = 6 = OR0[24:27] = 0110
- * TRLX = use relaxed timing = OR0[29] = 1
- * EAD = use external address latch delay = OR0[31] = 1
- *
- * OR0_64M:
- * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
- *
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
- * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
- */
-#define CONFIG_SYS_OR0_8M 0xff806e65
-#define CONFIG_SYS_OR0_64M 0xfc006e65
-
-/*
- * OR6_8M:
- * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
- * XAM = OR6[17:18] = 11
- * CSNT = OR6[20] = 1
- * ACS = half cycle delay = OR6[21:22] = 11
- * SCY = 6 = OR6[24:27] = 0110
- * TRLX = use relaxed timing = OR6[29] = 1
- * EAD = use external address latch delay = OR6[31] = 1
- *
- * OR6_64M:
- * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
- * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
- */
-#define CONFIG_SYS_OR6_8M 0xff806e65
-#define CONFIG_SYS_OR6_64M 0xfc006e65
-
-#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
-#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
-#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
-
-#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
-#else /* JP12 in alternate position */
-#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
-#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
-
-#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
-#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
-#endif
-
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_ALT_FLASH}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* CS5 = Local bus peripherals controlled by the EPLD */
-
-#define CONFIG_SYS_BR5_PRELIM 0xf8000801
-#define CONFIG_SYS_OR5_PRELIM 0xff006e65
-#define CONFIG_SYS_EPLD_BASE 0xf8000000
-#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
-#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
-#define CONFIG_SYS_BD_REV 0xf8300000
-#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
-
-/*
- * SDRAM on the Local Bus (CS3 and CS4)
- * Note that most boards have a hardware errata where both the
- * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
- * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
- * A hardware workaround is also available, see README.sbc8548 file.
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
-
-/*
- * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR3, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- */
-
-#define CONFIG_SYS_BR3_PRELIM 0xf0001861
-
-/*
- * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR3, need:
- * 64MB mask for AM, OR3[0:7] = 1111 1100
- * XAM, OR3[17:18] = 11
- * 10 columns OR3[19-21] = 011
- * 12 rows OR3[23-25] = 011
- * EAD set for extra time OR[31] = 0
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
- */
-
-#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
-
-/*
- * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
- * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
- *
- * For BR4, need:
- * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
- *
- */
-
-#define CONFIG_SYS_BR4_PRELIM 0xf4001861
-
-/*
- * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR4, need:
- * 64MB mask for AM, OR3[0:7] = 1111 1100
- * XAM, OR3[17:18] = 11
- * 10 columns OR3[19-21] = 011
- * 12 rows OR3[23-25] = 011
- * EAD set for extra time OR[31] = 0
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
- */
-
-#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
-
-#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-/*
- * Common settings for all Local Bus SDRAM commands.
- */
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
- | LSDMR_BSMA1516 \
- | LSDMR_PRETOACT3 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BUFCMD \
- | LSDMR_BL8 \
- | LSDMR_WRC2 \
- | LSDMR_CL3 \
- )
-
-#define CONFIG_SYS_LBC_LSDMR_PCHALL \
- (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
- (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_MRW \
- (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_RFEN \
- (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
- * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
- * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
- * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
- * thing for MONITOR_LEN in both cases.
- */
-#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
-
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-#endif
-
-#ifdef CONFIG_RIO
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
-#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
-#endif
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#undef CONFIG_MPC85XX_FEC
-
-#define TSEC1_PHY_ADDR 0x19
-#define TSEC2_PHY_ADDR 0x1a
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: eTSEC[0-3] */
-#define CONFIG_ETHPRIME "eTSEC0"
-#endif /* CONFIG_TSEC_ENET */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_IPADDR 192.168.0.55
-
-#define CONFIG_HOSTNAME "sbc8548"
-#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
-#define CONFIG_BOOTFILE "/uImage"
-#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
-
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"netdev=eth0\0" \
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
-"consoledev=ttyS0\0" \
-"ramdiskaddr=2000000\0" \
-"ramdiskfile=uRamdisk\0" \
-"fdtaddr=1e00000\0" \
-"fdtfile=sbc8548.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 13/27] ppc: Remove sbc8548 boards
2021-05-15 1:34 ` [PATCH 13/27] ppc: Remove sbc8548 boards Tom Rini
@ 2021-05-15 19:18 ` Paul Gortmaker
2021-07-08 2:52 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Paul Gortmaker @ 2021-05-15 19:18 UTC (permalink / raw)
To: u-boot
[[PATCH 13/27] ppc: Remove sbc8548 boards] On 14/05/2021 (Fri 21:34) Tom Rini wrote:
> These boards have not been converted to CONFIG_DM_PCI by the deadline and are
> also missing conversion to CONFIG_DM. Remove them.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Ack - kernel removal was queued several months ago, but has yet to be
merged to mainline or linux-next
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20210111082823.99562-2-paul.gortmaker at windriver.com/
Thanks,
Paul.
--
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> arch/powerpc/cpu/mpc85xx/Kconfig | 5 -
> board/sbc8548/Kconfig | 9 -
> board/sbc8548/MAINTAINERS | 10 -
> board/sbc8548/Makefile | 12 -
> board/sbc8548/README | 269 -------------
> board/sbc8548/ddr.c | 132 -------
> board/sbc8548/law.c | 54 ---
> board/sbc8548/sbc8548.c | 315 ---------------
> board/sbc8548/tlb.c | 121 ------
> configs/sbc8548_PCI_33_PCIE_defconfig | 42 --
> configs/sbc8548_PCI_33_defconfig | 42 --
> configs/sbc8548_PCI_66_PCIE_defconfig | 42 --
> configs/sbc8548_PCI_66_defconfig | 42 --
> configs/sbc8548_defconfig | 41 --
> include/configs/sbc8548.h | 540 --------------------------
> 15 files changed, 1676 deletions(-)
> delete mode 100644 board/sbc8548/Kconfig
> delete mode 100644 board/sbc8548/MAINTAINERS
> delete mode 100644 board/sbc8548/Makefile
> delete mode 100644 board/sbc8548/README
> delete mode 100644 board/sbc8548/ddr.c
> delete mode 100644 board/sbc8548/law.c
> delete mode 100644 board/sbc8548/sbc8548.c
> delete mode 100644 board/sbc8548/tlb.c
> delete mode 100644 configs/sbc8548_PCI_33_PCIE_defconfig
> delete mode 100644 configs/sbc8548_PCI_33_defconfig
> delete mode 100644 configs/sbc8548_PCI_66_PCIE_defconfig
> delete mode 100644 configs/sbc8548_PCI_66_defconfig
> delete mode 100644 configs/sbc8548_defconfig
> delete mode 100644 include/configs/sbc8548.h
>
> diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
> index 676aaf1d2ca6..22cfa4dc3499 100644
> --- a/arch/powerpc/cpu/mpc85xx/Kconfig
> +++ b/arch/powerpc/cpu/mpc85xx/Kconfig
> @@ -16,10 +16,6 @@ choice
> prompt "Target select"
> optional
>
> -config TARGET_SBC8548
> - bool "Support sbc8548"
> - select ARCH_MPC8548
> -
> config TARGET_SOCRATES
> bool "Support socrates"
> select ARCH_MPC8544
> @@ -1303,7 +1299,6 @@ source "board/freescale/t208xqds/Kconfig"
> source "board/freescale/t208xrdb/Kconfig"
> source "board/freescale/t4rdb/Kconfig"
> source "board/keymile/Kconfig"
> -source "board/sbc8548/Kconfig"
> source "board/socrates/Kconfig"
> source "board/xes/xpedite520x/Kconfig"
> source "board/xes/xpedite537x/Kconfig"
> diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig
> deleted file mode 100644
> index 626cbdf2ab27..000000000000
> --- a/board/sbc8548/Kconfig
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -if TARGET_SBC8548
> -
> -config SYS_BOARD
> - default "sbc8548"
> -
> -config SYS_CONFIG_NAME
> - default "sbc8548"
> -
> -endif
> diff --git a/board/sbc8548/MAINTAINERS b/board/sbc8548/MAINTAINERS
> deleted file mode 100644
> index ba1f2475eabf..000000000000
> --- a/board/sbc8548/MAINTAINERS
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -SBC8548 BOARD
> -M: Paul Gortmaker <paul.gortmaker@windriver.com>
> -S: Maintained
> -F: board/sbc8548/
> -F: include/configs/sbc8548.h
> -F: configs/sbc8548_defconfig
> -F: configs/sbc8548_PCI_33_defconfig
> -F: configs/sbc8548_PCI_33_PCIE_defconfig
> -F: configs/sbc8548_PCI_66_defconfig
> -F: configs/sbc8548_PCI_66_PCIE_defconfig
> diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
> deleted file mode 100644
> index 83d208cf1fe9..000000000000
> --- a/board/sbc8548/Makefile
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2004-2006
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -#
> -# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
> -# Added support for Wind River SBC8548 board
> -
> -obj-y += sbc8548.o
> -obj-y += law.o
> -obj-y += tlb.o
> -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
> diff --git a/board/sbc8548/README b/board/sbc8548/README
> deleted file mode 100644
> index 0def245bd9ce..000000000000
> --- a/board/sbc8548/README
> +++ /dev/null
> @@ -1,269 +0,0 @@
> -Intro:
> -======
> -
> -The SBC8548 is a stand alone single board computer with a 1GHz
> -MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
> -memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
> -and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
> -ethernet connections.
> -
> -U-Boot Configuration:
> -=====================
> -
> -The following possible U-Boot configuration targets are available:
> -
> - 1) sbc8548_config
> - 2) sbc8548_PCI_33_config
> - 3) sbc8548_PCI_66_config
> - 4) sbc8548_PCI_33_PCIE_config
> - 5) sbc8548_PCI_66_PCIE_config
> -
> -Generally speaking, most people should choose to use #5. Details
> -of each choice are listed below.
> -
> -Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
> -will be left empty (M66EN high), and so the board will operate with
> -a base clock of 66MHz. Note that you need both PCI enabled in U-Boot
> -and linux in order to have functional PCI under linux.
> -
> -The second enables PCI support and builds for a 33MHz clock rate. Note
> -that if a 33MHz 32bit card is inserted in the slot, then the whole board
> -will clock down to a 33MHz base clock instead of the default 66MHz. This
> -will change the baud clocks and mess up your serial console output if you
> -were previously running at 66MHz. If you want to use a 33MHz PCI card,
> -then you should build a U-Boot with a _PCI_33_ config and store this
> -to flash prior to powering down the board and inserting the 33MHz PCI
> -card. [The above discussion assumes that the SW2[1-4] has not been changed
> -to reflect a different CCB:SYSCLK ratio]
> -
> -The third option builds PCI support in, and leaves the clocking at the
> -default 66MHz. Options four and five are just repeats of option two
> -and three, but with PCI-e support enabled as well.
> -
> -PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
> -is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
> -a 33MHz PCI configuration is currently untested.)
> -
> - => pci 0
> - Scanning PCI devices on bus 0
> - BusDevFun VendorId DeviceId Device Class Sub-Class
> - _____________________________________________________________
> - 00.00.00 0x1057 0x0012 Processor 0x20
> - 00.01.00 0x8086 0x1026 Network controller 0x00
> - => pci 1
> - Scanning PCI devices on bus 1
> - BusDevFun VendorId DeviceId Device Class Sub-Class
> - _____________________________________________________________
> - 01.00.00 0x1957 0x0012 Processor 0x20
> - => pci 2
> - Scanning PCI devices on bus 2
> - BusDevFun VendorId DeviceId Device Class Sub-Class
> - _____________________________________________________________
> - 02.00.00 0x1148 0x9e00 Network controller 0x00
> - =>
> -
> -Memory Size and using SPD:
> -==========================
> -
> -The default configuration uses hard coded memory configuration settings
> -for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
> -EEPROM data to read what memory is installed.
> -
> -There is a hardware errata, which causes the older local bus SDRAM
> -SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
> -that the SPD data can not be read reliably. You can test if your
> -board has the errata fix by running "i2c probe". If you see 0x53
> -as a valid device, it has been fixed. If you only see 0x50, 0x51
> -then your board does not have the fix.
> -
> -You can also visually inspect the board to see if this hardware
> -fix has been applied:
> -
> - 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
> - the back of the PCB behind the DDR SDRAM SODIMM connector.
> - 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
> - to R313 pin 2. Pin 2 for each resistor is the end of the
> - resistor closest to the CPU.
> -
> -Boards without the mod will have R314 and R313 in parallel, like "||".
> -After the mod, they will be touching and form an "L" shape.
> -
> -If you want to upgrade to larger RAM size, you can simply enable
> - #define CONFIG_SPD_EEPROM
> - #define CONFIG_DDR_SPD
> -in include/configs/sbc8548.h file. (The lines are already there
> -but listed as #undef).
> -
> -If you did the i2c test, and your board does not have the errata
> -fix, then you will have to physically remove the LBC 128MB DIMM
> -from the board's socket to resolve the above i2c address overlap
> -issue and allow SPD autodetection of RAM to work.
> -
> -
> -Updating U-Boot with U-Boot:
> -============================
> -
> -Note that versions of U-Boot up to and including 2009.08 had U-Boot stored
> -at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
> -0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
> -update U-Boot with U-Boot and it uses the old address, you will render
> -your board inoperable, and you will require JTAG recovery.
> -
> -The following steps list how to update with the current address:
> -
> - tftp u-boot.bin
> - md 200000 10
> - protect off all
> - erase fffa0000 ffffffff
> - cp.b 200000 fffa0000 60000
> - md fffa0000 10
> - protect on all
> -
> -The "md" steps in the above are just a precautionary step that allow
> -you to confirm the U-Boot version that was downloaded, and then confirm
> -that it was copied to flash.
> -
> -The above assumes that you are using the default board settings which
> -have U-Boot in the 8MB flash, tied to /CS0.
> -
> -If you are running the default 8MB /CS0 settings but want to store an
> -image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
> -(as a backup, etc) then the steps will become:
> -
> - tftp u-boot.bin
> - md 200000 10
> - protect off all
> - era eff00000 efffffff
> - cp.b 200000 eff00000 100000
> - md eff00000 10
> - protect on all
> -
> -Finally, if you are running the alternate 64MB /CS0 settings and want
> -to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT
> -enabled) the steps will become:
> -
> - tftp u-boot.bin
> - md 200000 10
> - protect off all
> - era fff00000 ffffffff
> - cp.b 200000 fff00000 100000
> - md fff00000 10
> - protect on all
> -
> -
> -Hardware Reference:
> -===================
> -
> -The following contains some summary information on hardware settings
> -that are relevant to U-Boot, based on the board manual. For the
> -most up to date and complete details of the board, please request the
> -reference manual ERG-00327-001.pdf from www.windriver.com
> -
> -Boot flash:
> - intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
> -
> -Sodimm flash:
> - intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
> - Note that this address reflects the default setting for
> - the JTAG debugging tools, but since the alignment is
> - rather inconvenient, U-Boot puts it at 0xec00_0000.
> -
> -
> - Jumpers:
> -
> -Jumper Name ON OFF
> -----------------------------------------------------------------
> -JP12 CS0/CS6 swap see note[*] see note[*]
> -
> -JP13 SODIMM flash write OK writes disabled
> - write prot.
> -
> -JP14 HRESET/TRST joined isolated
> -
> -JP15 PWR ON when AC pwr use S1 for on/off
> -
> -JP16 Demo LEDs lit not lit
> -
> -JP19 PCI mode PCI PCI-X
> -
> -
> -[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
> -onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
> -is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
> -SODIMM flash and /CS6 is for the boot flash. Note that in this
> -alternate setting, you also need to switch SW2.8 to ON.
> -See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
> -and boot U-Boot from the 64MB SODIMM
> -
> -
> - Switches:
> -
> -The defaults are marked with a *
> -
> -Name Desc. ON OFF
> -------------------------------------------------------------------
> -S1 Pwr toggle n/a n/a
> -
> -SW2.1 CFG_SYS_PLL0 1 0*
> -SW2.2 CFG_SYS_PLL1 1* 0
> -SW2.3 CFG_SYS_PLL2 1* 0
> -SW2.4 CFG_SYS_PLL3 1 0*
> -SW2.5 CFG_CORE_PLL0 1* 0
> -SW2.6 CFG_CORE_PLL1 1 0*
> -SW2.7 CFG_CORE_PLL2 1* 0
> -SW2.8 CFG_ROM_LOC1 1 0*
> -
> -SW3.1 CFG_HOST_AGT0 1* 0
> -SW3.2 CFG_HOST_AGT1 1* 0
> -SW3.3 CFG_HOST_AGT2 1* 0
> -SW3.4 CFG_IO_PORTS0 1* 0
> -SW3.5 CFG_IO_PORTS0 1 0*
> -SW3.6 CFG_IO_PORTS0 1 0*
> -
> -SerDes CLK(MHz) SW5.1 SW5.2
> -----------------------------------------------
> -25 0 0
> -100* 1 0
> -125 0 1
> -200 1 1
> -
> -SerDes CLK spread SW5.3 SW5.4
> -----------------------------------------------
> -+/- 0.25% 0 0
> --0.50% 1 0
> --0.75% 0 1
> -No Spread* 1 1
> -
> -SW4 settings are readable from the EPLD and are currently not used for
> -any hardware settings (i.e. user configuration switches).
> -
> - LEDs:
> -
> -Name Desc. ON OFF
> -------------------------------------------------------------------
> -D13 PCI/PCI-X PCI-X PCI
> -D14 3.3V PWR 3.3V no power
> -D15 SYSCLK 66MHz 33MHz
> -
> -
> - Default Memory Map:
> -
> -start end CS<n> width Desc.
> -----------------------------------------------------------------------
> -0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
> -f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
> -f800_0000 f8b0_1fff CS5 - EPLD
> -fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
> -ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
> -
> -[*] fb80 represents the default programmed by WR JTAG register files,
> - but U-Boot places the flash at either ec00 or fc00 based on JP12.
> -
> -The EPLD on CS5 demuxes the following devices at the following offsets:
> -
> -offset size width device
> ---------------------------------------------------------
> -0 1fff 8 7 segment display LED
> -10_0000 1fff 4 user switches
> -30_0000 1fff 4 HW Rev. register
> -b0_0000 1fff 8 8kB EEPROM
> diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
> deleted file mode 100644
> index 61bc77c418a9..000000000000
> --- a/board/sbc8548/ddr.c
> +++ /dev/null
> @@ -1,132 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright 2008 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <i2c.h>
> -#include <linux/delay.h>
> -
> -#include <fsl_ddr_sdram.h>
> -#include <fsl_ddr_dimm_params.h>
> -
> -void fsl_ddr_board_options(memctl_options_t *popts,
> - dimm_params_t *pdimm,
> - unsigned int ctrl_num)
> -{
> - /*
> - * Factors to consider for clock adjust:
> - * - number of chips on bus
> - * - position of slot
> - * - DDR1 vs. DDR2?
> - * - ???
> - *
> - * This needs to be determined on a board-by-board basis.
> - * 0110 3/4 cycle late
> - * 0111 7/8 cycle late
> - */
> - popts->clk_adjust = 7;
> -
> - /*
> - * Factors to consider for CPO:
> - * - frequency
> - * - ddr1 vs. ddr2
> - */
> - popts->cpo_override = 10;
> -
> - /*
> - * Factors to consider for write data delay:
> - * - number of DIMMs
> - *
> - * 1 = 1/4 clock delay
> - * 2 = 1/2 clock delay
> - * 3 = 3/4 clock delay
> - * 4 = 1 clock delay
> - * 5 = 5/4 clock delay
> - * 6 = 3/2 clock delay
> - */
> - popts->write_data_delay = 3;
> -
> - /*
> - * Factors to consider for half-strength driver enable:
> - * - number of DIMMs installed
> - */
> - popts->half_strength_driver_enable = 0;
> -}
> -
> -#ifdef CONFIG_SPD_EEPROM
> -/*
> - * Workaround for hardware errata. An i2c address conflict
> - * existed on earlier boards; the workaround moved the DDR
> - * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
> - * if that fails, then fall back to reading at 0x51.
> - */
> -void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
> -{
> - int ret;
> -
> -#ifdef ALT_SPD_EEPROM_ADDRESS
> - if (i2c_address == SPD_EEPROM_ADDRESS) {
> - ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
> - sizeof(generic_spd_eeprom_t));
> - if (ret == 0)
> - return; /* Good data at 0x53 */
> - memset(spd, 0, sizeof(generic_spd_eeprom_t));
> - }
> -#endif
> - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
> - sizeof(generic_spd_eeprom_t));
> - if (ret) {
> - printf("DDR: failed to read SPD from addr %u\n", i2c_address);
> - memset(spd, 0, sizeof(generic_spd_eeprom_t));
> - }
> -}
> -
> -#else
> -/*
> - * fixed_sdram init -- doesn't use serial presence detect.
> - * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
> - */
> -phys_size_t fixed_sdram(void)
> -{
> - struct ccsr_ddr __iomem *ddr =
> - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
> -
> - out_be32(&ddr->cs0_bnds, 0x0000007f);
> - out_be32(&ddr->cs1_bnds, 0x008000ff);
> - out_be32(&ddr->cs2_bnds, 0x00000000);
> - out_be32(&ddr->cs3_bnds, 0x00000000);
> -
> - out_be32(&ddr->cs0_config, 0x80010101);
> - out_be32(&ddr->cs1_config, 0x80010101);
> - out_be32(&ddr->cs2_config, 0x00000000);
> - out_be32(&ddr->cs3_config, 0x00000000);
> -
> - out_be32(&ddr->timing_cfg_3, 0x00000000);
> - out_be32(&ddr->timing_cfg_0, 0x00220802);
> - out_be32(&ddr->timing_cfg_1, 0x38377322);
> - out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
> -
> - out_be32(&ddr->sdram_cfg, 0x4300C000);
> - out_be32(&ddr->sdram_cfg_2, 0x24401000);
> -
> - out_be32(&ddr->sdram_mode, 0x23C00542);
> - out_be32(&ddr->sdram_mode_2, 0x00000000);
> -
> - out_be32(&ddr->sdram_interval, 0x05080100);
> - out_be32(&ddr->sdram_md_cntl, 0x00000000);
> - out_be32(&ddr->sdram_data_init, 0x00000000);
> - out_be32(&ddr->sdram_clk_cntl, 0x03800000);
> - asm("sync;isync;msync");
> - udelay(500);
> -
> - #ifdef CONFIG_DDR_ECC
> - /* Enable ECC checking */
> - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
> - #else
> - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
> - #endif
> -
> - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> -}
> -#endif
> diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
> deleted file mode 100644
> index 97271ea6f66b..000000000000
> --- a/board/sbc8548/law.c
> +++ /dev/null
> @@ -1,54 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2008 Freescale Semiconductor, Inc.
> - *
> - * (C) Copyright 2000
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - */
> -
> -#include <common.h>
> -#include <asm/fsl_law.h>
> -#include <asm/mmu.h>
> -
> -/*
> - * LAW(Local Access Window) configuration:
> - *
> - * 0x0000_0000 0x0fff_ffff DDR 256M
> - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
> - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
> - * 0xe000_0000 0xe000_ffff CCSR 1M
> - * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
> - * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
> - * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
> - * 0xf000_0000 0xf7ff_ffff SDRAM 128M
> - * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
> - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
> - *
> - * If swapped CS0/CS6 via JP12+SW2.8:
> - * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
> - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
> - *
> - * Notes:
> - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
> - * If flash is 8M at default position (last 8M), no LAW needed.
> - */
> -
> -struct law_entry law_table[] = {
> -#ifdef CONFIG_SYS_ALT_BOOT
> - SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
> -#else
> - SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
> -#endif
> -#ifndef CONFIG_SPD_EEPROM
> - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
> -#endif
> -#ifdef CONFIG_SYS_LBC_SDRAM_BASE
> - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
> - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
> -#else
> - /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
> - SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
> -#endif
> -};
> -
> -int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
> deleted file mode 100644
> index bd4b528d03f7..000000000000
> --- a/board/sbc8548/sbc8548.c
> +++ /dev/null
> @@ -1,315 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
> - *
> - * Copyright 2007 Embedded Specialties, Inc.
> - *
> - * Copyright 2004, 2007 Freescale Semiconductor.
> - *
> - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
> - */
> -
> -#include <common.h>
> -#include <init.h>
> -#include <log.h>
> -#include <net.h>
> -#include <pci.h>
> -#include <asm/processor.h>
> -#include <asm/immap_85xx.h>
> -#include <asm/fsl_pci.h>
> -#include <fsl_ddr_sdram.h>
> -#include <asm/fsl_serdes.h>
> -#include <spd_sdram.h>
> -#include <netdev.h>
> -#include <tsec.h>
> -#include <miiphy.h>
> -#include <linux/delay.h>
> -#include <linux/libfdt.h>
> -#include <fdt_support.h>
> -
> -void local_bus_init(void);
> -
> -int board_early_init_f (void)
> -{
> - return 0;
> -}
> -
> -int checkboard (void)
> -{
> - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
> - volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
> -
> - printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
> - in_8(rev) >> 4);
> -
> - /*
> - * Initialize local bus.
> - */
> - local_bus_init ();
> -
> - out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
> - out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
> - return 0;
> -}
> -
> -/*
> - * Initialize Local Bus
> - */
> -void
> -local_bus_init(void)
> -{
> - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
> -
> - uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
> - sys_info_t sysinfo;
> -
> - get_sys_info(&sysinfo);
> -
> - lbc_mhz = sysinfo.freq_localbus / 1000000;
> - clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
> -
> - debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
> -
> - out_be32(&gur->lbiuiplldcr1, 0x00078080);
> - if (clkdiv == 16) {
> - out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
> - } else if (clkdiv == 8) {
> - out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
> - } else if (clkdiv == 4) {
> - out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
> - }
> -
> - /*
> - * Local Bus Clock > 83.3 MHz. According to timing
> - * specifications set LCRR[EADC] to 2 delay cycles.
> - */
> - if (lbc_mhz > 83) {
> - lcrr &= ~LCRR_EADC;
> - lcrr |= LCRR_EADC_2;
> - }
> -
> - /*
> - * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
> - * disable PLL bypass for Local Bus Clock > 83 MHz.
> - */
> - if (lbc_mhz >= 66)
> - lcrr &= (~LCRR_DBYP); /* DLL Enabled */
> -
> - else
> - lcrr |= LCRR_DBYP; /* DLL Bypass */
> -
> - out_be32(&lbc->lcrr, lcrr);
> - asm("sync;isync;msync");
> -
> - /*
> - * According to MPC8548ERMAD Rev.1.3 read back LCRR
> - * and terminate with isync
> - */
> - lcrr = in_be32(&lbc->lcrr);
> - asm ("isync;");
> -
> - /* let DLL stabilize */
> - udelay(500);
> -
> - out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
> - out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
> -}
> -
> -/*
> - * Initialize SDRAM memory on the Local Bus.
> - */
> -void lbc_sdram_init(void)
> -{
> -#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
> -
> - uint idx;
> - const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
> - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
> - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
> - uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
> -
> - puts(" SDRAM: ");
> -
> - print_size(size, "\n");
> -
> - /*
> - * Setup SDRAM Base and Option Registers
> - */
> - set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
> - set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
> - set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
> - set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
> -
> - out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
> - asm("msync");
> -
> - out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
> - out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
> - asm("msync");
> -
> - /*
> - * Issue PRECHARGE ALL command.
> - */
> - out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
> - asm("sync;msync");
> - *sdram_addr = 0xff;
> - ppcDcbf((unsigned long) sdram_addr);
> - *sdram_addr2 = 0xff;
> - ppcDcbf((unsigned long) sdram_addr2);
> - udelay(100);
> -
> - /*
> - * Issue 8 AUTO REFRESH commands.
> - */
> - for (idx = 0; idx < 8; idx++) {
> - out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
> - asm("sync;msync");
> - *sdram_addr = 0xff;
> - ppcDcbf((unsigned long) sdram_addr);
> - *sdram_addr2 = 0xff;
> - ppcDcbf((unsigned long) sdram_addr2);
> - udelay(100);
> - }
> -
> - /*
> - * Issue 8 MODE-set command.
> - */
> - out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
> - asm("sync;msync");
> - *sdram_addr = 0xff;
> - ppcDcbf((unsigned long) sdram_addr);
> - *sdram_addr2 = 0xff;
> - ppcDcbf((unsigned long) sdram_addr2);
> - udelay(100);
> -
> - /*
> - * Issue RFEN command.
> - */
> - out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
> - asm("sync;msync");
> - *sdram_addr = 0xff;
> - ppcDcbf((unsigned long) sdram_addr);
> - *sdram_addr2 = 0xff;
> - ppcDcbf((unsigned long) sdram_addr2);
> - udelay(200); /* Overkill. Must wait > 200 bus cycles */
> -
> -#endif /* enable SDRAM init */
> -}
> -
> -#if defined(CONFIG_SYS_DRAM_TEST)
> -int
> -testdram(void)
> -{
> - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
> - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
> - uint *p;
> -
> - printf("Testing DRAM from 0x%08x to 0x%08x\n",
> - CONFIG_SYS_MEMTEST_START,
> - CONFIG_SYS_MEMTEST_END);
> -
> - printf("DRAM test phase 1:\n");
> - for (p = pstart; p < pend; p++)
> - *p = 0xaaaaaaaa;
> -
> - for (p = pstart; p < pend; p++) {
> - if (*p != 0xaaaaaaaa) {
> - printf ("DRAM test fails at: %08x\n", (uint) p);
> - return 1;
> - }
> - }
> -
> - printf("DRAM test phase 2:\n");
> - for (p = pstart; p < pend; p++)
> - *p = 0x55555555;
> -
> - for (p = pstart; p < pend; p++) {
> - if (*p != 0x55555555) {
> - printf ("DRAM test fails at: %08x\n", (uint) p);
> - return 1;
> - }
> - }
> -
> - printf("DRAM test passed.\n");
> - return 0;
> -}
> -#endif
> -
> -#ifdef CONFIG_PCI1
> -static struct pci_controller pci1_hose;
> -#endif /* CONFIG_PCI1 */
> -
> -#ifdef CONFIG_PCI
> -void
> -pci_init_board(void)
> -{
> - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> - int first_free_busno = 0;
> -
> -#ifdef CONFIG_PCI1
> - struct fsl_pci_info pci_info;
> - u32 devdisr = in_be32(&gur->devdisr);
> - u32 pordevsr = in_be32(&gur->pordevsr);
> - u32 porpllsr = in_be32(&gur->porpllsr);
> -
> - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
> - uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
> - uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
> - uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
> - uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
> -
> - printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
> - (pci_32) ? 32 : 64,
> - (pci_speed == 33000000) ? "33" :
> - (pci_speed == 66000000) ? "66" : "unknown",
> - pci_clk_sel ? "sync" : "async",
> - pci_arb ? "arbiter" : "external-arbiter");
> -
> - SET_STD_PCI_INFO(pci_info, 1);
> - set_next_law(pci_info.mem_phys,
> - law_size_bits(pci_info.mem_size), pci_info.law);
> - set_next_law(pci_info.io_phys,
> - law_size_bits(pci_info.io_size), pci_info.law);
> -
> - first_free_busno = fsl_pci_init_port(&pci_info,
> - &pci1_hose, first_free_busno);
> - } else {
> - printf("PCI: disabled\n");
> - }
> -
> - puts("\n");
> -#else
> - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
> -#endif
> -
> - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
> -
> - fsl_pcie_init_board(first_free_busno);
> -}
> -#endif
> -
> -int board_eth_init(struct bd_info *bis)
> -{
> - tsec_standard_init(bis);
> - pci_eth_init(bis);
> - return 0; /* otherwise cpu_eth_init gets run */
> -}
> -
> -int last_stage_init(void)
> -{
> - return 0;
> -}
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, struct bd_info *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -
> -#ifdef CONFIG_FSL_PCI_INIT
> - FT_FSL_PCI_SETUP;
> -#endif
> -
> - return 0;
> -}
> -#endif
> diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
> deleted file mode 100644
> index 8ad01d10e49b..000000000000
> --- a/board/sbc8548/tlb.c
> +++ /dev/null
> @@ -1,121 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2008 Freescale Semiconductor, Inc.
> - *
> - * (C) Copyright 2000
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - */
> -
> -#include <common.h>
> -#include <asm/mmu.h>
> -
> -struct fsl_e_tlb_entry tlb_table[] = {
> - /* TLB 0 - for temp stack in cache */
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
> - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
> - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
> - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
> - MAS3_SX|MAS3_SW|MAS3_SR, 0,
> - 0, 0, BOOKE_PAGESZ_4K, 0),
> -
> - /*
> - * TLB 0: 64M Non-cacheable, guarded
> - * 0xfc000000 56M unused
> - * 0xff800000 8M boot FLASH
> - * .... or ....
> - * 0xfc000000 64M user flash
> - *
> - * Out of reset this entry is only 4K.
> - */
> - SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 0, BOOKE_PAGESZ_64M, 1),
> -
> - /*
> - * TLB 1: 1G Non-cacheable, guarded
> - * 0x80000000 512M PCI1 MEM
> - * 0xa0000000 512M PCIe MEM
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 1, BOOKE_PAGESZ_1G, 1),
> -
> - /*
> - * TLB 2: 64M Non-cacheable, guarded
> - * 0xe0000000 1M CCSRBAR
> - * 0xe2000000 8M PCI1 IO
> - * 0xe2800000 8M PCIe IO
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 2, BOOKE_PAGESZ_64M, 1),
> -
> -#ifdef CONFIG_SYS_LBC_SDRAM_BASE
> - /*
> - * TLB 3: 64M Cacheable, non-guarded
> - * 0xf0000000 64M LBC SDRAM First half
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
> - 0, 3, BOOKE_PAGESZ_64M, 1),
> -
> - /*
> - * TLB 4: 64M Cacheable, non-guarded
> - * 0xf4000000 64M LBC SDRAM Second half
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
> - CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
> - 0, 4, BOOKE_PAGESZ_64M, 1),
> -#endif
> -
> - /*
> - * TLB 5: 16M Cacheable, non-guarded
> - * 0xf8000000 1M 7-segment LED display
> - * 0xf8100000 1M User switches
> - * 0xf8300000 1M Board revision
> - * 0xf8b00000 1M EEPROM
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 5, BOOKE_PAGESZ_16M, 1),
> -
> -#ifndef CONFIG_SYS_ALT_BOOT
> - /*
> - * TLB 6: 64M Non-cacheable, guarded
> - * 0xec000000 64M 64MB user FLASH
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 6, BOOKE_PAGESZ_64M, 1),
> -#else
> - /*
> - * TLB 6: 4M Non-cacheable, guarded
> - * 0xef800000 4M 1st 1/2 8MB soldered FLASH
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 6, BOOKE_PAGESZ_4M, 1),
> -
> - /*
> - * TLB 7: 4M Non-cacheable, guarded
> - * 0xefc00000 4M 2nd half 8MB soldered FLASH
> - */
> - SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
> - CONFIG_SYS_ALT_FLASH + 0x400000,
> - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
> - 0, 7, BOOKE_PAGESZ_4M, 1),
> -#endif
> -
> -};
> -
> -int num_tlb_entries = ARRAY_SIZE(tlb_table);
> diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
> deleted file mode 100644
> index 3157ed92f396..000000000000
> --- a/configs/sbc8548_PCI_33_PCIE_defconfig
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFFFA0000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC85xx=y
> -# CONFIG_CMD_ERRATA is not set
> -CONFIG_TARGET_SBC8548=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
> -CONFIG_BOOTDELAY=10
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_BOARD_EARLY_INIT_F=y
> -# CONFIG_MISC_INIT_R is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -# CONFIG_CMD_HASH is not set
> -# CONFIG_CMD_IRQ is not set
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFFFE0000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_MII=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
> deleted file mode 100644
> index ac4dbd04215b..000000000000
> --- a/configs/sbc8548_PCI_33_defconfig
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFFFA0000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC85xx=y
> -# CONFIG_CMD_ERRATA is not set
> -CONFIG_TARGET_SBC8548=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="33"
> -CONFIG_BOOTDELAY=10
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_BOARD_EARLY_INIT_F=y
> -# CONFIG_MISC_INIT_R is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -# CONFIG_CMD_HASH is not set
> -# CONFIG_CMD_IRQ is not set
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFFFE0000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_MII=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
> deleted file mode 100644
> index b7cd900e5d8e..000000000000
> --- a/configs/sbc8548_PCI_66_PCIE_defconfig
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFFFA0000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC85xx=y
> -# CONFIG_CMD_ERRATA is not set
> -CONFIG_TARGET_SBC8548=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
> -CONFIG_BOOTDELAY=10
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_BOARD_EARLY_INIT_F=y
> -# CONFIG_MISC_INIT_R is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -# CONFIG_CMD_HASH is not set
> -# CONFIG_CMD_IRQ is not set
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFFFE0000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_MII=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
> deleted file mode 100644
> index eb3c56b47b07..000000000000
> --- a/configs/sbc8548_PCI_66_defconfig
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFFFA0000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC85xx=y
> -# CONFIG_CMD_ERRATA is not set
> -CONFIG_TARGET_SBC8548=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_SYS_EXTRA_OPTIONS="66"
> -CONFIG_BOOTDELAY=10
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_BOARD_EARLY_INIT_F=y
> -# CONFIG_MISC_INIT_R is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -# CONFIG_CMD_HASH is not set
> -# CONFIG_CMD_IRQ is not set
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFFFE0000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_MII=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
> deleted file mode 100644
> index 6e38d9257969..000000000000
> --- a/configs/sbc8548_defconfig
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xFFFA0000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC85xx=y
> -# CONFIG_CMD_ERRATA is not set
> -CONFIG_TARGET_SBC8548=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=10
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_BOARD_EARLY_INIT_F=y
> -# CONFIG_MISC_INIT_R is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -# CONFIG_CMD_HASH is not set
> -# CONFIG_CMD_IRQ is not set
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFFFE0000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_MII=y
> -CONFIG_TSEC_ENET=y
> -# CONFIG_PCI is not set
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
> deleted file mode 100644
> index 6e26d456ab74..000000000000
> --- a/include/configs/sbc8548.h
> +++ /dev/null
> @@ -1,540 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2007,2009 Wind River Systems <www.windriver.com>
> - * Copyright 2007 Embedded Specialties, Inc.
> - * Copyright 2004, 2007 Freescale Semiconductor.
> - */
> -
> -/*
> - * sbc8548 board configuration file
> - * Please refer to board/sbc8548/README for more info.
> - */
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -#include <linux/stringify.h>
> -
> -/*
> - * Top level Makefile configuration choices
> - */
> -#ifdef CONFIG_PCI
> -#define CONFIG_PCI_INDIRECT_BRIDGE
> -#define CONFIG_PCI1
> -#endif
> -
> -#ifdef CONFIG_66
> -#define CONFIG_SYS_CLK_DIV 1
> -#endif
> -
> -#ifdef CONFIG_33
> -#define CONFIG_SYS_CLK_DIV 2
> -#endif
> -
> -#ifdef CONFIG_PCIE
> -#define CONFIG_PCIE1
> -#endif
> -
> -/*
> - * High Level Configuration Options
> - */
> -
> -/*
> - * If you want to boot from the SODIMM flash, instead of the soldered
> - * on flash, set this, and change JP12, SW2:8 accordingly.
> - */
> -#undef CONFIG_SYS_ALT_BOOT
> -
> -#undef CONFIG_RIO
> -
> -#ifdef CONFIG_PCI
> -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
> -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
> -#endif
> -
> -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
> -
> -/*
> - * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
> - */
> -#ifndef CONFIG_SYS_CLK_DIV
> -#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
> -#endif
> -#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
> -
> -/*
> - * These can be toggled for performance analysis, otherwise use default.
> - */
> -#define CONFIG_L2_CACHE /* toggle L2 cache */
> -#define CONFIG_BTB /* toggle branch predition */
> -
> -/*
> - * Only possible on E500 Version 2 or newer cores.
> - */
> -#define CONFIG_ENABLE_36BIT_PHYS 1
> -
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -
> -#define CONFIG_SYS_CCSRBAR 0xe0000000
> -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
> -
> -/* DDR Setup */
> -#undef CONFIG_DDR_ECC /* only for ECC DDR module */
> -/*
> - * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
> - * to collide, meaning you couldn't reliably read either. So
> - * physically remove the LBC PC100 SDRAM module from the board
> - * before enabling the two SPD options below, or check that you
> - * have the hardware fix on your board via "i2c probe" and looking
> - * for a device at 0x53.
> - */
> -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
> -#undef CONFIG_DDR_SPD
> -
> -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
> -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
> -
> -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
> -#define CONFIG_VERY_BIG_RAM
> -
> -#define CONFIG_DIMM_SLOTS_PER_CTLR 1
> -#define CONFIG_CHIP_SELECTS_PER_CTRL 2
> -
> -/*
> - * The hardware fix for the I2C address collision puts the DDR
> - * SPD at 0x53, but if we are running on an older board w/o the
> - * fix, it will still be at 0x51. We check 0x53 1st.
> - */
> -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
> -#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
> -
> -/*
> - * Make sure required options are set
> - */
> -#ifndef CONFIG_SPD_EEPROM
> - #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
> - #define CONFIG_SYS_DDR_CONTROL 0xc300c000
> -#endif
> -
> -/*
> - * FLASH on the Local Bus
> - * Two banks, one 8MB the other 64MB, using the CFI driver.
> - * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
> - * CS0 the 8MB boot flash, and CS6 the 64MB flash.
> - *
> - * Default:
> - * ec00_0000 efff_ffff 64MB SODIMM
> - * ff80_0000 ffff_ffff 8MB soldered flash
> - *
> - * Alternate:
> - * ef80_0000 efff_ffff 8MB soldered flash
> - * fc00_0000 ffff_ffff 64MB SODIMM
> - *
> - * BR0_8M:
> - * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
> - * Port Size = 8 bits = BRx[19:20] = 01
> - * Use GPCM = BRx[24:26] = 000
> - * Valid = BRx[31] = 1
> - *
> - * BR0_64M:
> - * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
> - * Port Size = 32 bits = BRx[19:20] = 11
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
> - * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
> - */
> -#define CONFIG_SYS_BR0_8M 0xff800801
> -#define CONFIG_SYS_BR0_64M 0xfc001801
> -
> -/*
> - * BR6_8M:
> - * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
> - * Port Size = 8 bits = BRx[19:20] = 01
> - * Use GPCM = BRx[24:26] = 000
> - * Valid = BRx[31] = 1
> -
> - * BR6_64M:
> - * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
> - * Port Size = 32 bits = BRx[19:20] = 11
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
> - * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
> - */
> -#define CONFIG_SYS_BR6_8M 0xef800801
> -#define CONFIG_SYS_BR6_64M 0xec001801
> -
> -/*
> - * OR0_8M:
> - * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
> - * XAM = OR0[17:18] = 11
> - * CSNT = OR0[20] = 1
> - * ACS = half cycle delay = OR0[21:22] = 11
> - * SCY = 6 = OR0[24:27] = 0110
> - * TRLX = use relaxed timing = OR0[29] = 1
> - * EAD = use external address latch delay = OR0[31] = 1
> - *
> - * OR0_64M:
> - * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
> - *
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
> - * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
> - */
> -#define CONFIG_SYS_OR0_8M 0xff806e65
> -#define CONFIG_SYS_OR0_64M 0xfc006e65
> -
> -/*
> - * OR6_8M:
> - * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
> - * XAM = OR6[17:18] = 11
> - * CSNT = OR6[20] = 1
> - * ACS = half cycle delay = OR6[21:22] = 11
> - * SCY = 6 = OR6[24:27] = 0110
> - * TRLX = use relaxed timing = OR6[29] = 1
> - * EAD = use external address latch delay = OR6[31] = 1
> - *
> - * OR6_64M:
> - * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
> - * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
> - */
> -#define CONFIG_SYS_OR6_8M 0xff806e65
> -#define CONFIG_SYS_OR6_64M 0xfc006e65
> -
> -#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
> -#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
> -#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
> -
> -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
> -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
> -
> -#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
> -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
> -#else /* JP12 in alternate position */
> -#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
> -#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
> -
> -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
> -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
> -
> -#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
> -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
> -#endif
> -
> -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
> -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
> - CONFIG_SYS_ALT_FLASH}
> -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -
> -#define CONFIG_SYS_FLASH_EMPTY_INFO
> -
> -/* CS5 = Local bus peripherals controlled by the EPLD */
> -
> -#define CONFIG_SYS_BR5_PRELIM 0xf8000801
> -#define CONFIG_SYS_OR5_PRELIM 0xff006e65
> -#define CONFIG_SYS_EPLD_BASE 0xf8000000
> -#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
> -#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
> -#define CONFIG_SYS_BD_REV 0xf8300000
> -#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
> -
> -/*
> - * SDRAM on the Local Bus (CS3 and CS4)
> - * Note that most boards have a hardware errata where both the
> - * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
> - * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
> - * A hardware workaround is also available, see README.sbc8548 file.
> - */
> -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
> -#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
> -
> -/*
> - * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
> - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
> - *
> - * For BR3, need:
> - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
> - * port-size = 32-bits = BR2[19:20] = 11
> - * no parity checking = BR2[21:22] = 00
> - * SDRAM for MSEL = BR2[24:26] = 011
> - * Valid = BR[31] = 1
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
> - *
> - */
> -
> -#define CONFIG_SYS_BR3_PRELIM 0xf0001861
> -
> -/*
> - * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
> - *
> - * For OR3, need:
> - * 64MB mask for AM, OR3[0:7] = 1111 1100
> - * XAM, OR3[17:18] = 11
> - * 10 columns OR3[19-21] = 011
> - * 12 rows OR3[23-25] = 011
> - * EAD set for extra time OR[31] = 0
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
> - */
> -
> -#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
> -
> -/*
> - * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
> - * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
> - *
> - * For BR4, need:
> - * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
> - * port-size = 32-bits = BR2[19:20] = 11
> - * no parity checking = BR2[21:22] = 00
> - * SDRAM for MSEL = BR2[24:26] = 011
> - * Valid = BR[31] = 1
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
> - *
> - */
> -
> -#define CONFIG_SYS_BR4_PRELIM 0xf4001861
> -
> -/*
> - * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
> - *
> - * For OR4, need:
> - * 64MB mask for AM, OR3[0:7] = 1111 1100
> - * XAM, OR3[17:18] = 11
> - * 10 columns OR3[19-21] = 011
> - * 12 rows OR3[23-25] = 011
> - * EAD set for extra time OR[31] = 0
> - *
> - * 0 4 8 12 16 20 24 28
> - * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
> - */
> -
> -#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
> -
> -#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
> -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
> -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
> -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
> -
> -/*
> - * Common settings for all Local Bus SDRAM commands.
> - */
> -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
> - | LSDMR_BSMA1516 \
> - | LSDMR_PRETOACT3 \
> - | LSDMR_ACTTORW3 \
> - | LSDMR_BUFCMD \
> - | LSDMR_BL8 \
> - | LSDMR_WRC2 \
> - | LSDMR_CL3 \
> - )
> -
> -#define CONFIG_SYS_LBC_LSDMR_PCHALL \
> - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
> -#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
> - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
> -#define CONFIG_SYS_LBC_LSDMR_MRW \
> - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
> -#define CONFIG_SYS_LBC_LSDMR_RFEN \
> - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
> -
> -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -/*
> - * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
> - * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
> - * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
> - * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
> - * thing for MONITOR_LEN in both cases.
> - */
> -#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
> -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
> -
> -/* Serial Port */
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
> -
> -/*
> - * I2C
> - */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -
> -/*
> - * General PCI
> - * Memory space is mapped 1-1, but I/O space must start from 0.
> - */
> -#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
> -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
> -
> -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
> -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
> -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
> -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
> -#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
> -
> -#ifdef CONFIG_PCIE1
> -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
> -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
> -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
> -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
> -#endif
> -
> -#ifdef CONFIG_RIO
> -/*
> - * RapidIO MMU
> - */
> -#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
> -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
> -#endif
> -
> -#if defined(CONFIG_PCI)
> -
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -
> -#endif /* CONFIG_PCI */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "eTSEC0"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "eTSEC1"
> -#undef CONFIG_MPC85XX_FEC
> -
> -#define TSEC1_PHY_ADDR 0x19
> -#define TSEC2_PHY_ADDR 0x1a
> -
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -
> -/* Options are: eTSEC[0-3] */
> -#define CONFIG_ETHPRIME "eTSEC0"
> -#endif /* CONFIG_TSEC_ENET */
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -/*
> - * BOOTP options
> - */
> -#define CONFIG_BOOTP_BOOTFILESIZE
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 8 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_HAS_ETH0
> -#define CONFIG_HAS_ETH1
> -#endif
> -
> -#define CONFIG_IPADDR 192.168.0.55
> -
> -#define CONFIG_HOSTNAME "sbc8548"
> -#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
> -#define CONFIG_BOOTFILE "/uImage"
> -#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
> -
> -#define CONFIG_SERVERIP 192.168.0.2
> -#define CONFIG_GATEWAYIP 192.168.0.1
> -#define CONFIG_NETMASK 255.255.255.0
> -
> -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> -"netdev=eth0\0" \
> -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
> -"tftpflash=tftpboot $loadaddr $uboot; " \
> - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
> - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
> - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
> - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
> - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
> -"consoledev=ttyS0\0" \
> -"ramdiskaddr=2000000\0" \
> -"ramdiskfile=uRamdisk\0" \
> -"fdtaddr=1e00000\0" \
> -"fdtfile=sbc8548.dtb\0"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr - $fdtaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $fdtaddr $fdtfile;" \
> - "bootm $loadaddr $ramdiskaddr $fdtaddr"
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
> -
> -#endif /* __CONFIG_H */
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 13/27] ppc: Remove sbc8548 boards
2021-05-15 1:34 ` [PATCH 13/27] ppc: Remove sbc8548 boards Tom Rini
2021-05-15 19:18 ` Paul Gortmaker
@ 2021-07-08 2:52 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:52 UTC (permalink / raw)
To: u-boot; +Cc: Paul Gortmaker
[-- Attachment #1: Type: text/plain, Size: 351 bytes --]
On Fri, May 14, 2021 at 09:34:18PM -0400, Tom Rini wrote:
> These boards have not been converted to CONFIG_DM_PCI by the deadline and are
> also missing conversion to CONFIG_DM. Remove them.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 14/27] ppc: Remove TQM834x board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (11 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 13/27] ppc: Remove sbc8548 boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 15/27] ppc: Remove MPC8541CDS board Tom Rini
` (13 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 6 -
board/tqc/tqm834x/Kconfig | 12 -
board/tqc/tqm834x/MAINTAINERS | 6 -
board/tqc/tqm834x/Makefile | 9 -
board/tqc/tqm834x/pci.c | 98 -------
board/tqc/tqm834x/tqm834x.c | 433 -------------------------------
configs/TQM834x_defconfig | 166 ------------
include/configs/TQM834x.h | 277 --------------------
8 files changed, 1007 deletions(-)
delete mode 100644 board/tqc/tqm834x/Kconfig
delete mode 100644 board/tqc/tqm834x/MAINTAINERS
delete mode 100644 board/tqc/tqm834x/Makefile
delete mode 100644 board/tqc/tqm834x/pci.c
delete mode 100644 board/tqc/tqm834x/tqm834x.c
delete mode 100644 configs/TQM834x_defconfig
delete mode 100644 include/configs/TQM834x.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index e751daac6e2d..a67216a2f460 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -89,11 +89,6 @@ config TARGET_KMTEPR2
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
-config TARGET_TQM834X
- bool "Support TQM834x"
- select ARCH_MPC8349
-
-
config TARGET_GAZERBEAM
bool "Support gazerbeam"
select ARCH_MPC8308
@@ -277,7 +272,6 @@ source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig"
-source "board/tqc/tqm834x/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
endmenu
diff --git a/board/tqc/tqm834x/Kconfig b/board/tqc/tqm834x/Kconfig
deleted file mode 100644
index 028b8466e8a4..000000000000
--- a/board/tqc/tqm834x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_TQM834X
-
-config SYS_BOARD
- default "tqm834x"
-
-config SYS_VENDOR
- default "tqc"
-
-config SYS_CONFIG_NAME
- default "TQM834x"
-
-endif
diff --git a/board/tqc/tqm834x/MAINTAINERS b/board/tqc/tqm834x/MAINTAINERS
deleted file mode 100644
index 543ab1b55283..000000000000
--- a/board/tqc/tqm834x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TQM834X BOARD
-#M: -
-S: Maintained
-F: board/tqc/tqm834x/
-F: include/configs/TQM834x.h
-F: configs/TQM834x_defconfig
diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile
deleted file mode 100644
index 3aafbf79285d..000000000000
--- a/board/tqc/tqm834x/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# Copyright 2004 Freescale Semiconductor, Inc.
-
-obj-y += tqm834x.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
deleted file mode 100644
index 92bda6076524..000000000000
--- a/board/tqc/tqm834x/pci.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
- * per TQM834x design physical connections to external devices (PCI sockets)
- * are routed only to the PCI1 we do not account for the second one - this code
- * supports PCI1 module only. Should support for the PCI2 be required in the
- * future it needs a separate pci_controller structure (above) and handling -
- * please refer to other boards' implementation for dual PCI host controllers,
- * for example board/Marvell/db64360/pci.c, pci_init_board()
- *
- */
-void
-pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci1_regions };
- u32 reg32;
-
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT
- *
- * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
- * line actually used for clocking all external PCI devices in TQM83xx.
- * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
- * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
- * are known to hang the board; this issue is under investigation
- * (13 oct 05)
- */
- reg32 = OCCR_PCICOE1;
-#if 0
- /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
- reg32 = 0xff000000;
-#endif
- if (clk->spmr & SPMR_CKID) {
- /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
- * fields accordingly */
- reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
-
- reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
- | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
- | OCCR_PCICD6 | OCCR_PCICD7);
- }
-
- clk->occr = reg32;
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
-
- udelay(2000);
-
- mpc83xx_pci_init(1, reg);
-}
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
deleted file mode 100644
index 17b4662c167f..000000000000
--- a/board/tqc/tqm834x/tqm834x.c
+++ /dev/null
@@ -1,433 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <log.h>
-#include <mpc83xx.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <flash.h>
-#include <linux/delay.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define IOSYNC asm("eieio")
-#define ISYNC asm("isync")
-#define SYNC asm("sync")
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define DDR_MAX_SIZE_PER_CS 0x20000000
-
-#if defined(DDR_CASLAT_20)
-#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
-#define MODE_CASLAT DDR_MODE_CASLAT_20
-#else
-#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
-#define MODE_CASLAT DDR_MODE_CASLAT_25
-#endif
-
-#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
- CSCONFIG_COL_BIT_9)
-
-/* External definitions */
-ulong flash_get_size (ulong base, int banknum);
-
-/* Local functions */
-static int detect_num_flash_banks(void);
-static long int get_ddr_bank_size(short cs, long *base);
-static void set_cs_bounds(short cs, ulong base, ulong size);
-static void set_cs_config(short cs, long config);
-static void set_ddr_config(void);
-
-/* Local variable */
-static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-/**************************************************************************
- * Board initialzation after relocation to RAM. Used to detect the number
- * of Flash banks on TQM834x.
- */
-int board_early_init_r (void) {
- /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return 0;
-
- /* detect the number of Flash banks */
- return detect_num_flash_banks();
-}
-
-/**************************************************************************
- * DRAM initalization and size detection
- */
-int dram_init(void)
-{
- long bank_size;
- long size;
- int cs;
-
- /* during size detection, set up the max DDRLAW size */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE;
- im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
-
- /* set CS bounds to maximum size */
- for(cs = 0; cs < 4; ++cs) {
- set_cs_bounds(cs,
- CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS),
- DDR_MAX_SIZE_PER_CS);
-
- set_cs_config(cs, INITIAL_CS_CONFIG);
- }
-
- /* configure ddr controller */
- set_ddr_config();
-
- udelay(200);
-
- /* enable DDR controller */
- im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
- SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR1);
- SYNC;
-
- /* size detection */
- debug("\n");
- size = 0;
- for(cs = 0; cs < 4; ++cs) {
- debug("\nDetecting Bank%d\n", cs);
-
- bank_size = get_ddr_bank_size(cs,
- (long *)(CONFIG_SYS_SDRAM_BASE + size));
- size += bank_size;
-
- debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
-
- /* exit if less than one bank */
- if(size < DDR_MAX_SIZE_PER_CS) break;
- }
-
- gd->ram_size = size;
-
- return 0;
-}
-
-/**************************************************************************
- * checkboard()
- */
-int checkboard (void)
-{
- puts("Board: TQM834x\n");
-
-#ifdef CONFIG_PCI
- volatile immap_t * immr;
- u32 w, f;
-
- immr = (immap_t *)CONFIG_SYS_IMMR;
- if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
- printf("PCI: NOT in host mode..?!\n");
- return 0;
- }
-
- /* get bus width */
- w = 32;
- if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
- w = 64;
-
- /* get clock */
- f = gd->pci_clk;
-
- printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
-#else
- printf("PCI: disabled\n");
-#endif
- return 0;
-}
-
-
-/**************************************************************************
- *
- * Local functions
- *
- *************************************************************************/
-
-/**************************************************************************
- * Detect the number of flash banks (1 or 2). Store it in
- * a global variable tqm834x_num_flash_banks.
- * Bank detection code based on the Monitor code.
- */
-static int detect_num_flash_banks(void)
-{
- typedef unsigned long FLASH_PORT_WIDTH;
- typedef volatile unsigned long FLASH_PORT_WIDTHV;
- FPWV *bank1_base;
- FPWV *bank2_base;
- FPW bank1_read;
- FPW bank2_read;
- ulong bank1_size;
- ulong bank2_size;
- ulong total_size;
-
- cfi_flash_num_flash_banks = 2; /* assume two banks */
-
- /* Get bank 1 and 2 information */
- bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
- debug("Bank1 size: %lu\n", bank1_size);
- bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
- debug("Bank2 size: %lu\n", bank2_size);
- total_size = bank1_size + bank2_size;
-
- if (bank2_size > 0) {
- /* Seems like we've got bank 2, but maybe it's mirrored 1 */
-
- /* Set the base addresses */
- bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
- bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
-
- /* Put bank 2 into CFI command mode and read */
- bank2_base[0x55] = 0x00980098;
- IOSYNC;
- ISYNC;
- bank2_read = bank2_base[0x10];
-
- /* Read from bank 1 (it's in read mode) */
- bank1_read = bank1_base[0x10];
-
- /* Reset Flash */
- bank1_base[0] = 0x00F000F0;
- bank2_base[0] = 0x00F000F0;
-
- if (bank2_read == bank1_read) {
- /*
- * Looks like just one bank, but not sure yet. Let's
- * read from bank 2 in autosoelect mode.
- */
- bank2_base[0x0555] = 0x00AA00AA;
- bank2_base[0x02AA] = 0x00550055;
- bank2_base[0x0555] = 0x00900090;
- IOSYNC;
- ISYNC;
- bank2_read = bank2_base[0x10];
-
- /* Read from bank 1 (it's in read mode) */
- bank1_read = bank1_base[0x10];
-
- /* Reset Flash */
- bank1_base[0] = 0x00F000F0;
- bank2_base[0] = 0x00F000F0;
-
- if (bank2_read == bank1_read) {
- /*
- * In both CFI command and autoselect modes,
- * we got the some data reading from Flash.
- * There is only one mirrored bank.
- */
- cfi_flash_num_flash_banks = 1;
- total_size = bank1_size;
- }
- }
- }
-
- debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
-
- /* set OR0 and BR0 */
- set_lbc_or(0, OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 |
- OR_GPCM_TRLX | (-(total_size) & OR_GPCM_AM));
- set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
- (BR_MS_GPCM | BR_PS_32 | BR_V));
-
- return (0);
-}
-
-/*************************************************************************
- * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
- */
-static long int get_ddr_bank_size(short cs, long *base)
-{
- /* This array lists all valid DDR SDRAM configurations, with
- * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
- * The last entry has to to have size equal 0 and is igonred during
- * autodection. Bank sizes must be in increasing order of size
- */
- struct {
- long row;
- long col;
- long size;
- } conf[] = {
- {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
- {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
- {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
- {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
- {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
- {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
- {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
- {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
- {0, 0, 0}
- };
-
- int i;
- int detected;
- long size;
-
- detected = -1;
- for(i = 0; conf[i].size != 0; ++i) {
-
- /* set sdram bank configuration */
- set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
-
- debug("Getting RAM size...\n");
- size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
-
- if((size == conf[i].size) && (i == detected + 1))
- detected = i;
-
- debug("Trying %ld x %ld (%ld MiB)@addr %p, detected: %ld MiB\n",
- conf[i].row,
- conf[i].col,
- conf[i].size >> 20,
- base,
- size >> 20);
- }
-
- if(detected == -1){
- /* disable empty cs */
- debug("\nNo valid configurations for CS%d, disabling...\n", cs);
- set_cs_config(cs, 0);
- return 0;
- }
-
- debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
- conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
-
- /* configure cs ro detected params */
- set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
- conf[detected].col);
-
- set_cs_bounds(cs, (long)base, conf[detected].size);
-
- return(conf[detected].size);
-}
-
-/**************************************************************************
- * Sets DDR bank CS bounds.
- */
-static void set_cs_bounds(short cs, ulong base, ulong size)
-{
- debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
- if(size == 0){
- im->ddr.csbnds[cs].csbnds = 0x00000000;
- } else {
- im->ddr.csbnds[cs].csbnds =
- ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((base + size - 1) >> CSBNDS_EA_SHIFT) &
- CSBNDS_EA);
- }
- SYNC;
-}
-
-/**************************************************************************
- * Sets DDR banks CS configuration.
- * config == 0x00000000 disables the CS.
- */
-static void set_cs_config(short cs, long config)
-{
- debug("Setting config %08lx for cs %d\n", config, cs);
- im->ddr.cs_config[cs] = config;
- SYNC;
-}
-
-/**************************************************************************
- * Sets DDR clocks, timings and configuration.
- */
-static void set_ddr_config(void) {
- /* clock control */
- im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
- DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
- SYNC;
-
- /* timing configuration */
- im->ddr.timing_cfg_1 =
- (4 << TIMING_CFG1_PRETOACT_SHIFT) |
- (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
- (4 << TIMING_CFG1_ACTTORW_SHIFT) |
- (5 << TIMING_CFG1_REFREC_SHIFT) |
- (3 << TIMING_CFG1_WRREC_SHIFT) |
- (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
- (1 << TIMING_CFG1_WRTORD_SHIFT) |
- (TIMING_CFG1_CASLAT & TIMING_CASLAT);
-
- im->ddr.timing_cfg_2 =
- TIMING_CFG2_CPO_DEF |
- (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
- SYNC;
-
- /* don't enable DDR controller yet */
- im->ddr.sdram_cfg =
- SDRAM_CFG_SREN |
- SDRAM_CFG_SDRAM_TYPE_DDR1;
- SYNC;
-
- /* Set SDRAM mode */
- im->ddr.sdram_mode =
- ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
- SDRAM_MODE_ESD_SHIFT) |
- ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
- SDRAM_MODE_SD_SHIFT) |
- ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
- MODE_CASLAT);
- SYNC;
-
- /* Set fast SDRAM refresh rate */
- im->ddr.sdram_interval =
- (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
- (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
- SYNC;
-
- /* Workaround for DDR6 Erratum
- * see MPC8349E Device Errata Rev.8, 2/2006
- * This workaround influences the MPC internal "input enables"
- * dependent on CAS latency and MPC revision. According to errata
- * sheet the internal reserved registers for this workaround are
- * not available from revision 2.0 and up.
- */
-
- /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
- * (0x200)
- */
- if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
-
- /* There is a internal reserved register at IMMRBAR+0x2F00
- * which has to be written with a certain value defined by
- * errata sheet.
- */
- u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
-
-#if defined(DDR_CASLAT_20)
- *reserved_p = 0x201c0000;
-#else
- *reserved_p = 0x202c0000;
-#endif
- }
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif /* CONFIG_PCI */
-
- return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
deleted file mode 100644
index c29d8a8be1f3..000000000000
--- a/configs/TQM834x_defconfig
+++ /dev/null
@@ -1,166 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x80000000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66666000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_TQM834X=y
-CONFIG_SYS_IMMR=0xff400000
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM_LOWER"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="SDRAM_UPPER"
-CONFIG_BAT1_BASE=0x10000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="STACK_IN_DCACHE"
-CONFIG_BAT2_BASE=0x20000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="PCI_MEM_BASE"
-CONFIG_BAT3_BASE=0x90000000
-CONFIG_BAT3_LENGTH_256_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="PCI_MMIO"
-CONFIG_BAT4_BASE=0xA0000000
-CONFIG_BAT4_LENGTH_256_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT4_ICACHE_GUARDED=y
-CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT4_DCACHE_GUARDED=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="PCI_IO"
-CONFIG_BAT5_BASE=0xE2000000
-CONFIG_BAT5_LENGTH_16_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="IMMR"
-CONFIG_BAT6_BASE=0xFF400000
-CONFIG_BAT6_LENGTH_1_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_INHIBITED=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_INHIBITED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="FLASH"
-CONFIG_BAT7_BASE=0x80000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0x80000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_1_GBYTES=y
-CONFIG_LBLAW1=y
-# CONFIG_LBLAW1_ENABLE is not set
-CONFIG_LBLAW2=y
-# CONFIG_LBLAW2_ENABLE is not set
-CONFIG_LBLAW3=y
-# CONFIG_LBLAW3_ENABLE is not set
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0x80000000
-CONFIG_BR0_PORTSIZE_32BIT=y
-CONFIG_OR0_AM_1_GBYTES=y
-CONFIG_OR0_SCY_5=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_8=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=TQM834x-0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=TQM834x-0:256k(u-boot),256k(env),1m(kernel),2m(initrd),-(user);"
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0x80060000
-CONFIG_ENV_ADDR_REDUND=0x80080000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_EEPRO100=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
deleted file mode 100644
index aa70f01ddded..000000000000
--- a/include/configs/TQM834x.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-/*
- * TQM8349 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-/* board pre init: do not call, nothing to do */
-
-/* detect the number of flash banks */
-
-/*
- * DDR Setup
- */
- /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * FLASH on the Local Bus
- */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
-
-/*
- * FLASH bank number detection
- */
-
-/*
- * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
- * Flash banks has to be determined at runtime and stored in a gloabl variable
- * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
- * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
- * flash_info, and should be made sufficiently large to accomodate the number
- * of banks that might actually be detected. Since most (all?) Flash related
- * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
- * the board, it is defined as tqm834x_num_flash_banks.
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
-
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
-
-
-/* disable remaining mappings */
-#define CONFIG_SYS_BR1_PRELIM 0x00000000
-#define CONFIG_SYS_OR1_PRELIM 0x00000000
-
-#define CONFIG_SYS_BR2_PRELIM 0x00000000
-#define CONFIG_SYS_OR2_PRELIM 0x00000000
-
-#define CONFIG_SYS_BR3_PRELIM 0x00000000
-#define CONFIG_SYS_OR3_PRELIM 0x00000000
-
-/*
- * Monitor config
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#else
-# undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
- /* Reserve 384 kB = 3 sect. for Mon */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
- /* Reserve 512 kB for malloc */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-
-/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * TSEC
- */
-
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-/* PCI1 host bridge */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE \
- (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
- #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
- #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
-#endif
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-/* PCI */
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 400000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=tqm834x\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "flash_nfs_old=run nfsargs addip addcons;" \
- "bootm ${kernel_addr}\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "flash_self_old=run ramargs addip addcons;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
- "net_nfs_old=tftp 400000 ${bootfile};" \
- "run nfsargs addip addcons;bootm\0" \
- "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
- "tftp ${fdt_addr_r} ${fdt_file}; " \
- "run nfsargs addip addcons; " \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "bootfile=tqm834x/uImage\0" \
- "fdtfile=tqm834x/tqm834x.dtb\0" \
- "kernel_addr_r=400000\0" \
- "fdt_addr_r=600000\0" \
- "ramdisk_addr_r=800000\0" \
- "kernel_addr=800C0000\0" \
- "fdt_addr=800A0000\0" \
- "ramdisk_addr=80300000\0" \
- "u-boot=tqm834x/u-boot.bin\0" \
- "load=tftp 200000 ${u-boot}\0" \
- "update=protect off 80000000 +${filesize};" \
- "era 80000000 +${filesize};" \
- "cp.b 200000 80000000 ${filesize}\0" \
- "upd=run load update\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-/*
- * JFFS2 partitions
- */
-/* mtdparts command line support */
-
-/* default mtd partition table */
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 15/27] ppc: Remove MPC8541CDS board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (12 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 14/27] ppc: Remove TQM834x board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 16/27] ppc: Remove MPC8555CDS boards Tom Rini
` (12 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the only
MPC8541 target left, remove that architecture support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 18 +-
arch/powerpc/cpu/mpc85xx/cpu.c | 4 +-
arch/powerpc/cpu/mpc85xx/pci.c | 2 +-
arch/powerpc/cpu/mpc85xx/speed.c | 4 +-
arch/powerpc/include/asm/cpm_85xx.h | 2 +-
arch/powerpc/include/asm/fsl_lbc.h | 3 +-
arch/powerpc/include/asm/immap_85xx.h | 1 -
board/freescale/common/Makefile | 1 -
board/freescale/mpc8541cds/Kconfig | 12 -
board/freescale/mpc8541cds/MAINTAINERS | 7 -
board/freescale/mpc8541cds/Makefile | 10 -
board/freescale/mpc8541cds/ddr.c | 53 ---
board/freescale/mpc8541cds/law.c | 41 ---
board/freescale/mpc8541cds/mpc8541cds.c | 429 ------------------------
board/freescale/mpc8541cds/tlb.c | 95 ------
configs/MPC8541CDS_defconfig | 40 ---
configs/MPC8541CDS_legacy_defconfig | 41 ---
drivers/ddr/fsl/ctrl_regs.c | 2 +-
drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 2 +-
include/configs/MPC8541CDS.h | 384 ---------------------
20 files changed, 10 insertions(+), 1141 deletions(-)
delete mode 100644 board/freescale/mpc8541cds/Kconfig
delete mode 100644 board/freescale/mpc8541cds/MAINTAINERS
delete mode 100644 board/freescale/mpc8541cds/Makefile
delete mode 100644 board/freescale/mpc8541cds/ddr.c
delete mode 100644 board/freescale/mpc8541cds/law.c
delete mode 100644 board/freescale/mpc8541cds/mpc8541cds.c
delete mode 100644 board/freescale/mpc8541cds/tlb.c
delete mode 100644 configs/MPC8541CDS_defconfig
delete mode 100644 configs/MPC8541CDS_legacy_defconfig
delete mode 100644 include/configs/MPC8541CDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 22cfa4dc3499..0b1385695283 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -44,11 +44,6 @@ config TARGET_P5040DS
imply CMD_SATA
imply PANIC_HANG
-config TARGET_MPC8541CDS
- bool "Support MPC8541CDS"
- select ARCH_MPC8541
- select FSL_VIA
-
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
@@ -364,14 +359,6 @@ config ARCH_MPC8540
select FSL_LAW
select SYS_FSL_HAS_DDR1
-config ARCH_MPC8541
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
-
config ARCH_MPC8544
bool
select FSL_LAW
@@ -959,7 +946,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_C29X || \
ARCH_MPC8536 || \
ARCH_MPC8540 || \
- ARCH_MPC8541 || \
ARCH_MPC8544 || \
ARCH_MPC8548 || \
ARCH_MPC8555 || \
@@ -1193,7 +1179,6 @@ config SYS_FSL_NUM_LAWS
ARCH_MPC8548 || \
ARCH_MPC8568
default 8 if ARCH_MPC8540 || \
- ARCH_MPC8541 || \
ARCH_MPC8555 || \
ARCH_MPC8560
help
@@ -1267,7 +1252,7 @@ config SYS_FSL_IFC_CLK_DIV
config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
depends on FSL_ELBC || ARCH_MPC8540 || \
- ARCH_MPC8548 || ARCH_MPC8541 || \
+ ARCH_MPC8548 || \
ARCH_MPC8555 || ARCH_MPC8560 || \
ARCH_MPC8568
@@ -1286,7 +1271,6 @@ config FSL_VIA
source "board/emulation/qemu-ppce500/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
-source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index fc25bb28ad12..e8126c98f898 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -301,8 +301,8 @@ int checkcpu (void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
- defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8555) || \
+ defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index 9a6fc13b73f1..559730181ef1 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_register_hose(hose);
-#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
+#if defined(CONFIG_TARGET_MPC8555CDS)
/*
* This is a SW workaround for an apparent HW problem
* in the PCI controller on the MPC85555/41 CDS boards.
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 864c53ce2ecb..90c9fe1af51b 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -607,8 +607,8 @@ int get_clocks(void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
- defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560) || \
+ defined(CONFIG_ARCH_MPC8555)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index b46e20e5ce89..e6f1fab5fb95 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -77,7 +77,7 @@
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
+#if defined(CONFIG_ARCH_MPC8555)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#else /* MPC8540, MPC8560 */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index bf352d9a5617..ae176082760f 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -325,8 +325,7 @@ void lbc_sdram_init(void);
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
- defined(CONFIG_ARCH_MPC8560)
+ defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 59bc32fd172b..b6770c4cf4d3 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,7 +124,6 @@ typedef struct ccsr_i2c {
} ccsr_i2c_t;
#if defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8541) || \
defined(CONFIG_ARCH_MPC8548) || \
defined(CONFIG_ARCH_MPC8555)
/* DUART Registers */
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 114b7ba8f9f9..5d18567332fe 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -43,7 +43,6 @@ endif
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
-obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig
deleted file mode 100644
index 034eab25443d..000000000000
--- a/board/freescale/mpc8541cds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8541CDS
-
-config SYS_BOARD
- default "mpc8541cds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8541CDS"
-
-endif
diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS
deleted file mode 100644
index cf3b9cf5f723..000000000000
--- a/board/freescale/mpc8541cds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8541CDS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8541cds/
-F: include/configs/MPC8541CDS.h
-F: configs/MPC8541CDS_defconfig
-F: configs/MPC8541CDS_legacy_defconfig
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
deleted file mode 100644
index b2b721ac92d2..000000000000
--- a/board/freescale/mpc8541cds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += mpc8541cds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
deleted file mode 100644
index 05c56a85d246..000000000000
--- a/board/freescale/mpc8541cds/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 6;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
deleted file mode 100644
index 69f151b61513..000000000000
--- a/board/freescale/mpc8541cds/law.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
- * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
deleted file mode 100644
index 5b4fbd5e304e..000000000000
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ /dev/null
@@ -1,429 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <vsprintf.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-void local_bus_init(void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-int checkboard (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- char buf[32];
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
- uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
-
- uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
- printf("PCI1: %d bit, %s MHz, %s\n",
- (pci1_32) ? 32 : 64,
- strmhz(buf, pci1_speed),
- pci1_clk_sel ? "sync" : "async");
-
- if (pci_dual) {
- printf("PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf("PCI2: disabled\n");
- }
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
- uint temp_lbcdll;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66MHz, DLL bypass mode must be used.
- * If localbus freq is > 133MHz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
-
- } else {
- lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
- udelay(200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm("sync;isync;msync");
- }
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
- uint idx;
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint cpu_board_rev;
- uint lsdmr_common;
-
- puts("LBC SDRAM: ");
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
- "\n ");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("msync");
-
- /*
- * Determine which address lines to use baed on CPU board rev.
- */
- cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= LSDMR_BSMA1617;
- } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= LSDMR_BSMA1516;
- } else {
- /*
- * Assume something unable to identify itself is
- * really old, and likely has lines 16/17 mapped.
- */
- lsdmr_common |= LSDMR_BSMA1617;
- }
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CONFIG_PCI)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller hose[] = {
- { config_table: pci_mpc85xxcds_config_table,},
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
-};
-
-#endif /* CONFIG_PCI */
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(hose);
-#endif
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, struct bd_info *bd)
-{
- int node, tmp[2];
- const char *path;
-
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = hose[0].last_busno - hose[0].first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = hose[1].last_busno - hose[1].first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
- }
-}
-#endif
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
deleted file mode 100644
index d4ed51c54383..000000000000
--- a/board/freescale/mpc8541cds/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
- */
- SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
deleted file mode 100644
index cd2d19594e9d..000000000000
--- a/configs/MPC8541CDS_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8541CDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
deleted file mode 100644
index 32ed521faad6..000000000000
--- a/configs/MPC8541CDS_legacy_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8541CDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index c849ef3a4c7e..b80034478e11 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1866,7 +1866,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
unsigned int clk_adjust; /* Clock adjust */
unsigned int ss_en = 0; /* Source synchronous enable */
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
+#if defined(CONFIG_ARCH_MPC8555)
/* Per FSL Application Note: AN2805 */
ss_en = 1;
#endif
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 572f3703d51a..c642a5b1eec4 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -48,7 +48,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
+#if defined(CONFIG_ARCH_MPC8555)
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
#endif
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
deleted file mode 100644
index ea4da6a5fe41..000000000000
--- a/include/configs/MPC8541CDS.h
+++ /dev/null
@@ -1,384 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- */
-
-/*
- * mpc8541cds board configuration file
- *
- * Please refer to doc/README.mpc85xxcds for more info.
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_CPM2 1 /* has CPM2 */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/*
- * Make sure required options are set
- */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
-#endif
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * FLASH on the Local Bus
- * Two banks, 8M each, using the CFI driver.
- * Boot from BR0/OR0 bank at 0xff00_0000
- * Alternate BR1/OR1 bank at 0xff80_0000
- *
- * BR0, BR1:
- * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
- * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
- * Port Size = 16 bits = BRx[19:20] = 10
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
- *
- * OR0, OR1:
- * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
- * Reserved ORx[17:18] = 11, confusion here?
- * CSNT = ORx[20] = 1
- * ACS = half cycle delay = ORx[21:22] = 11
- * SCY = 6 = ORx[24:27] = 0110
- * TRLX = use relaxed timing = ORx[29] = 1
- * EAD = use external address latch delay = OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xff001001
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-/*
- * Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
- */
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7 \
- | LSDMR_BL8 \
- | LSDMR_WRC4 \
- | LSDMR_CL3 \
- | LSDMR_RFEN \
- )
-
-/*
- * The CADMUS registers are connected to CS3 on CDS.
- * The new memory map places CADMUS at 0xf8000000.
- *
- * For BR3, need:
- * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
- * port-size = 8-bits = BR[19:20] = 01
- * no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
- *
- * For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
- * disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
- * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
- */
-
-#define CONFIG_FSL_CADMUS
-
-#define CADMUS_BASE_ADDR 0xf8000000
-#define CONFIG_SYS_BR3_PRELIM 0xf8000801
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_CCID
-#define CONFIG_SYS_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
-#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
-
-#ifdef CONFIG_LEGACY
-#define BRIDGE_ID 17
-#define VIA_ID 2
-#else
-#define BRIDGE_ID 28
-#define VIA_ID 4
-#endif
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_MPC85XX_PCI2
-
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_IPADDR 192.168.1.253
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "your.uImage"
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 16/27] ppc: Remove MPC8555CDS boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (13 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 15/27] ppc: Remove MPC8541CDS board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT Tom Rini
` (11 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this is the only
ARCH_MPC8555 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 18 +-
arch/powerpc/cpu/mpc85xx/cpu.c | 3 +-
arch/powerpc/cpu/mpc85xx/pci.c | 23 --
arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
arch/powerpc/include/asm/cpm_85xx.h | 5 -
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/immap_85xx.h | 3 +-
board/freescale/common/Makefile | 1 -
board/freescale/mpc8555cds/Kconfig | 12 -
board/freescale/mpc8555cds/MAINTAINERS | 7 -
board/freescale/mpc8555cds/Makefile | 10 -
board/freescale/mpc8555cds/ddr.c | 53 ---
board/freescale/mpc8555cds/law.c | 41 ---
board/freescale/mpc8555cds/mpc8555cds.c | 430 ------------------------
board/freescale/mpc8555cds/tlb.c | 95 ------
configs/MPC8555CDS_defconfig | 40 ---
configs/MPC8555CDS_legacy_defconfig | 41 ---
drivers/ddr/fsl/ctrl_regs.c | 20 +-
drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 3 -
include/configs/MPC8555CDS.h | 380 ---------------------
20 files changed, 9 insertions(+), 1181 deletions(-)
delete mode 100644 board/freescale/mpc8555cds/Kconfig
delete mode 100644 board/freescale/mpc8555cds/MAINTAINERS
delete mode 100644 board/freescale/mpc8555cds/Makefile
delete mode 100644 board/freescale/mpc8555cds/ddr.c
delete mode 100644 board/freescale/mpc8555cds/law.c
delete mode 100644 board/freescale/mpc8555cds/mpc8555cds.c
delete mode 100644 board/freescale/mpc8555cds/tlb.c
delete mode 100644 configs/MPC8555CDS_defconfig
delete mode 100644 configs/MPC8555CDS_legacy_defconfig
delete mode 100644 include/configs/MPC8555CDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0b1385695283..891db4e37810 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -49,11 +49,6 @@ config TARGET_MPC8548CDS
select ARCH_MPC8548
select FSL_VIA
-config TARGET_MPC8555CDS
- bool "Support MPC8555CDS"
- select ARCH_MPC8555
- select FSL_VIA
-
config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
select ARCH_MPC8568
@@ -388,14 +383,6 @@ config ARCH_MPC8548
select SYS_PPC_E500_USE_DEBUG_TLB
imply CMD_REGINFO
-config ARCH_MPC8555
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
-
config ARCH_MPC8560
bool
select FSL_LAW
@@ -948,7 +935,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_MPC8540 || \
ARCH_MPC8544 || \
ARCH_MPC8548 || \
- ARCH_MPC8555 || \
ARCH_MPC8560 || \
ARCH_MPC8568 || \
ARCH_MPC8572 || \
@@ -1179,7 +1165,6 @@ config SYS_FSL_NUM_LAWS
ARCH_MPC8548 || \
ARCH_MPC8568
default 8 if ARCH_MPC8540 || \
- ARCH_MPC8555 || \
ARCH_MPC8560
help
Number of local access windows. This is fixed per SoC.
@@ -1253,7 +1238,7 @@ config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
depends on FSL_ELBC || ARCH_MPC8540 || \
ARCH_MPC8548 || \
- ARCH_MPC8555 || ARCH_MPC8560 || \
+ ARCH_MPC8560 || \
ARCH_MPC8568
default 2 if ARCH_P2041 || \
@@ -1272,7 +1257,6 @@ config FSL_VIA
source "board/emulation/qemu-ppce500/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
-source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index e8126c98f898..610a8ec43f5b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -301,8 +301,7 @@ int checkcpu (void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8555) || \
- defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index 559730181ef1..b7835c0fee54 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,29 +120,6 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_register_hose(hose);
-#if defined(CONFIG_TARGET_MPC8555CDS)
- /*
- * This is a SW workaround for an apparent HW problem
- * in the PCI controller on the MPC85555/41 CDS boards.
- * The first config cycle must be to a valid, known
- * device on the PCI bus in order to trick the PCI
- * controller state machine into a known valid state.
- * Without this, the first config cycle has the chance
- * of hanging the controller permanently, just leaving
- * it in a semi-working state, or leaving it working.
- *
- * Pick on the Tundra, Device 17, to get it right.
- */
- {
- u8 header_type;
-
- pci_hose_read_config_byte(hose,
- PCI_BDF(0,BRIDGE_ID,0),
- PCI_HEADER_TYPE,
- &header_type);
- }
-#endif
-
hose->last_busno = pci_hose_scan(hose);
#ifdef CONFIG_MPC85XX_PCI2
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 90c9fe1af51b..26067dd7132c 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -607,8 +607,7 @@ int get_clocks(void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560) || \
- defined(CONFIG_ARCH_MPC8555)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index e6f1fab5fb95..d42469c6e056 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -77,13 +77,8 @@
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
-#if defined(CONFIG_ARCH_MPC8555)
-#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
-#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
-#else /* MPC8540, MPC8560 */
#define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
-#endif
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index ae176082760f..3b26451928a0 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -325,7 +325,7 @@ void lbc_sdram_init(void);
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
+ defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index b6770c4cf4d3..1411b3f38b94 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,8 +124,7 @@ typedef struct ccsr_i2c {
} ccsr_i2c_t;
#if defined(CONFIG_ARCH_MPC8540) || \
- defined(CONFIG_ARCH_MPC8548) || \
- defined(CONFIG_ARCH_MPC8555)
+ defined(CONFIG_ARCH_MPC8548)
/* DUART Registers */
typedef struct ccsr_duart {
u8 res1[1280];
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 5d18567332fe..7862a791ac54 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -44,7 +44,6 @@ endif
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
-obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
diff --git a/board/freescale/mpc8555cds/Kconfig b/board/freescale/mpc8555cds/Kconfig
deleted file mode 100644
index 04bd572212a0..000000000000
--- a/board/freescale/mpc8555cds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8555CDS
-
-config SYS_BOARD
- default "mpc8555cds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8555CDS"
-
-endif
diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS
deleted file mode 100644
index 8f32febd9147..000000000000
--- a/board/freescale/mpc8555cds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8555CDS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8555cds/
-F: include/configs/MPC8555CDS.h
-F: configs/MPC8555CDS_defconfig
-F: configs/MPC8555CDS_legacy_defconfig
diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
deleted file mode 100644
index f121c2fa6b2a..000000000000
--- a/board/freescale/mpc8555cds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += mpc8555cds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
deleted file mode 100644
index 05c56a85d246..000000000000
--- a/board/freescale/mpc8555cds/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 6;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
deleted file mode 100644
index 69f151b61513..000000000000
--- a/board/freescale/mpc8555cds/law.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
- * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
- * 0xf000_0000 0xf7ff_ffff SDRAM 128M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
deleted file mode 100644
index 3bb8e769c80a..000000000000
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ /dev/null
@@ -1,430 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <vsprintf.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-void local_bus_init(void);
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-int checkboard (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- char buf[32];
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
- uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
-
- uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
- printf("PCI1: %d bit, %s MHz, %s\n",
- (pci1_32) ? 32 : 64,
- strmhz(buf, pci1_speed),
- pci1_clk_sel ? "sync" : "async");
-
- if (pci_dual) {
- printf("PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf("PCI2: disabled\n");
- }
-
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
- uint temp_lbcdll;
-
- /*
- * Errata LBC11.
- * Fix Local Bus clock glitch when DLL is enabled.
- *
- * If localbus freq is < 66MHz, DLL bypass mode must be used.
- * If localbus freq is > 133MHz, DLL can be safely enabled.
- * Between 66 and 133, the DLL is enabled with an override workaround.
- */
-
- get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & LCRR_CLKDIV;
- lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
-
- } else if (lbc_hz >= 133) {
- lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
-
- } else {
- lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
- udelay(200);
-
- /*
- * Sample LBC DLL ctrl reg, upshift it to set the
- * override bits.
- */
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
- asm("sync;isync;msync");
- }
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
- uint idx;
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint cpu_board_rev;
- uint lsdmr_common;
-
- puts("LBC SDRAM: ");
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
- "\n ");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("msync");
-
- /*
- * Determine which address lines to use baed on CPU board rev.
- */
- cpu_board_rev = get_cpu_board_revision();
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= LSDMR_BSMA1617;
- } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= LSDMR_BSMA1516;
- } else {
- /*
- * Assume something unable to identify itself is
- * really old, and likely has lines 16/17 mapped.
- */
- lsdmr_common |= LSDMR_BSMA1617;
- }
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#ifdef CONFIG_PCI
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-
-static struct pci_controller hose[] = {
- {
- config_table: pci_mpc85xxcds_config_table,
- },
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
-};
-
-#endif
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(hose);
-#endif
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, struct bd_info *bd)
-{
- int node, tmp[2];
- const char *path;
-
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = hose[0].last_busno - hose[0].first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
-#ifdef CONFIG_MPC85XX_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = hose[1].last_busno - hose[1].first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
- }
-}
-#endif
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
deleted file mode 100644
index 4a18f05af0d1..000000000000
--- a/board/freescale/mpc8555cds/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI1 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCI2 MEM First half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 4: 256M Non-cacheable, guarded
- * 0xb0000000 256M PCI2 MEM Second half
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 16M PCI1 IO
- * 0xe300_0000 16M PCI2 IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
- */
- SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
deleted file mode 100644
index e7a5ca00b980..000000000000
--- a/configs/MPC8555CDS_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8555CDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
deleted file mode 100644
index 5780138f85d7..000000000000
--- a/configs/MPC8555CDS_legacy_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8555CDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
-CONFIG_BOOTDELAY=10
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFC0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index b80034478e11..b5122d1a1c37 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1863,25 +1863,13 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
- unsigned int clk_adjust; /* Clock adjust */
- unsigned int ss_en = 0; /* Source synchronous enable */
-
-#if defined(CONFIG_ARCH_MPC8555)
- /* Per FSL Application Note: AN2805 */
- ss_en = 1;
-#endif
- if (fsl_ddr_get_version(0) >= 0x40701) {
+ if (fsl_ddr_get_version(0) >= 0x40701)
/* clk_adjust in 5-bits on T-series and LS-series */
- clk_adjust = (popts->clk_adjust & 0x1F) << 22;
- } else {
+ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22;
+ else
/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
- clk_adjust = (popts->clk_adjust & 0xF) << 23;
- }
+ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
- ddr->ddr_sdram_clk_cntl = (0
- | ((ss_en & 0x1) << 31)
- | clk_adjust
- );
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index c642a5b1eec4..9c2ddeaf932f 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -48,9 +48,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_ARCH_MPC8555)
- out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#endif
/*
* 200 painful micro-seconds must elapse between
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
deleted file mode 100644
index 79e309c95c13..000000000000
--- a/include/configs/MPC8555CDS.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2011 Freescale Semiconductor.
- */
-
-/*
- * mpc8555cds board configuration file
- *
- * Please refer to doc/README.mpc85xxcds for more info.
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_CPM2 1 /* has CPM2 */
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
-#endif
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * FLASH on the Local Bus
- * Two banks, 8M each, using the CFI driver.
- * Boot from BR0/OR0 bank at 0xff00_0000
- * Alternate BR1/OR1 bank at 0xff80_0000
- *
- * BR0, BR1:
- * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
- * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
- * Port Size = 16 bits = BRx[19:20] = 10
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
- *
- * OR0, OR1:
- * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
- * Reserved ORx[17:18] = 11, confusion here?
- * CSNT = ORx[20] = 1
- * ACS = half cycle delay = ORx[21:22] = 11
- * SCY = 6 = ORx[24:27] = 0110
- * TRLX = use relaxed timing = ORx[29] = 1
- * EAD = use external address latch delay = OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xff001001
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-/*
- * Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
- */
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7 \
- | LSDMR_BL8 \
- | LSDMR_WRC4 \
- | LSDMR_CL3 \
- | LSDMR_RFEN \
- )
-
-/*
- * The CADMUS registers are connected to CS3 on CDS.
- * The new memory map places CADMUS at 0xf8000000.
- *
- * For BR3, need:
- * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
- * port-size = 8-bits = BR[19:20] = 01
- * no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
- *
- * For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
- * disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
- * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
- */
-
-#define CONFIG_FSL_CADMUS
-
-#define CADMUS_BASE_ADDR 0xf8000000
-#define CONFIG_SYS_BR3_PRELIM 0xf8000801
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_CCID
-#define CONFIG_SYS_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
-#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#ifdef CONFIG_LEGACY
-#define BRIDGE_ID 17
-#define VIA_ID 2
-#else
-#define BRIDGE_ID 28
-#define VIA_ID 4
-#endif
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_MPC85XX_PCI2
-
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#endif
-
-#define CONFIG_IPADDR 192.168.1.253
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "your.uImage"
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (14 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 16/27] ppc: Remove MPC8555CDS boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 18/27] ppc: Remove MPC8568MDS board Tom Rini
` (10 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
the only ARCH_T1023 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 37 +---------
arch/powerpc/cpu/mpc85xx/Makefile | 2 -
arch/powerpc/cpu/mpc85xx/speed.c | 4 +-
arch/powerpc/include/asm/config_mpc85xx.h | 2 +-
arch/powerpc/include/asm/fsl_secure_boot.h | 1 -
arch/powerpc/include/asm/immap_85xx.h | 4 +-
board/freescale/t102xrdb/MAINTAINERS | 5 --
configs/T1023RDB_NAND_defconfig | 80 ----------------------
configs/T1023RDB_SDCARD_defconfig | 77 ---------------------
configs/T1023RDB_SPIFLASH_defconfig | 79 ---------------------
configs/T1023RDB_defconfig | 64 -----------------
configs/T1024RDB_SECURE_BOOT_defconfig | 70 -------------------
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 1 -
14 files changed, 6 insertions(+), 421 deletions(-)
delete mode 100644 configs/T1023RDB_NAND_defconfig
delete mode 100644 configs/T1023RDB_SDCARD_defconfig
delete mode 100644 configs/T1023RDB_SPIFLASH_defconfig
delete mode 100644 configs/T1023RDB_defconfig
delete mode 100644 configs/T1024RDB_SECURE_BOOT_defconfig
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 891db4e37810..0a2921ddb323 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -113,16 +113,6 @@ config TARGET_QEMU_PPCE500
select ARCH_QEMU_E500
select PHYS_64BIT
-config TARGET_T1023RDB
- bool "Support T1023RDB"
- select ARCH_T1023
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- select FSL_DDR_INTERACTIVE
- imply CMD_EEPROM
- imply PANIC_HANG
-
config TARGET_T1024RDB
bool "Support T1024RDB"
select ARCH_T1024
@@ -692,27 +682,6 @@ config ARCH_P5040
config ARCH_QEMU_E500
bool
-config ARCH_T1023
- bool
- select E500MC
- select FSL_LAW
- select SYS_FSL_DDR_VER_50
- select SYS_FSL_ERRATUM_A008378
- select SYS_FSL_ERRATUM_A008109
- select SYS_FSL_ERRATUM_A009663
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_DDR4
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS2
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_5
- select FSL_IFC
- imply CMD_EEPROM
- imply CMD_NAND
- imply CMD_REGINFO
-
config ARCH_T1024
bool
select E500MC
@@ -916,7 +885,6 @@ config MAX_CPUS
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020 || \
- ARCH_T1023 || \
ARCH_T1024
default 1
help
@@ -952,7 +920,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5040 || \
- ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
@@ -1144,8 +1111,7 @@ config SYS_FSL_NUM_LAWS
ARCH_T2080 || \
ARCH_T4160 || \
ARCH_T4240
- default 16 if ARCH_T1023 || \
- ARCH_T1024 || \
+ default 16 if ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
default 12 if ARCH_BSC9131 || \
@@ -1224,7 +1190,6 @@ config SYS_FSL_IFC_CLK_DIV
default 2 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_T1024 || \
- ARCH_T1023 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T4160 || \
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index b9d87ddb655e..4d9a07b5d9c3 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
-obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
@@ -83,7 +82,6 @@ obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
-obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 26067dd7132c..e6e3f17bb272 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -201,7 +201,7 @@ void get_sys_info(sys_info_t *sys_info)
defined(CONFIG_ARCH_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#elif defined(CONFIG_ARCH_T1024)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
@@ -211,7 +211,7 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#if defined(CONFIG_ARCH_T1024)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 20535487310f..a52b31ec3950 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -313,7 +313,7 @@
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#elif defined(CONFIG_ARCH_T1024)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 53bfb8f64af7..991d75312a34 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -28,7 +28,6 @@
defined(CONFIG_TARGET_T1042RDB) || \
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
- defined(CONFIG_ARCH_T1023) || \
defined(CONFIG_ARCH_T1024)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 1411b3f38b94..bb6a684d5b05 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1792,7 +1792,7 @@ typedef struct ccsr_gur {
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#elif defined(CONFIG_ARCH_T1024)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
@@ -2500,7 +2500,7 @@ typedef struct ccsr_gur {
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define MAX_SERDES 4
-#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#if defined(CONFIG_ARCH_T1024)
#define SRDS_MAX_LANES 4
#else
#define SRDS_MAX_LANES 8
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
index ebb17b81313b..914c5063df9f 100644
--- a/board/freescale/t102xrdb/MAINTAINERS
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -7,8 +7,3 @@ F: configs/T1024RDB_defconfig
F: configs/T1024RDB_NAND_defconfig
F: configs/T1024RDB_SDCARD_defconfig
F: configs/T1024RDB_SPIFLASH_defconfig
-F: configs/T1024RDB_SECURE_BOOT_defconfig
-F: configs/T1023RDB_defconfig
-F: configs/T1023RDB_NAND_defconfig
-F: configs/T1023RDB_SDCARD_defconfig
-F: configs/T1023RDB_SPIFLASH_defconfig
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
deleted file mode 100644
index 0dc1d29c8def..000000000000
--- a/configs/T1023RDB_NAND_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
deleted file mode 100644
index 6cf2d6ce409e..000000000000
--- a/configs/T1023RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
deleted file mode 100644
index d9b0cf0535e0..000000000000
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x40000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_SPI_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
deleted file mode 100644
index 5756db7c4ba3..000000000000
--- a/configs/T1023RDB_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index df639b2fa996..000000000000
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1024RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 382639044bff..0220dd2a5f2d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -732,7 +732,6 @@ config SYS_DPAA_QBMAN
ARCH_B4420 || \
ARCH_P1023 || \
ARCH_P2041 || \
- ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index b4ede61113fc..c988e4e9257f 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_P4080) += p4080.o
obj-$(CONFIG_ARCH_P5040) += p5040.o
obj-$(CONFIG_ARCH_T1040) += t1040.o
obj-$(CONFIG_ARCH_T1042) += t1040.o
-obj-$(CONFIG_ARCH_T1023) += t1024.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T4240) += t4240.o
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
2021-05-15 1:34 ` [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT Tom Rini
@ 2021-07-08 2:52 ` Tom Rini
2021-07-15 8:24 ` gianluca
0 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:52 UTC (permalink / raw)
To: u-boot; +Cc: Priyanka Jain
[-- Attachment #1: Type: text/plain, Size: 421 bytes --]
On Fri, May 14, 2021 at 09:34:22PM -0400, Tom Rini wrote:
> These boards have not been converted to CONFIG_DM_PCI by the deadline
> and is also missing conversion to CONFIG_DM. Remove them. As this is
> the only ARCH_T1023 platform left, remove that support as well.
>
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
2021-07-08 2:52 ` Tom Rini
@ 2021-07-15 8:24 ` gianluca
2021-07-15 21:06 ` Tom Rini
0 siblings, 1 reply; 71+ messages in thread
From: gianluca @ 2021-07-15 8:24 UTC (permalink / raw)
To: u-boot
Hello list!
I know this mail will be OT, but I am worried about what will happen to
a new project using the PowerPC T2080,e6500 64-bit PPC on this web site:
https://www.powerpc-notebook.org
I suspect the same architecture will be move outside the official Linux
release when the same device-model will not match the kernel. And this
will be a pity for all people who are believe on architectures and the
power of opensource other than x86 and arm processors.
So, this project will be a no-go or dead project before it will be launched.
Are my worries overkill?
I hope so.
On 7/8/21 4:52 AM, Tom Rini wrote:
> On Fri, May 14, 2021 at 09:34:22PM -0400, Tom Rini wrote:
>
>> These boards have not been converted to CONFIG_DM_PCI by the deadline
>> and is also missing conversion to CONFIG_DM. Remove them. As this is
>> the only ARCH_T1023 platform left, remove that support as well.
>>
>> Cc: Priyanka Jain <priyanka.jain@nxp.com>
>> Signed-off-by: Tom Rini <trini@konsulko.com>
>
> Applied to u-boot/master, thanks!
>
--
Eurek s.r.l. |
Electronic Engineering | http://www.eurek.it
via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120
p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
2021-07-15 8:24 ` gianluca
@ 2021-07-15 21:06 ` Tom Rini
2021-07-19 6:19 ` gianluca
0 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-07-15 21:06 UTC (permalink / raw)
To: gianluca; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 895 bytes --]
On Thu, Jul 15, 2021 at 10:24:09AM +0200, gianluca wrote:
> Hello list!
> I know this mail will be OT, but I am worried about what will happen to a
> new project using the PowerPC T2080,e6500 64-bit PPC on this web site:
>
> https://www.powerpc-notebook.org
>
> I suspect the same architecture will be move outside the official Linux
> release when the same device-model will not match the kernel. And this will
> be a pity for all people who are believe on architectures and the power of
> opensource other than x86 and arm processors.
>
> So, this project will be a no-go or dead project before it will be launched.
>
> Are my worries overkill?
>
> I hope so.
The platform can come back if someone is going to be actively
maintaining the support. No one had been doing that, so I'm not sure
what hidden breakage existed underneath the technical debt.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
2021-07-15 21:06 ` Tom Rini
@ 2021-07-19 6:19 ` gianluca
0 siblings, 0 replies; 71+ messages in thread
From: gianluca @ 2021-07-19 6:19 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On 7/15/21 11:06 PM, Tom Rini wrote:
> On Thu, Jul 15, 2021 at 10:24:09AM +0200, gianluca wrote:
>
>> Hello list!
>> I know this mail will be OT, but I am worried about what will happen to a
>> new project using the PowerPC T2080,e6500 64-bit PPC on this web site:
>>
>> https://www.powerpc-notebook.org
>>
>> I suspect the same architecture will be move outside the official Linux
>> release when the same device-model will not match the kernel. And this will
>> be a pity for all people who are believe on architectures and the power of
>> opensource other than x86 and arm processors.
>>
>> So, this project will be a no-go or dead project before it will be launched.
>>
>> Are my worries overkill?
>>
>> I hope so.
>
> The platform can come back if someone is going to be actively
> maintaining the support. No one had been doing that, so I'm not sure
> what hidden breakage existed underneath the technical debt.
>
Thanks a lot Tom. I will report this to the open progress ppc platform
group.
I think they will do whatever it takes to maintain this platform as soon
as possible.
Regards,
--
Eurek s.r.l. |
Electronic Engineering | http://www.eurek.it
via Celletta 8/B, 40026 Imola, Italy | Phone: +39-(0)542-609120
p.iva 00690621206 - c.f. 04020030377 | Fax: +39-(0)542-609212
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 18/27] ppc: Remove MPC8568MDS board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (15 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 17/27] ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:52 ` Tom Rini
2021-05-15 1:34 ` [PATCH 19/27] ppc: Remove kmcoge4 board Tom Rini
` (9 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_MPC8568 platform, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 21 +-
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c | 58 ----
arch/powerpc/include/asm/config_mpc85xx.h | 10 -
arch/powerpc/include/asm/immap_85xx.h | 6 +-
board/freescale/mpc8568mds/Kconfig | 12 -
board/freescale/mpc8568mds/MAINTAINERS | 6 -
board/freescale/mpc8568mds/Makefile | 11 -
board/freescale/mpc8568mds/bcsr.c | 61 ----
board/freescale/mpc8568mds/bcsr.h | 92 -----
board/freescale/mpc8568mds/ddr.c | 53 ---
board/freescale/mpc8568mds/law.c | 40 ---
board/freescale/mpc8568mds/mpc8568mds.c | 359 -------------------
board/freescale/mpc8568mds/tlb.c | 83 -----
configs/MPC8568MDS_defconfig | 42 ---
include/configs/MPC8568MDS.h | 400 ----------------------
16 files changed, 3 insertions(+), 1252 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
delete mode 100644 board/freescale/mpc8568mds/Kconfig
delete mode 100644 board/freescale/mpc8568mds/MAINTAINERS
delete mode 100644 board/freescale/mpc8568mds/Makefile
delete mode 100644 board/freescale/mpc8568mds/bcsr.c
delete mode 100644 board/freescale/mpc8568mds/bcsr.h
delete mode 100644 board/freescale/mpc8568mds/ddr.c
delete mode 100644 board/freescale/mpc8568mds/law.c
delete mode 100644 board/freescale/mpc8568mds/mpc8568mds.c
delete mode 100644 board/freescale/mpc8568mds/tlb.c
delete mode 100644 configs/MPC8568MDS_defconfig
delete mode 100644 include/configs/MPC8568MDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0a2921ddb323..cd7aa953567b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -49,10 +49,6 @@ config TARGET_MPC8548CDS
select ARCH_MPC8548
select FSL_VIA
-config TARGET_MPC8568MDS
- bool "Support MPC8568MDS"
- select ARCH_MPC8568
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
@@ -378,15 +374,6 @@ config ARCH_MPC8560
select FSL_LAW
select SYS_FSL_HAS_DDR1
-config ARCH_MPC8568
- bool
- select FSL_LAW
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR2
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
-
config ARCH_MPC8572
bool
select FSL_LAW
@@ -904,7 +891,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_MPC8544 || \
ARCH_MPC8548 || \
ARCH_MPC8560 || \
- ARCH_MPC8568 || \
ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
@@ -1128,8 +1114,7 @@ config SYS_FSL_NUM_LAWS
ARCH_P1025 || \
ARCH_P2020
default 10 if ARCH_MPC8544 || \
- ARCH_MPC8548 || \
- ARCH_MPC8568
+ ARCH_MPC8548
default 8 if ARCH_MPC8540 || \
ARCH_MPC8560
help
@@ -1203,8 +1188,7 @@ config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
depends on FSL_ELBC || ARCH_MPC8540 || \
ARCH_MPC8548 || \
- ARCH_MPC8560 || \
- ARCH_MPC8568
+ ARCH_MPC8560
default 2 if ARCH_P2041 || \
ARCH_P3041 || \
@@ -1222,7 +1206,6 @@ config FSL_VIA
source "board/emulation/qemu-ppce500/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
-source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 4d9a07b5d9c3..8cd4b44ec5f9 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
-obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
deleted file mode 100644
index 81b66c3fa6a2..000000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 8
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index a52b31ec3950..33a3b3a13db7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -28,16 +28,6 @@
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_ARCH_MPC8568)
-#define QE_MURAM_SIZE 0x10000UL
-#define MAX_QE_RISC 2
-#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_RMU
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index bb6a684d5b05..900b8f43c82e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2457,11 +2457,7 @@ typedef struct ccsr_gur {
u32 svr; /* System version */
u8 res10[8];
u32 rstcr; /* Reset control */
-#if defined(CONFIG_ARCH_MPC8568)
- u8 res11a[76];
- par_io_t qe_par_io[7];
- u8 res11b[1600];
-#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig
deleted file mode 100644
index 4e178c503968..000000000000
--- a/board/freescale/mpc8568mds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8568MDS
-
-config SYS_BOARD
- default "mpc8568mds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8568MDS"
-
-endif
diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS
deleted file mode 100644
index f4747866d2bd..000000000000
--- a/board/freescale/mpc8568mds/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8568MDS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8568mds/
-F: include/configs/MPC8568MDS.h
-F: configs/MPC8568MDS_defconfig
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
deleted file mode 100644
index 1e9095bdddd6..000000000000
--- a/board/freescale/mpc8568mds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004-2007 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += mpc8568mds.o
-obj-y += bcsr.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
deleted file mode 100644
index b1e638af5aec..000000000000
--- a/board/freescale/mpc8568mds/bcsr.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007 Freescale Semiconductor.
- */
-
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-
-#include "bcsr.h"
-
-void enable_8568mds_duart(void)
-{
- volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
- volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
- volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
- *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
- *devices = 0; /* Enable all peripheral devices */
- bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
-}
-
-void enable_8568mds_flash_write(void)
-{
- volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
- bcsr[9] |= 0x01;
-}
-
-void disable_8568mds_flash_write(void)
-{
- volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
- bcsr[9] &= ~(0x01);
-}
-
-void enable_8568mds_qe_mdio(void)
-{
- u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
- bcsr[7] |= 0x01;
-}
-
-#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
-void reset_8568mds_uccs(void)
-{
- volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
-
- /* Turn off UCC1 & UCC2 */
- out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
- out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
-
- /* Mode is RGMII, all bits clear */
- out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
- BCSR_UCC2_MODE_MSK));
-
- /* Turn UCC1 & UCC2 on */
- out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
- out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
-}
-#endif
diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
deleted file mode 100644
index a8e13a2a5577..000000000000
--- a/board/freescale/mpc8568mds/bcsr.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007 Freescale Semiconductor.
- */
-
-#ifndef __BCSR_H_
-#define __BCSR_H_
-
-#include <common.h>
-
-/* BCSR Bit definitions
- * BCSR 0 *
- 0:3 ccb sys pll
- 4:6 cfg core pll
- 7 cfg boot seq
-
- * BCSR 1 *
- 0:2 cfg rom lock
- 3:5 cfg host agent
- 6 PCI IO
- 7 cfg RIO size
-
- * BCSR 2 *
- 0:4 QE PLL
- 5 QE clock
- 6 cfg PCI arbiter
-
- * BCSR 3 *
- 0 TSEC1 reduce
- 1 TSEC2 reduce
- 2:3 TSEC1 protocol
- 4:5 TSEC2 protocol
- 6 PHY1 slave
- 7 PHY2 slave
-
- * BCSR 4 *
- 4 clock enable
- 5 boot EPROM
- 6 GETH transactive reset
- 7 BRD write potect
-
- * BCSR 5 *
- 1:3 Leds 1-3
- 4 UPC1 enable
- 5 UPC2 enable
- 6 UPC2 pos
- 7 RS232 enable
-
- * BCSR 6 *
- 0 CFG ver 0
- 1 CFG ver 1
- 6 Register config led
- 7 Power on reset
-
- * BCSR 7 *
- 2 board host mode indication
- 5 enable TSEC1 PHY
- 6 enable TSEC2 PHY
-
- * BCSR 8 *
- 0 UCC GETH1 enable
- 1 UCC GMII enable
- 3 UCC TBI enable
- 5 UCC MII enable
- 7 Real time clock reset
-
- * BCSR 9 *
- 0 UCC2 GETH enable
- 1 UCC2 GMII enable
- 3 UCC2 TBI enable
- 5 UCC2 MII enable
- 6 Ready only - indicate flash ready after burning
- 7 Flash write protect
-*/
-
-#define BCSR_UCC1_GETH_EN (0x1 << 7)
-#define BCSR_UCC2_GETH_EN (0x1 << 7)
-#define BCSR_UCC1_MODE_MSK (0x3 << 4)
-#define BCSR_UCC2_MODE_MSK (0x3 << 0)
-
-/*BCSR Utils functions*/
-
-void enable_8568mds_duart(void);
-void enable_8568mds_flash_write(void);
-void disable_8568mds_flash_write(void);
-void enable_8568mds_qe_mdio(void);
-
-#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
-void reset_8568mds_uccs(void);
-#endif
-
-#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
deleted file mode 100644
index 58a979dbc76c..000000000000
--- a/board/freescale/mpc8568mds/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 6;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
deleted file mode 100644
index c04c36b5d82c..000000000000
--- a/board/freescale/mpc8568mds/law.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0) 0x0000_0000 0x7fff_ffff DDR 2G
- *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
- *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
- *-) 0xe000_0000 0xe00f_ffff CCSR 1M
- *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
- *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
- *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
- *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
- *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
- *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
- *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
- *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
- *
- *Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- */
-
-struct law_entry law_table[] = {
- /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
deleted file mode 100644
index 7b379464cd59..000000000000
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ /dev/null
@@ -1,359 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <flash.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <ioports.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-#include "bcsr.h"
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* GETH1 */
- {4, 10, 1, 0, 2}, /* TxD0 */
- {4, 9, 1, 0, 2}, /* TxD1 */
- {4, 8, 1, 0, 2}, /* TxD2 */
- {4, 7, 1, 0, 2}, /* TxD3 */
- {4, 23, 1, 0, 2}, /* TxD4 */
- {4, 22, 1, 0, 2}, /* TxD5 */
- {4, 21, 1, 0, 2}, /* TxD6 */
- {4, 20, 1, 0, 2}, /* TxD7 */
- {4, 15, 2, 0, 2}, /* RxD0 */
- {4, 14, 2, 0, 2}, /* RxD1 */
- {4, 13, 2, 0, 2}, /* RxD2 */
- {4, 12, 2, 0, 2}, /* RxD3 */
- {4, 29, 2, 0, 2}, /* RxD4 */
- {4, 28, 2, 0, 2}, /* RxD5 */
- {4, 27, 2, 0, 2}, /* RxD6 */
- {4, 26, 2, 0, 2}, /* RxD7 */
- {4, 11, 1, 0, 2}, /* TX_EN */
- {4, 24, 1, 0, 2}, /* TX_ER */
- {4, 16, 2, 0, 2}, /* RX_DV */
- {4, 30, 2, 0, 2}, /* RX_ER */
- {4, 17, 2, 0, 2}, /* RX_CLK */
- {4, 19, 1, 0, 2}, /* GTX_CLK */
- {1, 31, 2, 0, 3}, /* GTX125 */
-
- /* GETH2 */
- {5, 10, 1, 0, 2}, /* TxD0 */
- {5, 9, 1, 0, 2}, /* TxD1 */
- {5, 8, 1, 0, 2}, /* TxD2 */
- {5, 7, 1, 0, 2}, /* TxD3 */
- {5, 23, 1, 0, 2}, /* TxD4 */
- {5, 22, 1, 0, 2}, /* TxD5 */
- {5, 21, 1, 0, 2}, /* TxD6 */
- {5, 20, 1, 0, 2}, /* TxD7 */
- {5, 15, 2, 0, 2}, /* RxD0 */
- {5, 14, 2, 0, 2}, /* RxD1 */
- {5, 13, 2, 0, 2}, /* RxD2 */
- {5, 12, 2, 0, 2}, /* RxD3 */
- {5, 29, 2, 0, 2}, /* RxD4 */
- {5, 28, 2, 0, 2}, /* RxD5 */
- {5, 27, 2, 0, 3}, /* RxD6 */
- {5, 26, 2, 0, 2}, /* RxD7 */
- {5, 11, 1, 0, 2}, /* TX_EN */
- {5, 24, 1, 0, 2}, /* TX_ER */
- {5, 16, 2, 0, 2}, /* RX_DV */
- {5, 30, 2, 0, 2}, /* RX_ER */
- {5, 17, 2, 0, 2}, /* RX_CLK */
- {5, 19, 1, 0, 2}, /* GTX_CLK */
- {1, 31, 2, 0, 3}, /* GTX125 */
- {4, 6, 3, 0, 2}, /* MDIO */
- {4, 5, 1, 0, 2}, /* MDC */
-
- /* UART1 */
- {2, 0, 1, 0, 2}, /* UART_SOUT1 */
- {2, 1, 1, 0, 2}, /* UART_RTS1 */
- {2, 2, 2, 0, 2}, /* UART_CTS1 */
- {2, 3, 2, 0, 2}, /* UART_SIN1 */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-void local_bus_init(void);
-
-int board_early_init_f (void)
-{
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- enable_8568mds_duart();
- enable_8568mds_flash_write();
-#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
- reset_8568mds_uccs();
-#endif
-#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
- enable_8568mds_qe_mdio();
-#endif
-
-#ifdef CONFIG_SYS_I2C2_OFFSET
- /* Enable I2C2_SCL and I2C2_SDA */
- volatile struct par_io *port_c;
- port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
- port_c->cpdir2 |= 0x0f000000;
- port_c->cppar2 &= ~0x0f000000;
- port_c->cppar2 |= 0x0a000000;
-#endif
-
- return 0;
-}
-
-int checkboard (void)
-{
- printf ("Board: 8568 MDS\n");
-
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-
- gur->lbiuiplldcr1 = 0x00078080;
- if (clkdiv == 16) {
- gur->lbiuiplldcr0 = 0x7c0f1bf0;
- } else if (clkdiv == 8) {
- gur->lbiuiplldcr0 = 0x6c0f1bf0;
- } else if (clkdiv == 4) {
- gur->lbiuiplldcr0 = 0x5c0f1bf0;
- }
-
- lbc->lcrr |= 0x00030000;
-
- asm("sync;isync;msync");
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
- uint idx;
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint lsdmr_common;
-
- puts("LBC SDRAM: ");
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
- "\n ");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- asm("msync");
-
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("msync");
-
- /*
- * MPC8568 uses "new" 15-16 style addressing.
- */
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= LSDMR_BSMA1516;
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CONFIG_PCI)
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8568mds_config_table[] = {
- {
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- pci_cfgfunc_config_device,
- {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
- },
- {}
-};
-#endif
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-/*
- * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
- */
-void
-pib_init(void)
-{
- u8 val8, orig_i2c_bus;
- /*
- * Assign PIB PMC2/3 to PCI bus
- */
-
- /*switch temporarily to I2C bus #2 */
- orig_i2c_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- val8 = 0x00;
- i2c_write(0x23, 0x6, 1, &val8, 1);
- i2c_write(0x23, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x23, 0x2, 1, &val8, 1);
- i2c_write(0x23, 0x3, 1, &val8, 1);
-
- val8 = 0x00;
- i2c_write(0x26, 0x6, 1, &val8, 1);
- val8 = 0x34;
- i2c_write(0x26, 0x7, 1, &val8, 1);
- val8 = 0xf9;
- i2c_write(0x26, 0x2, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0x00;
- i2c_write(0x27, 0x6, 1, &val8, 1);
- i2c_write(0x27, 0x7, 1, &val8, 1);
- val8 = 0xff;
- i2c_write(0x27, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x27, 0x3, 1, &val8, 1);
-
- asm("eieio");
- i2c_set_bus_num(orig_i2c_bus);
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- int first_free_busno = 0;
-#ifdef CONFIG_PCI1
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr, io_sel;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug(" %s: devdisr=%x, io_sel=%x\n", __func__, devdisr, io_sel);
-
- pci_speed = 66666000;
- pci_32 = 1;
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- (pci_speed == 33333000) ? "33" :
- (pci_speed == 66666000) ? "66" : "unknown",
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
-#ifndef CONFIG_PCI_PNP
- pci1_hose.config_table = pci_mpc8568mds_config_table;
-#endif
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
- } else {
- printf("PCI: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
- fsl_pcie_init_board(first_free_busno);
-}
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
deleted file mode 100644
index fea1606a1d3f..000000000000
--- a/board/freescale/mpc8568mds/tlb.c
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 Initializations */
- /*
- * TLBe 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH (upper half)
- * Out of reset this entry is only 4K.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * TLBe 1: 16M Non-cacheable, guarded
- * 0xfe000000 16M FLASH (lower half)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /*
- * TLBe 2: 1G Non-cacheable, guarded
- * 0x80000000 512M PCI1 MEM
- * 0xa0000000 512M PCIe MEM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1G, 1),
-
- /*
- * TLBe 3: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 8M PCI1 IO
- * 0xe280_0000 8M PCIe IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLBe 4: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLBe 5: 256K Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
deleted file mode 100644
index 106e1a274673..000000000000
--- a/configs/MPC8568MDS_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8568MDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF60000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
deleted file mode 100644
index 2c43981a1cc7..000000000000
--- a/include/configs/MPC8568MDS.h
+++ /dev/null
@@ -1,400 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
- */
-
-/*
- * mpc8568mds board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCI1 1 /* PCI controller */
-#define CONFIG_PCIE1 1 /* PCIE controller */
-#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif /*Replace a call to get_clock_freq (after it is implemented)*/
-#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * FLASH on the Local Bus
- * Two banks, 8M each, using the CFI driver.
- * Boot from BR0/OR0 bank at 0xff00_0000
- * Alternate BR1/OR1 bank at 0xff80_0000
- *
- * BR0, BR1:
- * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
- * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
- * Port Size = 16 bits = BRx[19:20] = 10
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
- *
- * OR0, OR1:
- * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
- * Reserved ORx[17:18] = 11, confusion here?
- * CSNT = ORx[20] = 1
- * ACS = half cycle delay = ORx[21:22] = 11
- * SCY = 6 = ORx[24:27] = 0110
- * TRLX = use relaxed timing = ORx[29] = 1
- * EAD = use external address latch delay = OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
- */
-#define CONFIG_SYS_BCSR_BASE 0xf8000000
-
-#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
-
-/*Chip select 0 - Flash*/
-#define CONFIG_SYS_BR0_PRELIM 0xfe001001
-#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
-
-/*Chip slelect 1 - BCSR*/
-#define CONFIG_SYS_BR1_PRELIM 0xf8000801
-#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
-
-/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/*
- * SDRAM on the LocalBus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*Chip select 2 - SDRAM*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-/*
- * Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
- */
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7 \
- | LSDMR_BL8 \
- | LSDMR_WRC4 \
- | LSDMR_CL3 \
- | LSDMR_RFEN \
- )
-
-/*
- * The bcsr registers are connected to CS3 on MDS.
- * The new memory map places bcsr at 0xf8000000.
- *
- * For BR3, need:
- * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
- * port-size = 8-bits = BR[19:20] = 01
- * no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
- *
- * For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
- * disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
- * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
- */
-#define CONFIG_SYS_BCSR (0xf8000000)
-
-/*Chip slelect 4 - PIB*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8008801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
-
-/*Chip select 5 - PIB*/
-#define CONFIG_SYS_BR5_PRELIM 0xf8010801
-#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-
-/*
- * General PCI
- * Memory Addresses are mapped 1-1. I/O is mapped from 0
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
-
-#define CONFIG_SYS_PCIE1_NAME "Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-#ifdef CONFIG_QE
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#ifndef CONFIG_TSEC_ENET
-#define CONFIG_ETHPRIME "UEC0"
-#endif
-#define CONFIG_PHY_MODE_NEED_CHANGE
-#define CONFIG_eTSEC_MDIO_BUS
-
-#ifdef CONFIG_eTSEC_MDIO_BUS
-#define CONFIG_MIIM_ADDRESS 0xE0024520
-#endif
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 7
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#endif
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 1
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#endif
-#endif /* CONFIG_QE */
-
-#if defined(CONFIG_PCI)
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-
-#define TSEC1_PHY_ADDR 2
-#define TSEC2_PHY_ADDR 3
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME "eTSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR 192.168.1.253
-
-#define CONFIG_HOSTNAME "unknown"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "your.uImage"
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs\0" \
-
-#define CONFIG_NFSBOOTCOMMAND \
- "run nfsargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "run ramargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 19/27] ppc: Remove kmcoge4 board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (16 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 18/27] ppc: Remove MPC8568MDS board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:53 ` Tom Rini
2021-05-15 1:34 ` [PATCH 20/27] ppc: Remove xpedite boards Tom Rini
` (8 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
board/keymile/Kconfig | 1 -
board/keymile/kmp204x/Kconfig | 20 --
board/keymile/kmp204x/MAINTAINERS | 6 -
board/keymile/kmp204x/Makefile | 10 -
board/keymile/kmp204x/ddr.c | 70 -----
board/keymile/kmp204x/eth.c | 71 -----
board/keymile/kmp204x/kmp204x.c | 265 ----------------
board/keymile/kmp204x/kmp204x.h | 8 -
board/keymile/kmp204x/law.c | 39 ---
board/keymile/kmp204x/pbi.cfg | 74 -----
board/keymile/kmp204x/pci.c | 125 --------
board/keymile/kmp204x/rcw_kmp204x.cfg | 11 -
board/keymile/kmp204x/tlb.c | 109 -------
configs/kmcoge4_defconfig | 72 -----
include/configs/kmp204x.h | 416 --------------------------
15 files changed, 1297 deletions(-)
delete mode 100644 board/keymile/kmp204x/Kconfig
delete mode 100644 board/keymile/kmp204x/MAINTAINERS
delete mode 100644 board/keymile/kmp204x/Makefile
delete mode 100644 board/keymile/kmp204x/ddr.c
delete mode 100644 board/keymile/kmp204x/eth.c
delete mode 100644 board/keymile/kmp204x/kmp204x.c
delete mode 100644 board/keymile/kmp204x/kmp204x.h
delete mode 100644 board/keymile/kmp204x/law.c
delete mode 100644 board/keymile/kmp204x/pbi.cfg
delete mode 100644 board/keymile/kmp204x/pci.c
delete mode 100644 board/keymile/kmp204x/rcw_kmp204x.cfg
delete mode 100644 board/keymile/kmp204x/tlb.c
delete mode 100644 configs/kmcoge4_defconfig
delete mode 100644 include/configs/kmp204x.h
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 86a667067de9..b76ad485f565 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -125,7 +125,6 @@ config SYS_IVM_EEPROM_PAGE_LEN
source "board/keymile/km83xx/Kconfig"
source "board/keymile/kmcent2/Kconfig"
-source "board/keymile/kmp204x/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/keymile/pg-wcom-ls102xa/Kconfig"
diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig
deleted file mode 100644
index f74d4295c7ad..000000000000
--- a/board/keymile/kmp204x/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-if TARGET_KMP204X
-
-config SYS_BOARD
- default "kmp204x"
-
-config SYS_VENDOR
- default "keymile"
-
-config SYS_CONFIG_NAME
- default "kmp204x"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select ARCH_P2041
- select FSL_DDR_INTERACTIVE
- select PHYS_64BIT
- imply CMD_CRAMFS
- imply FS_CRAMFS
-
-endif
diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS
deleted file mode 100644
index 8b9afffdc721..000000000000
--- a/board/keymile/kmp204x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KMP204X BOARD
-M: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
-S: Maintained
-F: board/keymile/kmp204x/
-F: include/configs/kmp204x.h
-F: configs/kmcoge4_defconfig
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
deleted file mode 100644
index 5523ee99aae8..000000000000
--- a/board/keymile/kmp204x/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001-2007
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-
-obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o ../common/common.o\
- ../common/ivm.o ../common/qrio.o
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
deleted file mode 100644
index 77a00c55c951..000000000000
--- a/board/keymile/kmp204x/ddr.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
-
- /* automatic calibration for nb of cycles between read and DQS pre */
- popts->cpo_override = 0xFF;
-
- /* 1/2 clk delay between wr command and data strobe */
- popts->write_data_delay = 4;
- /* clk lauched 1/2 applied cylcle after address command */
- popts->clk_adjust = 4;
- /* 1T timing: command/address held for only 1 cycle */
- popts->twot_en = 0;
-
- /* we have only one module, half str should be OK */
- popts->half_strength_driver_enable = 1;
-
- /* wrlvl values overridden as recommended by ddr init func */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
- popts->wrlvl_start = 0x6;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size = 0;
-
- puts("Initializing with SPD\n");
-
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c
deleted file mode 100644
index 29c5b339ae8c..000000000000
--- a/board/keymile/kmp204x/eth.c
+++ /dev/null
@@ -1,71 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <phy.h>
-
-int board_eth_init(struct bd_info *bis)
-{
- int ret = 0;
-#ifdef CONFIG_FMAN_ENET
- struct fsl_pq_mdio_info dtsec_mdio_info;
-
- printf("Initializing Fman\n");
-
- dtsec_mdio_info.regs =
- (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the real 1G MDIO bus */
- fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
- /* DTESC1/2 don't have a PHY, they are temporarily disabled
- * so that u-boot doesn't try to unsuccessfuly enable them */
- fm_disable_port(FM1_DTSEC1);
- fm_disable_port(FM1_DTSEC2);
-
- /*
- * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
- * This is the debug interface, the only one used in u-boot
- */
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
- fm_info_set_mdio(FM1_DTSEC5,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
-
- ret = cpu_eth_init(bis);
-
- /* reenable DTSEC1/2 for later (kernel) */
- fm_enable_port(FM1_DTSEC1);
- fm_enable_port(FM1_DTSEC2);
-#endif
-
- return ret;
-}
-
-#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
-
-#define mv88E1118_PAGE_REG 22
-
-int board_phy_config(struct phy_device *phydev)
-{
- if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
- /* driver config is good */
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- /* but we still need to fix the LEDs */
- phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
- phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
- }
-
- return 0;
-}
-#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
deleted file mode 100644
index 29dde7a8024c..000000000000
--- a/board/keymile/kmp204x/kmp204x.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2011,2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "../common/common.h"
-#include "../common/qrio.h"
-#include "kmp204x.h"
-
-static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
-
-int checkboard(void)
-{
- printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
-
- return 0;
-}
-
-#define ZL30158_RST 8
-#define BFTIC4_RST 0
-#define RSTRQSR1_WDT_RR 0x00200000
-#define RSTRQSR1_SW_RR 0x00100000
-
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- bool cpuwd_flag = false;
-
- /* configure mode for uP reset request */
- qrio_uprstreq(UPREQ_CORE_RST);
-
- /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
- setbits_be32(&gur->ddrclkdr, 0x001f000f);
-
- /* set reset reason according CPU register */
- if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
- RSTRQSR1_WDT_RR)
- cpuwd_flag = true;
-
- qrio_cpuwd_flag(cpuwd_flag);
- /* clear CPU bits by writing 1 */
- setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
-
- /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
- qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
- /* and enable WD on it */
- qrio_wdmask(BFTIC4_RST, true);
-
- /* set the ZL30138's prstcfg to reset at power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- /* and take it out of reset as soon as possible (needed for Hooper) */
- qrio_prst(ZL30158_RST, false, false);
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- int ret = 0;
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- set_liodns();
- setup_qbman_portals();
-
- ret = trigger_fpga_config();
- if (ret)
- printf("error triggering PCIe FPGA config\n");
-
- /* enable the Unit LED (red) & Boot LED (on) */
- qrio_set_leds();
-
- /* enable Application Buffer */
- qrio_enable_app_buffer();
-
- return 0;
-}
-
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
- return 66666666;
-}
-
-#define ETH_FRONT_PHY_RST 15
-#define QSFP2_RST 11
-#define QSFP1_RST 10
-#define ZL30343_RST 9
-
-int misc_init_f(void)
-{
- /* configure QRIO pis for i2c deblocking */
- i2c_deblock_gpio_cfg();
-
- /* configure the front phy's prstcfg and take it out of reset */
- qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
- qrio_prst(ETH_FRONT_PHY_RST, false, false);
-
- /* set the ZL30343 prstcfg to reset at power-up only */
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
- /* and enable the WD on it */
- qrio_wdmask(ZL30343_RST, true);
-
- /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
- qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
- qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
-
- /* and enable the WD on them */
- qrio_wdmask(QSFP1_RST, true);
- qrio_wdmask(QSFP2_RST, true);
-
- return 0;
-}
-
-#define NUM_SRDS_BANKS 2
-
-int misc_init_r(void)
-{
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
- u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
- SRDS_PLLCR0_RFCK_SEL_125};
- unsigned int i;
-
- /* check SERDES reference clocks */
- for (i = 0; i < NUM_SRDS_BANKS; i++) {
- u32 actual = in_be32(®s->bank[i].pllcr0);
- actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
- if (actual != expected[i]) {
- printf("Warning: SERDES bank %u expects reference \
- clock %sMHz, but actual is %sMHz\n", i + 1,
- serdes_clock_to_string(expected[i]),
- serdes_clock_to_string(actual));
- }
- }
-
- ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
- CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
- return 0;
-}
-
-#if defined(CONFIG_HUSH_INIT_VAR)
-int hush_init_var(void)
-{
- ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
- return 0;
-}
-#endif
-
-#if defined(CONFIG_LAST_STAGE_INIT)
-
-int last_stage_init(void)
-{
-#if defined(CONFIG_KMCOGE4)
- /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
- struct bfticu_iomap *bftic4 =
- (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
- u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
-
- if (dip_switch != 0) {
- /* start bootloader */
- puts("DIP: Enabled\n");
- env_set("actual_bank", "0");
- }
-#endif
- set_km_env();
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-void fdt_fixup_fman_mac_addresses(void *blob)
-{
- int node, i, ret;
- char *tmp, *end;
- unsigned char mac_addr[6];
-
- /* get the mac addr from env */
- tmp = env_get("ethaddr");
- if (!tmp) {
- printf("ethaddr env variable not defined\n");
- return;
- }
- for (i = 0; i < 6; i++) {
- mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
- if (tmp)
- tmp = (*end) ? end+1 : end;
- }
-
- /* find the correct fdt ethernet path and correct it */
- node = fdt_path_offset(blob, "/soc/fman/ethernet at e8000");
- if (node < 0) {
- printf("no /soc/fman/ethernet path offset\n");
- return;
- }
- ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
- if (ret) {
- printf("error setting local-mac-address property\n");
- return;
- }
-}
-#endif
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
- fsl_fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
- fdt_fixup_fman_mac_addresses(blob);
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_POST)
-
-/* DIC26_SELFTEST GPIO used to start factory test sw */
-#define SELFTEST_PORT QRIO_GPIO_A
-#define SELFTEST_PIN 31
-
-int post_hotkeys_pressed(void)
-{
- qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
- return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
-}
-#endif
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
deleted file mode 100644
index 3b858a557117..000000000000
--- a/board/keymile/kmp204x/kmp204x.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-
-void pci_of_setup(void *blob, struct bd_info *bd);
diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c
deleted file mode 100644
index 2d83dfea15f8..000000000000
--- a/board/keymile/kmp204x/law.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
-#endif
- SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
- SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#endif
-#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
- SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
deleted file mode 100644
index 3fdfb47ab235..000000000000
--- a/board/keymile/kmp204x/pbi.cfg
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2012 Freescale Semiconductor, Inc.
-# Refer docs/README.pblimage for more details about how-to configure
-# and create PBL boot image
-#
-
-#PBI commands
-#Configure ALTCBAR for DCSR -> DCSR at 89000000
-091380c0 000009C4
-09000010 00000000
-091380c0 000009C4
-09000014 00000000
-091380c0 000009C4
-09000018 81d00000
-#Workaround for A-004849
-091380c0 000009C4
-890B0050 00000002
-091380c0 000009C4
-890B0054 00000002
-091380c0 000009C4
-890B0058 00000002
-091380c0 000009C4
-890B005C 00000002
-091380c0 000009C4
-890B0090 00000002
-091380c0 000009C4
-890B0094 00000002
-091380c0 000009C4
-890B0098 00000002
-091380c0 000009C4
-890B009C 00000002
-091380c0 000009C4
-890B0108 00000012
-091380c0 000009C4
-#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
-89021008 0000f000
-091380c0 000009C4
-89021028 0000f000
-091380c0 000009C4
-89021048 0000f000
-091380c0 000009C4
-89021068 0000f000
-091380c0 000009C4
-#Flush PBL data
-09138000 00000000
-#Disable ALTCBAR
-09000018 00000000
-091380c0 000009C4
-#Initialize CPC1 as 1MB SRAM
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-09010100 00000000
-09010104 fff0000b
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff00000
-09000d08 81000013
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Initialize eSPI controller, default configuration is slow for eSPI to
-#load data, this configuration comes from u-boot eSPI driver.
-09110000 80000403
-09110020 27170008
-09110024 00100008
-09110028 00100008
-0911002c 00100008
-#Flush PBL data
-09138000 00000000
-091380c0 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
deleted file mode 100644
index cdb498da03b0..000000000000
--- a/board/keymile/kmp204x/pci.c
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-#include <linux/errno.h>
-
-#include "../common/qrio.h"
-#include "kmp204x.h"
-
-#define PROM_SEL_L 11
-/* control the PROM_SEL_L signal*/
-static void toggle_fpga_eeprom_bus(bool cpu_own)
-{
- qrio_gpio_direction_output(QRIO_GPIO_A, PROM_SEL_L, !cpu_own);
-}
-
-#define CONF_SEL_L 10
-#define FPGA_PROG_L 19
-#define FPGA_DONE 18
-#define FPGA_INIT_L 17
-
-int trigger_fpga_config(void)
-{
- int ret = 0, init_l;
- /* approx 10ms */
- u32 timeout = 10000;
-
- /* make sure the FPGA_can access the EEPROM */
- toggle_fpga_eeprom_bus(false);
-
- /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
- qrio_gpio_direction_output(QRIO_GPIO_A, CONF_SEL_L, 0);
-
- /* trigger the config start */
- qrio_gpio_direction_output(QRIO_GPIO_A, FPGA_PROG_L, 0);
-
- /* small delay for INIT_L line */
- udelay(10);
-
- /* wait for FPGA_INIT to be asserted */
- do {
- init_l = qrio_get_gpio(QRIO_GPIO_A, FPGA_INIT_L);
- if (timeout-- == 0) {
- printf("FPGA_INIT timeout\n");
- ret = -EFAULT;
- break;
- }
- udelay(10);
- } while (init_l);
-
- /* deassert FPGA_PROG, config should start */
- qrio_set_gpio(QRIO_GPIO_A, FPGA_PROG_L, 1);
-
- return ret;
-}
-
-/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
-static int wait_for_fpga_config(void)
-{
- int ret = 0, done;
- /* approx 5 s */
- u32 timeout = 500000;
-
- printf("PCIe FPGA config:");
- do {
- done = qrio_get_gpio(QRIO_GPIO_A, FPGA_DONE);
- if (timeout-- == 0) {
- printf(" FPGA_DONE timeout\n");
- ret = -EFAULT;
- goto err_out;
- }
- udelay(10);
- } while (!done);
-
- printf(" done\n");
-
-err_out:
- /* deactive CONF_SEL and give the CPU conf EEPROM access */
- qrio_set_gpio(QRIO_GPIO_A, CONF_SEL_L, 1);
- toggle_fpga_eeprom_bus(true);
-
- return ret;
-}
-
-#define PCIE_SW_RST 14
-#define PEXHC_RST 13
-#define HOOPER_RST 12
-
-void pci_init_board(void)
-{
- qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
- qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
- qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
-
- /* wait for the PCIe FPGA to be configured
- * it has been triggered earlier in board_early_init_r */
- if (wait_for_fpga_config())
- printf("error finishing PCIe FPGA config\n");
-
- qrio_prst(PCIE_SW_RST, false, false);
- qrio_prst(PEXHC_RST, false, false);
- qrio_prst(HOOPER_RST, false, false);
- /* Hooper is not direcly PCIe capable */
- mdelay(50);
-
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
deleted file mode 100644
index 236d5138bc7e..000000000000
--- a/board/keymile/kmp204x/rcw_kmp204x.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Default RCW for kmp204x boards
-#
-
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#64 bytes RCW data
-14600000 00000000 28200000 00000000
-148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F0428816
-00000000 00000000 00000000 00000000
diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c
deleted file mode 100644
index a268bd8e959c..000000000000
--- a/board/keymile/kmp204x/tlb.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- *
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- /* TLB 1 */
- /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
- * SRAM is at 0xfff00000, it covered the 0xfffff000.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
- /* QRIO */
- SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64K, 1),
- /* *I*G* - PCI1 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_512M, 1),
- /* *I*G* - PCI3 */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_512M, 1),
- /* *I*G* - PCI1&3 I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_128K, 1),
-#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
- /* LBAPP1 */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-#endif
-#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
- /* LBAPP2 */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-#endif
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_4M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_32K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig
deleted file mode 100644
index 462e5677964e..000000000000
--- a/configs/kmcoge4_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff40000
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
-CONFIG_ENV_OFFSET_REDUND=0x110000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_KMP204X=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4"
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_MISC_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=fsl_elbc_nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fsl_elbc_nand:-(ubi0);"
-# CONFIG_CMD_IRQ is not set
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_DM=y
-CONFIG_BOOTCOUNT_LIMIT=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_BCH=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
deleted file mode 100644
index af3b03be4909..000000000000
--- a/include/configs/kmp204x.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Keymile AG
- * Valentin Longchamp <valentin.longchamp@keymile.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if defined(CONFIG_KMCOGE4)
-#define CONFIG_HOSTNAME "kmcoge4"
-
-#else
-#error ("Board not supported")
-#endif
-
-#define CONFIG_KMP204X
-
-/* an additionnal option is required for UBI as subpage access is
- * supported in u-boot
- */
-#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
-
-#define CONFIG_NAND_ECC_BCH
-
-/* common KM defines */
-#include "km/keymile-common.h"
-
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_DPAA_RMAN /* RMan */
-
-/* Environment in SPI Flash */
-#define CONFIG_ENV_TOTAL_SIZE 0x020000
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BACKSIDE_L2_CACHE
-#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
-#define CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
-#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
- CONFIG_RAMBOOT_TEXT_BASE)
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#define CONFIG_DDR_SPD
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/******************************************************************************
- * (PRAM usage)
- * ... -------------------------------------------------------
- * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
- * ... |<------------------- pram -------------------------->|
- * ... -------------------------------------------------------
- * @END_OF_RAM:
- * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
- * @CONFIG_KM_PHRAM: address for /var
- * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
- * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
- */
-
-/* size of rootfs in RAM */
-#define CONFIG_KM_ROOTFSSIZE 0x0
-/* pseudo-non volatile RAM [hex] */
-#define CONFIG_KM_PNVRAM 0x80000
-/* physical RAM MTD size [hex] */
-#define CONFIG_KM_PHRAM 0x100000
-/* reserved pram area at the end of memory [hex]
- * u-boot reserves some memory for the MP boot page
- */
-#define CONFIG_KM_RESERVED_PRAM 0x1000
-/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
- * is not valid yet, which is the case for when u-boot copies itself to RAM
- */
-#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
-
-/*
- * Local Bus Definitions
- */
-
-/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
-
-/* Nand Flash */
-#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_NAND_BASE 0xffa00000
-#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
-
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-/* NAND flash config */
-#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
- | OR_FCM_BCTLD /* LBCTL not ass */ \
- | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
- | OR_FCM_RST /* 1 clk read setup */ \
- | OR_FCM_PGS /* Large page size */ \
- | OR_FCM_CST) /* 0.25 command setup */
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-/* QRIO FPGA */
-#define CONFIG_SYS_QRIO_BASE 0xfb000000
-#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
-
-#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
- | BR_PS_8 /* Port Size 8 bits */ \
- | BR_DECC_OFF /* no error corr */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
- | OR_GPCM_BCTLD /* no LCTL assert */ \
- | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
- | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
- | OR_GPCM_TRLX /* relaxed tmgs */ \
- | OR_GPCM_EAD) /* extra bus clk cycles */
-
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
-
-#define CONFIG_KM_CONSOLE_TTY "ttyS0"
-
-/* I2C */
-/* QRIO GPIOs used for deblocking */
-#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
-#define KM_I2C_DEBLOCK_SCL 20
-#define KM_I2C_DEBLOCK_SDA 21
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
-#define CONFIG_SYS_NUM_I2C_BUSES 3
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
- {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
- }
-
-#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-
-/* Qman/Bman */
-#define CONFIG_SYS_BMAN_NUM_PORTALS 10
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 10
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-/* Default address of microcode for the Linux Fman driver
- * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
- * ucode is stored after env, so we got 0x120000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x120000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-/* RGMII (FM1 at DTESC5) is used as debug itf, it's the only one configured */
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
-#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_ETHPRIME "FM1 at DTSEC5"
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Hardware Watchdog
- */
-#define CONFIG_WATCHDOG /* enable CPU watchdog */
-#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
-#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
-
-/*
- * additionnal command line configuration.
- */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-#define __USB_PHY_TYPE utmi
-#define CONFIG_USB_EHCI_FSL
-
-/*
- * Environment Configuration
- */
-#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
-#define CONFIG_KM_DEF_ENV "km-common=empty\0"
-#endif
-
-/* architecture specific default bootargs */
-#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
-
-/* FIXME: FDT_ADDR is unspecified */
-#define CONFIG_KM_DEF_ENV_CPU \
- "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
- "cramfsloadfdt=" \
- "cramfsload ${fdt_addr_r} " \
- "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
- "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \
- "update=" \
- "sf probe 0;sf erase 0 +${filesize};" \
- "sf write ${load_addr_r} 0 ${filesize};\0" \
- "set_fdthigh=true\0" \
- "checkfdt=true\0" \
- ""
-
-#define CONFIG_HW_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
- "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
- "usb_dr_mode=host\0"
-
-#define CONFIG_KM_NEW_ENV \
- "newenv=sf probe 0;" \
- "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
- __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
-
-/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
-#ifndef CONFIG_KM_DEF_ARCH
-#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_DEF_ENV \
- CONFIG_KM_DEF_ARCH \
- CONFIG_KM_NEW_ENV \
- CONFIG_HW_ENV_SETTINGS \
- "EEprom_ivm=pca9547:70:9\0" \
- ""
-
-/* App2 Local bus */
-#define CONFIG_SYS_LBAPP2_BASE 0xE0000000
-#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
-
-#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
- | BR_PS_8 /* Port Size 8 bits */ \
- | BR_DECC_OFF /* no error corr */ \
- | BR_MS_GPCM /* MSEL = GPCM */ \
- | BR_V) /* valid */
-
-#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
- | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
- | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
- | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
- | OR_GPCM_TRLX /* relaxed tmgs */ \
- | OR_GPCM_EAD) /* extra bus clk cycles */
-/* Local bus app2 Base Address */
-#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
-/* Local bus app2 Options */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 20/27] ppc: Remove xpedite boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (17 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 19/27] ppc: Remove kmcoge4 board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-17 16:49 ` Peter Tyser
2021-07-08 2:53 ` Tom Rini
2021-05-15 1:34 ` [PATCH 21/27] ppc: Remove sbc8641d board Tom Rini
` (7 subsequent siblings)
26 siblings, 2 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this includes
the last ARCH_MPC8572 platform, remove that as well.
Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 40 +-
arch/powerpc/cpu/mpc85xx/Makefile | 1 -
arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c | 74 ---
arch/powerpc/cpu/mpc86xx/Kconfig | 5 -
arch/powerpc/include/asm/fsl_law.h | 4 +-
arch/powerpc/include/asm/immap_85xx.h | 2 +-
board/xes/common/Makefile | 1 -
board/xes/xpedite517x/Kconfig | 12 -
board/xes/xpedite517x/MAINTAINERS | 6 -
board/xes/xpedite517x/Makefile | 8 -
board/xes/xpedite517x/ddr.c | 124 -----
board/xes/xpedite517x/law.c | 27 -
board/xes/xpedite517x/xpedite517x.c | 86 ---
board/xes/xpedite520x/Kconfig | 12 -
board/xes/xpedite520x/MAINTAINERS | 6 -
board/xes/xpedite520x/Makefile | 11 -
board/xes/xpedite520x/ddr.c | 68 ---
board/xes/xpedite520x/law.c | 26 -
board/xes/xpedite520x/tlb.c | 68 ---
board/xes/xpedite520x/xpedite520x.c | 82 ---
board/xes/xpedite537x/Kconfig | 12 -
board/xes/xpedite537x/MAINTAINERS | 6 -
board/xes/xpedite537x/Makefile | 11 -
board/xes/xpedite537x/ddr.c | 234 --------
board/xes/xpedite537x/law.c | 25 -
board/xes/xpedite537x/tlb.c | 82 ---
board/xes/xpedite537x/xpedite537x.c | 82 ---
board/xes/xpedite550x/Kconfig | 12 -
board/xes/xpedite550x/MAINTAINERS | 6 -
board/xes/xpedite550x/Makefile | 8 -
board/xes/xpedite550x/ddr.c | 135 -----
board/xes/xpedite550x/law.c | 25 -
board/xes/xpedite550x/tlb.c | 81 ---
board/xes/xpedite550x/xpedite550x.c | 82 ---
configs/xpedite517x_defconfig | 54 --
configs/xpedite520x_defconfig | 54 --
configs/xpedite537x_defconfig | 57 --
configs/xpedite550x_defconfig | 57 --
drivers/ddr/fsl/Kconfig | 1 -
env/Kconfig | 2 +-
include/configs/xpedite517x.h | 646 ----------------------
include/configs/xpedite520x.h | 445 ---------------
include/configs/xpedite537x.h | 496 -----------------
include/configs/xpedite550x.h | 494 -----------------
44 files changed, 5 insertions(+), 3765 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
delete mode 100644 board/xes/xpedite517x/Kconfig
delete mode 100644 board/xes/xpedite517x/MAINTAINERS
delete mode 100644 board/xes/xpedite517x/Makefile
delete mode 100644 board/xes/xpedite517x/ddr.c
delete mode 100644 board/xes/xpedite517x/law.c
delete mode 100644 board/xes/xpedite517x/xpedite517x.c
delete mode 100644 board/xes/xpedite520x/Kconfig
delete mode 100644 board/xes/xpedite520x/MAINTAINERS
delete mode 100644 board/xes/xpedite520x/Makefile
delete mode 100644 board/xes/xpedite520x/ddr.c
delete mode 100644 board/xes/xpedite520x/law.c
delete mode 100644 board/xes/xpedite520x/tlb.c
delete mode 100644 board/xes/xpedite520x/xpedite520x.c
delete mode 100644 board/xes/xpedite537x/Kconfig
delete mode 100644 board/xes/xpedite537x/MAINTAINERS
delete mode 100644 board/xes/xpedite537x/Makefile
delete mode 100644 board/xes/xpedite537x/ddr.c
delete mode 100644 board/xes/xpedite537x/law.c
delete mode 100644 board/xes/xpedite537x/tlb.c
delete mode 100644 board/xes/xpedite537x/xpedite537x.c
delete mode 100644 board/xes/xpedite550x/Kconfig
delete mode 100644 board/xes/xpedite550x/MAINTAINERS
delete mode 100644 board/xes/xpedite550x/Makefile
delete mode 100644 board/xes/xpedite550x/ddr.c
delete mode 100644 board/xes/xpedite550x/law.c
delete mode 100644 board/xes/xpedite550x/tlb.c
delete mode 100644 board/xes/xpedite550x/xpedite550x.c
delete mode 100644 configs/xpedite517x_defconfig
delete mode 100644 configs/xpedite520x_defconfig
delete mode 100644 configs/xpedite537x_defconfig
delete mode 100644 configs/xpedite550x_defconfig
delete mode 100644 include/configs/xpedite517x.h
delete mode 100644 include/configs/xpedite520x.h
delete mode 100644 include/configs/xpedite537x.h
delete mode 100644 include/configs/xpedite550x.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index cd7aa953567b..876f768e8601 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -185,20 +185,6 @@ config TARGET_KMCENT2
bool "Support kmcent2"
select VENDOR_KM
-config TARGET_XPEDITE520X
- bool "Support xpedite520x"
- select ARCH_MPC8548
-
-config TARGET_XPEDITE537X
- bool "Support xpedite537x"
- select ARCH_MPC8572
-# Use DDR3 controller with DDR2 DIMMs on this board
- select SYS_FSL_DDRC_GEN3
-
-config TARGET_XPEDITE550X
- bool "Support xpedite550x"
- select ARCH_P2020
-
config TARGET_UCP1020
bool "Support uCP1020"
select ARCH_P1020
@@ -374,23 +360,6 @@ config ARCH_MPC8560
select FSL_LAW
select SYS_FSL_HAS_DDR1
-config ARCH_MPC8572
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_DDR_115
- select SYS_FSL_ERRATUM_DDR111_DDR134
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR2
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_ELBC
- imply CMD_NAND
-
config ARCH_P1010
bool
select FSL_LAW
@@ -865,7 +834,6 @@ config MAX_CPUS
ARCH_T2080
default 2 if ARCH_B4420 || \
ARCH_BSC9132 || \
- ARCH_MPC8572 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1023 || \
@@ -891,7 +859,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_MPC8544 || \
ARCH_MPC8548 || \
ARCH_MPC8560 || \
- ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
ARCH_P1020 || \
@@ -1104,7 +1071,6 @@ config SYS_FSL_NUM_LAWS
ARCH_BSC9132 || \
ARCH_C29X || \
ARCH_MPC8536 || \
- ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
ARCH_P1020 || \
@@ -1151,8 +1117,7 @@ config SYS_PPC_E500_DEBUG_TLB
depends on SYS_PPC_E500_USE_DEBUG_TLB
default 0 if ARCH_MPC8544 || ARCH_MPC8548
default 1 if ARCH_MPC8536
- default 2 if ARCH_MPC8572 || \
- ARCH_P1011 || \
+ default 2 if ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
@@ -1216,9 +1181,6 @@ source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
source "board/socrates/Kconfig"
-source "board/xes/xpedite520x/Kconfig"
-source "board/xes/xpedite537x/Kconfig"
-source "board/xes/xpedite550x/Kconfig"
source "board/Arcturus/ucp1020/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 8cd4b44ec5f9..bbaae0d8454f 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
-obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
deleted file mode 100644
index 1b4e6149184d..000000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 8
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
- [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
- [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC1);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC2);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC3);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC4);
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 7de42b5f2576..1ee87038bed4 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -13,10 +13,6 @@ config TARGET_SBC8641D
select ARCH_MPC8641
select BOARD_EARLY_INIT_F
-config TARGET_XPEDITE517X
- bool "Support xpedite517x"
- select ARCH_MPC8641
-
endchoice
config ARCH_MPC8610
@@ -52,6 +48,5 @@ config SYS_FSL_NUM_LAWS
If not sure, do not change.
source "board/sbc8641d/Kconfig"
-source "board/xes/xpedite517x/Kconfig"
endmenu
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 888640df6f81..77cdc80fdcd0 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -84,7 +84,7 @@ enum law_trgt_if {
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
-#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
+#if !defined(CONFIG_ARCH_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
#endif
@@ -120,7 +120,7 @@ enum law_trgt_if {
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
-#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
+#if defined(CONFIG_ARCH_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 900b8f43c82e..70112c91fc51 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2853,7 +2853,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
-#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
+#if defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
#else
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index b5c6900021c4..49320305470e 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -4,7 +4,6 @@
# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
-obj-$(CONFIG_ARCH_MPC8572) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
diff --git a/board/xes/xpedite517x/Kconfig b/board/xes/xpedite517x/Kconfig
deleted file mode 100644
index 91bbd22451b1..000000000000
--- a/board/xes/xpedite517x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE517X
-
-config SYS_BOARD
- default "xpedite517x"
-
-config SYS_VENDOR
- default "xes"
-
-config SYS_CONFIG_NAME
- default "xpedite517x"
-
-endif
diff --git a/board/xes/xpedite517x/MAINTAINERS b/board/xes/xpedite517x/MAINTAINERS
deleted file mode 100644
index 26e0acccb056..000000000000
--- a/board/xes/xpedite517x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE517X BOARD
-M: Peter Tyser <ptyser@xes-inc.com>
-S: Maintained
-F: board/xes/xpedite517x/
-F: include/configs/xpedite517x.h
-F: configs/xpedite517x_defconfig
diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile
deleted file mode 100644
index 10ac76a37a19..000000000000
--- a/board/xes/xpedite517x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += xpedite517x.o
-obj-y += ddr.o
-obj-y += law.o
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
deleted file mode 100644
index a3fd2fc8ca89..000000000000
--- a/board/xes/xpedite517x/ddr.c
+++ /dev/null
@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <log.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
- i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
- sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork. These are:
- * 1.) CPO (Read Capture Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths and
- * chip-specific internal delays.
- * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths.
- * Unless clock and DQ lanes are very different
- * lengths (>2"), this should be set to the nominal value
- * of 1/2 clock delay.
- * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- * - DDR_SDRAM_CLK_CNTL register
- * Source: Signal Integrity Simulations
- * 4.) 2T Timing on Addr/Ctl
- * - TIMING_CFG_2 register
- * Source: Signal Integrity Simulations
- * Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
- * so we use the XPedite5370 settings as a basis for the XPedite5170.
- */
-
-typedef struct board_memctl_options {
- uint16_t datarate_mhz_low;
- uint16_t datarate_mhz_high;
- uint8_t clk_adjust;
- uint8_t cpo_override;
- uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
- {
- /* Controller 0 */
- {
- /* DDR2 600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo_override = 8,
- .write_data_delay = 2,
- },
- {
- /* DDR2 800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo_override = 9,
- .write_data_delay = 2,
- },
- },
- {
- /* Controller 1 */
- {
- /* DDR2 600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo_override = 7,
- .write_data_delay = 2,
- },
- {
- /* DDR2 800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo_override = 8,
- .write_data_delay = 2,
- },
- },
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
- sys_info_t sysinfo;
- int i;
- unsigned int datarate;
-
- get_sys_info(&sysinfo);
- datarate = get_ddr_freq(0) / 1000000;
-
- for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
- if ((bopts[i].datarate_mhz_low <= datarate) &&
- (bopts[i].datarate_mhz_high >= datarate)) {
- debug("controller %d:\n", ctrl_num);
- debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
- debug(" cpo = %d\n", bopts[i].cpo_override);
- debug(" write_data_delay = %d\n",
- bopts[i].write_data_delay);
- popts->clk_adjust = bopts[i].clk_adjust;
- popts->cpo_override = bopts[i].cpo_override;
- popts->write_data_delay = bopts[i].write_data_delay;
- }
- }
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c
deleted file mode 100644
index b82f9f0d3b11..000000000000
--- a/board/xes/xpedite517x/law.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- * CCSRBAR don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE
- /* NAND LAW covers 2 NAND flashes */
- SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
deleted file mode 100644
index 8a5b52c49527..000000000000
--- a/board/xes/xpedite517x/xpedite517x.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-#include "../common/fsl_8xxx_misc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-#endif
-
-/*
- * Print out which flash was booted from and if booting from the 2nd flash,
- * swap flash chip selects to maintain consistent flash numbering/addresses.
- */
-static void flash_cs_fixup(void)
-{
- int flash_sel;
-
- /*
- * Print boot dev and swap flash flash chip selects if booted from 2nd
- * flash. Swapping chip selects presents user with a common memory
- * map regardless of which flash was booted from.
- */
- flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
- CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
- if (flash_sel) {
- set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
- set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
- set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
- set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
- }
-}
-
-int board_early_init_r(void)
-{
- /* Initialize PCA9557 devices */
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
- flash_cs_fixup();
-
- return 0;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size = fsl_ddr_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /* Initialize and enable DDR ECC */
- ddr_enable_ecc(dram_size);
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
- ft_board_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/xes/xpedite520x/Kconfig b/board/xes/xpedite520x/Kconfig
deleted file mode 100644
index 9c0c2461fde8..000000000000
--- a/board/xes/xpedite520x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE520X
-
-config SYS_BOARD
- default "xpedite520x"
-
-config SYS_VENDOR
- default "xes"
-
-config SYS_CONFIG_NAME
- default "xpedite520x"
-
-endif
diff --git a/board/xes/xpedite520x/MAINTAINERS b/board/xes/xpedite520x/MAINTAINERS
deleted file mode 100644
index f7bd437cc66d..000000000000
--- a/board/xes/xpedite520x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE520X BOARD
-M: Peter Tyser <ptyser@xes-inc.com>
-S: Maintained
-F: board/xes/xpedite520x/
-F: include/configs/xpedite520x.h
-F: configs/xpedite520x_defconfig
diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile
deleted file mode 100644
index 12e75da5b3cf..000000000000
--- a/board/xes/xpedite520x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += xpedite520x.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
deleted file mode 100644
index c142bec406e5..000000000000
--- a/board/xes/xpedite520x/ddr.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
-{
- i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
-
- /* We use soldered memory, but use an SPD EEPROM to describe it.
- * The SPD has an unspecified dimm type, but the DDR2 initialization
- * code requires a specific type to be specified. This sets the type
- * as a standard unregistered SO-DIMM. */
- if (spd->dimm_type == 0) {
- spd->dimm_type = 0x4;
- ((uchar *)spd)[63] += 0x4;
- }
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 9;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
deleted file mode 100644
index 10613ead3f21..000000000000
--- a/board/xes/xpedite520x/law.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite520x/tlb.c b/board/xes/xpedite520x/tlb.c
deleted file mode 100644
index d45f532861ea..000000000000
--- a/board/xes/xpedite520x/tlb.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* W**G* - NOR flashes */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G* - NAND flash */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if CONFIG_PCI1
- /* *I*G* - PCI MEM */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#if CONFIG_PCI2
- /* *I*G* - PCI MEM */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
- /* *I*G* - PCI IO */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_16M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c
deleted file mode 100644
index 63e1e0efe54c..000000000000
--- a/board/xes/xpedite520x/xpedite520x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2004, 2007 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
- int flash_sel;
-
- /*
- * Print boot dev and swap flash flash chip selects if booted from 2nd
- * flash. Swapping chip selects presents user with a common memory
- * map regardless of which flash was booted from.
- */
- flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
- CONFIG_SYS_PCA953X_FLASH_PASS_CS));
- printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
- if (flash_sel) {
- set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
- set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
- set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
- set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
- }
-}
-
-int board_early_init_r(void)
-{
- /* Initialize PCA9557 devices */
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-
- /*
- * Remap NOR flash region to caching-inhibited
- * so that flash can be erased/programmed properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* Invalidate existing TLB entry for NOR flash */
- disable_tlb(0);
- set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1);
-
- flash_cs_fixup();
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
- ft_board_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/xes/xpedite537x/Kconfig b/board/xes/xpedite537x/Kconfig
deleted file mode 100644
index 35b3917a6da9..000000000000
--- a/board/xes/xpedite537x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE537X
-
-config SYS_BOARD
- default "xpedite537x"
-
-config SYS_VENDOR
- default "xes"
-
-config SYS_CONFIG_NAME
- default "xpedite537x"
-
-endif
diff --git a/board/xes/xpedite537x/MAINTAINERS b/board/xes/xpedite537x/MAINTAINERS
deleted file mode 100644
index b6123acc0f99..000000000000
--- a/board/xes/xpedite537x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE537X BOARD
-M: Peter Tyser <ptyser@xes-inc.com>
-S: Maintained
-F: board/xes/xpedite537x/
-F: include/configs/xpedite537x.h
-F: configs/xpedite537x_defconfig
diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile
deleted file mode 100644
index 82575cf05ec6..000000000000
--- a/board/xes/xpedite537x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += xpedite537x.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
deleted file mode 100644
index f55102a072e9..000000000000
--- a/board/xes/xpedite537x/ddr.c
+++ /dev/null
@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <log.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
- i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
- sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork. These are:
- * 1.) CPO (Read Capture Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths and
- * chip-specific internal delays.
- * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths.
- * Unless clock and DQ lanes are very different
- * lengths (>2"), this should be set to the nominal value
- * of 1/2 clock delay.
- * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- * - DDR_SDRAM_CLK_CNTL register
- * Source: Signal Integrity Simulations
- * 4.) 2T Timing on Addr/Ctl
- * - TIMING_CFG_2 register
- * Source: Signal Integrity Simulations
- * Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- * ====== XPedite5370 DDR2-600 read delay calculations ======
- *
- * See Freescale's App Note AN2583 as refrence. This document also
- * contains the chip-specific delays for 8548E, 8572, etc.
- *
- * For MPC8572E
- * Minimum chip delay (Ch 0): 1.372ns
- * Maximum chip delay (Ch 0): 2.914ns
- * Minimum chip delay (Ch 1): 1.220ns
- * Maximum chip delay (Ch 1): 2.595ns
- *
- * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
- *
- * Minimum delay calc (Ch 0):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
- * = 3808ps
- * = 3.808ns
- *
- * Maximum delay calc (Ch 0):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
- * = 6240ps
- * = 6.240ns
- *
- * Minimum delay calc (Ch 1):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
- * = 3288ps
- * = 3.288ns
- *
- * Maximum delay calc (Ch 1):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
- * = 5536ps
- * = 5.536ns
- *
- * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
- * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
- * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
- *
- *
- * ====== XPedite5370 DDR2-800 read delay calculations ======
- *
- * See Freescale's App Note AN2583 as refrence. This document also
- * contains the chip-specific delays for 8548E, 8572, etc.
- *
- * For MPC8572E
- * Minimum chip delay (Ch 0): 1.372ns
- * Maximum chip delay (Ch 0): 2.914ns
- * Minimum chip delay (Ch 1): 1.220ns
- * Maximum chip delay (Ch 1): 2.595ns
- *
- * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
- *
- * Minimum delay calc (Ch 0):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
- * = 3341ps
- * = 3.341ns
- *
- * Maximum delay calc (Ch 0):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
- * = 5673ps
- * = 5.673ns
- *
- * Minimum delay calc (Ch 1):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
- * = 2822ps
- * = 2.822ns
- *
- * Maximum delay calc (Ch 1):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
- * = 4968ps
- * = 4.968ns
- *
- * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
- * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
- * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
- * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- *
- * Write latency (WR_DATA_DELAY) is calculated by doing the following:
- *
- * The DDR SDRAM specification requires DQS be received no sooner than
- * 75% of an SDRAM clock period??and no later than 125% of a clock
- * period??from the capturing clock edge of the command/address at the
- * SDRAM.
- *
- * Based on the above tracelengths, the following are calculated:
- * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
- * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
- * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
- * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
- *
- * Difference in arrival time CLK vs. DQS:
- * Ch. 0 0.072ns
- * Ch. 1 0.138ns
- *
- * Both of these values are much less than 25% of the clock
- * period at DDR2-600 or DDR2-800, so no additional delay is needed over
- * the 1/2 cycle which normally aligns the first DQS transition
- * exactly WL (CAS latency minus one cycle) after the CAS strobe.
- * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
- * terminology corresponds to exactly one clock period delay after
- * the CAS strobe. (due to the fact that the "delay" is referenced
- * from the *falling* edge of the CLK, just after the rising edge
- * which the CAS strobe is latched on.
- */
-
-typedef struct board_memctl_options {
- uint16_t datarate_mhz_low;
- uint16_t datarate_mhz_high;
- uint8_t clk_adjust;
- uint8_t cpo_override;
- uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
- {
- /* Controller 0 */
- {
- /* DDR2 600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo_override = 8,
- .write_data_delay = 2,
- },
- {
- /* DDR2 800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo_override = 9,
- .write_data_delay = 2,
- },
- },
- {
- /* Controller 1 */
- {
- /* DDR2 600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo_override = 7,
- .write_data_delay = 2,
- },
- {
- /* DDR2 800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo_override = 8,
- .write_data_delay = 2,
- },
- },
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
- sys_info_t sysinfo;
- int i;
- unsigned int datarate;
-
- get_sys_info(&sysinfo);
- datarate = sysinfo.freq_ddrbus / 1000 / 1000;
-
- for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
- if ((bopts[i].datarate_mhz_low <= datarate) &&
- (bopts[i].datarate_mhz_high >= datarate)) {
- debug("controller %d:\n", ctrl_num);
- debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
- debug(" cpo = %d\n", bopts[i].cpo_override);
- debug(" write_data_delay = %d\n",
- bopts[i].write_data_delay);
- popts->clk_adjust = bopts[i].clk_adjust;
- popts->cpo_override = bopts[i].cpo_override;
- popts->write_data_delay = bopts[i].write_data_delay;
- }
- }
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c
deleted file mode 100644
index a1f375900cbe..000000000000
--- a/board/xes/xpedite537x/law.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite537x/tlb.c b/board/xes/xpedite537x/tlb.c
deleted file mode 100644
index 6d50360f069c..000000000000
--- a/board/xes/xpedite537x/tlb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* W**G* - NOR flashes */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G* - NAND flash */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1M, 1),
-
- /* **M** - Boot page for secondary processors */
- SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c
deleted file mode 100644
index 437b57d4ff6e..000000000000
--- a/board/xes/xpedite537x/xpedite537x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
- int flash_sel;
-
- /*
- * Print boot dev and swap flash flash chip selects if booted from 2nd
- * flash. Swapping chip selects presents user with a common memory
- * map regardless of which flash was booted from.
- */
- flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
- CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
- if (flash_sel) {
- set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
- set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
- set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
- set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
- }
-}
-
-int board_early_init_r(void)
-{
- /* Initialize PCA9557 devices */
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
- /*
- * Remap NOR flash region to caching-inhibited
- * so that flash can be erased/programmed properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* Invalidate existing TLB entry for NOR flash */
- disable_tlb(0);
- set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1);
-
- flash_cs_fixup();
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
- ft_board_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/xes/xpedite550x/Kconfig b/board/xes/xpedite550x/Kconfig
deleted file mode 100644
index 1b00137a48c2..000000000000
--- a/board/xes/xpedite550x/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE550X
-
-config SYS_BOARD
- default "xpedite550x"
-
-config SYS_VENDOR
- default "xes"
-
-config SYS_CONFIG_NAME
- default "xpedite550x"
-
-endif
diff --git a/board/xes/xpedite550x/MAINTAINERS b/board/xes/xpedite550x/MAINTAINERS
deleted file mode 100644
index 017f3687578b..000000000000
--- a/board/xes/xpedite550x/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE550X BOARD
-M: Peter Tyser <ptyser@xes-inc.com>
-S: Maintained
-F: board/xes/xpedite550x/
-F: include/configs/xpedite550x.h
-F: configs/xpedite550x_defconfig
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
deleted file mode 100644
index 1aacb375cc50..000000000000
--- a/board/xes/xpedite550x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007-2008 Freescale Semiconductor, Inc.
-
-obj-y += xpedite550x.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
deleted file mode 100644
index ad52c9455b8b..000000000000
--- a/board/xes/xpedite550x/ddr.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
-{
- i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
- sizeof(ddr3_spd_eeprom_t));
-}
-
-/*
- * There are traditionally three board-specific SDRAM timing parameters
- * which must be calculated based on the particular PCB artwork. These are:
- * 1.) CPO (Read Capture Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths and
- * chip-specific internal delays.
- * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- * - DDR_SDRAM_CLK_CNTL register
- * Source: Signal Integrity Simulations
- * 3.) 2T Timing on Addr/Ctl
- * - TIMING_CFG_2 register
- * Source: Signal Integrity Simulations
- * Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- * ====== XPedite550x DDR3-800 read delay calculations ======
- *
- * The P2020 processor provides an autoleveling option. Setting CPO to
- * 0x1f enables this auto configuration.
- */
-
-typedef struct {
- unsigned short datarate_mhz_low;
- unsigned short datarate_mhz_high;
- unsigned char clk_adjust;
- unsigned char cpo;
-} board_specific_parameters_t;
-
-const board_specific_parameters_t board_specific_parameters[][20] = {
- {
- /* Controller 0 */
- {
- /* DDR3-600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo = 31,
- },
- {
- /* DDR3-800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo = 31,
- },
- },
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const board_specific_parameters_t *pbsp =
- &(board_specific_parameters[ctrl_num][0]);
- u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
- sizeof(board_specific_parameters[0][0]);
- u32 i;
- ulong ddr_freq;
-
- /*
- * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i&1) { /* odd CS */
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 0;
- } else { /* even CS */
- if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 4;
- } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
- popts->cs_local_opts[i].odt_rd_cfg = 3;
- popts->cs_local_opts[i].odt_wr_cfg = 3;
- }
- }
- }
-
- /*
- * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
-
- for (i = 0; i < num_params; i++) {
- if (ddr_freq >= pbsp->datarate_mhz_low &&
- ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->twot_en = 0;
- break;
- }
- pbsp++;
- }
-
- if (i == num_params) {
- printf("Warning: board specific timing not found "
- "for data rate %lu MT/s!\n", ddr_freq);
- }
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-
- /*
- * Enable on-die termination.
- * From the Micron Technical Node TN-41-04, RTT_Nom should typically
- * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
- * is handled in the Freescale DDR3 driver. Set RTT_Nom here.
- */
- popts->rtt_override = 1;
- popts->rtt_override_value = 3;
-}
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
deleted file mode 100644
index 1e2d604d9d48..000000000000
--- a/board/xes/xpedite550x/law.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c
deleted file mode 100644
index 7cb6cd677067..000000000000
--- a/board/xes/xpedite550x/tlb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* W**G* - NOR flashes */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G* - NAND flash */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1M, 1),
-
- /* **M** - Boot page for secondary processors */
- SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
deleted file mode 100644
index 9089a0cc72a0..000000000000
--- a/board/xes/xpedite550x/xpedite550x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
-
-static void flash_cs_fixup(void)
-{
- int flash_sel;
-
- /*
- * Print boot dev and swap flash flash chip selects if booted from 2nd
- * flash. Swapping chip selects presents user with a common memory
- * map regardless of which flash was booted from.
- */
- flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
- CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
- if (flash_sel) {
- set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
- set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
- set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
- set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
- }
-}
-
-int board_early_init_r(void)
-{
- /* Initialize PCA9557 devices */
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
- /*
- * Remap NOR flash region to caching-inhibited
- * so that flash can be erased/programmed properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* Invalidate existing TLB entry for NOR flash */
- disable_tlb(0);
- set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1);
-
- flash_cs_fixup();
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_PCI
- ft_board_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
deleted file mode 100644
index caf95458b4d2..000000000000
--- a/configs/xpedite517x_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff00000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_XPEDITE517X=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_IRQ=y
-CONFIG_ENV_ADDR=0xFFF80000
-CONFIG_CMD_PCA953X=y
-CONFIG_DS4510=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
deleted file mode 100644
index 87f2e4d8a619..000000000000
--- a/configs/xpedite520x_defconfig
+++ /dev/null
@@ -1,54 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_XPEDITE520X=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_JFFS2=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_ADDR=0xFFF40000
-CONFIG_CMD_PCA953X=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
deleted file mode 100644
index 17c4b2c3f71f..000000000000
--- a/configs/xpedite537x_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_XPEDITE537X=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_JFFS2=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_ADDR=0xFFF40000
-CONFIG_SYS_FSL_DDR2=y
-CONFIG_CMD_PCA953X=y
-CONFIG_DS4510=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
deleted file mode 100644
index be528151b91b..000000000000
--- a/configs/xpedite550x_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_XPEDITE550X=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_PREBOOT=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_JFFS2=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF40000
-CONFIG_CMD_PCA953X=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 8b480dfd6901..890e62190b1a 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS
ARCH_T4240
default 2 if ARCH_B4860 || \
ARCH_BSC9132 || \
- ARCH_MPC8572 || \
ARCH_MPC8641 || \
ARCH_P4080 || \
ARCH_P5040 || \
diff --git a/env/Kconfig b/env/Kconfig
index ea0ee1e8bafa..c06b8ba8cb7e 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -85,7 +85,7 @@ config ENV_IS_IN_FLASH
default y if M548x || M547x || M5282
default y if MCF532x || MCF52x2
default y if MPC86xx || MPC83xx
- default y if ARCH_MPC8572 || ARCH_MPC8548 || ARCH_MPC8641
+ default y if ARCH_MPC8548 || ARCH_MPC8641
default y if SH && !CPU_SH4
help
Define this if you have a flash device which you want to use for the
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
deleted file mode 100644
index d3bb92964e04..000000000000
--- a/include/configs/xpedite517x.h
+++ /dev/null
@@ -1,646 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-/*
- * xpedite517x board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SYS_BOARD_NAME "XPedite5170"
-#define CONFIG_SYS_FORM_3U_VPX 1
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_ALTIVEC 1
-
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-/*
- * DDR config
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
-#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
-#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
-
-/*
- * virtual address to be used for temporary mappings. There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA 0xe0000000
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
-
-/*
- * L2CR setup
- */
-#define CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E)
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
-
-/*
- * Diagnostics
- */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
- CONFIG_SYS_POST_I2C)
-/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
-#define I2C_ADDR_IGNORE_LIST {0x50}
-
-/*
- * Memory map
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
- * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
- * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
- * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
- * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
- * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
- * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
- * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
- * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
- */
-
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
-
-/*
- * NAND flash configuration
- */
-#define CONFIG_SYS_NAND_BASE 0xef800000
-#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_NAND_ACTL
-#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
-#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
-#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
-#define CONFIG_SYS_NAND_ACTL_DELAY 25
-#define CONFIG_JFFS2_NAND
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000
-#define CONFIG_SYS_FLASH_BASE2 0xf0000000
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
- {0xf7f00000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
-
-/*
- * Chip select configuration
- */
-/* NOR Flash 0 on CS0 */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
- BR_PS_16 |\
- BR_V)
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
- OR_GPCM_CSNT |\
- OR_GPCM_XACS |\
- OR_GPCM_ACS_DIV2 |\
- OR_GPCM_SCY_8 |\
- OR_GPCM_TRLX |\
- OR_GPCM_EHTR |\
- OR_GPCM_EAD)
-
-/* NOR Flash 1 on CS1 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
- BR_PS_16 |\
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
- BR_PS_8 |\
- BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
- OR_GPCM_BCTLD |\
- OR_GPCM_CSNT |\
- OR_GPCM_ACS_DIV4 |\
- OR_GPCM_SCY_4 |\
- OR_GPCM_TRLX |\
- OR_GPCM_EHTR)
-
-/* Optional NAND flash on CS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
- BR_PS_8 |\
- BR_V)
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-
-/*
- * Use L1 as initial stack
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 100000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* PEX8518 slave I2C interface */
-#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
-
-/* I2C DS1631 temperature sensor */
-#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
-
-/* I2C EEPROM - AT24C128B */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/* GPIO */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
-#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
-#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
-#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
-#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
-#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
-
-/*
- * PU = pulled high, PD = pulled low
- * I = input, O = output, IO = input/output
- */
-/* PCA9557 @ 0x18*/
-#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
-#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
-#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
-#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
-#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
-#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
-
-/* PCA9557 @ 0x1c*/
-#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
-#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
-#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
-#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
-#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
-#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
-#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
-#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
-
-/* PCA9557 @ 0x1e*/
-#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
-#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
-
-/* PCA9557 @ 0x1f */
-#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
-#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
-#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
-#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* PCIE1 - PEX8518 */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
-/* PCIE2 - VPX P1 */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
-
-/*
- * Networking options
- */
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define CONFIG_HAS_ETH0
-
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_PHY_ADDR 2
-#define TSEC2_PHYIDX 0
-#define CONFIG_HAS_ETH1
-
-/*
- * BAT mappings
- */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
- BATU_BL_1M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
- */
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
-
-/*
- * BAT1 1G Cache-inhibited, guarded
- * 0x8000_0000 1G PCI-Express 1 Memory
- */
-#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
- BATU_BL_1G |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/*
- * BAT2 512M Cache-inhibited, guarded
- * 0xc000_0000 512M PCI-Express 2 Memory
- */
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
- BATU_BL_512M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-
-/*
- * BAT3 1M Cache-inhibited, guarded
- * 0xe000_0000 1M CCSR
- */
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
- BATU_BL_1M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 16M PCI-Express 1 I/O
- * 0xe300_0000 16M PCI-Express 2 I/0
- */
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
- BATU_BL_32M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
-/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
- BATL_PP_RW |\
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
- BATU_BL_128K |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
-
-/*
- * BAT6 256M Cache-inhibited, guarded
- * 0xf000_0000 256M FLASH
- */
-#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
- BATU_BL_256M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
- BATL_PP_RW |\
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
- BATU_BL_1M |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
- BATL_PP_RW |\
- BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-
-/*
- * BAT7 64M Cache-inhibited, guarded
- * 0xe800_0000 64K NAND FLASH
- * 0xe804_0000 128K DUART Registers
- */
-#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT |\
- BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
- BATU_BL_512K |\
- BATU_VS |\
- BATU_VP)
-#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
- BATL_PP_RW |\
- BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-/*
- * Flash memory map:
- * fffc0000 - ffffffff Pri FDT (256KB)
- * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
- * fff00000 - fff7ffff Pri U-Boot (512 KB)
- * fef00000 - ffefffff Pri OS image (16MB)
- * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
- *
- * f7fc0000 - f7ffffff Sec FDT (256KB)
- * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
- * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
- * f6f00000 - f7efffff Sec OS image (16MB)
- * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
- */
-#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
-#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
-#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
-#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
-#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
-
-#define CONFIG_PROG_UBOOT1 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_UBOOT2 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_BOOT_OS_NET \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "if test -n $fdtaddr; then " \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "bootm $osaddr - $fdtaddr; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi; " \
- "else; " \
- "bootm $osaddr; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS1 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS2 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT1 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT2 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=yes\0" \
- "download_cmd=tftp\0" \
- "console_args=console=ttyS0,115200\0" \
- "root_args=root=/dev/nfs rw\0" \
- "misc_args=ip=on\0" \
- "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
- "bootfile=/home/user/file\0" \
- "osfile=/home/user/board.uImage\0" \
- "fdtfile=/home/user/board.dtb\0" \
- "ubootfile=/home/user/u-boot.bin\0" \
- "fdtaddr=0x1e00000\0" \
- "osaddr=0x1000000\0" \
- "loadaddr=0x1000000\0" \
- "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
- "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
- "prog_os1="CONFIG_PROG_OS1"\0" \
- "prog_os2="CONFIG_PROG_OS2"\0" \
- "prog_fdt1="CONFIG_PROG_FDT1"\0" \
- "prog_fdt2="CONFIG_PROG_FDT2"\0" \
- "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
- "bootcmd_flash1=run set_bootargs; " \
- "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
- "bootcmd_flash2=run set_bootargs; " \
- "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
- "bootcmd=run bootcmd_flash1\0"
-#endif /* __CONFIG_H */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
deleted file mode 100644
index c9bd369029dd..000000000000
--- a/include/configs/xpedite520x.h
+++ /dev/null
@@ -1,445 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2004-2008 Freescale Semiconductor, Inc.
- */
-
-/*
- * xpedite520x board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SYS_BOARD_NAME "XPedite5200"
-#define CONFIG_SYS_FORM_PMC_XMC 1
-
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCI1 1 /* PCI controller 1 */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-/*
- * DDR config
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_SYS_CCSRBAR 0xef000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/*
- * Diagnostics
- */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_I2C)
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_PCA953X_ADDR0, \
- CONFIG_SYS_I2C_PCA953X_ADDR1, \
- CONFIG_SYS_I2C_RTC_ADDR}
-
-/*
- * Memory map
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
- * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
- * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
- * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
- * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
- * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
- * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
- */
-
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
-
-/*
- * NAND flash configuration
- */
-#define CONFIG_SYS_NAND_BASE 0xef800000
-#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused@this time */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_ACTL
-#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
-#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
-#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
-#define CONFIG_SYS_NAND_ACTL_DELAY 25
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000
-#define CONFIG_SYS_FLASH_BASE2 0xf8000000
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
- {0xfbf40000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-/*
- * Chip select configuration
- */
-/* NOR Flash 0 on CS0 */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | \
- BR_V)
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
- OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_8)
-
-/* NOR Flash 1 on CS1 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
- BR_PS_16 | \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
- BR_PS_8 | \
- BR_V)
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
- OR_GPCM_BCTLD | \
- OR_GPCM_CSNT | \
- OR_GPCM_ACS_DIV4 | \
- OR_GPCM_SCY_4 | \
- OR_GPCM_TRLX | \
- OR_GPCM_EHTR)
-
-/* NAND flash on CS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
- BR_PS_8 | \
- BR_V)
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-
-/*
- * Use L1 as initial stack
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* I2C EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/* GPIO */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
-#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
-#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
-
-/* PCA957 @ 0x18 */
-#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
-#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
-#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
-#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
-#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
-#define CONFIG_SYS_PCA953X_NVM_WP 0x20
-#define CONFIG_SYS_PCA953X_MONARCH 0x40
-#define CONFIG_SYS_PCA953X_EREADY 0x80
-
-/* PCA957 @ 0x19 */
-#define CONFIG_SYS_PCA953X_P14_IO0 0x01
-#define CONFIG_SYS_PCA953X_P14_IO1 0x02
-#define CONFIG_SYS_PCA953X_P14_IO2 0x04
-#define CONFIG_SYS_PCA953X_P14_IO3 0x08
-#define CONFIG_SYS_PCA953X_P14_IO4 0x10
-#define CONFIG_SYS_PCA953X_P14_IO5 0x20
-#define CONFIG_SYS_PCA953X_P14_IO6 0x40
-#define CONFIG_SYS_PCA953X_P14_IO7 0x80
-
-/* 12-bit ADC used to measure CPU diode */
-#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
-
-/*
- * Networking options
- */
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define CONFIG_HAS_ETH0
-
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHY_ADDR 2
-#define TSEC2_PHYIDX 0
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define TSEC3_FLAGS TSEC_GIGABIT
-#define TSEC3_PHY_ADDR 3
-#define TSEC3_PHYIDX 0
-#define CONFIG_HAS_ETH2
-
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
-#define TSEC4_FLAGS TSEC_GIGABIT
-#define TSEC4_PHY_ADDR 4
-#define TSEC4_PHYIDX 0
-#define CONFIG_HAS_ETH3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-/*
- * Flash memory map:
- * fff80000 - ffffffff Pri U-Boot (512 KB)
- * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
- * fff00000 - fff3ffff Pri FDT (256KB)
- * fef00000 - ffefffff Pri OS image (16MB)
- * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
- *
- * fbf80000 - fbffffff Sec U-Boot (512 KB)
- * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
- * fbf00000 - fbf3ffff Sec FDT (256KB)
- * faf00000 - fbefffff Sec OS image (16MB)
- * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
- */
-#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
-#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
-#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
-
-#define CONFIG_PROG_UBOOT1 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_UBOOT2 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_BOOT_OS_NET \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "if test -n $fdtaddr; then " \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "bootm $osaddr - $fdtaddr; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi; " \
- "else; " \
- "bootm $osaddr; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS1 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS2 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT1 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT2 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=yes\0" \
- "download_cmd=tftp\0" \
- "console_args=console=ttyS0,115200\0" \
- "root_args=root=/dev/nfs rw\0" \
- "misc_args=ip=on\0" \
- "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
- "bootfile=/home/user/file\0" \
- "osfile=/home/user/board.uImage\0" \
- "fdtfile=/home/user/board.dtb\0" \
- "ubootfile=/home/user/u-boot.bin\0" \
- "fdtaddr=0x1e00000\0" \
- "osaddr=0x1000000\0" \
- "loadaddr=0x1000000\0" \
- "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
- "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
- "prog_os1="CONFIG_PROG_OS1"\0" \
- "prog_os2="CONFIG_PROG_OS2"\0" \
- "prog_fdt1="CONFIG_PROG_FDT1"\0" \
- "prog_fdt2="CONFIG_PROG_FDT2"\0" \
- "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
- "bootcmd_flash1=run set_bootargs; " \
- "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
- "bootcmd_flash2=run set_bootargs; " \
- "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
- "bootcmd=run bootcmd_flash1\0"
-#endif /* __CONFIG_H */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
deleted file mode 100644
index 7262c86908a2..000000000000
--- a/include/configs/xpedite537x.h
+++ /dev/null
@@ -1,496 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-/*
- * xpedite537x board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SYS_BOARD_NAME "XPedite5370"
-#define CONFIG_SYS_FORM_3U_VPX 1
-
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-/*
- * Multicore config
- */
-#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
-#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
-
-/*
- * DDR config
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
-#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
-#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-extern unsigned long get_board_ddr_clk(unsigned long dummy);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_SYS_CCSRBAR 0xef000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/*
- * Diagnostics
- */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_I2C)
-/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
-#define I2C_ADDR_IGNORE_LIST {0x50}
-
-/*
- * Memory map
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
- * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
- * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
- * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
- * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
- * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
- * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
- * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
- * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
- * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
- */
-
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
-
-/*
- * NAND flash configuration
- */
-#define CONFIG_SYS_NAND_BASE 0xef800000
-#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
- CONFIG_SYS_NAND_BASE2}
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_NAND_FSL_ELBC
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000
-#define CONFIG_SYS_FLASH_BASE2 0xf0000000
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
- {0xf7f40000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-/*
- * Chip select configuration
- */
-/* NOR Flash 0 on CS0 */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | \
- BR_V)
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
- OR_GPCM_CSNT | \
- OR_GPCM_XACS | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_8 | \
- OR_GPCM_TRLX | \
- OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-/* NOR Flash 1 on CS1 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
- BR_PS_16 | \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
- (2<<BR_DECC_SHIFT) | \
- BR_PS_8 | \
- BR_MS_FCM | \
- BR_V)
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
- OR_FCM_PGS | \
- OR_FCM_CSCT | \
- OR_FCM_CST | \
- OR_FCM_CHT | \
- OR_FCM_SCY_1 | \
- OR_FCM_TRLX | \
- OR_FCM_EHTR)
-
-/* NAND flash on CS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
- (2<<BR_DECC_SHIFT) | \
- BR_PS_8 | \
- BR_MS_FCM | \
- BR_V)
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-
-/*
- * Use L1 as initial stack
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* PEX8518 slave I2C interface */
-#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
-
-/* I2C DS1631 temperature sensor */
-#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
-
-/* I2C EEPROM - AT24C128B */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/* GPIO */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
-#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
-#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
-#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
-#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
-
-/*
- * PU = pulled high, PD = pulled low
- * I = input, O = output, IO = input/output
- */
-/* PCA9557 @ 0x18*/
-#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
-#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
-#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
-#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
-#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
-#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
-#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
-#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
-
-/* PCA9557 @ 0x1c*/
-#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
-#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
-#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
-#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
-#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
-#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
-#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
-#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
-
-/* PCA9557 @ 0x1e*/
-#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
-#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
-#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
-
-/* PCA9557 @ 0x1f */
-#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
-#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
-#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
-#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
-#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-/* PCIE1 - VPX P1 */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
-/* PCIE2 - PEX8518 */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
-
-/*
- * Networking options
- */
-#define CONFIG_TSEC_TBI
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_ETHPRIME "eTSEC2"
-
-/*
- * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
- * 1000mbps SGMII link
- */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define CONFIG_HAS_ETH0
-
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_PHY_ADDR 2
-#define TSEC2_PHYIDX 0
-#define CONFIG_HAS_ETH1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-/*
- * Flash memory map:
- * fff80000 - ffffffff Pri U-Boot (512 KB)
- * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
- * fff00000 - fff3ffff Pri FDT (256KB)
- * fef00000 - ffefffff Pri OS image (16MB)
- * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
- *
- * f7f80000 - f7ffffff Sec U-Boot (512 KB)
- * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
- * f7f00000 - f7f3ffff Sec FDT (256KB)
- * f6f00000 - f7efffff Sec OS image (16MB)
- * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
- */
-#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
-
-#define CONFIG_PROG_UBOOT1 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_UBOOT2 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_BOOT_OS_NET \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "if test -n $fdtaddr; then " \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "bootm $osaddr - $fdtaddr; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi; " \
- "else; " \
- "bootm $osaddr; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS1 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS2 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT1 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT2 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=yes\0" \
- "download_cmd=tftp\0" \
- "console_args=console=ttyS0,115200\0" \
- "root_args=root=/dev/nfs rw\0" \
- "misc_args=ip=on\0" \
- "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
- "bootfile=/home/user/file\0" \
- "osfile=/home/user/board.uImage\0" \
- "fdtfile=/home/user/board.dtb\0" \
- "ubootfile=/home/user/u-boot.bin\0" \
- "fdtaddr=0x1e00000\0" \
- "osaddr=0x1000000\0" \
- "loadaddr=0x1000000\0" \
- "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
- "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
- "prog_os1="CONFIG_PROG_OS1"\0" \
- "prog_os2="CONFIG_PROG_OS2"\0" \
- "prog_fdt1="CONFIG_PROG_FDT1"\0" \
- "prog_fdt2="CONFIG_PROG_FDT2"\0" \
- "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
- "bootcmd_flash1=run set_bootargs; " \
- "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
- "bootcmd_flash2=run set_bootargs; " \
- "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
- "bootcmd=run bootcmd_flash1\0"
-#endif /* __CONFIG_H */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
deleted file mode 100644
index b9c9ac4ba8df..000000000000
--- a/include/configs/xpedite550x.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010 Extreme Engineering Solutions, Inc.
- * Copyright 2007-2008 Freescale Semiconductor, Inc.
- */
-
-/*
- * xpedite550x board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_SYS_BOARD_NAME "XPedite5500"
-#define CONFIG_SYS_FORM_PMC_XMC 1
-#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
-
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-/*
- * Multicore config
- */
-#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
-#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
-
-/*
- * DDR config
- */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#define SPD_EEPROM_ADDRESS 0x54
-#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-extern unsigned long get_board_ddr_clk(unsigned long dummy);
-#endif
-
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_SYS_CCSRBAR 0xef000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/*
- * Diagnostics
- */
-#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_I2C)
-#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
- CONFIG_SYS_I2C_LM75_ADDR, \
- CONFIG_SYS_I2C_LM90_ADDR, \
- CONFIG_SYS_I2C_PCA953X_ADDR0, \
- CONFIG_SYS_I2C_PCA953X_ADDR2, \
- CONFIG_SYS_I2C_PCA953X_ADDR3, \
- CONFIG_SYS_I2C_RTC_ADDR}
-
-/*
- * Memory map
- * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
- * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
- * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
- * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
- * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
- * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
- * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
- * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
- * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
- */
-
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
-
-/*
- * NAND flash configuration
- */
-#define CONFIG_SYS_NAND_BASE 0xef800000
-#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
-#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
- CONFIG_SYS_NAND_BASE2}
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_NAND_FSL_ELBC
-
-/*
- * NOR flash configuration
- */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000
-#define CONFIG_SYS_FLASH_BASE2 0xf0000000
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
- {0xf7f40000, 0xc0000} }
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-/*
- * Chip select configuration
- */
-/* NOR Flash 0 on CS0 */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
- BR_PS_16 | \
- BR_V)
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
- OR_GPCM_CSNT | \
- OR_GPCM_XACS | \
- OR_GPCM_ACS_DIV2 | \
- OR_GPCM_SCY_8 | \
- OR_GPCM_TRLX | \
- OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-/* NOR Flash 1 on CS1 */
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
- BR_PS_16 | \
- BR_V)
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
- (2<<BR_DECC_SHIFT) | \
- BR_PS_8 | \
- BR_MS_FCM | \
- BR_V)
-
-/* NAND flash on CS2 */
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
- OR_FCM_PGS | \
- OR_FCM_CSCT | \
- OR_FCM_CST | \
- OR_FCM_CHT | \
- OR_FCM_SCY_1 | \
- OR_FCM_TRLX | \
- OR_FCM_EHTR)
-
-/* NAND flash on CS3 */
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
- (2<<BR_DECC_SHIFT) | \
- BR_PS_8 | \
- BR_MS_FCM | \
- BR_V)
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
-
-/*
- * Use L1 as initial stack
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-
-/* I2C DS7505 temperature sensor */
-#define CONFIG_SYS_I2C_LM75_ADDR 0x48
-
-/* I2C ADT7461 temperature sensor */
-#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
-
-/* I2C EEPROM - AT24C128B */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/* GPIO */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
-#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
-#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
-#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
-#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
-
-/*
- * GPIO pin definitions, PU = pulled high, PD = pulled low
- */
-/* PCA9557 @ 0x18*/
-#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
-#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
-#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
-#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
-#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
-#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
-
-/* PCA9557 @ 0x1e*/
-#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
-#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
-#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
-#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
-#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
-#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
-#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
-
-/* PCA9557 @ 0x1f */
-#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
-#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1 - PEX8112 or XMC, depending on build option */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
-/*
- * Networking options
- */
-#define CONFIG_TSEC_TBI
-#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
-#define CONFIG_ETHPRIME "eTSEC2"
-
-/*
- * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
- * 1000mbps SGMII link
- */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
- TBICR_PHY_RESET \
- | TBICR_FULL_DUPLEX \
- | TBICR_SPEED1_SET \
- )
-
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define CONFIG_HAS_ETH0
-
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_PHY_ADDR 2
-#define TSEC2_PHYIDX 0
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_PHY_ADDR 3
-#define TSEC3_PHYIDX 0
-#define CONFIG_HAS_ETH2
-
-/*
- * USB
- */
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
-
-/*
- * Environment Configuration
- */
-
-/*
- * Flash memory map:
- * fff80000 - ffffffff Pri U-Boot (512 KB)
- * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
- * fff00000 - fff3ffff Pri FDT (256KB)
- * fef00000 - ffefffff Pri OS image (16MB)
- * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
- *
- * f7f80000 - f7ffffff Sec U-Boot (512 KB)
- * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
- * f7f00000 - f7f3ffff Sec FDT (256KB)
- * f6f00000 - f7efffff Sec OS image (16MB)
- * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
- */
-#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
-
-#define CONFIG_PROG_UBOOT1 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_UBOOT2 \
- "$download_cmd $loadaddr $ubootfile; " \
- "if test $? -eq 0; then " \
- "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
- "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
- "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
- "if test $? -ne 0; then " \
- "echo PROGRAM FAILED; " \
- "else; " \
- "echo PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_BOOT_OS_NET \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "if test -n $fdtaddr; then " \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "bootm $osaddr - $fdtaddr; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi; " \
- "else; " \
- "bootm $osaddr; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS1 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_OS2 \
- "$download_cmd $osaddr $osfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
- "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo OS PROGRAM FAILED; " \
- "else; " \
- "echo OS PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo OS DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT1 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_PROG_FDT2 \
- "$download_cmd $fdtaddr $fdtfile; " \
- "if test $? -eq 0; then " \
- "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
- "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
- "if test $? -ne 0; then " \
- "echo FDT PROGRAM FAILED; " \
- "else; " \
- "echo FDT PROGRAM SUCCEEDED; " \
- "fi; " \
- "else; " \
- "echo FDT DOWNLOAD FAILED; " \
- "fi;"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=yes\0" \
- "download_cmd=tftp\0" \
- "console_args=console=ttyS0,115200\0" \
- "root_args=root=/dev/nfs rw\0" \
- "misc_args=ip=on\0" \
- "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
- "bootfile=/home/user/file\0" \
- "osfile=/home/user/board.uImage\0" \
- "fdtfile=/home/user/board.dtb\0" \
- "ubootfile=/home/user/u-boot.bin\0" \
- "fdtaddr=0x1e00000\0" \
- "osaddr=0x1000000\0" \
- "loadaddr=0x1000000\0" \
- "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
- "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
- "prog_os1="CONFIG_PROG_OS1"\0" \
- "prog_os2="CONFIG_PROG_OS2"\0" \
- "prog_fdt1="CONFIG_PROG_FDT1"\0" \
- "prog_fdt2="CONFIG_PROG_FDT2"\0" \
- "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
- "bootcmd_flash1=run set_bootargs; " \
- "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
- "bootcmd_flash2=run set_bootargs; " \
- "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
- "bootcmd=run bootcmd_flash1\0"
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 20/27] ppc: Remove xpedite boards
2021-05-15 1:34 ` [PATCH 20/27] ppc: Remove xpedite boards Tom Rini
@ 2021-05-17 16:49 ` Peter Tyser
2021-07-08 2:53 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Peter Tyser @ 2021-05-17 16:49 UTC (permalink / raw)
To: u-boot
Acked-by: Peter Tyser <ptyser@xes-inc.com>
----- Original Message -----
> From: "Tom Rini" <trini@konsulko.com>
> To: "U-Boot Mailing List" <u-boot@lists.denx.de>
> Cc: "ptyser" <ptyser@xes-inc.com>
> Sent: Friday, May 14, 2021 8:34:25 PM
> Subject: [PATCH 20/27] ppc: Remove xpedite boards
> These boards have not been converted to CONFIG_DM_PCI by the deadline and is
> also missing conversion to CONFIG_DM. Remove them. As this includes
> the last ARCH_MPC8572 platform, remove that as well.
>
> Cc: Peter Tyser <ptyser@xes-inc.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> arch/powerpc/cpu/mpc85xx/Kconfig | 40 +-
> arch/powerpc/cpu/mpc85xx/Makefile | 1 -
> arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c | 74 ---
> arch/powerpc/cpu/mpc86xx/Kconfig | 5 -
> arch/powerpc/include/asm/fsl_law.h | 4 +-
> arch/powerpc/include/asm/immap_85xx.h | 2 +-
> board/xes/common/Makefile | 1 -
> board/xes/xpedite517x/Kconfig | 12 -
> board/xes/xpedite517x/MAINTAINERS | 6 -
> board/xes/xpedite517x/Makefile | 8 -
> board/xes/xpedite517x/ddr.c | 124 -----
> board/xes/xpedite517x/law.c | 27 -
> board/xes/xpedite517x/xpedite517x.c | 86 ---
> board/xes/xpedite520x/Kconfig | 12 -
> board/xes/xpedite520x/MAINTAINERS | 6 -
> board/xes/xpedite520x/Makefile | 11 -
> board/xes/xpedite520x/ddr.c | 68 ---
> board/xes/xpedite520x/law.c | 26 -
> board/xes/xpedite520x/tlb.c | 68 ---
> board/xes/xpedite520x/xpedite520x.c | 82 ---
> board/xes/xpedite537x/Kconfig | 12 -
> board/xes/xpedite537x/MAINTAINERS | 6 -
> board/xes/xpedite537x/Makefile | 11 -
> board/xes/xpedite537x/ddr.c | 234 --------
> board/xes/xpedite537x/law.c | 25 -
> board/xes/xpedite537x/tlb.c | 82 ---
> board/xes/xpedite537x/xpedite537x.c | 82 ---
> board/xes/xpedite550x/Kconfig | 12 -
> board/xes/xpedite550x/MAINTAINERS | 6 -
> board/xes/xpedite550x/Makefile | 8 -
> board/xes/xpedite550x/ddr.c | 135 -----
> board/xes/xpedite550x/law.c | 25 -
> board/xes/xpedite550x/tlb.c | 81 ---
> board/xes/xpedite550x/xpedite550x.c | 82 ---
> configs/xpedite517x_defconfig | 54 --
> configs/xpedite520x_defconfig | 54 --
> configs/xpedite537x_defconfig | 57 --
> configs/xpedite550x_defconfig | 57 --
> drivers/ddr/fsl/Kconfig | 1 -
> env/Kconfig | 2 +-
> include/configs/xpedite517x.h | 646 ----------------------
> include/configs/xpedite520x.h | 445 ---------------
> include/configs/xpedite537x.h | 496 -----------------
> include/configs/xpedite550x.h | 494 -----------------
> 44 files changed, 5 insertions(+), 3765 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
> delete mode 100644 board/xes/xpedite517x/Kconfig
> delete mode 100644 board/xes/xpedite517x/MAINTAINERS
> delete mode 100644 board/xes/xpedite517x/Makefile
> delete mode 100644 board/xes/xpedite517x/ddr.c
> delete mode 100644 board/xes/xpedite517x/law.c
> delete mode 100644 board/xes/xpedite517x/xpedite517x.c
> delete mode 100644 board/xes/xpedite520x/Kconfig
> delete mode 100644 board/xes/xpedite520x/MAINTAINERS
> delete mode 100644 board/xes/xpedite520x/Makefile
> delete mode 100644 board/xes/xpedite520x/ddr.c
> delete mode 100644 board/xes/xpedite520x/law.c
> delete mode 100644 board/xes/xpedite520x/tlb.c
> delete mode 100644 board/xes/xpedite520x/xpedite520x.c
> delete mode 100644 board/xes/xpedite537x/Kconfig
> delete mode 100644 board/xes/xpedite537x/MAINTAINERS
> delete mode 100644 board/xes/xpedite537x/Makefile
> delete mode 100644 board/xes/xpedite537x/ddr.c
> delete mode 100644 board/xes/xpedite537x/law.c
> delete mode 100644 board/xes/xpedite537x/tlb.c
> delete mode 100644 board/xes/xpedite537x/xpedite537x.c
> delete mode 100644 board/xes/xpedite550x/Kconfig
> delete mode 100644 board/xes/xpedite550x/MAINTAINERS
> delete mode 100644 board/xes/xpedite550x/Makefile
> delete mode 100644 board/xes/xpedite550x/ddr.c
> delete mode 100644 board/xes/xpedite550x/law.c
> delete mode 100644 board/xes/xpedite550x/tlb.c
> delete mode 100644 board/xes/xpedite550x/xpedite550x.c
> delete mode 100644 configs/xpedite517x_defconfig
> delete mode 100644 configs/xpedite520x_defconfig
> delete mode 100644 configs/xpedite537x_defconfig
> delete mode 100644 configs/xpedite550x_defconfig
> delete mode 100644 include/configs/xpedite517x.h
> delete mode 100644 include/configs/xpedite520x.h
> delete mode 100644 include/configs/xpedite537x.h
> delete mode 100644 include/configs/xpedite550x.h
>
<snip>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 20/27] ppc: Remove xpedite boards
2021-05-15 1:34 ` [PATCH 20/27] ppc: Remove xpedite boards Tom Rini
2021-05-17 16:49 ` Peter Tyser
@ 2021-07-08 2:53 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:53 UTC (permalink / raw)
To: u-boot; +Cc: Peter Tyser
[-- Attachment #1: Type: text/plain, Size: 457 bytes --]
On Fri, May 14, 2021 at 09:34:25PM -0400, Tom Rini wrote:
> These boards have not been converted to CONFIG_DM_PCI by the deadline and is
> also missing conversion to CONFIG_DM. Remove them. As this includes
> the last ARCH_MPC8572 platform, remove that as well.
>
> Cc: Peter Tyser <ptyser@xes-inc.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Acked-by: Peter Tyser <ptyser@xes-inc.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 21/27] ppc: Remove sbc8641d board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (18 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 20/27] ppc: Remove xpedite boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-15 15:20 ` Simon Glass
` (2 more replies)
2021-05-15 1:34 ` [PATCH 22/27] ppc: Remove MPC8315ERDB board Tom Rini
` (6 subsequent siblings)
26 siblings, 3 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. This is also the last
of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
.azure-pipelines.yml | 2 +-
MAINTAINERS | 6 -
README | 3 +-
arch/powerpc/Kconfig | 7 -
arch/powerpc/cpu/mpc86xx/Kconfig | 52 -
arch/powerpc/cpu/mpc86xx/Makefile | 24 -
arch/powerpc/cpu/mpc86xx/cache.S | 332 ------
arch/powerpc/cpu/mpc86xx/config.mk | 6 -
arch/powerpc/cpu/mpc86xx/cpu.c | 207 ----
arch/powerpc/cpu/mpc86xx/cpu_init.c | 104 --
arch/powerpc/cpu/mpc86xx/fdt.c | 52 -
arch/powerpc/cpu/mpc86xx/interrupts.c | 116 --
arch/powerpc/cpu/mpc86xx/mp.c | 130 ---
arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 87 --
arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 96 --
arch/powerpc/cpu/mpc86xx/release.S | 149 ---
arch/powerpc/cpu/mpc86xx/speed.c | 134 ---
arch/powerpc/cpu/mpc86xx/start.S | 982 -----------------
arch/powerpc/cpu/mpc86xx/traps.c | 199 ----
arch/powerpc/cpu/mpc86xx/u-boot.lds | 77 --
arch/powerpc/include/asm/config.h | 4 -
arch/powerpc/include/asm/config_mpc86xx.h | 9 -
arch/powerpc/include/asm/fsl_law.h | 7 -
arch/powerpc/include/asm/fsl_pci.h | 2 +-
arch/powerpc/include/asm/immap_86xx.h | 1221 ---------------------
arch/powerpc/include/asm/ppc.h | 4 -
board/sbc8641d/Kconfig | 9 -
board/sbc8641d/MAINTAINERS | 6 -
board/sbc8641d/Makefile | 8 -
board/sbc8641d/README | 49 -
board/sbc8641d/ddr.c | 53 -
board/sbc8641d/law.c | 39 -
board/sbc8641d/sbc8641d.c | 268 -----
configs/sbc8641d_defconfig | 39 -
doc/git-mailrc | 1 -
drivers/ddr/fsl/Kconfig | 12 +-
drivers/ddr/fsl/Makefile | 1 -
drivers/ddr/fsl/mpc86xx_ddr.c | 84 --
env/Kconfig | 2 +-
include/configs/sbc8641d.h | 509 ---------
include/post.h | 5 -
41 files changed, 6 insertions(+), 5091 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc86xx/Kconfig
delete mode 100644 arch/powerpc/cpu/mpc86xx/Makefile
delete mode 100644 arch/powerpc/cpu/mpc86xx/cache.S
delete mode 100644 arch/powerpc/cpu/mpc86xx/config.mk
delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu_init.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/fdt.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/interrupts.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/mp.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/release.S
delete mode 100644 arch/powerpc/cpu/mpc86xx/speed.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/start.S
delete mode 100644 arch/powerpc/cpu/mpc86xx/traps.c
delete mode 100644 arch/powerpc/cpu/mpc86xx/u-boot.lds
delete mode 100644 arch/powerpc/include/asm/config_mpc86xx.h
delete mode 100644 arch/powerpc/include/asm/immap_86xx.h
delete mode 100644 board/sbc8641d/Kconfig
delete mode 100644 board/sbc8641d/MAINTAINERS
delete mode 100644 board/sbc8641d/Makefile
delete mode 100644 board/sbc8641d/README
delete mode 100644 board/sbc8641d/ddr.c
delete mode 100644 board/sbc8641d/law.c
delete mode 100644 board/sbc8641d/sbc8641d.c
delete mode 100644 configs/sbc8641d_defconfig
delete mode 100644 drivers/ddr/fsl/mpc86xx_ddr.c
delete mode 100644 include/configs/sbc8641d.h
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 59e99b8894c5..8a567832ddac 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -415,7 +415,7 @@ jobs:
t208xrdb_corenet_ds:
BUILDMAN: "t208xrdb corenet_ds"
fsl_ppc:
- BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
+ BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
t102x:
BUILDMAN: "t102*"
p1_p2_rdb_pc:
diff --git a/MAINTAINERS b/MAINTAINERS
index 20092cb36740..7e36eb56a3af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -973,12 +973,6 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
-POWERPC MPC86XX
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-T: git https://source.denx.de/u-boot/custodians/u-boot-mpc86xx.git
-F: arch/powerpc/cpu/mpc86xx/
-
RISC-V
M: Rick Chen <rick@andestech.com>
S: Maintained
diff --git a/README b/README
index ad13092bbb7a..63568dc43c74 100644
--- a/README
+++ b/README
@@ -423,8 +423,7 @@ The following options need to be configured:
CONFIG_SYS_FSL_DDR
Freescale DDR driver in use. This type of DDR controller is
- found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
- SoCs.
+ found in mpc83xx, mpc85xx as well as some ARM core SoCs.
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 133447648cc6..737bdd8edb41 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -25,12 +25,6 @@ config MPC85xx
imply CMD_IRQ
imply USB_EHCI_HCD if USB
-config MPC86xx
- bool "MPC86xx"
- select SYS_FSL_DDR
- select SYS_FSL_DDR_BE
- imply CMD_REGINFO
-
config MPC8xx
bool "MPC8xx"
select BOARD_EARLY_INIT_F
@@ -47,7 +41,6 @@ config HIGH_BATS
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
-source "arch/powerpc/cpu/mpc86xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
source "arch/powerpc/lib/Kconfig"
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
deleted file mode 100644
index 1ee87038bed4..000000000000
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-menu "mpc86xx CPU"
- depends on MPC86xx
-
-config SYS_CPU
- default "mpc86xx"
-
-choice
- prompt "Target select"
- optional
-
-config TARGET_SBC8641D
- bool "Support sbc8641d"
- select ARCH_MPC8641
- select BOARD_EARLY_INIT_F
-
-endchoice
-
-config ARCH_MPC8610
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_DDR2
-
-config ARCH_MPC8641
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_DDR2
-
-config FSL_LAW
- bool
- help
- Use Freescale common code for Local Access Window
-
-config SYS_CCSRBAR_DEFAULT
- hex "Default CCSRBAR address"
- default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
- help
- Default value of CCSRBAR comes from power-on-reset. It
- is fixed on each SoC. Some SoCs can have different value
- if changed by pre-boot regime. The value here must match
- the current value in SoC. If not sure, do not change.
-config SYS_FSL_NUM_LAWS
- int "Number of local access windows"
- default 10 if ARCH_MPC8610 || ARCH_MPC8641
- help
- Number of local access windows. This is fixed per SoC.
- If not sure, do not change.
-
-source "board/sbc8641d/Kconfig"
-
-endmenu
diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
deleted file mode 100644
index 6e12be6a3f24..000000000000
--- a/arch/powerpc/cpu/mpc86xx/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2002,2003 Motorola Inc.
-# Xianghua Xiao,X.Xiao at motorola.com
-#
-# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
-# Jeff Brown
-#
-
-extra-y = start.o
-extra-y += traps.o
-
-obj-y += cache.o
-obj-$(CONFIG_MP) += release.o
-
-obj-y += cpu.o
-obj-y += cpu_init.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
-obj-y += interrupts.o
-obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o
-obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o
-obj-y += speed.o
diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S
deleted file mode 100644
index 34968c604d7b..000000000000
--- a/arch/powerpc/cpu/mpc86xx/cache.S
+++ /dev/null
@@ -1,332 +0,0 @@
-#include <config.h>
-#include <mpc86xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#ifndef CACHE_LINE_SIZE
-# define CACHE_LINE_SIZE L1_CACHE_BYTES
-#endif
-
-#if CACHE_LINE_SIZE == 128
-#define LG_CACHE_LINE_SIZE 7
-#elif CACHE_LINE_SIZE == 32
-#define LG_CACHE_LINE_SIZE 5
-#elif CACHE_LINE_SIZE == 16
-#define LG_CACHE_LINE_SIZE 4
-#elif CACHE_LINE_SIZE == 8
-#define LG_CACHE_LINE_SIZE 3
-#else
-# error "Invalid cache line size!"
-#endif
-
-/*
- * Most of this code is taken from 74xx_7xx/cache.S
- * and then cleaned up a bit
- */
-
-/*
- * Invalidate L1 instruction cache.
- */
-_GLOBAL(invalidate_l1_instruction_cache)
- /* use invalidate-all bit in HID0 */
- mfspr r3,HID0
- ori r3,r3,HID0_ICFI
- mtspr HID0,r3
- isync
- blr
-
-/*
- * Invalidate L1 data cache.
- */
-_GLOBAL(invalidate_l1_data_cache)
- mfspr r3,HID0
- ori r3,r3,HID0_DCFI
- mtspr HID0,r3
- isync
- blr
-
-/*
- * Flush data cache.
- */
-_GLOBAL(flush_dcache)
- lis r3,0
- lis r5,CACHE_LINE_SIZE
-flush:
- cmp 0,1,r3,r5
- bge done
- lwz r5,0(r3)
- lis r5,CACHE_LINE_SIZE
- addi r3,r3,0x4
- b flush
-done:
- blr
-/*
- * Write any modified data cache blocks out to memory
- * and invalidate the corresponding instruction cache blocks.
- * This is a no-op on the 601.
- *
- * flush_icache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(flush_icache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5
- subf r4,r3,r4
- add r4,r4,r5
- srwi. r4,r4,LG_CACHE_LINE_SIZE
- beqlr
- mtctr r4
- mr r6,r3
-1: dcbst 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- mtctr r4
-2: icbi 0,r6
- addi r6,r6,CACHE_LINE_SIZE
- bdnz 2b
- sync /* additional sync needed on g4 */
- isync
- blr
-/*
- * Write any modified data cache blocks out to memory.
- * Does not invalidate the corresponding cache lines (especially for
- * any corresponding instruction cache).
- *
- * clean_dcache_range(unsigned long start, unsigned long stop)
- */
-_GLOBAL(clean_dcache_range)
- li r5,CACHE_LINE_SIZE-1
- andc r3,r3,r5 /* align r3 down to cache line */
- subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
- add r4,r4,r5 /* r4 += cache_line_size-1 */
- srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
- beqlr /* if r4 == 0 return */
- mtctr r4 /* ctr = r4 */
-
- sync
-1: dcbst 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync /* wait for dcbst's to get to ram */
- blr
-
-/*
- * Flush a particular page from the data cache to RAM.
- * Note: this is necessary because the instruction cache does *not*
- * snoop from the data cache.
- *
- * void __flush_page_to_ram(void *page)
- */
-_GLOBAL(__flush_page_to_ram)
- rlwinm r3,r3,0,0,19 /* Get page base address */
- li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
- mtctr r4
- mr r6,r3
-0: dcbst 0,r3 /* Write line to ram */
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 0b
- sync
- mtctr r4
-1: icbi 0,r6
- addi r6,r6,CACHE_LINE_SIZE
- bdnz 1b
- sync
- isync
- blr
-
-/*
- * Flush a particular page from the instruction cache.
- * Note: this is necessary because the instruction cache does *not*
- * snoop from the data cache.
- *
- * void __flush_icache_page(void *page)
- */
-_GLOBAL(__flush_icache_page)
- li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
- mtctr r4
-1: icbi 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- sync
- isync
- blr
-
-/*
- * Clear a page using the dcbz instruction, which doesn't cause any
- * memory traffic (except to write out any cache lines which get
- * displaced). This only works on cacheable memory.
- */
-_GLOBAL(clear_page)
- li r0,4096/CACHE_LINE_SIZE
- mtctr r0
-1: dcbz 0,r3
- addi r3,r3,CACHE_LINE_SIZE
- bdnz 1b
- blr
-
-/*
- * Enable L1 Instruction cache
- */
-_GLOBAL(icache_enable)
- mfspr r3, HID0
- li r5, HID0_ICFI|HID0_ILOCK
- andc r3, r3, r5
- ori r3, r3, HID0_ICE
- ori r5, r3, HID0_ICFI
- mtspr HID0, r5
- mtspr HID0, r3
- isync
- blr
-
-/*
- * Disable L1 Instruction cache
- */
-_GLOBAL(icache_disable)
- mflr r4
- bl invalidate_l1_instruction_cache /* uses r3 */
- sync
- mtlr r4
- mfspr r3, HID0
- li r5, 0
- ori r5, r5, HID0_ICE
- andc r3, r3, r5
- mtspr HID0, r3
- isync
- blr
-
-/*
- * Is instruction cache enabled?
- */
-_GLOBAL(icache_status)
- mfspr r3, HID0
- andi. r3, r3, HID0_ICE
- blr
-
-
-_GLOBAL(l1dcache_enable)
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
- sync
- blr
-
-/*
- * Enable data cache(s) - L1 and optionally L2
- * Calls l2cache_enable. LR saved in r5
- */
-_GLOBAL(dcache_enable)
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
- sync
-#ifdef CONFIG_SYS_L2
- mflr r5
- bl l2cache_enable /* uses r3 and r4 */
- sync
- mtlr r5
-#endif
- blr
-
-
-/*
- * Disable data cache(s) - L1 and optionally L2
- * Calls flush_dcache and l2cache_disable_no_flush.
- * LR saved in r4
- */
-_GLOBAL(dcache_disable)
- mflr r4 /* save link register */
- bl flush_dcache /* uses r3 and r5 */
- sync
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- li r5, HID0_DCE|HID0_DCFI
- andc r3, r3, r5 /* no enable, no invalidate */
- mtspr HID0, r3
- sync
-#ifdef CONFIG_SYS_L2
- bl l2cache_disable_no_flush /* uses r3 */
-#endif
- mtlr r4 /* restore link register */
- blr
-
-/*
- * Is data cache enabled?
- */
-_GLOBAL(dcache_status)
- mfspr r3, HID0
- andi. r3, r3, HID0_DCE
- blr
-
-/*
- * Invalidate L2 cache using L2I, assume L2 is enabled
- */
-_GLOBAL(l2cache_invalidate)
- mfspr r3, l2cr
- rlwinm. r3, r3, 0, 0, 0
- beq 1f
-
- mfspr r3, l2cr
- rlwinm r3, r3, 0, 1, 31
-
-#ifdef CONFIG_ALTIVEC
- dssall
-#endif
- sync
- mtspr l2cr, r3
- sync
-1: mfspr r3, l2cr
- oris r3, r3, L2CR_L2I at h
- mtspr l2cr, r3
-
-invl2:
- mfspr r3, l2cr
- andis. r3, r3, L2CR_L2I at h
- bne invl2
- blr
-
-/*
- * Enable L2 cache
- * Calls l2cache_invalidate. LR is saved in r4
- */
-_GLOBAL(l2cache_enable)
- mflr r4 /* save link register */
- bl l2cache_invalidate /* uses r3 */
- sync
- lis r3, L2_ENABLE at h
- ori r3, r3, L2_ENABLE at l
- mtspr l2cr, r3
- isync
- mtlr r4 /* restore link register */
- blr
-
-/*
- * Disable L2 cache
- * Calls flush_dcache. LR is saved in r4
- */
-_GLOBAL(l2cache_disable)
- mflr r4 /* save link register */
- bl flush_dcache /* uses r3 and r5 */
- sync
- mtlr r4 /* restore link register */
-l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
- lis r3, L2_INIT at h
- ori r3, r3, L2_INIT at l
- mtspr l2cr, r3
- isync
- blr
diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk
deleted file mode 100644
index 5db5b0b4ed7e..000000000000
--- a/arch/powerpc/cpu/mpc86xx/config.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2004 Freescale Semiconductor.
-# Jeff Brown
-
-PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
deleted file mode 100644
index 98b42bff7a3b..000000000000
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <log.h>
-#include <time.h>
-#include <vsprintf.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <mpc86xx.h>
-#include <asm/fsl_law.h>
-#include <asm/ppc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Default board reset function
- */
-static void
-__board_reset(void)
-{
- /* Do nothing */
-}
-void board_reset(void) __attribute__((weak, alias("__board_reset")));
-
-
-int
-checkcpu(void)
-{
- sys_info_t sysinfo;
- uint pvr, svr;
- uint major, minor;
- char buf1[32], buf2[32];
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- struct cpu_type *cpu;
- uint msscr0 = mfspr(MSSCR0);
-
- svr = get_svr();
- major = SVR_MAJ(svr);
- minor = SVR_MIN(svr);
-
- if (cpu_numcores() > 1) {
-#ifndef CONFIG_MP
- puts("Unicore software on multiprocessor system!!\n"
- "To enable mutlticore build define CONFIG_MP\n");
-#endif
- }
- puts("CPU: ");
-
- cpu = gd->arch.cpu;
-
- puts(cpu->name);
-
- printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
- puts("Core: ");
-
- pvr = get_pvr();
- major = PVR_E600_MAJ(pvr);
- minor = PVR_E600_MIN(pvr);
-
- printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
- if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
- puts("\n Core1Translation Enabled");
- debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
-
- printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
-
- get_sys_info(&sysinfo);
-
- puts("Clock Configuration:\n");
- printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
- printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
- printf(" DDR:%-4s MHz (%s MT/s data rate), ",
- strmhz(buf1, sysinfo.freq_systembus / 2),
- strmhz(buf2, sysinfo.freq_systembus));
-
- if (sysinfo.freq_localbus > LCRR_CLKDIV) {
- printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
- } else {
- printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
- sysinfo.freq_localbus);
- }
-
- puts("L1: D-cache 32 KiB enabled\n");
- puts(" I-cache 32 KiB enabled\n");
-
- puts("L2: ");
- if (get_l2cr() & 0x80000000) {
-#if defined(CONFIG_ARCH_MPC8610)
- puts("256");
-#elif defined(CONFIG_ARCH_MPC8641)
- puts("512");
-#endif
- puts(" KiB enabled\n");
- } else {
- puts("Disabled\n");
- }
-
- return 0;
-}
-
-
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
-
- /* Attempt board-specific reset */
- board_reset();
-
- /* Next try asserting HRESET_REQ */
- out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
-
- while (1)
- ;
-
- return 1;
-}
-
-
-/*
- * Get timebase clock frequency
- */
-unsigned long
-get_tbclk(void)
-{
- sys_info_t sys_info;
-
- get_sys_info(&sys_info);
- return (sys_info.freq_systembus + 3L) / 4L;
-}
-
-
-#if defined(CONFIG_WATCHDOG)
-void
-watchdog_reset(void)
-{
-#if defined(CONFIG_ARCH_MPC8610)
- /*
- * This actually feed the hard enabled watchdog.
- */
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_wdt_t *wdt = &immap->im_wdt;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- u32 tmp = gur->pordevsr;
-
- if (tmp & 0x4000) {
- wdt->swsrr = 0x556c;
- wdt->swsrr = 0xaa39;
- }
-#endif
-}
-#endif /* CONFIG_WATCHDOG */
-
-/*
- * Print out the state of various machine registers.
- * Currently prints out LAWs, BR0/OR0, and BATs
- */
-void print_reginfo(void)
-{
- print_bats();
- print_laws();
- print_lbc_regs();
-}
-
-/*
- * Set the DDR BATs to reflect the actual size of DDR.
- *
- * dram_size is the actual size of DDR, in bytes
- *
- * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
- * are using a single BAT to cover DDR.
- *
- * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
- * is not defined) then we might have a situation where U-Boot will attempt
- * to relocated itself outside of the region mapped by DBAT0.
- * This will cause a machine check.
- *
- * Currently we are limited to power of two sized DDR since we only use a
- * single bat. If a non-power of two size is used that is less than
- * CONFIG_MAX_MEM_MAPPED u-boot will crash.
- *
- */
-void setup_ddr_bat(phys_addr_t dram_size)
-{
- unsigned long batu, bl;
-
- bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
-
- if (BATU_SIZE(bl) != dram_size) {
- u64 sz = (u64)dram_size - BATU_SIZE(bl);
- print_size(sz, " left unmapped\n");
- }
-
- batu = bl | BATU_VS | BATU_VP;
- write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
- write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
-}
diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c
deleted file mode 100644
index 73779f862c2a..000000000000
--- a/arch/powerpc/cpu/mpc86xx/cpu_init.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- */
-
-/*
- * cpu_init.c - low level cpu init
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <common.h>
-#include <init.h>
-#include <mpc86xx.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/mp.h>
-
-extern void srio_init(void);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Breathe some life into the CPU...
- *
- * Set up the memory map
- * initialize a bunch of registers
- */
-
-void cpu_init_f(void)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
-
-#ifdef CONFIG_FSL_LAW
- init_laws();
-#endif
-
- setup_bats();
-
- init_early_memctl_regs();
-
-#if defined(CONFIG_FSL_DMA)
- dma_init();
-#endif
-
- /* enable the timebase bit in HID0 */
- set_hid0(get_hid0() | 0x4000000);
-
- /* enable EMCP, SYNCBE | ABE bits in HID1 */
- set_hid1(get_hid1() | 0x80000C00);
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
- /* needs to be in ram since code uses global static vars */
- fsl_serdes_init();
-
-#ifdef CONFIG_SYS_SRIO
- srio_init();
-#endif
-
-#if defined(CONFIG_MP)
- setup_mp();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_ADDR_MAP
-/* Initialize address mapping array */
-void init_addr_map(void)
-{
- int i;
- ppc_bat_t bat = DBAT0;
- phys_size_t size;
- unsigned long upper, lower;
-
- for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
- if (read_bat(bat, &upper, &lower) != -1) {
- if (!BATU_VALID(upper))
- size = 0;
- else
- size = BATU_SIZE(upper);
- addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
- size, i);
- }
-#ifdef CONFIG_HIGH_BATS
- /* High bats are not contiguous with low BAT numbers */
- if (bat == DBAT3)
- bat = DBAT4 - 1;
-#endif
- }
-}
-#endif
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
deleted file mode 100644
index 1313d8adde66..000000000000
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008, 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/global_data.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/mp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void ft_fixup_num_cores(void *blob);
-extern void ft_srio_setup(void *blob);
-
-void ft_cpu_setup(void *blob, struct bd_info *bd)
-{
-#ifdef CONFIG_MP
- int off;
- u32 bootpg = determine_mp_bootpg(NULL);
-#endif
-
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", bd->bi_busfreq / 4, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "bus-frequency", bd->bi_busfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", bd->bi_intfreq, 1);
- do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
- "bus-frequency", bd->bi_busfreq, 1);
-
- fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
-
-#ifdef CONFIG_SYS_NS16550
- do_fixup_by_compat_u32(blob, "ns16550",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
-#endif
-
-#ifdef CONFIG_MP
- /* Reserve the boot page so OSes dont use it */
- off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
- if (off < 0)
- printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
-
- ft_fixup_num_cores(blob);
-#endif
-
-#ifdef CONFIG_SYS_SRIO
- ft_srio_setup(blob);
-#endif
-}
diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c
deleted file mode 100644
index 5a916600ed62..000000000000
--- a/arch/powerpc/cpu/mpc86xx/interrupts.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * (C) Copyright 2002 (440 port)
- * Scott McNutt, Artesyn Communication Producs, smcnutt at artsyncp.com
- *
- * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
- * Xianghua Xiao (X.Xiao at motorola.com)
- *
- * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- */
-
-#include <common.h>
-#include <irq_func.h>
-#include <log.h>
-#include <mpc86xx.h>
-#include <command.h>
-#include <time.h>
-#include <asm/processor.h>
-#ifdef CONFIG_POST
-#include <post.h>
-#endif
-#include <asm/ptrace.h>
-
-void interrupt_init_cpu(unsigned *decrementer_count)
-{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_pic_t *pic = &immr->im_pic;
-
-#ifdef CONFIG_POST
- /*
- * The POST word is stored in the PIC's TFRR register which gets
- * cleared when the PIC is reset. Save it off so we can restore it
- * later.
- */
- ulong post_word = post_word_load();
-#endif
-
- pic->gcr = MPC86xx_PICGCR_RST;
- while (pic->gcr & MPC86xx_PICGCR_RST)
- ;
- pic->gcr = MPC86xx_PICGCR_MODE;
-
- *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
- debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
- (get_tbclk() / 1000000),
- *decrementer_count);
-
-#ifdef CONFIG_INTERRUPTS
-
- pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
- debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
-
- pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
- debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
-
- pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
- debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
-
-#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
- pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
- debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
-#endif
-#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
- pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
- debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
-#endif
-
- pic->ctpr = 0; /* 40080 clear current task priority register */
-#endif
-
-#ifdef CONFIG_POST
- post_word_store(post_word);
-#endif
-}
-
-/*
- * timer_interrupt - gets called when the decrementer overflows,
- * with interrupts disabled.
- * Trivial implementation - no need to be really accurate.
- */
-void timer_interrupt_cpu(struct pt_regs *regs)
-{
- /* nothing to do here */
-}
-
-/*
- * Install and free a interrupt handler. Not implemented yet.
- */
-void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
-{
-}
-
-void irq_free_handler(int vec)
-{
-}
-
-/*
- * irqinfo - print information about PCI devices,not implemented.
- */
-int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- return 0;
-}
-
-/*
- * Handle external interrupts
- */
-void external_interrupt(struct pt_regs *regs)
-{
- puts("external_interrupt(oops!)\n");
-}
diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
deleted file mode 100644
index e6795e06c98b..000000000000
--- a/arch/powerpc/cpu/mpc86xx/mp.c
+++ /dev/null
@@ -1,130 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <ioports.h>
-#include <lmb.h>
-#include <asm/io.h>
-#include <asm/mp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cpu_reset(u32 nr)
-{
- /* dummy function so common/cmd_mp.c will build
- * should be implemented in the future, when cpu_release()
- * is supported. Be aware there may be a similiar bug
- * as exists on MPC85xx w/its PIC having a timing window
- * associated to resetting the core */
- return 1;
-}
-
-int cpu_status(u32 nr)
-{
- /* dummy function so common/cmd_mp.c will build */
- return 0;
-}
-
-int cpu_disable(u32 nr)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
-
- switch (nr) {
- case 0:
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
- break;
- case 1:
- setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
- break;
- default:
- printf("Invalid cpu number for disable %d\n", nr);
- return 1;
- }
-
- return 0;
-}
-
-int is_core_disabled(int nr) {
- immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- ccsr_gur_t *gur = &immap->im_gur;
- u32 devdisr = in_be32(&gur->devdisr);
-
- switch (nr) {
- case 0:
- return (devdisr & MPC86xx_DEVDISR_CPU0);
- case 1:
- return (devdisr & MPC86xx_DEVDISR_CPU1);
- default:
- printf("Invalid cpu number for disable %d\n", nr);
- }
-
- return 0;
-}
-
-int cpu_release(u32 nr, int argc, char *const argv[])
-{
- /* dummy function so common/cmd_mp.c will build
- * should be implemented in the future */
- return 1;
-}
-
-u32 determine_mp_bootpg(unsigned int *pagesize)
-{
- if (pagesize)
- *pagesize = 4096;
-
- /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
- if ((u64)gd->ram_size > 0xfffff000)
- return (0xfff00000);
-
- return (gd->ram_size - (1024 * 1024));
-}
-
-void cpu_mp_lmb_reserve(struct lmb *lmb)
-{
- u32 bootpg = determine_mp_bootpg(NULL);
-
- /* tell u-boot we stole a page */
- lmb_reserve(lmb, bootpg, 4096);
-}
-
-/*
- * Copy the code for other cpus to execute into an
- * aligned location accessible via BPTR
- */
-void setup_mp(void)
-{
- extern ulong __secondary_start_page;
- ulong fixup = (ulong)&__secondary_start_page;
- u32 bootpg = determine_mp_bootpg(NULL);
- u32 bootpg_va;
-
- if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
- /* We're not covered by the DDR mapping, set up BAT */
- write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
- BATU_VS | BATU_VP,
- bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
- bootpg_va = CONFIG_SYS_SCRATCH_VA;
- } else {
- bootpg_va = bootpg;
- }
-
- memcpy((void *)bootpg_va, (void *)fixup, 4096);
- flush_cache(bootpg_va, 4096);
-
- /* remove the temporary BAT mapping */
- if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
- write_bat(DBAT7, 0, 0);
-
- /* If the physical location of bootpg is not at fff00000, set BPTR */
- if (bootpg != 0xfff00000)
- out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
- (bootpg >> 12));
-}
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
deleted file mode 100644
index ecc88ba43746..000000000000
--- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 4
-#define SRDS2_MAX_LANES 4
-
-static u32 serdes1_prtcl_map, serdes2_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0x7] = {NONE, NONE, NONE, NONE},
-};
-
-static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
- [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
- [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
- [0x7] = {NONE, NONE, NONE, NONE},
-};
-
-int is_serdes_configured(enum srds_prtcl device)
-{
- int ret;
-
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- ret = (1 << device) & serdes1_prtcl_map;
-
- if (ret)
- return ret;
-
- if (!(serdes2_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << device) & serdes2_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- ccsr_gur_t *gur = &immap->im_gur;
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
- MPC8610_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE) &&
- serdes2_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-
- if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
- serdes2_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes2_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
deleted file mode 100644
index 4df446618c09..000000000000
--- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 4
-#define SRDS2_MAX_LANES 4
-
-static u32 serdes1_prtcl_map, serdes2_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1},
- [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
- [0x3] = {PCIE2, PCIE2, PCIE2, PCIE2},
- [0x5] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0x6] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0x7] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0xe] = {PCIE2, PCIE2, PCIE2, PCIE2},
- [0xf] = {PCIE2, PCIE2, PCIE2, PCIE2},
-};
-
-int is_serdes_configured(enum srds_prtcl device)
-{
- int ret;
-
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- ret = (1 << device) & serdes1_prtcl_map;
-
- if (ret)
- return ret;
-
- if (!(serdes2_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << device) & serdes2_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- ccsr_gur_t *gur = &immap->im_gur;
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >>
- MPC8641_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE) &&
- serdes2_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-
- if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
- serdes2_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes2_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc86xx/release.S b/arch/powerpc/cpu/mpc86xx/release.S
deleted file mode 100644
index 72ad8834c979..000000000000
--- a/arch/powerpc/cpu/mpc86xx/release.S
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2007, 2008 Freescale Semiconductor.
- * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
- */
-#include <config.h>
-#include <mpc86xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-/* If this is a multi-cpu system then we need to handle the
- * 2nd cpu. The assumption is that the 2nd cpu is being
- * held in boot holdoff mode until the 1st cpu unlocks it
- * from Linux. We'll do some basic cpu init and then pass
- * it to the Linux Reset Vector.
- * Sri: Much of this initialization is not required. Linux
- * rewrites the bats, and the sprs and also enables the L1 cache.
- *
- * Core 0 must copy this to a 1M aligned region and set BPTR
- * to point to it.
- */
- .align 12
-.globl __secondary_start_page
-__secondary_start_page:
- .space 0x100 /* space over to reset vector loc */
- mfspr r0, MSSCR0
- andi. r0, r0, 0x0020
- rlwinm r0,r0,27,31,31
- mtspr PIR, r0
-
- /* Invalidate BATs */
- li r0, 0
- mtspr IBAT0U, r0
- mtspr IBAT1U, r0
- mtspr IBAT2U, r0
- mtspr IBAT3U, r0
- mtspr IBAT4U, r0
- mtspr IBAT5U, r0
- mtspr IBAT6U, r0
- mtspr IBAT7U, r0
- isync
- mtspr DBAT0U, r0
- mtspr DBAT1U, r0
- mtspr DBAT2U, r0
- mtspr DBAT3U, r0
- mtspr DBAT4U, r0
- mtspr DBAT5U, r0
- mtspr DBAT6U, r0
- mtspr DBAT7U, r0
- isync
- sync
-
- /* enable extended addressing */
- mfspr r0, HID0
- lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
- ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
- mtspr HID0, r0
- sync
- isync
-
-#ifdef CONFIG_SYS_L2
- /* init the L2 cache */
- addis r3, r0, L2_INIT at h
- ori r3, r3, L2_INIT at l
- sync
- mtspr l2cr, r3
-#ifdef CONFIG_ALTIVEC
- dssall
-#endif
- /* invalidate the L2 cache */
- mfspr r3, l2cr
- rlwinm. r3, r3, 0, 0, 0
- beq 1f
-
- mfspr r3, l2cr
- rlwinm r3, r3, 0, 1, 31
-
-#ifdef CONFIG_ALTIVEC
- dssall
-#endif
- sync
- mtspr l2cr, r3
- sync
-1: mfspr r3, l2cr
- oris r3, r3, L2CR_L2I at h
- mtspr l2cr, r3
-
-invl2:
- mfspr r3, l2cr
- andis. r3, r3, L2CR_L2I at h
- bne invl2
- sync
-#endif
-
- /* enable and invalidate the data cache */
- mfspr r3, HID0
- li r5, HID0_DCFI|HID0_DLOCK
- andc r3, r3, r5
- mtspr HID0, r3 /* no invalidate, unlock */
- ori r3, r3, HID0_DCE
- ori r5, r3, HID0_DCFI
- mtspr HID0, r5 /* enable + invalidate */
- mtspr HID0, r3 /* enable */
- sync
-#ifdef CONFIG_SYS_L2
- sync
- lis r3, L2_ENABLE at h
- ori r3, r3, L2_ENABLE at l
- mtspr l2cr, r3
- isync
- sync
-#endif
-
- /* enable and invalidate the instruction cache*/
- mfspr r3, HID0
- li r5, HID0_ICFI|HID0_ILOCK
- andc r3, r3, r5
- ori r3, r3, HID0_ICE
- ori r5, r3, HID0_ICFI
- mtspr HID0, r5
- mtspr HID0, r3
- isync
- sync
-
- /* TBEN in HID0 */
- mfspr r4, HID0
- oris r4, r4, 0x0400
- mtspr HID0, r4
- sync
- isync
-
- /* MCP|SYNCBE|ABE in HID1 */
- mfspr r4, HID1
- oris r4, r4, 0x8000
- ori r4, r4, 0x0C00
- mtspr HID1, r4
- sync
- isync
-
- lis r3, CONFIG_LINUX_RESET_VEC at h
- ori r3, r3, CONFIG_LINUX_RESET_VEC at l
- mtlr r3
- blr
-
- /* Never Returns, Running in Linux Now */
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
deleted file mode 100644
index 86c1709c4ca2..000000000000
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <mpc86xx.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-
-void get_sys_info(sys_info_t *sys_info)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- uint plat_ratio, e600_ratio;
-
- plat_ratio = (gur->porpllsr) & 0x0000003e;
- plat_ratio >>= 1;
-
- switch (plat_ratio) {
- case 0x0:
- sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
- break;
- case 0x02:
- case 0x03:
- case 0x04:
- case 0x05:
- case 0x06:
- case 0x08:
- case 0x09:
- case 0x0a:
- case 0x0c:
- case 0x10:
- sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
- break;
- default:
- sys_info->freq_systembus = 0;
- break;
- }
-
- e600_ratio = (gur->porpllsr) & 0x003f0000;
- e600_ratio >>= 16;
-
- switch (e600_ratio) {
- case 0x10:
- sys_info->freq_processor = 2 * sys_info->freq_systembus;
- break;
- case 0x19:
- sys_info->freq_processor = 5 * sys_info->freq_systembus / 2;
- break;
- case 0x20:
- sys_info->freq_processor = 3 * sys_info->freq_systembus;
- break;
- case 0x39:
- sys_info->freq_processor = 7 * sys_info->freq_systembus / 2;
- break;
- case 0x28:
- sys_info->freq_processor = 4 * sys_info->freq_systembus;
- break;
- case 0x1d:
- sys_info->freq_processor = 9 * sys_info->freq_systembus / 2;
- break;
- default:
- sys_info->freq_processor = e600_ratio +
- sys_info->freq_systembus;
- break;
- }
-
- sys_info->freq_localbus = sys_info->freq_systembus;
-}
-
-
-/*
- * Measure CPU clock speed (core clock GCLK1, GCLK2)
- * (Approx. GCLK frequency in Hz)
- */
-
-int get_clocks(void)
-{
- sys_info_t sys_info;
-
- get_sys_info(&sys_info);
- gd->cpu_clk = sys_info.freq_processor;
- gd->bus_clk = sys_info.freq_systembus;
- gd->arch.lbc_clk = sys_info.freq_localbus;
-
- /*
- * The base clock for I2C depends on the actual SOC. Unfortunately,
- * there is no pattern that can be used to determine the frequency, so
- * the only choice is to look up the actual SOC number and use the value
- * for that SOC. This information is taken from application note
- * AN2919.
- */
-#ifdef CONFIG_ARCH_MPC8610
- gd->arch.i2c1_clk = sys_info.freq_systembus;
-#else
- gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
-#endif
- gd->arch.i2c2_clk = gd->arch.i2c1_clk;
-
- if (gd->cpu_clk != 0)
- return 0;
- else
- return 1;
-}
-
-
-/*
- * get_bus_freq
- * Return system bus freq in Hz
- */
-
-ulong get_bus_freq(ulong dummy)
-{
- ulong val;
- sys_info_t sys_info;
-
- get_sys_info(&sys_info);
- val = sys_info.freq_systembus;
-
- return val;
-}
diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S
deleted file mode 100644
index f4651ce8d46f..000000000000
--- a/arch/powerpc/cpu/mpc86xx/start.S
+++ /dev/null
@@ -1,982 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004, 2007, 2011 Freescale Semiconductor.
- * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
- */
-
-/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
- *
- *
- * The processor starts at 0xfff00100 and the code is executed
- * from flash. The code is organized to be at an other address
- * in memory, but as long we don't jump around before relocating.
- * board_init lies at a quite high address and when the cpu has
- * jumped there, everything is ok.
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <mpc86xx.h>
-#include <version.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/u-boot.h>
-
-/*
- * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
- */
-
-/*
- * Set up GOT: Global Offset Table
- *
- * Use r12 to access the GOT
- */
- START_GOT
- GOT_ENTRY(_GOT2_TABLE_)
- GOT_ENTRY(_FIXUP_TABLE_)
-
- GOT_ENTRY(_start)
- GOT_ENTRY(_start_of_vectors)
- GOT_ENTRY(_end_of_vectors)
- GOT_ENTRY(transfer_to_handler)
-
- GOT_ENTRY(__init_end)
- GOT_ENTRY(__bss_end)
- GOT_ENTRY(__bss_start)
- END_GOT
-
-/*
- * r3 - 1st arg to board_init(): IMMP pointer
- * r4 - 2nd arg to board_init(): boot flag
- */
- .text
- .long 0x27051956 /* U-Boot Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION_STRING, "\0"
-
- . = EXC_OFF_SYS_RESET
- .globl _start
-_start:
- b boot_cold
-
- /* the boot code is located below the exception table */
-
- .globl _start_of_vectors
-_start_of_vectors:
-
-/* Machine check */
- STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
-
-/* Data Storage exception. */
- STD_EXCEPTION(0x300, DataStorage, UnknownException)
-
-/* Instruction Storage exception. */
- STD_EXCEPTION(0x400, InstStorage, UnknownException)
-
-/* External Interrupt exception. */
- STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-
-/* Alignment exception. */
- . = 0x600
-Alignment:
- EXCEPTION_PROLOG(SRR0, SRR1)
- mfspr r4,DAR
- stw r4,_DAR(r21)
- mfspr r5,DSISR
- stw r5,_DSISR(r21)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
-
-/* Program check exception */
- . = 0x700
-ProgramCheck:
- EXCEPTION_PROLOG(SRR0, SRR1)
- addi r3,r1,STACK_FRAME_OVERHEAD
- EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
- MSR_KERNEL, COPY_EE)
-
- STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
-
- /* I guess we could implement decrementer, and may have
- * to someday for timekeeping.
- */
- STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
- STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
- STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
- STD_EXCEPTION(0xc00, SystemCall, UnknownException)
- STD_EXCEPTION(0xd00, SingleStep, UnknownException)
- STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
- STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
- STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
- STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
- STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
- STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
- STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
- STD_EXCEPTION(0x1500, Reserved5, UnknownException)
- STD_EXCEPTION(0x1600, Reserved6, UnknownException)
- STD_EXCEPTION(0x1700, Reserved7, UnknownException)
- STD_EXCEPTION(0x1800, Reserved8, UnknownException)
- STD_EXCEPTION(0x1900, Reserved9, UnknownException)
- STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
- STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
- STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
- STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
- STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
- STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
-
- .globl _end_of_vectors
-_end_of_vectors:
-
- . = 0x2000
-
-boot_cold:
- /*
- * NOTE: Only Cpu 0 will ever come here. Other cores go to an
- * address specified by the BPTR
- */
-1:
-#ifdef CONFIG_SYS_RAMBOOT
- /* disable everything */
- li r0, 0
- mtspr HID0, r0
- sync
- mtmsr 0
-#endif
-
- /* Invalidate BATs */
- bl invalidate_bats
- sync
- /* Invalidate all of TLB before MMU turn on */
- bl clear_tlbs
- sync
-
-#ifdef CONFIG_SYS_L2
- /* init the L2 cache */
- lis r3, L2_INIT at h
- ori r3, r3, L2_INIT at l
- mtspr l2cr, r3
- /* invalidate the L2 cache */
- bl l2cache_invalidate
- sync
-#endif
-
- /*
- * Calculate absolute address in FLASH and jump there
- *------------------------------------------------------*/
- lis r3, CONFIG_SYS_MONITOR_BASE_EARLY at h
- ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY at l
- addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
- mtlr r3
- blr
-
-in_flash:
- /* let the C-code set up the rest */
- /* */
- /* Be careful to keep code relocatable ! */
- /*------------------------------------------------------*/
- /* perform low-level init */
-
- /* enable extended addressing */
- bl enable_ext_addr
-
- /* setup the bats */
- bl early_bats
-
- /*
- * Cache must be enabled here for stack-in-cache trick.
- * This means we need to enable the BATS.
- * Cache should be turned on after BATs, since by default
- * everything is write-through.
- */
-
- /* enable address translation */
- mfmsr r5
- ori r5, r5, (MSR_IR | MSR_DR)
- lis r3,addr_trans_enabled at h
- ori r3, r3, addr_trans_enabled at l
- mtspr SPRN_SRR0,r3
- mtspr SPRN_SRR1,r5
- rfi
-
-addr_trans_enabled:
- /* enable and invalidate the data cache */
-/* bl l1dcache_enable */
- bl dcache_enable
- sync
-
-#if 1
- bl icache_enable
-#endif
-
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
- bl lock_ram_in_cache
- sync
-#endif
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
- bl setup_ccsrbar
-#endif
-
- /* set up the stack pointer in our newly created
- * cache-ram (r1) */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
-
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
- GET_GOT /* initialize GOT access */
-
- /* run low-level CPU init code (from Flash) */
- bl cpu_init_f
- sync
-
-#ifdef RUN_DIAG
-
- /* Load PX_AUX register address in r4 */
- lis r4, PIXIS_BASE at h
- ori r4, r4, 0x6
- /* Load contents of PX_AUX in r3 bits 24 to 31*/
- lbz r3, 0(r4)
-
- /* Mask and obtain the bit in r3 */
- rlwinm. r3, r3, 0, 24, 24
- /* If not zero, jump and continue with u-boot */
- bne diag_done
-
- /* Load back contents of PX_AUX in r3 bits 24 to 31 */
- lbz r3, 0(r4)
- /* Set the MSB of the register value */
- ori r3, r3, 0x80
- /* Write value in r3 back to PX_AUX */
- stb r3, 0(r4)
-
- /* Get the address to jump to in r3*/
- lis r3, CONFIG_SYS_DIAG_ADDR at h
- ori r3, r3, CONFIG_SYS_DIAG_ADDR at l
-
- /* Load the LR with the branch address */
- mtlr r3
-
- /* Branch to diagnostic */
- blr
-
-diag_done:
-#endif
-
-/* bl l2cache_enable */
-
- /* run 1st part of board init code (from Flash) */
- li r3, 0 /* clear boot_flag for calling board_init_f */
- bl board_init_f
- sync
-
- /* NOTREACHED - board_init_f() does not return */
-
- .globl invalidate_bats
-invalidate_bats:
-
- li r0, 0
- /* invalidate BATs */
- mtspr IBAT0U, r0
- mtspr IBAT1U, r0
- mtspr IBAT2U, r0
- mtspr IBAT3U, r0
- mtspr IBAT4U, r0
- mtspr IBAT5U, r0
- mtspr IBAT6U, r0
- mtspr IBAT7U, r0
-
- isync
- mtspr DBAT0U, r0
- mtspr DBAT1U, r0
- mtspr DBAT2U, r0
- mtspr DBAT3U, r0
- mtspr DBAT4U, r0
- mtspr DBAT5U, r0
- mtspr DBAT6U, r0
- mtspr DBAT7U, r0
-
- isync
- sync
- blr
-
-#define CONFIG_BAT_PAIR(n) \
- lis r4, CONFIG_SYS_IBAT##n##L at h; \
- ori r4, r4, CONFIG_SYS_IBAT##n##L at l; \
- lis r3, CONFIG_SYS_IBAT##n##U at h; \
- ori r3, r3, CONFIG_SYS_IBAT##n##U at l; \
- mtspr IBAT##n##L, r4; \
- mtspr IBAT##n##U, r3; \
- lis r4, CONFIG_SYS_DBAT##n##L at h; \
- ori r4, r4, CONFIG_SYS_DBAT##n##L at l; \
- lis r3, CONFIG_SYS_DBAT##n##U at h; \
- ori r3, r3, CONFIG_SYS_DBAT##n##U at l; \
- mtspr DBAT##n##L, r4; \
- mtspr DBAT##n##U, r3;
-
-/*
- * setup_bats:
- *
- * Set up the final BAT registers now that setup is done.
- *
- * Assumes that:
- * 1) Address translation is enabled upon entry
- * 2) The boot rom is still accessible via 1:1 translation
- */
- .globl setup_bats
-setup_bats:
- mflr r5
- sync
-
- /*
- * When we disable address translation, we will get 1:1 (VA==PA)
- * translation. The only place we know for sure is safe for that is
- * the bootrom where we originally started out. Pop back into there.
- */
- lis r4, CONFIG_SYS_MONITOR_BASE_EARLY at h
- ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY at l
- addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
-
- /* disable address translation */
- mfmsr r3
- rlwinm r3, r3, 0, 28, 25
- mtspr SRR0, r4
- mtspr SRR1, r3
- rfi
-
-trans_disabled:
-#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
- && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
- CONFIG_BAT_PAIR(0)
-#endif
- CONFIG_BAT_PAIR(1)
- CONFIG_BAT_PAIR(2)
- CONFIG_BAT_PAIR(3)
- CONFIG_BAT_PAIR(4)
- CONFIG_BAT_PAIR(5)
- CONFIG_BAT_PAIR(6)
- CONFIG_BAT_PAIR(7)
-
- sync
- isync
-
- /* Turn translation back on and return */
- mfmsr r3
- ori r3, r3, (MSR_IR | MSR_DR)
- mtspr SPRN_SRR0,r5
- mtspr SPRN_SRR1,r3
- rfi
-
-/*
- * early_bats:
- *
- * Set up bats needed early on - this is usually the BAT for the
- * stack-in-cache, the Flash, and CCSR space
- */
- .globl early_bats
-early_bats:
- /* IBAT 3 */
- lis r4, CONFIG_SYS_IBAT3L at h
- ori r4, r4, CONFIG_SYS_IBAT3L at l
- lis r3, CONFIG_SYS_IBAT3U at h
- ori r3, r3, CONFIG_SYS_IBAT3U at l
- mtspr IBAT3L, r4
- mtspr IBAT3U, r3
- isync
-
- /* DBAT 3 */
- lis r4, CONFIG_SYS_DBAT3L at h
- ori r4, r4, CONFIG_SYS_DBAT3L at l
- lis r3, CONFIG_SYS_DBAT3U at h
- ori r3, r3, CONFIG_SYS_DBAT3U at l
- mtspr DBAT3L, r4
- mtspr DBAT3U, r3
- isync
-
- /* IBAT 5 */
- lis r4, CONFIG_SYS_IBAT5L at h
- ori r4, r4, CONFIG_SYS_IBAT5L at l
- lis r3, CONFIG_SYS_IBAT5U at h
- ori r3, r3, CONFIG_SYS_IBAT5U at l
- mtspr IBAT5L, r4
- mtspr IBAT5U, r3
- isync
-
- /* DBAT 5 */
- lis r4, CONFIG_SYS_DBAT5L at h
- ori r4, r4, CONFIG_SYS_DBAT5L at l
- lis r3, CONFIG_SYS_DBAT5U at h
- ori r3, r3, CONFIG_SYS_DBAT5U at l
- mtspr DBAT5L, r4
- mtspr DBAT5U, r3
- isync
-
- /* IBAT 6 */
- lis r4, CONFIG_SYS_IBAT6L_EARLY at h
- ori r4, r4, CONFIG_SYS_IBAT6L_EARLY at l
- lis r3, CONFIG_SYS_IBAT6U_EARLY at h
- ori r3, r3, CONFIG_SYS_IBAT6U_EARLY at l
- mtspr IBAT6L, r4
- mtspr IBAT6U, r3
- isync
-
- /* DBAT 6 */
- lis r4, CONFIG_SYS_DBAT6L_EARLY at h
- ori r4, r4, CONFIG_SYS_DBAT6L_EARLY at l
- lis r3, CONFIG_SYS_DBAT6U_EARLY at h
- ori r3, r3, CONFIG_SYS_DBAT6U_EARLY at l
- mtspr DBAT6L, r4
- mtspr DBAT6U, r3
- isync
-
-#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
- /* IBAT 7 */
- lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at h
- ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at l
- lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at h
- ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at l
- mtspr IBAT7L, r4
- mtspr IBAT7U, r3
- isync
-
- /* DBAT 7 */
- lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at h
- ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at l
- lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at h
- ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at l
- mtspr DBAT7L, r4
- mtspr DBAT7U, r3
- isync
-#endif
- blr
-
- .globl clear_tlbs
-clear_tlbs:
- addis r3, 0, 0x0000
- addis r5, 0, 0x4
- isync
-tlblp:
- tlbie r3
- sync
- addi r3, r3, 0x1000
- cmp 0, 0, r3, r5
- blt tlblp
- blr
-
- .globl disable_addr_trans
-disable_addr_trans:
- /* disable address translation */
- mflr r4
- mfmsr r3
- andi. r0, r3, (MSR_IR | MSR_DR)
- beqlr
- andc r3, r3, r0
- mtspr SRR0, r4
- mtspr SRR1, r3
- rfi
-
-/*
- * This code finishes saving the registers to the exception frame
- * and jumps to the appropriate handler for the exception.
- * Register r21 is pointer into trap frame, r1 has new stack pointer.
- */
- .globl transfer_to_handler
-transfer_to_handler:
- stw r22,_NIP(r21)
- lis r22,MSR_POW at h
- andc r23,r23,r22
- stw r23,_MSR(r21)
- SAVE_GPR(7, r21)
- SAVE_4GPRS(8, r21)
- SAVE_8GPRS(12, r21)
- SAVE_8GPRS(24, r21)
- mflr r23
- andi. r24,r23,0x3f00 /* get vector offset */
- stw r24,TRAP(r21)
- li r22,0
- stw r22,RESULT(r21)
- mtspr SPRG2,r22 /* r1 is now kernel sp */
- lwz r24,0(r23) /* virtual address of handler */
- lwz r23,4(r23) /* where to go when done */
- mtspr SRR0,r24
- mtspr SRR1,r20
- mtlr r23
- SYNC
- rfi /* jump to handler, enable MMU */
-
-int_return:
- mfmsr r28 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r28,r28,r4
- SYNC /* Some chip revs need this... */
- mtmsr r28
- SYNC
- lwz r2,_CTR(r1)
- lwz r0,_LINK(r1)
- mtctr r2
- mtlr r0
- lwz r2,_XER(r1)
- lwz r0,_CCR(r1)
- mtspr XER,r2
- mtcrf 0xFF,r0
- REST_10GPRS(3, r1)
- REST_10GPRS(13, r1)
- REST_8GPRS(23, r1)
- REST_GPR(31, r1)
- lwz r2,_NIP(r1) /* Restore environment */
- lwz r0,_MSR(r1)
- mtspr SRR0,r2
- mtspr SRR1,r0
- lwz r0,GPR0(r1)
- lwz r2,GPR2(r1)
- lwz r1,GPR1(r1)
- SYNC
- rfi
-
- .globl dc_read
-dc_read:
- blr
-
-
-/*
- * Function: in8
- * Description: Input 8 bits
- */
- .globl in8
-in8:
- lbz r3,0x0000(r3)
- blr
-
-/*
- * Function: out8
- * Description: Output 8 bits
- */
- .globl out8
-out8:
- stb r4,0x0000(r3)
- blr
-
-/*
- * Function: out16
- * Description: Output 16 bits
- */
- .globl out16
-out16:
- sth r4,0x0000(r3)
- blr
-
-/*
- * Function: out16r
- * Description: Byte reverse and output 16 bits
- */
- .globl out16r
-out16r:
- sthbrx r4,r0,r3
- blr
-
-/*
- * Function: out32
- * Description: Output 32 bits
- */
- .globl out32
-out32:
- stw r4,0x0000(r3)
- blr
-
-/*
- * Function: out32r
- * Description: Byte reverse and output 32 bits
- */
- .globl out32r
-out32r:
- stwbrx r4,r0,r3
- blr
-
-/*
- * Function: in16
- * Description: Input 16 bits
- */
- .globl in16
-in16:
- lhz r3,0x0000(r3)
- blr
-
-/*
- * Function: in16r
- * Description: Input 16 bits and byte reverse
- */
- .globl in16r
-in16r:
- lhbrx r3,r0,r3
- blr
-
-/*
- * Function: in32
- * Description: Input 32 bits
- */
- .globl in32
-in32:
- lwz 3,0x0000(3)
- blr
-
-/*
- * Function: in32r
- * Description: Input 32 bits and byte reverse
- */
- .globl in32r
-in32r:
- lwbrx r3,r0,r3
- blr
-
-/*
- * void relocate_code(addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
- .globl relocate_code
-relocate_code:
-
- mr r1, r3 /* Set new stack pointer */
- mr r9, r4 /* Save copy of Global Data pointer */
- mr r10, r5 /* Save copy of Destination Address */
-
- GET_GOT
- mr r3, r5 /* Destination Address */
- lis r4, CONFIG_SYS_MONITOR_BASE at h /* Source Address */
- ori r4, r4, CONFIG_SYS_MONITOR_BASE at l
- lwz r5, GOT(__init_end)
- sub r5, r5, r4
- li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
-
- /*
- * Fix GOT pointer:
- *
- * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
- *
- * Offset:
- */
- sub r15, r10, r4
-
- /* First our own GOT */
- add r12, r12, r15
- /* then the one used by the C code */
- add r30, r30, r15
-
- /*
- * Now relocate code
- */
- cmplw cr1,r3,r4
- addi r0,r5,3
- srwi. r0,r0,2
- beq cr1,4f /* In place copy is not necessary */
- beq 7f /* Protect against 0 count */
- mtctr r0
- bge cr1,2f
-
- la r8,-4(r4)
- la r7,-4(r3)
-1: lwzu r0,4(r8)
- stwu r0,4(r7)
- bdnz 1b
- b 4f
-
-2: slwi r0,r0,2
- add r8,r4,r0
- add r7,r3,r0
-3: lwzu r0,-4(r8)
- stwu r0,-4(r7)
- bdnz 3b
-/*
- * Now flush the cache: note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4: cmpwi r6,0
- add r5,r3,r5
- beq 7f /* Always flush prefetch queue in any case */
- subi r0,r6,1
- andc r3,r3,r0
- mr r4,r3
-5: dcbst 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 5b
- sync /* Wait for all dcbst to complete on bus */
- mr r4,r3
-6: icbi 0,r4
- add r4,r4,r6
- cmplw r4,r5
- blt 6b
-7: sync /* Wait for all icbi to complete on bus */
- isync
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
- mtlr r0
- blr
-
-in_ram:
- /*
- * Relocation Function, r12 point to got2+0x8000
- *
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
- */
- li r0,__got2_entries at sectoff@l
- la r3,GOT(_GOT2_TABLE_)
- lwz r11,GOT(_GOT2_TABLE_)
- mtctr r0
- sub r11,r3,r11
- addi r3,r3,-4
-1: lwzu r0,4(r3)
- cmpwi r0,0
- beq- 2f
- add r0,r0,r11
- stw r0,0(r3)
-2: bdnz 1b
-
- /*
- * Now adjust the fixups and the pointers to the fixups
- * in case we need to move ourselves again.
- */
- li r0,__fixup_entries at sectoff@l
- lwz r3,GOT(_FIXUP_TABLE_)
- cmpwi r0,0
- mtctr r0
- addi r3,r3,-4
- beq 4f
-3: lwzu r4,4(r3)
- lwzux r0,r4,r11
- cmpwi r0,0
- add r0,r0,r11
- stw r4,0(r3)
- beq- 5f
- stw r0,0(r4)
-5: bdnz 3b
-4:
-/* clear_bss: */
- /*
- * Now clear BSS segment
- */
- lwz r3,GOT(__bss_start)
- lwz r4,GOT(__bss_end)
-
- cmplw 0, r3, r4
- beq 6f
-
- li r0, 0
-5:
- stw r0, 0(r3)
- addi r3, r3, 4
- cmplw 0, r3, r4
- bne 5b
-6:
- mr r3, r9 /* Init Date pointer */
- mr r4, r10 /* Destination Address */
- bl board_init_r
-
- /* not reached - end relocate_code */
-/*-----------------------------------------------------------------------*/
-
- /*
- * Copy exception vector code to low memory
- *
- * r3: dest_addr
- * r7: source address, r8: end address, r9: target address
- */
- .globl trap_init
-trap_init:
- mflr r4 /* save link register */
- GET_GOT
- lwz r7, GOT(_start)
- lwz r8, GOT(_end_of_vectors)
-
- li r9, 0x100 /* reset vector always at 0x100 */
-
- cmplw 0, r7, r8
- bgelr /* return if r7>=r8 - just in case */
-1:
- lwz r0, 0(r7)
- stw r0, 0(r9)
- addi r7, r7, 4
- addi r9, r9, 4
- cmplw 0, r7, r8
- bne 1b
-
- /*
- * relocate `hdlr' and `int_return' entries
- */
- li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
- li r8, Alignment - _start + EXC_OFF_SYS_RESET
-2:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 2b
-
- li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
- bl trap_reloc
-
- li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
- bl trap_reloc
-
- li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
- li r8, SystemCall - _start + EXC_OFF_SYS_RESET
-3:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 3b
-
- li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
- li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
-4:
- bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
- blt 4b
-
- /* enable execptions from RAM vectors */
- mfmsr r7
- li r8,MSR_IP
- andc r7,r7,r8
- ori r7,r7,MSR_ME /* Enable Machine Check */
- mtmsr r7
-
- mtlr r4 /* restore link register */
- blr
-
-.globl enable_ext_addr
-enable_ext_addr:
- mfspr r0, HID0
- lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
- ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
- mtspr HID0, r0
- sync
- isync
- blr
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-.globl setup_ccsrbar
-setup_ccsrbar:
- /* Special sequence needed to update CCSRBAR itself */
- lis r4, CONFIG_SYS_CCSRBAR_DEFAULT at h
- ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT at l
-
- lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at h
- ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at l
- srwi r5,r5,12
- li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
- rlwimi r5,r6,20,8,11
- stw r5, 0(r4) /* Store physical value of CCSR */
- isync
-
- lis r5, CONFIG_SYS_TEXT_BASE at h
- ori r5,r5,CONFIG_SYS_TEXT_BASE at l
- lwz r5, 0(r5)
- isync
-
- /* Use VA of CCSR to do read */
- lis r3, CONFIG_SYS_CCSRBAR at h
- lwz r5, CONFIG_SYS_CCSRBAR at l(r3)
- isync
-
- blr
-#endif
-
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
-lock_ram_in_cache:
- /* Allocate Initial RAM in data cache.
- */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
- (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r4
-1:
- dcbz r0, r3
- addi r3, r3, 32
- bdnz 1b
-#if 1
-/* Lock the data cache */
- mfspr r0, HID0
- ori r0, r0, 0x1000
- sync
- mtspr HID0, r0
- sync
- blr
-#endif
-#if 0
- /* Lock the first way of the data cache */
- mfspr r0, LDSTCR
- ori r0, r0, 0x0080
-#if defined(CONFIG_ALTIVEC)
- dssall
-#endif
- sync
- mtspr LDSTCR, r0
- sync
- isync
- blr
-#endif
-
-.globl unlock_ram_in_cache
-unlock_ram_in_cache:
- /* invalidate the INIT_RAM section */
- lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
- li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
- (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
- mtctr r4
-1: icbi r0, r3
- addi r3, r3, 32
- bdnz 1b
- sync /* Wait for all icbi to complete on bus */
- isync
-#if 1
-/* Unlock the data cache and invalidate it */
- mfspr r0, HID0
- li r3,0x1000
- andc r0,r0,r3
- li r3,0x0400
- or r0,r0,r3
- sync
- mtspr HID0, r0
- sync
- blr
-#endif
-#if 0
- /* Unlock the first way of the data cache */
- mfspr r0, LDSTCR
- li r3,0x0080
- andc r0,r0,r3
-#ifdef CONFIG_ALTIVEC
- dssall
-#endif
- sync
- mtspr LDSTCR, r0
- sync
- isync
- li r3,0x0400
- or r0,r0,r3
- sync
- mtspr HID0, r0
- sync
- blr
-#endif
-#endif
diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c
deleted file mode 100644
index 46006ece4160..000000000000
--- a/arch/powerpc/cpu/mpc86xx/traps.c
+++ /dev/null
@@ -1,199 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 1995-1996 Gary Thomas (gdt at linuxppc.org)
- *
- * Modified by Cort Dougan (cort at cs.nmt.edu)
- * and Paul Mackerras (paulus at cs.anu.edu.au)
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-/*
- * This file handles the architecture-dependent parts of hardware exceptions
- */
-
-#include <common.h>
-#include <asm/global_data.h>
-#include <asm/ptrace.h>
-#include <command.h>
-#include <init.h>
-#include <kgdb.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table(unsigned long);
-
-/*
- * End of addressable memory. This may be less than the actual
- * amount of memory on the system if we're unable to keep all
- * the memory mapped in.
- */
-#define END_OF_MEM (gd->ram_base + get_effective_memsize())
-
-/*
- * Trap & Exception support
- */
-
-static void print_backtrace(unsigned long *sp)
-{
- int cnt = 0;
- unsigned long i;
-
- printf("Call backtrace: ");
- while (sp) {
- if ((uint) sp > END_OF_MEM)
- break;
-
- i = sp[1];
- if (cnt++ % 7 == 0)
- printf("\n");
- printf("%08lX ", i);
- if (cnt > 32)
- break;
- sp = (unsigned long *)*sp;
- }
- printf("\n");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
-
- printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
- " %p TRAP: %04lx DAR: %08lX\n",
- regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- printf("MSR: %08lx EE: %01x PR: %01x FP:"
- " %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr & MSR_EE ? 1 : 0,
- regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
- regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
- regs->msr & MSR_DR ? 1 : 0);
-
- printf("\n");
- for (i = 0; i < 32; i++) {
- if ((i % 8) == 0) {
- printf("GPR%02d: ", i);
- }
-
- printf("%08lX ", regs->gpr[i]);
- if ((i % 8) == 7) {
- printf("\n");
- }
- }
-}
-
-
-static void _exception(int signr, struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
- unsigned long fixup;
-
- /* Probing PCI using config cycles cause this exception
- * when a device is not present. Catch it and return to
- * the PCI exception handler.
- */
- if ((fixup = search_exception_table(regs->nip)) != 0) {
- regs->nip = fixup;
- return;
- }
-
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler) (regs))
- return;
-#endif
-
- printf("Machine check in kernel mode.\n");
- printf("Caused by (from msr): ");
- printf("regs %p ", regs);
- switch ( regs->msr & 0x001F0000) {
- case (0x80000000>>11):
- printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0));
- break;
- case (0x80000000>>12):
- printf("Machine check signal - probably due to mm fault\n"
- "with mmu off\n");
- break;
- case (0x80000000 >> 13):
- printf("Transfer error ack signal\n");
- break;
- case (0x80000000 >> 14):
- printf("Data parity signal\n");
- break;
- case (0x80000000 >> 15):
- printf("Address parity signal\n");
- break;
- default:
- printf("Unknown values in msr\n");
- }
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler) (regs))
- return;
-#endif
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
- unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
- int i, j;
-
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler) (regs))
- return;
-#endif
- show_regs(regs);
-
- p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0);
- p -= 32;
- for (i = 0; i < 256; i += 16) {
- printf("%08x: ", (unsigned int)p + i);
- for (j = 0; j < 16; j++) {
- printf("%02x ", p[i + j]);
- }
- printf("\n");
- }
-
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Program Check Exception");
-}
-
-void SoftEmuException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler) (regs))
- return;
-#endif
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Software Emulation Exception");
-}
-
-void UnknownException(struct pt_regs *regs)
-{
-#if defined(CONFIG_CMD_KGDB)
- if (debugger_exception_handler && (*debugger_exception_handler) (regs))
- return;
-#endif
- printf("UnknownException regs@%lx\n", (ulong)regs);
- printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
- regs->nip, regs->msr, regs->trap);
- _exception(0, regs);
-}
diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
deleted file mode 100644
index 94f07c6b7dd2..000000000000
--- a/arch/powerpc/cpu/mpc86xx/u-boot.lds
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2006, 2007 Freescale Semiconductor, Inc.
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-
- /* Read-only sections, merged into text segment: */
- .text :
- {
- arch/powerpc/cpu/mpc86xx/start.o (.text*)
- arch/powerpc/cpu/mpc86xx/traps.o (.text*)
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 99b410dc9b09..2c96378efef8 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -10,10 +10,6 @@
#include <asm/config_mpc85xx.h>
#endif
-#ifdef CONFIG_MPC86xx
-#include <asm/config_mpc86xx.h>
-#endif
-
#ifndef HWCONFIG_BUFFER_SIZE
#define HWCONFIG_BUFFER_SIZE 256
#endif
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
deleted file mode 100644
index f19ff7a6a128..000000000000
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#ifndef _ASM_MPC86xx_CONFIG_H_
-#define _ASM_MPC86xx_CONFIG_H_
-
-#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 77cdc80fdcd0..39fbc04e4744 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -78,9 +78,6 @@ enum law_trgt_if {
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
-#ifndef CONFIG_ARCH_MPC8641
- LAW_TRGT_IF_PCIE_1 = 0x02,
-#endif
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
@@ -116,10 +113,6 @@ enum law_trgt_if {
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
-#ifdef CONFIG_ARCH_MPC8641
-#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
-#endif
-
#if defined(CONFIG_ARCH_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 508834829b95..06f9bfb8ac73 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -30,7 +30,7 @@ void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
/*
- * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ * Common PCI/PCIE Register structure for mpc85xx
*/
/*
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
deleted file mode 100644
index 1fbc63a5ceb8..000000000000
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ /dev/null
@@ -1,1221 +0,0 @@
-/*
- * MPC86xx Internal Memory Map
- *
- * Copyright 2004, 2011 Freescale Semiconductor
- * Jeff Brown (Jeffrey at freescale.com)
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- *
- */
-
-#ifndef __IMMAP_86xx__
-#define __IMMAP_86xx__
-
-#include <fsl_immap.h>
-#include <asm/types.h>
-#include <asm/fsl_dma.h>
-#include <asm/fsl_lbc.h>
-#include <asm/fsl_i2c.h>
-
-/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
-typedef struct ccsr_local_mcm {
- uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
- char res1[4];
- uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
- char res2[4];
- uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
- char res3[12];
- uint bptr; /* 0x20 - Boot Page Translation Register */
- char res4[3044];
- uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
- char res5[4];
- uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
- char res6[20];
- uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
- char res7[4];
- uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
- char res8[20];
- uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
- char res9[4];
- uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
- char res10[20];
- uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
- char res11[4];
- uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
- char res12[20];
- uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
- char res13[4];
- uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
- char res14[20];
- uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
- char res15[4];
- uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
- char res16[20];
- uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
- char res17[4];
- uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
- char res18[20];
- uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
- char res19[4];
- uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
- char res20[20];
- uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
- char res21[4];
- uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
- char res22[20];
- uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
- char res23[4];
- uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
- char res24[716];
- uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
- char res25[4];
- uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
- char res26[4];
- uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
- char res27[44];
- uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
- uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
- uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
- uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
- char res28[16];
- uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
- uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
- uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
- char res29[3476];
- uint edr; /* 0x1e00 - MCM Error Detect Register */
- char res30[4];
- uint eer; /* 0x1e08 - MCM Error Enable Register */
- uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
- uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
- uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
- char res31[488];
-} ccsr_local_mcm_t;
-
-/* Daul I2C Registers(0x3000-0x4000) */
-typedef struct ccsr_i2c {
- struct fsl_i2c_base i2c[2];
- u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)];
-} ccsr_i2c_t;
-
-/* DUART Registers(0x4000-0x5000) */
-typedef struct ccsr_duart {
- char res1[1280];
- u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
- u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
- u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
- u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
- u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
- u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
- u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
- u_char uscr1; /* 0x4507 - UART1 Scratch Register */
- char res2[8];
- u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
- char res3[239];
- u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
- u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
- u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
- u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
- u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
- u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
- u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
- u_char uscr2; /* 0x4607 - UART2 Scratch Register */
- char res4[8];
- u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
- char res5[2543];
-} ccsr_duart_t;
-
-/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
-typedef struct ccsr_pex {
- uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
- uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
- char res1[4];
- uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
- char res2[16];
- uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
- uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
- uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
- uint pm_command; /* 0x802c - PEX PM Command register */
- char res3[3016];
- uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
- uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
- uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
- uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
- char res4[8];
- uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
- char res5[12];
- uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
- uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
- uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
- char res6[4];
- uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
- char res7[12];
- uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
- uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
- uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
- char res8[4];
- uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
- char res9[12];
- uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
- uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
- uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
- char res10[4];
- uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
- char res11[12];
- uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
- uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
- uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
- char res12[4];
- uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
- char res13[12];
- char res14[256];
- uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
- char res15[4];
- uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
- uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
- uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
- char res16[12];
- uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
- char res17[4];
- uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
- uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
- uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
- char res18[12];
- uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
- char res19[4];
- uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
- uint piwbear1;
- uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
- char res20[12];
- uint pedr; /* 0x8e00 - PEX Error Detect Register */
- char res21[4];
- uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
- char res22[4];
- uint pecdr; /* 0x8e10 - PEX Error Disable Register */
- char res23[12];
- uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
- char res24[4];
- uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
- uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
- uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
- uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
- char res25[452];
- char res26[4];
-} ccsr_pex_t;
-
-/* Hyper Transport Register Block (0xA000-0xB000) */
-typedef struct ccsr_ht {
- uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
- uint hcfg_data; /* 0xa004 - HT Configuration Data register */
- char res1[3064];
- uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
- char res2[12];
- uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
- char res3[12];
- uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
- char res4[4];
- uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
- char res5[4];
- uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
- char res6[12];
- uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
- char res7[4];
- uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
- char res8[4];
- uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
- char res9[12];
- uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
- char res10[4];
- uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
- char res11[4];
- uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
- char res12[12];
- uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
- char res13[4];
- uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
- char res14[4];
- uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
- char res15[236];
- uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
- char res16[4];
- uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
- char res17[4];
- uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
- char res18[12];
- uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
- char res19[4];
- uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
- char res20[4];
- uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
- char res21[12];
- uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
- char res22[4];
- uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
- char res23[4];
- uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
- char res24[12];
- uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
- char res25[4];
- uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
- char res26[4];
- uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
- char res27[12];
- uint hedr; /* 0xae00 - HT Error Detect register */
- char res28[4];
- uint heier; /* 0xae08 - HT Error Interrupt Enable register */
- char res29[4];
- uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
- char res30[12];
- uint hecsr; /* 0xae20 - HT Error Capture Status register */
- char res31[4];
- uint hec0; /* 0xae28 - HT Error Capture 0 register */
- uint hec1; /* 0xae2c - HT Error Capture 1 register */
- uint hec2; /* 0xae30 - HT Error Capture 2 register */
- char res32[460];
-} ccsr_ht_t;
-
-/* DMA Registers(0x2_1000-0x2_2000) */
-typedef struct ccsr_dma {
- char res1[256];
- struct fsl_dma dma[4];
- uint dgsr; /* 0x21300 - DMA General Status Register */
- char res2[3324];
-} ccsr_dma_t;
-
-/* tsec1-4: 24000-28000 */
-typedef struct ccsr_tsec {
- uint id; /* 0x24000 - Controller ID Register */
- char res1[12];
- uint ievent; /* 0x24010 - Interrupt Event Register */
- uint imask; /* 0x24014 - Interrupt Mask Register */
- uint edis; /* 0x24018 - Error Disabled Register */
- char res2[4];
- uint ecntrl; /* 0x24020 - Ethernet Control Register */
- char res2_1[4];
- uint ptv; /* 0x24028 - Pause Time Value Register */
- uint dmactrl; /* 0x2402c - DMA Control Register */
- uint tbipa; /* 0x24030 - TBI PHY Address Register */
- char res3[88];
- uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
- char res4[8];
- uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
- uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
- char res4_1[4];
- uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
- uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
- char res5[84];
- uint tctrl; /* 0x24100 - Transmit Control Register */
- uint tstat; /* 0x24104 - Transmit Status Register */
- uint dfvlan; /* 0x24108 - Default VLAN control word */
- char res6[4];
- uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
- uint tqueue; /* 0x24114 - Transmit Queue Control Register */
- char res7[40];
- uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
- uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
- char res8[52];
- uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
- char res9[4];
- uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
- char res10[4];
- uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
- char res11[4];
- uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
- char res12[4];
- uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
- char res13[4];
- uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
- char res14[4];
- uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
- char res15[4];
- uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
- char res16[4];
- uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
- char res17[64];
- uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
- uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
- char res18[4];
- uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
- char res19[4];
- uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
- char res20[4];
- uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
- char res21[4];
- uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
- char res22[4];
- uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
- char res23[4];
- uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
- char res24[4];
- uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
- char res25[192];
- uint rctrl; /* 0x24300 - Receive Control Register */
- uint rstat; /* 0x24304 - Receive Status Register */
- char res26[8];
- uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
- uint rqueue; /* 0x24314 - Receive queue control register */
- char res27[24];
- uint rbifx; /* 0x24330 - Receive bit field extract control Register */
- uint rqfar; /* 0x24334 - Receive queue filing table address Register */
- uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
- uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
- uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
- char res28[56];
- uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
- char res29[4];
- uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
- char res30[4];
- uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
- char res31[4];
- uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
- char res32[4];
- uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
- char res33[4];
- uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
- char res34[4];
- uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
- char res35[4];
- uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
- char res36[4];
- uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
- char res37[64];
- uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
- uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
- char res38[4];
- uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
- char res39[4];
- uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
- char res40[4];
- uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
- char res41[4];
- uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
- char res42[4];
- uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
- char res43[4];
- uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
- char res44[4];
- uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
- char res45[192];
- uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
- uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
- uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
- uint hafdup; /* 0x2450c - Half Duplex Register */
- uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
- char res46[12];
- uint miimcfg; /* 0x24520 - MII Management Configuration Register */
- uint miimcom; /* 0x24524 - MII Management Command Register */
- uint miimadd; /* 0x24528 - MII Management Address Register */
- uint miimcon; /* 0x2452c - MII Management Control Register */
- uint miimstat; /* 0x24530 - MII Management Status Register */
- uint miimind; /* 0x24534 - MII Management Indicator Register */
- uint ifctrl; /* 0x24538 - Interface Contrl Register */
- uint ifstat; /* 0x2453c - Interface Status Register */
- uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
- uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
- uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
- uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
- uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
- uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
- uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
- uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
- uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
- uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
- uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
- uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
- uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
- uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
- uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
- uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
- uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
- uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
- uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
- uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
- uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
- uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
- uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
- uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
- uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
- uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
- uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
- uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
- uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
- uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
- uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
- uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
- char res48[192];
- uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
- uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
- uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
- uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
- uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
- uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
- uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
- uint rbyt; /* 0x2469c - Receive Byte Counter */
- uint rpkt; /* 0x246a0 - Receive Packet Counter */
- uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
- uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
- uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
- uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
- uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
- uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
- uint raln; /* 0x246bc - Receive Alignment Error Counter */
- uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
- uint rcde; /* 0x246c4 - Receive Code Error Counter */
- uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
- uint rund; /* 0x246cc - Receive Undersize Packet Counter */
- uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
- uint rfrg; /* 0x246d4 - Receive Fragments Counter */
- uint rjbr; /* 0x246d8 - Receive Jabber Counter */
- uint rdrp; /* 0x246dc - Receive Drop Counter */
- uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
- uint tpkt; /* 0x246e4 - Transmit Packet Counter */
- uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
- uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
- uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
- uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
- uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
- uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
- uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
- uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
- uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
- uint tncl; /* 0x2470c - Transmit Total Collision Counter */
- char res49[4];
- uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
- uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
- uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
- uint txcf; /* 0x24720 - Transmit Control Frame Counter */
- uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
- uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
- uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
- uint car1; /* 0x24730 - Carry Register One */
- uint car2; /* 0x24734 - Carry Register Two */
- uint cam1; /* 0x24738 - Carry Mask Register One */
- uint cam2; /* 0x2473c - Carry Mask Register Two */
- uint rrej; /* 0x24740 - Receive filer rejected packet counter */
- char res50[188];
- uint iaddr0; /* 0x24800 - Indivdual address register 0 */
- uint iaddr1; /* 0x24804 - Indivdual address register 1 */
- uint iaddr2; /* 0x24808 - Indivdual address register 2 */
- uint iaddr3; /* 0x2480c - Indivdual address register 3 */
- uint iaddr4; /* 0x24810 - Indivdual address register 4 */
- uint iaddr5; /* 0x24814 - Indivdual address register 5 */
- uint iaddr6; /* 0x24818 - Indivdual address register 6 */
- uint iaddr7; /* 0x2481c - Indivdual address register 7 */
- char res51[96];
- uint gaddr0; /* 0x24880 - Global address register 0 */
- uint gaddr1; /* 0x24884 - Global address register 1 */
- uint gaddr2; /* 0x24888 - Global address register 2 */
- uint gaddr3; /* 0x2488c - Global address register 3 */
- uint gaddr4; /* 0x24890 - Global address register 4 */
- uint gaddr5; /* 0x24894 - Global address register 5 */
- uint gaddr6; /* 0x24898 - Global address register 6 */
- uint gaddr7; /* 0x2489c - Global address register 7 */
- char res52[352];
- uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
- char res53[500];
- uint attr; /* 0x24BF8 - DMA Attribute register */
- uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
- char res54[1024];
-} ccsr_tsec_t;
-
-/* PIC Registers(0x4_0000-0x6_1000) */
-
-typedef struct ccsr_pic {
- char res1[64];
- uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
- char res2[12];
- uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
- char res3[12];
- uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
- char res4[12];
- uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
- char res5[12];
- uint ctpr; /* 0x40080 - Current Task Priority Register */
- char res6[12];
- uint whoami; /* 0x40090 - Who Am I Register */
- char res7[12];
- uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
- char res8[12];
- uint eoi; /* 0x400b0 - End Of Interrupt Register */
- char res9[3916];
- uint frr; /* 0x41000 - Feature Reporting Register */
- char res10[28];
- uint gcr; /* 0x41020 - Global Configuration Register */
-#define MPC86xx_PICGCR_RST 0x80000000
-#define MPC86xx_PICGCR_MODE 0x20000000
- char res11[92];
- uint vir; /* 0x41080 - Vendor Identification Register */
- char res12[12];
- uint pir; /* 0x41090 - Processor Initialization Register */
- char res13[12];
- uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
- char res14[12];
- uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
- char res15[12];
- uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
- char res16[12];
- uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
- char res17[12];
- uint svr; /* 0x410e0 - Spurious Vector Register */
- char res18[12];
- uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
- char res19[12];
- uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
- char res20[12];
- uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
- char res21[12];
- uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
- char res22[12];
- uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
- char res23[12];
- uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
- char res24[12];
- uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
- char res25[12];
- uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
- char res26[12];
- uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
- char res27[12];
- uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
- char res28[12];
- uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
- char res29[12];
- uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
- char res30[12];
- uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
- char res31[12];
- uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
- char res32[12];
- uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
- char res33[12];
- uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
- char res34[12];
- uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
- char res35[268];
- uint tcr; /* 0x41300 - Timer Control Register */
- char res36[12];
- uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
- char res37[12];
- uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
- char res38[12];
- uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
- char res39[12];
- uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
- char res40[12];
- uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
- char res41[12];
- uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
- char res42[12];
- uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
- char res43[12];
- uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
- char res44[12];
- uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
- char res45[12];
- uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
- char res46[12];
- uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
- char res47[12];
- uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
- char res48[60];
- uint msgr0; /* 0x41400 - Message Register 0 */
- char res49[12];
- uint msgr1; /* 0x41410 - Message Register 1 */
- char res50[12];
- uint msgr2; /* 0x41420 - Message Register 2 */
- char res51[12];
- uint msgr3; /* 0x41430 - Message Register 3 */
- char res52[204];
- uint mer; /* 0x41500 - Message Enable Register */
- char res53[12];
- uint msr; /* 0x41510 - Message Status Register */
- char res54[60140];
- uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
- char res55[12];
- uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
- char res56[12];
- uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
- char res57[12];
- uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
- char res58[12];
- uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
- char res59[12];
- uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
- char res60[12];
- uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
- char res61[12];
- uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
- char res62[12];
- uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
- char res63[12];
- uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
- char res64[12];
- uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
- char res65[12];
- uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
- char res66[12];
- uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
- char res67[12];
- uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
- char res68[12];
- uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
- char res69[12];
- uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
- char res70[12];
- uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
- char res71[12];
- uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
- char res72[12];
- uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
- char res73[12];
- uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
- char res74[12];
- uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
- char res75[12];
- uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
- char res76[12];
- uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
- char res77[12];
- uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
- char res78[140];
- uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
- char res79[12];
- uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
- char res80[12];
- uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
- char res81[12];
- uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
- char res82[12];
- uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
- char res83[12];
- uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
- char res84[12];
- uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
- char res85[12];
- uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
- char res86[12];
- uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
- char res87[12];
- uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
- char res88[12];
- uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
- char res89[12];
- uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
- char res90[12];
- uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
- char res91[12];
- uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
- char res92[12];
- uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
- char res93[12];
- uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
- char res94[12];
- uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
- char res95[12];
- uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
- char res96[12];
- uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
- char res97[12];
- uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
- char res98[12];
- uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
- char res99[12];
- uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
- char res100[12];
- uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
- char res101[12];
- uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
- char res102[12];
- uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
- char res103[12];
- uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
- char res104[12];
- uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
- char res105[12];
- uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
- char res106[12];
- uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
- char res107[12];
- uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
- char res108[12];
- uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
- char res109[12];
- uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
- char res110[12];
- uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
- char res111[12];
- uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
- char res112[12];
- uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
- char res113[12];
- uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
- char res114[12];
- uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
- char res115[12];
- uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
- char res116[12];
- uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
- char res117[12];
- uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
- char res118[12];
- uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
- char res119[12];
- uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
- char res120[12];
- uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
- char res121[12];
- uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
- char res122[12];
- uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
- char res123[12];
- uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
- char res124[12];
- uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
- char res125[12];
- uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
- char res126[12];
- uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
- char res127[12];
- uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
- char res128[12];
- uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
- char res129[12];
- uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
- char res130[12];
- uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
- char res131[12];
- uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
- char res132[12];
- uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
- char res133[12];
- uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
- char res134[12];
- uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
- char res135[12];
- uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
- char res136[12];
- uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
- char res137[12];
- uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
- char res138[12];
- uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
- char res139[12];
- uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
- char res140[12];
- uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
- char res141[12];
- uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
- char res142[4108];
- uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
- char res143[12];
- uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
- char res144[12];
- uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
- char res145[12];
- uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
- char res146[12];
- uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
- char res147[12];
- uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
- char res148[12];
- uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
- char res149[12];
- uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
- char res150[59852];
- uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
- char res151[12];
- uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
- char res152[12];
- uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
- char res153[12];
- uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
- char res154[12];
- uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
- char res155[12];
- uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
- char res156[12];
- uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
- char res157[12];
- uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
- char res158[3916];
-} ccsr_pic_t;
-
-/* RapidIO Registers(0xc_0000-0xe_0000) */
-
-typedef struct ccsr_rio {
- uint didcar; /* 0xc0000 - Device Identity Capability Register */
- uint dicar; /* 0xc0004 - Device Information Capability Register */
- uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
- uint aicar; /* 0xc000c - Assembly Information Capability Register */
- uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
- uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
- uint socar; /* 0xc0018 - Source Operations Capability Register */
- uint docar; /* 0xc001c - Destination Operations Capability Register */
- char res1[32];
- uint msr; /* 0xc0040 - Mailbox Command And Status Register */
- uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
- char res2[4];
- uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
- char res3[12];
- uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
- uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
- char res4[4];
- uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
- uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
- char res5[144];
- uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
- char res6[28];
- uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
- uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
- char res7[20];
- uint pgccsr; /* 0xc013c - Port General Command and Status Register */
- uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
- uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
- uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
- char res8[12];
- uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
- uint pccsr; /* 0xc015c - Port Control Command and Status Register */
- char res9[1184];
- uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
- char res10[4];
- uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
- uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
- char res11[4];
- uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
- uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
- uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
- char res12[32];
- uint edcsr; /* 0xc0640 - Port 0 error detect status register */
- uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
- uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
- uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
- uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
- uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
- uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
- char res13[12];
- uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
- uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
- char res14[63892];
- uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
- char res15[12];
- uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
- char res16[12];
- uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
- char res17[92];
- uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
- char res18[124];
- uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
- char res19[28];
- uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
- char res20[12];
- uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
- char res21[12];
- uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
- char res22[20];
- uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
- char res23[4];
- uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
- char res24[2716];
- uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
- uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
- char res25[8];
- uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
- char res26[12];
- uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
- uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
- uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
- char res27[4];
- uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
- uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
- uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
- uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
- uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
- uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
- uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
- char res28[4];
- uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
- uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
- uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
- uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
- uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
- uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
- uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
- char res29[4];
- uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
- uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
- uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
- uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
- uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
- uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
- uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
- char res30[4];
- uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
- uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
- uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
- uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
- uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
- uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
- uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
- char res31[4];
- uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
- uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
- uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
- uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
- uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
- uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
- uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
- char res32[4];
- uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
- uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
- uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
- uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
- uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
- uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
- uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
- char res33[4];
- uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
- uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
- uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
- uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
- uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
- uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
- uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
- char res34[4];
- uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
- uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
- uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
- uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
- char res35[64];
- uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
- uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
- char res36[4];
- uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
- char res37[12];
- uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
- char res38[4];
- uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
- char res39[4];
- uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
- char res40[12];
- uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
- char res41[4];
- uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
- char res42[4];
- uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
- char res43[12];
- uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
- char res44[4];
- uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
- char res45[4];
- uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
- char res46[12];
- uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
- char res47[12];
- uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
- char res48[12];
- uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
- uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
- uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
- uint pecr; /* 0xd0e0c - Port Error Control Register */
- uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
- uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
- uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
- char res49[4];
- uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
- char res50[4];
- uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
- uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
- char res51[8656];
- uint omr; /* 0xd3000 - Outbound Mode Register */
- uint osr; /* 0xd3004 - Outbound Status Register */
- uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
- uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
- uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
- uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
- uint odpr; /* 0xd3018 - Outbound Destination Port Register */
- uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
- uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
- uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
- uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
- uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
- uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
- uint omlr; /* 0xd3034 - Outbound Multicast List Register */
- char res52[40];
- uint imr; /* 0xd3060 - Outbound Mode Register */
- uint isr; /* 0xd3064 - Inbound Status Register */
- uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
- uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
- uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
- uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
- uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
- char res53[900];
- uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
- uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
- char res54[16];
- uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
- uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
- char res55[12];
- uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
- char res56[48];
- uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
- uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
- uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
- uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
- uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
- uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
- uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
- char res57[100];
- uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
- uint pwsr; /* 0xd34e4 - Port-Write Status Register */
- uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
- uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
- char res58[51984];
-} ccsr_rio_t;
-
-/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
-typedef struct ccsr_gur {
- uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
- uint porbmsr; /* 0xe0004 - POR boot mode status register */
- uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
- uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
- uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
- char res1[12];
- uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
- char res2[12];
- uint gpiocr; /* 0xe0030 - GPIO control register */
- char res3[12];
- uint gpoutdr; /* 0xe0040 - General-purpose output data register */
- char res4[12];
- uint gpindr; /* 0xe0050 - General-purpose input data register */
- char res5[12];
- uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
- char res6[12];
- uint devdisr; /* 0xe0070 - Device disable control */
- char res7[12];
- uint powmgtcsr; /* 0xe0080 - Power management status and control register */
- char res8[12];
- uint mcpsumr; /* 0xe0090 - Machine check summary register */
- uint rstrscr; /* 0xe0094 - Reset request status and control register */
- char res9[8];
- uint pvr; /* 0xe00a0 - Processor version register */
- uint svr; /* 0xe00a4 - System version register */
- char res10a[8];
- uint rstcr; /* 0xe00b0 - Reset control register */
- char res10b[1868];
- uint clkdvdr; /* 0xe0800 - Clock Divide register */
- char res10c[796];
- uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
- char res10d[4];
- uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
- char res10e[724];
- uint clkocr; /* 0xe0e00 - Clock out select register */
- char res11[12];
- uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
- char res12[12];
- uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
- char res13a[224];
- uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
- char res13b[4];
- uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
- char res14[24];
- uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
- char res15a[24];
- uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
- uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
- char res16[184];
-} ccsr_gur_t;
-
-#define MPC8610_PORBMSR_HA 0x00070000
-#define MPC8610_PORBMSR_HA_SHIFT 16
-#define MPC8641_PORBMSR_HA 0x00060000
-#define MPC8641_PORBMSR_HA_SHIFT 17
-#define MPC8610_PORDEVSR_IO_SEL 0x00380000
-#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
-#define MPC8641_PORDEVSR_IO_SEL 0x000F0000
-#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
-#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
-#define MPC86xx_DEVDISR_PCIEX1 0x80000000
-#define MPC86xx_DEVDISR_PCIEX2 0x40000000
-#define MPC86xx_DEVDISR_PCI1 0x80000000
-#define MPC86xx_DEVDISR_PCIE1 0x40000000
-#define MPC86xx_DEVDISR_PCIE2 0x20000000
-#define MPC86xx_DEVDISR_SRIO 0x00080000
-#define MPC86xx_DEVDISR_RMSG 0x00040000
-#define MPC86xx_DEVDISR_CPU0 0x00008000
-#define MPC86xx_DEVDISR_CPU1 0x00004000
-#define MPC86xx_RSTCR_HRST_REQ 0x00000002
-
-/*
- * Watchdog register block(0xe_4000-0xe_4fff)
- */
-typedef struct ccsr_wdt {
- uint res0;
- uint swcrr; /* System watchdog control register */
- uint swcnr; /* System watchdog count register */
- char res1[2];
- ushort swsrr; /* System watchdog service register */
- char res2[4080];
-} ccsr_wdt_t;
-
-typedef struct immap {
- ccsr_local_mcm_t im_local_mcm;
- struct ccsr_ddr im_ddr1;
- ccsr_i2c_t im_i2c;
- ccsr_duart_t im_duart;
- fsl_lbc_t im_lbc;
- struct ccsr_ddr im_ddr2;
- char res1[4096];
- ccsr_pex_t im_pex1;
- ccsr_pex_t im_pex2;
- ccsr_ht_t im_ht;
- char res2[90112];
- ccsr_dma_t im_dma;
- char res3[8192];
- ccsr_tsec_t im_tsec1;
- ccsr_tsec_t im_tsec2;
- ccsr_tsec_t im_tsec3;
- ccsr_tsec_t im_tsec4;
- char res4[98304];
- ccsr_pic_t im_pic;
- char res5[389120];
- ccsr_rio_t im_rio;
- ccsr_gur_t im_gur;
- char res6[12288];
- ccsr_wdt_t im_wdt;
-} immap_t;
-
-extern immap_t *immr;
-
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
-#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
-#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
-#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
-
-
-#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
-#ifdef CONFIG_ARCH_MPC8610
-#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
-#else
-#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
-#endif
-#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
-
-#define CONFIG_SYS_PCI1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
-#define CONFIG_SYS_PCI2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
-#define CONFIG_SYS_PCIE1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
-#define CONFIG_SYS_PCIE2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
-
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_MDIO1_OFFSET 0x24000
-#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
-
-#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
-
-#endif /*__IMMAP_86xx__*/
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 055364c58fd9..2923350bd7b9 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -15,10 +15,6 @@
#if defined(CONFIG_MPC8xx)
#include <asm/immap_8xx.h>
#endif
-#ifdef CONFIG_MPC86xx
-#include <mpc86xx.h>
-#include <asm/immap_86xx.h>
-#endif
#ifdef CONFIG_MPC85xx
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig
deleted file mode 100644
index 8dfc90cf8bc9..000000000000
--- a/board/sbc8641d/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SBC8641D
-
-config SYS_BOARD
- default "sbc8641d"
-
-config SYS_CONFIG_NAME
- default "sbc8641d"
-
-endif
diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS
deleted file mode 100644
index a50b541ffe84..000000000000
--- a/board/sbc8641d/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SBC8641D BOARD
-M: Paul Gortmaker <paul.gortmaker@windriver.com>
-S: Maintained
-F: board/sbc8641d/
-F: include/configs/sbc8641d.h
-F: configs/sbc8641d_defconfig
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
deleted file mode 100644
index c48f82d3d931..000000000000
--- a/board/sbc8641d/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += sbc8641d.o
-obj-y += law.o
-obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8641d/README b/board/sbc8641d/README
deleted file mode 100644
index 4999b7763c9c..000000000000
--- a/board/sbc8641d/README
+++ /dev/null
@@ -1,49 +0,0 @@
-Wind River SBC8641D reference board
-===========================
-
-Created 06/14/2007 Joe Hamman
-Copyright 2007, Embedded Specialties, Inc.
-Copyright 2007 Wind River Systems, Inc.
------------------------------
-
-1. Building U-Boot
-------------------
-The SBC8641D code is known to build using ELDK 4.1.
-
- $ make sbc8641d_config
- Configuring for sbc8641d board...
-
- $ make
-
-
-2. Switch and Jumper Settings
------------------------------
-All Jumpers & Switches are in their default positions. Please refer to
-the board documentation for details. Some settings control CPU voltages
-and settings may change with board revisions.
-
-3. Known limitations
---------------------
-PCI:
- The PCI command may hang if no boards are present in either slot.
-
-4. Reflashing U-Boot
---------------------
-The board has two independent flash devices which can be used for dual
-booting, or for U-Boot backup and recovery. A two pin jumper on the
-three pin JP10 determines which device is attached to /CS0 line.
-
-Assuming one device has a functional U-Boot, and the other device has
-a recently installed non-functional image, to perform a recovery from
-that non-functional image goes essentially as follows:
-
-a) power down the board and jumper JP10 to select the functional image.
-b) power on the board and let it get to U-Boot prompt.
-c) while on, using static precautions, move JP10 back to the failed image.
-d) use "md fff00000" to confirm you are looking at the failed image
-e) turn off write protect with "prot off all"
-f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin"
-g) erase failed image: "erase FFF00000 FFF5FFFF"
-h) copy in new image: "cp.b 200000 FFF00000 60000"
-i) ensure new image is written: "md fff00000"
-k) power cycle the board and confirm new image works.
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
deleted file mode 100644
index b6c1847b141b..000000000000
--- a/board/sbc8641d/ddr.c
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
deleted file mode 100644
index dc4696d123f4..000000000000
--- a/board/sbc8641d/law.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW (Local Access Window) configuration:
- *
- * 0x0000_0000 DDR 256M
- * 0x1000_0000 DDR2 256M
- * 0x8000_0000 PCIE1 MEM 512M
- * 0xa000_0000 PCIE2 MEM 512M
- * 0xc000_0000 RapidIO 512M
- * 0xe200_0000 PCIE1 IO 16M
- * 0xe300_0000 PCIE2 IO 16M
- * 0xf800_0000 CCSRBAR 2M
- * 0xfe00_0000 FLASH (boot bank) 32M
- *
- */
-
-
-struct law_entry law_table[] = {
-#if !defined(CONFIG_SPD_EEPROM)
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
-#endif
- SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
deleted file mode 100644
index a67092daf47f..000000000000
--- a/board/sbc8641d/sbc8641d.c
+++ /dev/null
@@ -1,268 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
- * Copyright 2007 Embedded Specialties, Inc.
- * Joe Hamman joe.hamman at embeddedspecialties.com
- *
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/processor.h>
-#include <asm/immap_86xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-long int fixed_sdram (void);
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("Board: Wind River SBC8641D\n");
-
- return 0;
-}
-
-int dram_init(void)
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fixed_sdram ();
-#endif
-
- debug(" DDR: ");
- gd->ram_size = dram_size;
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram(void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- puts ("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- puts ("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- puts ("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-long int fixed_sdram (void)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
- ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
- ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
- ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
- ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
-
- asm ("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
- asm ("sync; isync");
-
- udelay(500);
- ddr = &immap->im_ddr2;
-
- ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
- ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
- ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
- ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
- ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
- ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
- ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
- ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
- ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
- ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
- ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
-
- asm ("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
- asm ("sync; isync");
-
- udelay(500);
-#endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- return 0;
-}
-#endif
-
-void sbc8641d_reset_board (void)
-{
- puts ("Resetting board....\n");
-}
-
-/*
- * get_board_sys_clk
- * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
- */
-
-unsigned long get_board_sys_clk (ulong dummy)
-{
- int i;
- ulong val = 0;
-
- i = 5;
- i &= 0x07;
-
- switch (i) {
- case 0:
- val = 33000000;
- break;
- case 1:
- val = 40000000;
- break;
- case 2:
- val = 50000000;
- break;
- case 3:
- val = 66000000;
- break;
- case 4:
- val = 83000000;
- break;
- case 5:
- val = 100000000;
- break;
- case 6:
- val = 134000000;
- break;
- case 7:
- val = 166000000;
- break;
- }
-
- return val;
-}
-
-void board_reset(void)
-{
-#ifdef CONFIG_SYS_RESET_ADDRESS
- ulong addr = CONFIG_SYS_RESET_ADDRESS;
-
- /* flush and disable I/D cache */
- __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
- __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
- __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
- __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 4");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("mtspr 1008, 5");
- __asm__ __volatile__ ("isync");
- __asm__ __volatile__ ("sync");
-
- /*
- * SRR0 has system reset vector, SRR1 has default MSR value
- * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
- */
- __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
- __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
- __asm__ __volatile__ ("mtspr 27, 4");
- __asm__ __volatile__ ("rfi");
-#endif
-}
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
deleted file mode 100644
index ea601dea6f40..000000000000
--- a/configs/sbc8641d_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xfff00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC86xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_SBC8641D=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFFF60000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/doc/git-mailrc b/doc/git-mailrc
index f520ff89b390..b8299a1a6c30 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -99,7 +99,6 @@ alias ppc powerpc
alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@c-s.fr>
alias mpc83xx uboot, mariosix
alias mpc85xx uboot, afleming, priyankajain
-alias mpc86xx uboot, afleming, priyankajain
alias sandbox sjg
alias sb sandbox
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 890e62190b1a..e6a51f560978 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -2,8 +2,8 @@ config SYS_FSL_DDR
bool
help
Select Freescale General DDR driver, shared between most Freescale
- PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
- based Layerscape SoCs (such as ls2080a).
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
+ Layerscape SoCs (such as ls2080a).
config SYS_FSL_MMDC
bool
@@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS
ARCH_T4240
default 2 if ARCH_B4860 || \
ARCH_BSC9132 || \
- ARCH_MPC8641 || \
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_LX2160A || \
@@ -79,12 +78,6 @@ config SYS_FSL_DDRC_GEN2
help
Enable Freescale DDR2 controller.
-config SYS_FSL_DDRC_86XX_GEN2
- bool
- depends on MPC86xx
- help
- Enable Freescale DDR2 controller for MPC86xx SoCs.
-
config SYS_FSL_DDRC_GEN3
bool
depends on PPC
@@ -136,7 +129,6 @@ config SYS_FSL_DDR2
bool "Freescale DDR2 controller"
depends on SYS_FSL_HAS_DDR2
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
- select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
config SYS_FSL_DDR1
bool "Freescale DDR1 controller"
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index c675f44ab00c..8081d0cd82f3 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
-obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
deleted file mode 100644
index 43ed1ba432de..000000000000
--- a/drivers/ddr/fsl/mpc86xx_ddr.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <fsl_ddr_sdram.h>
-#include <linux/delay.h>
-
-#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
-#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
-#endif
-
-void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num, int step)
-{
- unsigned int i;
- struct ccsr_ddr __iomem *ddr;
-
- switch (ctrl_num) {
- case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
- break;
- case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
- break;
- default:
- printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
- return;
- }
-
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i == 0) {
- out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs0_config, regs->cs[i].config);
-
- } else if (i == 1) {
- out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs1_config, regs->cs[i].config);
-
- } else if (i == 2) {
- out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs2_config, regs->cs[i].config);
-
- } else if (i == 3) {
- out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
- out_be32(&ddr->cs3_config, regs->cs[i].config);
- }
- }
-
- out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
- out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
- out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
- out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
- out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
- out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
- out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
- out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
- out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
- out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
- out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
- out_be32(&ddr->init_addr, regs->ddr_init_addr);
- out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-
- debug("before go\n");
-
- /*
- * 200 painful micro-seconds must elapse between
- * the DDR clock setup and the DDR config enable.
- */
- udelay(200);
- asm volatile("sync;isync");
-
- out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
-
- /*
- * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
- */
- while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
- udelay(10000); /* throttle polling rate */
- }
-}
diff --git a/env/Kconfig b/env/Kconfig
index c06b8ba8cb7e..691f4d480cc4 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -85,7 +85,7 @@ config ENV_IS_IN_FLASH
default y if M548x || M547x || M5282
default y if MCF532x || MCF52x2
default y if MPC86xx || MPC83xx
- default y if ARCH_MPC8548 || ARCH_MPC8641
+ default y if ARCH_MPC8548
default y if SH && !CPU_SH4
help
Define this if you have a flash device which you want to use for the
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
deleted file mode 100644
index 3d5aee0dd58a..000000000000
--- a/include/configs/sbc8641d.h
+++ /dev/null
@@ -1,509 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007 Wind River Systems <www.windriver.com>
- * Copyright 2007 Embedded Specialties, Inc.
- * Joe Hamman <joe.hamman@embeddedspecialties.com>
- *
- * Copyright 2006 Freescale Semiconductor.
- *
- * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
- */
-
-/*
- * SBC8641D board configuration file
- *
- * Make sure you change the MAC address and other network params first,
- * search for CONFIG_SERVERIP, etc in this file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-
-#ifdef RUN_DIAG
-#define CONFIG_SYS_DIAG_ADDR 0xff800000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
-
-/*
- * virtual address to be used for temporary mappings. There
- * should be 128k free at this VA.
- */
-#define CONFIG_SYS_SCRATCH_VA 0xe8000000
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-
-#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-
-#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CACHE_LINE_INTERLEAVING 0x20000000
-#define PAGE_INTERLEAVING 0x21000000
-#define BANK_INTERLEAVING 0x22000000
-#define SUPER_BANK_INTERLEAVING 0x23000000
-
-#define CONFIG_ALTIVEC 1
-
-/*
- * L2CR setup -- make sure this is right for your board!
- */
-#define CONFIG_SYS_L2
-#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E)
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
-#endif
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
-#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 2
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-#if defined(CONFIG_SPD_EEPROM)
- /*
- * Determine DDR configuration from I2C interface.
- */
- #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
- #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
- #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
- #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
-
-#else
- /*
- * Manually set up DDR1 & DDR2 parameters
- */
-
- #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-
- #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
- #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
- #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
- #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
- #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
- #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
- #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
- #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
- #define CONFIG_SYS_DDR_TIMING_3 0x00000000
- #define CONFIG_SYS_DDR_TIMING_0 0x00220802
- #define CONFIG_SYS_DDR_TIMING_1 0x38377322
- #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
- #define CONFIG_SYS_DDR_CFG_1A 0x43008008
- #define CONFIG_SYS_DDR_CFG_2 0x24401000
- #define CONFIG_SYS_DDR_MODE_1 0x23c00542
- #define CONFIG_SYS_DDR_MODE_2 0x00000000
- #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
- #define CONFIG_SYS_DDR_INTERVAL 0x05080100
- #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
- #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
- #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
-
- #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
- #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
- #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
- #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
- #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
- #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
- #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
- #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
- #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
- #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
- #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
- #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
- #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
- #define CONFIG_SYS_DDR2_CFG_2 0x24401000
- #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
- #define CONFIG_SYS_DDR2_MODE_2 0x00000000
- #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
- #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
- #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
- #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
- #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
-
-#endif
-
-/* #define CONFIG_ID_EEPROM 1
-#define ID_EEPROM_ADDR 0x57 */
-
-/*
- * The SBC8641D contains 16MB flash space at ff000000.
- */
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-
-/* Flash */
-#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
-
-/* 64KB EEPROM */
-#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
-
-/* EPLD - User switches, board id, LEDs */
-#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
-
-/* Local bus SDRAM 128MB */
-#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
-#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
-#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
-
-/* Disk on Chip (DOC) 128MB */
-#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
-#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
-
-/* LCD */
-#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
-#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
-
-/* Control logic & misc peripherals */
-#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
-#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
-
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#ifndef CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
-#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
-#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
-#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
-
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
-#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
-#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xe0000000
- #define PCI_ENET0_MEMADDR 0xe0000000
- #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC3"
-#define CONFIG_TSEC4 1
-#define CONFIG_TSEC4_NAME "eTSEC4"
-
-#define TSEC1_PHY_ADDR 0x1F
-#define TSEC2_PHY_ADDR 0x00
-#define TSEC3_PHY_ADDR 0x01
-#define TSEC4_PHY_ADDR 0x02
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC3_FLAGS TSEC_GIGABIT
-#define TSEC4_FLAGS TSEC_GIGABIT
-
-#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
-
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * BAT0 2G Cacheable, non-guarded
- * 0x0000_0000 2G DDR
- */
-#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
-
-/*
- * BAT1 1G Cache-inhibited, guarded
- * 0x8000_0000 512M PCI-Express 1 Memory
- * 0xa000_0000 512M PCI-Express 2 Memory
- * Changed it for operating from 0xd0000000
- */
-#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
-
-/*
- * BAT2 512M Cache-inhibited, guarded
- * 0xc000_0000 512M RapidIO Memory
- */
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
-
-/*
- * BAT3 4M Cache-inhibited, guarded
- * 0xf800_0000 4M CCSR
- */
-#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
- | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
-#endif
-
-/*
- * BAT4 32M Cache-inhibited, guarded
- * 0xe200_0000 16M PCI-Express 1 I/O
- * 0xe300_0000 16M PCI-Express 2 I/0
- * Note that this is at 0xe0000000
- */
-#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
-
-/*
- * BAT5 128K Cacheable, non-guarded
- * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
- */
-#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
-#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
-
-/*
- * BAT6 32M Cache-inhibited, guarded
- * 0xfe00_0000 32M FLASH
- */
-#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
-
-/* Map the last 1M of flash where we're running from reset */
-#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
-
-#define CONFIG_SYS_DBAT7L 0x00000000
-#define CONFIG_SYS_DBAT7U 0x00000000
-#define CONFIG_SYS_IBAT7L 0x00000000
-#define CONFIG_SYS_IBAT7U 0x00000000
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 32768
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_ETH0 1
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_HAS_ETH2 1
-#define CONFIG_HAS_ETH3 1
-
-#define CONFIG_IPADDR 192.168.0.50
-
-#define CONFIG_HOSTNAME "sbc8641d"
-#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_NETMASK 255.255.255.0
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=uRamdisk\0" \
- "dtbaddr=400000\0" \
- "dtbfile=sbc8641d.dtb\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
- "maxcpus=1"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr $ramdiskaddr $dtbaddr"
-
-#define CONFIG_FLASHBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "bootm ffd00000 ffb00000 ffa00000"
-
-#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/post.h b/include/post.h
index 5695e2b5334f..a07a6bc5e252 100644
--- a/include/post.h
+++ b/include/post.h
@@ -29,11 +29,6 @@
#include <asm/immap_85xx.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
offsetof(ccsr_pic_t, tfrr))
-
-#elif defined (CONFIG_MPC86xx)
-#include <asm/immap_86xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
- offsetof(ccsr_pic_t, tfrr))
#endif
#ifndef _POST_WORD_ADDR
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 21/27] ppc: Remove sbc8641d board
2021-05-15 1:34 ` [PATCH 21/27] ppc: Remove sbc8641d board Tom Rini
@ 2021-05-15 15:20 ` Simon Glass
2021-05-15 19:15 ` Paul Gortmaker
2021-07-08 2:53 ` Tom Rini
2 siblings, 0 replies; 71+ messages in thread
From: Simon Glass @ 2021-05-15 15:20 UTC (permalink / raw)
To: u-boot
Hi Tom,
On Fri, 14 May 2021 at 20:48, Tom Rini <trini@konsulko.com> wrote:
>
> This board has not been converted to CONFIG_DM_PCI by the deadline and is
> also missing conversion to CONFIG_DM. Remove it. This is also the last
> of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> .azure-pipelines.yml | 2 +-
> MAINTAINERS | 6 -
> README | 3 +-
> arch/powerpc/Kconfig | 7 -
> arch/powerpc/cpu/mpc86xx/Kconfig | 52 -
> arch/powerpc/cpu/mpc86xx/Makefile | 24 -
> arch/powerpc/cpu/mpc86xx/cache.S | 332 ------
> arch/powerpc/cpu/mpc86xx/config.mk | 6 -
> arch/powerpc/cpu/mpc86xx/cpu.c | 207 ----
> arch/powerpc/cpu/mpc86xx/cpu_init.c | 104 --
> arch/powerpc/cpu/mpc86xx/fdt.c | 52 -
> arch/powerpc/cpu/mpc86xx/interrupts.c | 116 --
> arch/powerpc/cpu/mpc86xx/mp.c | 130 ---
> arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 87 --
> arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 96 --
> arch/powerpc/cpu/mpc86xx/release.S | 149 ---
> arch/powerpc/cpu/mpc86xx/speed.c | 134 ---
> arch/powerpc/cpu/mpc86xx/start.S | 982 -----------------
> arch/powerpc/cpu/mpc86xx/traps.c | 199 ----
> arch/powerpc/cpu/mpc86xx/u-boot.lds | 77 --
> arch/powerpc/include/asm/config.h | 4 -
> arch/powerpc/include/asm/config_mpc86xx.h | 9 -
> arch/powerpc/include/asm/fsl_law.h | 7 -
> arch/powerpc/include/asm/fsl_pci.h | 2 +-
> arch/powerpc/include/asm/immap_86xx.h | 1221 ---------------------
> arch/powerpc/include/asm/ppc.h | 4 -
> board/sbc8641d/Kconfig | 9 -
> board/sbc8641d/MAINTAINERS | 6 -
> board/sbc8641d/Makefile | 8 -
> board/sbc8641d/README | 49 -
> board/sbc8641d/ddr.c | 53 -
> board/sbc8641d/law.c | 39 -
> board/sbc8641d/sbc8641d.c | 268 -----
> configs/sbc8641d_defconfig | 39 -
> doc/git-mailrc | 1 -
> drivers/ddr/fsl/Kconfig | 12 +-
> drivers/ddr/fsl/Makefile | 1 -
> drivers/ddr/fsl/mpc86xx_ddr.c | 84 --
> env/Kconfig | 2 +-
> include/configs/sbc8641d.h | 509 ---------
> include/post.h | 5 -
> 41 files changed, 6 insertions(+), 5091 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc86xx/Kconfig
> delete mode 100644 arch/powerpc/cpu/mpc86xx/Makefile
> delete mode 100644 arch/powerpc/cpu/mpc86xx/cache.S
> delete mode 100644 arch/powerpc/cpu/mpc86xx/config.mk
> delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu_init.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/fdt.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/interrupts.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/mp.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/release.S
> delete mode 100644 arch/powerpc/cpu/mpc86xx/speed.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/start.S
> delete mode 100644 arch/powerpc/cpu/mpc86xx/traps.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/u-boot.lds
> delete mode 100644 arch/powerpc/include/asm/config_mpc86xx.h
> delete mode 100644 arch/powerpc/include/asm/immap_86xx.h
> delete mode 100644 board/sbc8641d/Kconfig
> delete mode 100644 board/sbc8641d/MAINTAINERS
> delete mode 100644 board/sbc8641d/Makefile
> delete mode 100644 board/sbc8641d/README
> delete mode 100644 board/sbc8641d/ddr.c
> delete mode 100644 board/sbc8641d/law.c
> delete mode 100644 board/sbc8641d/sbc8641d.c
> delete mode 100644 configs/sbc8641d_defconfig
> delete mode 100644 drivers/ddr/fsl/mpc86xx_ddr.c
> delete mode 100644 include/configs/sbc8641d.h
>
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 21/27] ppc: Remove sbc8641d board
2021-05-15 1:34 ` [PATCH 21/27] ppc: Remove sbc8641d board Tom Rini
2021-05-15 15:20 ` Simon Glass
@ 2021-05-15 19:15 ` Paul Gortmaker
2021-07-08 2:53 ` Tom Rini
2 siblings, 0 replies; 71+ messages in thread
From: Paul Gortmaker @ 2021-05-15 19:15 UTC (permalink / raw)
To: u-boot
[[PATCH 21/27] ppc: Remove sbc8641d board] On 14/05/2021 (Fri 21:34) Tom Rini wrote:
> This board has not been converted to CONFIG_DM_PCI by the deadline and is
> also missing conversion to CONFIG_DM. Remove it. This is also the last
> of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Ack'd -- I'd sent the kernel removal several months ago, but that hasn't
been merged yet...
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20210111082823.99562-3-paul.gortmaker at windriver.com/
Thanks,
Paul.
--
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> .azure-pipelines.yml | 2 +-
> MAINTAINERS | 6 -
> README | 3 +-
> arch/powerpc/Kconfig | 7 -
> arch/powerpc/cpu/mpc86xx/Kconfig | 52 -
> arch/powerpc/cpu/mpc86xx/Makefile | 24 -
> arch/powerpc/cpu/mpc86xx/cache.S | 332 ------
> arch/powerpc/cpu/mpc86xx/config.mk | 6 -
> arch/powerpc/cpu/mpc86xx/cpu.c | 207 ----
> arch/powerpc/cpu/mpc86xx/cpu_init.c | 104 --
> arch/powerpc/cpu/mpc86xx/fdt.c | 52 -
> arch/powerpc/cpu/mpc86xx/interrupts.c | 116 --
> arch/powerpc/cpu/mpc86xx/mp.c | 130 ---
> arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 87 --
> arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 96 --
> arch/powerpc/cpu/mpc86xx/release.S | 149 ---
> arch/powerpc/cpu/mpc86xx/speed.c | 134 ---
> arch/powerpc/cpu/mpc86xx/start.S | 982 -----------------
> arch/powerpc/cpu/mpc86xx/traps.c | 199 ----
> arch/powerpc/cpu/mpc86xx/u-boot.lds | 77 --
> arch/powerpc/include/asm/config.h | 4 -
> arch/powerpc/include/asm/config_mpc86xx.h | 9 -
> arch/powerpc/include/asm/fsl_law.h | 7 -
> arch/powerpc/include/asm/fsl_pci.h | 2 +-
> arch/powerpc/include/asm/immap_86xx.h | 1221 ---------------------
> arch/powerpc/include/asm/ppc.h | 4 -
> board/sbc8641d/Kconfig | 9 -
> board/sbc8641d/MAINTAINERS | 6 -
> board/sbc8641d/Makefile | 8 -
> board/sbc8641d/README | 49 -
> board/sbc8641d/ddr.c | 53 -
> board/sbc8641d/law.c | 39 -
> board/sbc8641d/sbc8641d.c | 268 -----
> configs/sbc8641d_defconfig | 39 -
> doc/git-mailrc | 1 -
> drivers/ddr/fsl/Kconfig | 12 +-
> drivers/ddr/fsl/Makefile | 1 -
> drivers/ddr/fsl/mpc86xx_ddr.c | 84 --
> env/Kconfig | 2 +-
> include/configs/sbc8641d.h | 509 ---------
> include/post.h | 5 -
> 41 files changed, 6 insertions(+), 5091 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc86xx/Kconfig
> delete mode 100644 arch/powerpc/cpu/mpc86xx/Makefile
> delete mode 100644 arch/powerpc/cpu/mpc86xx/cache.S
> delete mode 100644 arch/powerpc/cpu/mpc86xx/config.mk
> delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu_init.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/fdt.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/interrupts.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/mp.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/release.S
> delete mode 100644 arch/powerpc/cpu/mpc86xx/speed.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/start.S
> delete mode 100644 arch/powerpc/cpu/mpc86xx/traps.c
> delete mode 100644 arch/powerpc/cpu/mpc86xx/u-boot.lds
> delete mode 100644 arch/powerpc/include/asm/config_mpc86xx.h
> delete mode 100644 arch/powerpc/include/asm/immap_86xx.h
> delete mode 100644 board/sbc8641d/Kconfig
> delete mode 100644 board/sbc8641d/MAINTAINERS
> delete mode 100644 board/sbc8641d/Makefile
> delete mode 100644 board/sbc8641d/README
> delete mode 100644 board/sbc8641d/ddr.c
> delete mode 100644 board/sbc8641d/law.c
> delete mode 100644 board/sbc8641d/sbc8641d.c
> delete mode 100644 configs/sbc8641d_defconfig
> delete mode 100644 drivers/ddr/fsl/mpc86xx_ddr.c
> delete mode 100644 include/configs/sbc8641d.h
>
> diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
> index 59e99b8894c5..8a567832ddac 100644
> --- a/.azure-pipelines.yml
> +++ b/.azure-pipelines.yml
> @@ -415,7 +415,7 @@ jobs:
> t208xrdb_corenet_ds:
> BUILDMAN: "t208xrdb corenet_ds"
> fsl_ppc:
> - BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
> + BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
> t102x:
> BUILDMAN: "t102*"
> p1_p2_rdb_pc:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 20092cb36740..7e36eb56a3af 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -973,12 +973,6 @@ S: Maintained
> T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
> F: arch/powerpc/cpu/mpc85xx/
>
> -POWERPC MPC86XX
> -M: Priyanka Jain <priyanka.jain@nxp.com>
> -S: Maintained
> -T: git https://source.denx.de/u-boot/custodians/u-boot-mpc86xx.git
> -F: arch/powerpc/cpu/mpc86xx/
> -
> RISC-V
> M: Rick Chen <rick@andestech.com>
> S: Maintained
> diff --git a/README b/README
> index ad13092bbb7a..63568dc43c74 100644
> --- a/README
> +++ b/README
> @@ -423,8 +423,7 @@ The following options need to be configured:
>
> CONFIG_SYS_FSL_DDR
> Freescale DDR driver in use. This type of DDR controller is
> - found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
> - SoCs.
> + found in mpc83xx, mpc85xx as well as some ARM core SoCs.
>
> CONFIG_SYS_FSL_DDR_ADDR
> Freescale DDR memory-mapped register base.
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 133447648cc6..737bdd8edb41 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -25,12 +25,6 @@ config MPC85xx
> imply CMD_IRQ
> imply USB_EHCI_HCD if USB
>
> -config MPC86xx
> - bool "MPC86xx"
> - select SYS_FSL_DDR
> - select SYS_FSL_DDR_BE
> - imply CMD_REGINFO
> -
> config MPC8xx
> bool "MPC8xx"
> select BOARD_EARLY_INIT_F
> @@ -47,7 +41,6 @@ config HIGH_BATS
>
> source "arch/powerpc/cpu/mpc83xx/Kconfig"
> source "arch/powerpc/cpu/mpc85xx/Kconfig"
> -source "arch/powerpc/cpu/mpc86xx/Kconfig"
> source "arch/powerpc/cpu/mpc8xx/Kconfig"
> source "arch/powerpc/lib/Kconfig"
>
> diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
> deleted file mode 100644
> index 1ee87038bed4..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/Kconfig
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -menu "mpc86xx CPU"
> - depends on MPC86xx
> -
> -config SYS_CPU
> - default "mpc86xx"
> -
> -choice
> - prompt "Target select"
> - optional
> -
> -config TARGET_SBC8641D
> - bool "Support sbc8641d"
> - select ARCH_MPC8641
> - select BOARD_EARLY_INIT_F
> -
> -endchoice
> -
> -config ARCH_MPC8610
> - bool
> - select FSL_LAW
> - select SYS_FSL_HAS_DDR1
> - select SYS_FSL_HAS_DDR2
> -
> -config ARCH_MPC8641
> - bool
> - select FSL_LAW
> - select SYS_FSL_HAS_DDR1
> - select SYS_FSL_HAS_DDR2
> -
> -config FSL_LAW
> - bool
> - help
> - Use Freescale common code for Local Access Window
> -
> -config SYS_CCSRBAR_DEFAULT
> - hex "Default CCSRBAR address"
> - default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
> - help
> - Default value of CCSRBAR comes from power-on-reset. It
> - is fixed on each SoC. Some SoCs can have different value
> - if changed by pre-boot regime. The value here must match
> - the current value in SoC. If not sure, do not change.
> -config SYS_FSL_NUM_LAWS
> - int "Number of local access windows"
> - default 10 if ARCH_MPC8610 || ARCH_MPC8641
> - help
> - Number of local access windows. This is fixed per SoC.
> - If not sure, do not change.
> -
> -source "board/sbc8641d/Kconfig"
> -
> -endmenu
> diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
> deleted file mode 100644
> index 6e12be6a3f24..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/Makefile
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright 2007 Freescale Semiconductor, Inc.
> -# (C) Copyright 2002,2003 Motorola Inc.
> -# Xianghua Xiao,X.Xiao at motorola.com
> -#
> -# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
> -# Jeff Brown
> -#
> -
> -extra-y = start.o
> -extra-y += traps.o
> -
> -obj-y += cache.o
> -obj-$(CONFIG_MP) += release.o
> -
> -obj-y += cpu.o
> -obj-y += cpu_init.o
> -obj-$(CONFIG_OF_LIBFDT) += fdt.o
> -obj-y += interrupts.o
> -obj-$(CONFIG_MP) += mp.o
> -obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o
> -obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o
> -obj-y += speed.o
> diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S
> deleted file mode 100644
> index 34968c604d7b..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/cache.S
> +++ /dev/null
> @@ -1,332 +0,0 @@
> -#include <config.h>
> -#include <mpc86xx.h>
> -
> -#include <ppc_asm.tmpl>
> -#include <ppc_defs.h>
> -
> -#include <asm/cache.h>
> -#include <asm/mmu.h>
> -
> -#ifndef CACHE_LINE_SIZE
> -# define CACHE_LINE_SIZE L1_CACHE_BYTES
> -#endif
> -
> -#if CACHE_LINE_SIZE == 128
> -#define LG_CACHE_LINE_SIZE 7
> -#elif CACHE_LINE_SIZE == 32
> -#define LG_CACHE_LINE_SIZE 5
> -#elif CACHE_LINE_SIZE == 16
> -#define LG_CACHE_LINE_SIZE 4
> -#elif CACHE_LINE_SIZE == 8
> -#define LG_CACHE_LINE_SIZE 3
> -#else
> -# error "Invalid cache line size!"
> -#endif
> -
> -/*
> - * Most of this code is taken from 74xx_7xx/cache.S
> - * and then cleaned up a bit
> - */
> -
> -/*
> - * Invalidate L1 instruction cache.
> - */
> -_GLOBAL(invalidate_l1_instruction_cache)
> - /* use invalidate-all bit in HID0 */
> - mfspr r3,HID0
> - ori r3,r3,HID0_ICFI
> - mtspr HID0,r3
> - isync
> - blr
> -
> -/*
> - * Invalidate L1 data cache.
> - */
> -_GLOBAL(invalidate_l1_data_cache)
> - mfspr r3,HID0
> - ori r3,r3,HID0_DCFI
> - mtspr HID0,r3
> - isync
> - blr
> -
> -/*
> - * Flush data cache.
> - */
> -_GLOBAL(flush_dcache)
> - lis r3,0
> - lis r5,CACHE_LINE_SIZE
> -flush:
> - cmp 0,1,r3,r5
> - bge done
> - lwz r5,0(r3)
> - lis r5,CACHE_LINE_SIZE
> - addi r3,r3,0x4
> - b flush
> -done:
> - blr
> -/*
> - * Write any modified data cache blocks out to memory
> - * and invalidate the corresponding instruction cache blocks.
> - * This is a no-op on the 601.
> - *
> - * flush_icache_range(unsigned long start, unsigned long stop)
> - */
> -_GLOBAL(flush_icache_range)
> - li r5,CACHE_LINE_SIZE-1
> - andc r3,r3,r5
> - subf r4,r3,r4
> - add r4,r4,r5
> - srwi. r4,r4,LG_CACHE_LINE_SIZE
> - beqlr
> - mtctr r4
> - mr r6,r3
> -1: dcbst 0,r3
> - addi r3,r3,CACHE_LINE_SIZE
> - bdnz 1b
> - sync /* wait for dcbst's to get to ram */
> - mtctr r4
> -2: icbi 0,r6
> - addi r6,r6,CACHE_LINE_SIZE
> - bdnz 2b
> - sync /* additional sync needed on g4 */
> - isync
> - blr
> -/*
> - * Write any modified data cache blocks out to memory.
> - * Does not invalidate the corresponding cache lines (especially for
> - * any corresponding instruction cache).
> - *
> - * clean_dcache_range(unsigned long start, unsigned long stop)
> - */
> -_GLOBAL(clean_dcache_range)
> - li r5,CACHE_LINE_SIZE-1
> - andc r3,r3,r5 /* align r3 down to cache line */
> - subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
> - add r4,r4,r5 /* r4 += cache_line_size-1 */
> - srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
> - beqlr /* if r4 == 0 return */
> - mtctr r4 /* ctr = r4 */
> -
> - sync
> -1: dcbst 0,r3
> - addi r3,r3,CACHE_LINE_SIZE
> - bdnz 1b
> - sync /* wait for dcbst's to get to ram */
> - blr
> -
> -/*
> - * Flush a particular page from the data cache to RAM.
> - * Note: this is necessary because the instruction cache does *not*
> - * snoop from the data cache.
> - *
> - * void __flush_page_to_ram(void *page)
> - */
> -_GLOBAL(__flush_page_to_ram)
> - rlwinm r3,r3,0,0,19 /* Get page base address */
> - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
> - mtctr r4
> - mr r6,r3
> -0: dcbst 0,r3 /* Write line to ram */
> - addi r3,r3,CACHE_LINE_SIZE
> - bdnz 0b
> - sync
> - mtctr r4
> -1: icbi 0,r6
> - addi r6,r6,CACHE_LINE_SIZE
> - bdnz 1b
> - sync
> - isync
> - blr
> -
> -/*
> - * Flush a particular page from the instruction cache.
> - * Note: this is necessary because the instruction cache does *not*
> - * snoop from the data cache.
> - *
> - * void __flush_icache_page(void *page)
> - */
> -_GLOBAL(__flush_icache_page)
> - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
> - mtctr r4
> -1: icbi 0,r3
> - addi r3,r3,CACHE_LINE_SIZE
> - bdnz 1b
> - sync
> - isync
> - blr
> -
> -/*
> - * Clear a page using the dcbz instruction, which doesn't cause any
> - * memory traffic (except to write out any cache lines which get
> - * displaced). This only works on cacheable memory.
> - */
> -_GLOBAL(clear_page)
> - li r0,4096/CACHE_LINE_SIZE
> - mtctr r0
> -1: dcbz 0,r3
> - addi r3,r3,CACHE_LINE_SIZE
> - bdnz 1b
> - blr
> -
> -/*
> - * Enable L1 Instruction cache
> - */
> -_GLOBAL(icache_enable)
> - mfspr r3, HID0
> - li r5, HID0_ICFI|HID0_ILOCK
> - andc r3, r3, r5
> - ori r3, r3, HID0_ICE
> - ori r5, r3, HID0_ICFI
> - mtspr HID0, r5
> - mtspr HID0, r3
> - isync
> - blr
> -
> -/*
> - * Disable L1 Instruction cache
> - */
> -_GLOBAL(icache_disable)
> - mflr r4
> - bl invalidate_l1_instruction_cache /* uses r3 */
> - sync
> - mtlr r4
> - mfspr r3, HID0
> - li r5, 0
> - ori r5, r5, HID0_ICE
> - andc r3, r3, r5
> - mtspr HID0, r3
> - isync
> - blr
> -
> -/*
> - * Is instruction cache enabled?
> - */
> -_GLOBAL(icache_status)
> - mfspr r3, HID0
> - andi. r3, r3, HID0_ICE
> - blr
> -
> -
> -_GLOBAL(l1dcache_enable)
> - mfspr r3, HID0
> - li r5, HID0_DCFI|HID0_DLOCK
> - andc r3, r3, r5
> - mtspr HID0, r3 /* no invalidate, unlock */
> - ori r3, r3, HID0_DCE
> - ori r5, r3, HID0_DCFI
> - mtspr HID0, r5 /* enable + invalidate */
> - mtspr HID0, r3 /* enable */
> - sync
> - blr
> -
> -/*
> - * Enable data cache(s) - L1 and optionally L2
> - * Calls l2cache_enable. LR saved in r5
> - */
> -_GLOBAL(dcache_enable)
> - mfspr r3, HID0
> - li r5, HID0_DCFI|HID0_DLOCK
> - andc r3, r3, r5
> - mtspr HID0, r3 /* no invalidate, unlock */
> - ori r3, r3, HID0_DCE
> - ori r5, r3, HID0_DCFI
> - mtspr HID0, r5 /* enable + invalidate */
> - mtspr HID0, r3 /* enable */
> - sync
> -#ifdef CONFIG_SYS_L2
> - mflr r5
> - bl l2cache_enable /* uses r3 and r4 */
> - sync
> - mtlr r5
> -#endif
> - blr
> -
> -
> -/*
> - * Disable data cache(s) - L1 and optionally L2
> - * Calls flush_dcache and l2cache_disable_no_flush.
> - * LR saved in r4
> - */
> -_GLOBAL(dcache_disable)
> - mflr r4 /* save link register */
> - bl flush_dcache /* uses r3 and r5 */
> - sync
> - mfspr r3, HID0
> - li r5, HID0_DCFI|HID0_DLOCK
> - andc r3, r3, r5
> - mtspr HID0, r3 /* no invalidate, unlock */
> - li r5, HID0_DCE|HID0_DCFI
> - andc r3, r3, r5 /* no enable, no invalidate */
> - mtspr HID0, r3
> - sync
> -#ifdef CONFIG_SYS_L2
> - bl l2cache_disable_no_flush /* uses r3 */
> -#endif
> - mtlr r4 /* restore link register */
> - blr
> -
> -/*
> - * Is data cache enabled?
> - */
> -_GLOBAL(dcache_status)
> - mfspr r3, HID0
> - andi. r3, r3, HID0_DCE
> - blr
> -
> -/*
> - * Invalidate L2 cache using L2I, assume L2 is enabled
> - */
> -_GLOBAL(l2cache_invalidate)
> - mfspr r3, l2cr
> - rlwinm. r3, r3, 0, 0, 0
> - beq 1f
> -
> - mfspr r3, l2cr
> - rlwinm r3, r3, 0, 1, 31
> -
> -#ifdef CONFIG_ALTIVEC
> - dssall
> -#endif
> - sync
> - mtspr l2cr, r3
> - sync
> -1: mfspr r3, l2cr
> - oris r3, r3, L2CR_L2I at h
> - mtspr l2cr, r3
> -
> -invl2:
> - mfspr r3, l2cr
> - andis. r3, r3, L2CR_L2I at h
> - bne invl2
> - blr
> -
> -/*
> - * Enable L2 cache
> - * Calls l2cache_invalidate. LR is saved in r4
> - */
> -_GLOBAL(l2cache_enable)
> - mflr r4 /* save link register */
> - bl l2cache_invalidate /* uses r3 */
> - sync
> - lis r3, L2_ENABLE at h
> - ori r3, r3, L2_ENABLE at l
> - mtspr l2cr, r3
> - isync
> - mtlr r4 /* restore link register */
> - blr
> -
> -/*
> - * Disable L2 cache
> - * Calls flush_dcache. LR is saved in r4
> - */
> -_GLOBAL(l2cache_disable)
> - mflr r4 /* save link register */
> - bl flush_dcache /* uses r3 and r5 */
> - sync
> - mtlr r4 /* restore link register */
> -l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
> - lis r3, L2_INIT at h
> - ori r3, r3, L2_INIT at l
> - mtspr l2cr, r3
> - isync
> - blr
> diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk
> deleted file mode 100644
> index 5db5b0b4ed7e..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/config.mk
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2004 Freescale Semiconductor.
> -# Jeff Brown
> -
> -PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float
> diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
> deleted file mode 100644
> index 98b42bff7a3b..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/cpu.c
> +++ /dev/null
> @@ -1,207 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
> - * Jeff Brown
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - */
> -
> -#include <common.h>
> -#include <cpu_func.h>
> -#include <log.h>
> -#include <time.h>
> -#include <vsprintf.h>
> -#include <watchdog.h>
> -#include <command.h>
> -#include <asm/cache.h>
> -#include <asm/global_data.h>
> -#include <asm/mmu.h>
> -#include <mpc86xx.h>
> -#include <asm/fsl_law.h>
> -#include <asm/ppc.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/*
> - * Default board reset function
> - */
> -static void
> -__board_reset(void)
> -{
> - /* Do nothing */
> -}
> -void board_reset(void) __attribute__((weak, alias("__board_reset")));
> -
> -
> -int
> -checkcpu(void)
> -{
> - sys_info_t sysinfo;
> - uint pvr, svr;
> - uint major, minor;
> - char buf1[32], buf2[32];
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> - volatile ccsr_gur_t *gur = &immap->im_gur;
> - struct cpu_type *cpu;
> - uint msscr0 = mfspr(MSSCR0);
> -
> - svr = get_svr();
> - major = SVR_MAJ(svr);
> - minor = SVR_MIN(svr);
> -
> - if (cpu_numcores() > 1) {
> -#ifndef CONFIG_MP
> - puts("Unicore software on multiprocessor system!!\n"
> - "To enable mutlticore build define CONFIG_MP\n");
> -#endif
> - }
> - puts("CPU: ");
> -
> - cpu = gd->arch.cpu;
> -
> - puts(cpu->name);
> -
> - printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
> - puts("Core: ");
> -
> - pvr = get_pvr();
> - major = PVR_E600_MAJ(pvr);
> - minor = PVR_E600_MIN(pvr);
> -
> - printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
> - if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
> - puts("\n Core1Translation Enabled");
> - debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
> -
> - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
> -
> - get_sys_info(&sysinfo);
> -
> - puts("Clock Configuration:\n");
> - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
> - printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
> - printf(" DDR:%-4s MHz (%s MT/s data rate), ",
> - strmhz(buf1, sysinfo.freq_systembus / 2),
> - strmhz(buf2, sysinfo.freq_systembus));
> -
> - if (sysinfo.freq_localbus > LCRR_CLKDIV) {
> - printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
> - } else {
> - printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
> - sysinfo.freq_localbus);
> - }
> -
> - puts("L1: D-cache 32 KiB enabled\n");
> - puts(" I-cache 32 KiB enabled\n");
> -
> - puts("L2: ");
> - if (get_l2cr() & 0x80000000) {
> -#if defined(CONFIG_ARCH_MPC8610)
> - puts("256");
> -#elif defined(CONFIG_ARCH_MPC8641)
> - puts("512");
> -#endif
> - puts(" KiB enabled\n");
> - } else {
> - puts("Disabled\n");
> - }
> -
> - return 0;
> -}
> -
> -
> -int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
> -{
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile ccsr_gur_t *gur = &immap->im_gur;
> -
> - /* Attempt board-specific reset */
> - board_reset();
> -
> - /* Next try asserting HRESET_REQ */
> - out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
> -
> - while (1)
> - ;
> -
> - return 1;
> -}
> -
> -
> -/*
> - * Get timebase clock frequency
> - */
> -unsigned long
> -get_tbclk(void)
> -{
> - sys_info_t sys_info;
> -
> - get_sys_info(&sys_info);
> - return (sys_info.freq_systembus + 3L) / 4L;
> -}
> -
> -
> -#if defined(CONFIG_WATCHDOG)
> -void
> -watchdog_reset(void)
> -{
> -#if defined(CONFIG_ARCH_MPC8610)
> - /*
> - * This actually feed the hard enabled watchdog.
> - */
> - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
> - volatile ccsr_wdt_t *wdt = &immap->im_wdt;
> - volatile ccsr_gur_t *gur = &immap->im_gur;
> - u32 tmp = gur->pordevsr;
> -
> - if (tmp & 0x4000) {
> - wdt->swsrr = 0x556c;
> - wdt->swsrr = 0xaa39;
> - }
> -#endif
> -}
> -#endif /* CONFIG_WATCHDOG */
> -
> -/*
> - * Print out the state of various machine registers.
> - * Currently prints out LAWs, BR0/OR0, and BATs
> - */
> -void print_reginfo(void)
> -{
> - print_bats();
> - print_laws();
> - print_lbc_regs();
> -}
> -
> -/*
> - * Set the DDR BATs to reflect the actual size of DDR.
> - *
> - * dram_size is the actual size of DDR, in bytes
> - *
> - * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
> - * are using a single BAT to cover DDR.
> - *
> - * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
> - * is not defined) then we might have a situation where U-Boot will attempt
> - * to relocated itself outside of the region mapped by DBAT0.
> - * This will cause a machine check.
> - *
> - * Currently we are limited to power of two sized DDR since we only use a
> - * single bat. If a non-power of two size is used that is less than
> - * CONFIG_MAX_MEM_MAPPED u-boot will crash.
> - *
> - */
> -void setup_ddr_bat(phys_addr_t dram_size)
> -{
> - unsigned long batu, bl;
> -
> - bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
> -
> - if (BATU_SIZE(bl) != dram_size) {
> - u64 sz = (u64)dram_size - BATU_SIZE(bl);
> - print_size(sz, " left unmapped\n");
> - }
> -
> - batu = bl | BATU_VS | BATU_VP;
> - write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
> - write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c
> deleted file mode 100644
> index 73779f862c2a..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c
> +++ /dev/null
> @@ -1,104 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
> - * Jeff Brown
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - */
> -
> -/*
> - * cpu_init.c - low level cpu init
> - */
> -
> -#include <asm-offsets.h>
> -#include <config.h>
> -#include <common.h>
> -#include <init.h>
> -#include <mpc86xx.h>
> -#include <asm/global_data.h>
> -#include <asm/mmu.h>
> -#include <asm/fsl_law.h>
> -#include <asm/fsl_serdes.h>
> -#include <asm/mp.h>
> -
> -extern void srio_init(void);
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/*
> - * Breathe some life into the CPU...
> - *
> - * Set up the memory map
> - * initialize a bunch of registers
> - */
> -
> -void cpu_init_f(void)
> -{
> - /* Pointer is writable since we allocated a register for it */
> - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
> -
> - /* Clear initial global data */
> - memset ((void *) gd, 0, sizeof (gd_t));
> -
> -#ifdef CONFIG_FSL_LAW
> - init_laws();
> -#endif
> -
> - setup_bats();
> -
> - init_early_memctl_regs();
> -
> -#if defined(CONFIG_FSL_DMA)
> - dma_init();
> -#endif
> -
> - /* enable the timebase bit in HID0 */
> - set_hid0(get_hid0() | 0x4000000);
> -
> - /* enable EMCP, SYNCBE | ABE bits in HID1 */
> - set_hid1(get_hid1() | 0x80000C00);
> -}
> -
> -/*
> - * initialize higher level parts of CPU like timers
> - */
> -int cpu_init_r(void)
> -{
> - /* needs to be in ram since code uses global static vars */
> - fsl_serdes_init();
> -
> -#ifdef CONFIG_SYS_SRIO
> - srio_init();
> -#endif
> -
> -#if defined(CONFIG_MP)
> - setup_mp();
> -#endif
> - return 0;
> -}
> -
> -#ifdef CONFIG_ADDR_MAP
> -/* Initialize address mapping array */
> -void init_addr_map(void)
> -{
> - int i;
> - ppc_bat_t bat = DBAT0;
> - phys_size_t size;
> - unsigned long upper, lower;
> -
> - for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
> - if (read_bat(bat, &upper, &lower) != -1) {
> - if (!BATU_VALID(upper))
> - size = 0;
> - else
> - size = BATU_SIZE(upper);
> - addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
> - size, i);
> - }
> -#ifdef CONFIG_HIGH_BATS
> - /* High bats are not contiguous with low BAT numbers */
> - if (bat == DBAT3)
> - bat = DBAT4 - 1;
> -#endif
> - }
> -}
> -#endif
> diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
> deleted file mode 100644
> index 1313d8adde66..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/fdt.c
> +++ /dev/null
> @@ -1,52 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright 2008, 2011 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <asm/global_data.h>
> -#include <linux/libfdt.h>
> -#include <fdt_support.h>
> -#include <asm/mp.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -extern void ft_fixup_num_cores(void *blob);
> -extern void ft_srio_setup(void *blob);
> -
> -void ft_cpu_setup(void *blob, struct bd_info *bd)
> -{
> -#ifdef CONFIG_MP
> - int off;
> - u32 bootpg = determine_mp_bootpg(NULL);
> -#endif
> -
> - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> - "timebase-frequency", bd->bi_busfreq / 4, 1);
> - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> - "bus-frequency", bd->bi_busfreq, 1);
> - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> - "clock-frequency", bd->bi_intfreq, 1);
> - do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
> - "bus-frequency", bd->bi_busfreq, 1);
> -
> - fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
> -
> -#ifdef CONFIG_SYS_NS16550
> - do_fixup_by_compat_u32(blob, "ns16550",
> - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
> -#endif
> -
> -#ifdef CONFIG_MP
> - /* Reserve the boot page so OSes dont use it */
> - off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
> - if (off < 0)
> - printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
> -
> - ft_fixup_num_cores(blob);
> -#endif
> -
> -#ifdef CONFIG_SYS_SRIO
> - ft_srio_setup(blob);
> -#endif
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c
> deleted file mode 100644
> index 5a916600ed62..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/interrupts.c
> +++ /dev/null
> @@ -1,116 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * (C) Copyright 2000-2002
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - *
> - * (C) Copyright 2002 (440 port)
> - * Scott McNutt, Artesyn Communication Producs, smcnutt at artsyncp.com
> - *
> - * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
> - * Xianghua Xiao (X.Xiao at motorola.com)
> - *
> - * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
> - * Jeff Brown
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - */
> -
> -#include <common.h>
> -#include <irq_func.h>
> -#include <log.h>
> -#include <mpc86xx.h>
> -#include <command.h>
> -#include <time.h>
> -#include <asm/processor.h>
> -#ifdef CONFIG_POST
> -#include <post.h>
> -#endif
> -#include <asm/ptrace.h>
> -
> -void interrupt_init_cpu(unsigned *decrementer_count)
> -{
> - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
> - volatile ccsr_pic_t *pic = &immr->im_pic;
> -
> -#ifdef CONFIG_POST
> - /*
> - * The POST word is stored in the PIC's TFRR register which gets
> - * cleared when the PIC is reset. Save it off so we can restore it
> - * later.
> - */
> - ulong post_word = post_word_load();
> -#endif
> -
> - pic->gcr = MPC86xx_PICGCR_RST;
> - while (pic->gcr & MPC86xx_PICGCR_RST)
> - ;
> - pic->gcr = MPC86xx_PICGCR_MODE;
> -
> - *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
> - debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
> - (get_tbclk() / 1000000),
> - *decrementer_count);
> -
> -#ifdef CONFIG_INTERRUPTS
> -
> - pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
> - debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
> -
> - pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
> - debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
> -
> - pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
> - debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
> -
> -#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
> - pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
> - debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
> -#endif
> -#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
> - pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
> - debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
> -#endif
> -
> - pic->ctpr = 0; /* 40080 clear current task priority register */
> -#endif
> -
> -#ifdef CONFIG_POST
> - post_word_store(post_word);
> -#endif
> -}
> -
> -/*
> - * timer_interrupt - gets called when the decrementer overflows,
> - * with interrupts disabled.
> - * Trivial implementation - no need to be really accurate.
> - */
> -void timer_interrupt_cpu(struct pt_regs *regs)
> -{
> - /* nothing to do here */
> -}
> -
> -/*
> - * Install and free a interrupt handler. Not implemented yet.
> - */
> -void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
> -{
> -}
> -
> -void irq_free_handler(int vec)
> -{
> -}
> -
> -/*
> - * irqinfo - print information about PCI devices,not implemented.
> - */
> -int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
> -{
> - return 0;
> -}
> -
> -/*
> - * Handle external interrupts
> - */
> -void external_interrupt(struct pt_regs *regs)
> -{
> - puts("external_interrupt(oops!)\n");
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
> deleted file mode 100644
> index e6795e06c98b..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/mp.c
> +++ /dev/null
> @@ -1,130 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2008-2010 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <cpu_func.h>
> -#include <asm/global_data.h>
> -#include <asm/processor.h>
> -#include <asm/mmu.h>
> -#include <ioports.h>
> -#include <lmb.h>
> -#include <asm/io.h>
> -#include <asm/mp.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int cpu_reset(u32 nr)
> -{
> - /* dummy function so common/cmd_mp.c will build
> - * should be implemented in the future, when cpu_release()
> - * is supported. Be aware there may be a similiar bug
> - * as exists on MPC85xx w/its PIC having a timing window
> - * associated to resetting the core */
> - return 1;
> -}
> -
> -int cpu_status(u32 nr)
> -{
> - /* dummy function so common/cmd_mp.c will build */
> - return 0;
> -}
> -
> -int cpu_disable(u32 nr)
> -{
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
> - volatile ccsr_gur_t *gur = &immap->im_gur;
> -
> - switch (nr) {
> - case 0:
> - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
> - break;
> - case 1:
> - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
> - break;
> - default:
> - printf("Invalid cpu number for disable %d\n", nr);
> - return 1;
> - }
> -
> - return 0;
> -}
> -
> -int is_core_disabled(int nr) {
> - immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
> - ccsr_gur_t *gur = &immap->im_gur;
> - u32 devdisr = in_be32(&gur->devdisr);
> -
> - switch (nr) {
> - case 0:
> - return (devdisr & MPC86xx_DEVDISR_CPU0);
> - case 1:
> - return (devdisr & MPC86xx_DEVDISR_CPU1);
> - default:
> - printf("Invalid cpu number for disable %d\n", nr);
> - }
> -
> - return 0;
> -}
> -
> -int cpu_release(u32 nr, int argc, char *const argv[])
> -{
> - /* dummy function so common/cmd_mp.c will build
> - * should be implemented in the future */
> - return 1;
> -}
> -
> -u32 determine_mp_bootpg(unsigned int *pagesize)
> -{
> - if (pagesize)
> - *pagesize = 4096;
> -
> - /* if we have 4G or more of memory, put the boot page at 4Gb-1M */
> - if ((u64)gd->ram_size > 0xfffff000)
> - return (0xfff00000);
> -
> - return (gd->ram_size - (1024 * 1024));
> -}
> -
> -void cpu_mp_lmb_reserve(struct lmb *lmb)
> -{
> - u32 bootpg = determine_mp_bootpg(NULL);
> -
> - /* tell u-boot we stole a page */
> - lmb_reserve(lmb, bootpg, 4096);
> -}
> -
> -/*
> - * Copy the code for other cpus to execute into an
> - * aligned location accessible via BPTR
> - */
> -void setup_mp(void)
> -{
> - extern ulong __secondary_start_page;
> - ulong fixup = (ulong)&__secondary_start_page;
> - u32 bootpg = determine_mp_bootpg(NULL);
> - u32 bootpg_va;
> -
> - if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
> - /* We're not covered by the DDR mapping, set up BAT */
> - write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
> - BATU_VS | BATU_VP,
> - bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
> - bootpg_va = CONFIG_SYS_SCRATCH_VA;
> - } else {
> - bootpg_va = bootpg;
> - }
> -
> - memcpy((void *)bootpg_va, (void *)fixup, 4096);
> - flush_cache(bootpg_va, 4096);
> -
> - /* remove the temporary BAT mapping */
> - if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
> - write_bat(DBAT7, 0, 0);
> -
> - /* If the physical location of bootpg is not at fff00000, set BPTR */
> - if (bootpg != 0xfff00000)
> - out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
> - (bootpg >> 12));
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
> deleted file mode 100644
> index ecc88ba43746..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
> +++ /dev/null
> @@ -1,87 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2010 Freescale Semiconductor, Inc.
> - */
> -
> -#include <config.h>
> -#include <common.h>
> -#include <log.h>
> -#include <asm/io.h>
> -#include <asm/immap_86xx.h>
> -#include <asm/fsl_serdes.h>
> -
> -#define SRDS1_MAX_LANES 4
> -#define SRDS2_MAX_LANES 4
> -
> -static u32 serdes1_prtcl_map, serdes2_prtcl_map;
> -
> -static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
> - [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0x7] = {NONE, NONE, NONE, NONE},
> -};
> -
> -static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
> - [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
> - [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
> - [0x7] = {NONE, NONE, NONE, NONE},
> -};
> -
> -int is_serdes_configured(enum srds_prtcl device)
> -{
> - int ret;
> -
> - if (!(serdes1_prtcl_map & (1 << NONE)))
> - fsl_serdes_init();
> -
> - ret = (1 << device) & serdes1_prtcl_map;
> -
> - if (ret)
> - return ret;
> -
> - if (!(serdes2_prtcl_map & (1 << NONE)))
> - fsl_serdes_init();
> -
> - return (1 << device) & serdes2_prtcl_map;
> -}
> -
> -void fsl_serdes_init(void)
> -{
> - immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
> - ccsr_gur_t *gur = &immap->im_gur;
> - u32 pordevsr = in_be32(&gur->pordevsr);
> - u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
> - MPC8610_PORDEVSR_IO_SEL_SHIFT;
> - int lane;
> -
> - if (serdes1_prtcl_map & (1 << NONE) &&
> - serdes2_prtcl_map & (1 << NONE))
> - return;
> -
> - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
> -
> - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
> - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
> - return;
> - }
> - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
> - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
> - serdes1_prtcl_map |= (1 << lane_prtcl);
> - }
> -
> - /* Set the first bit to indicate serdes has been initialized */
> - serdes1_prtcl_map |= (1 << NONE);
> -
> - if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
> - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
> - return;
> - }
> -
> - for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
> - enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
> - serdes2_prtcl_map |= (1 << lane_prtcl);
> - }
> -
> - /* Set the first bit to indicate serdes has been initialized */
> - serdes2_prtcl_map |= (1 << NONE);
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
> deleted file mode 100644
> index 4df446618c09..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
> +++ /dev/null
> @@ -1,96 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2010 Freescale Semiconductor, Inc.
> - */
> -
> -#include <config.h>
> -#include <common.h>
> -#include <log.h>
> -#include <asm/io.h>
> -#include <asm/immap_86xx.h>
> -#include <asm/fsl_serdes.h>
> -
> -#define SRDS1_MAX_LANES 4
> -#define SRDS2_MAX_LANES 4
> -
> -static u32 serdes1_prtcl_map, serdes2_prtcl_map;
> -
> -static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
> - [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1},
> - [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
> -};
> -
> -static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
> - [0x3] = {PCIE2, PCIE2, PCIE2, PCIE2},
> - [0x5] = {SRIO1, SRIO1, SRIO1, SRIO1},
> - [0x6] = {SRIO1, SRIO1, SRIO1, SRIO1},
> - [0x7] = {SRIO1, SRIO1, SRIO1, SRIO1},
> - [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
> - [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
> - [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
> - [0xe] = {PCIE2, PCIE2, PCIE2, PCIE2},
> - [0xf] = {PCIE2, PCIE2, PCIE2, PCIE2},
> -};
> -
> -int is_serdes_configured(enum srds_prtcl device)
> -{
> - int ret;
> -
> - if (!(serdes1_prtcl_map & (1 << NONE)))
> - fsl_serdes_init();
> -
> - ret = (1 << device) & serdes1_prtcl_map;
> -
> - if (ret)
> - return ret;
> -
> - if (!(serdes2_prtcl_map & (1 << NONE)))
> - fsl_serdes_init();
> -
> - return (1 << device) & serdes2_prtcl_map;
> -}
> -
> -void fsl_serdes_init(void)
> -{
> - immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
> - ccsr_gur_t *gur = &immap->im_gur;
> - u32 pordevsr = in_be32(&gur->pordevsr);
> - u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >>
> - MPC8641_PORDEVSR_IO_SEL_SHIFT;
> - int lane;
> -
> - if (serdes1_prtcl_map & (1 << NONE) &&
> - serdes2_prtcl_map & (1 << NONE))
> - return;
> -
> - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
> -
> - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
> - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
> - return;
> - }
> - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
> - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
> - serdes1_prtcl_map |= (1 << lane_prtcl);
> - }
> -
> - /* Set the first bit to indicate serdes has been initialized */
> - serdes1_prtcl_map |= (1 << NONE);
> -
> - if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
> - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
> - return;
> - }
> -
> - for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
> - enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
> - serdes2_prtcl_map |= (1 << lane_prtcl);
> - }
> -
> - /* Set the first bit to indicate serdes has been initialized */
> - serdes2_prtcl_map |= (1 << NONE);
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/release.S b/arch/powerpc/cpu/mpc86xx/release.S
> deleted file mode 100644
> index 72ad8834c979..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/release.S
> +++ /dev/null
> @@ -1,149 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2004, 2007, 2008 Freescale Semiconductor.
> - * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
> - */
> -#include <config.h>
> -#include <mpc86xx.h>
> -
> -#include <ppc_asm.tmpl>
> -#include <ppc_defs.h>
> -
> -#include <asm/cache.h>
> -#include <asm/mmu.h>
> -
> -/* If this is a multi-cpu system then we need to handle the
> - * 2nd cpu. The assumption is that the 2nd cpu is being
> - * held in boot holdoff mode until the 1st cpu unlocks it
> - * from Linux. We'll do some basic cpu init and then pass
> - * it to the Linux Reset Vector.
> - * Sri: Much of this initialization is not required. Linux
> - * rewrites the bats, and the sprs and also enables the L1 cache.
> - *
> - * Core 0 must copy this to a 1M aligned region and set BPTR
> - * to point to it.
> - */
> - .align 12
> -.globl __secondary_start_page
> -__secondary_start_page:
> - .space 0x100 /* space over to reset vector loc */
> - mfspr r0, MSSCR0
> - andi. r0, r0, 0x0020
> - rlwinm r0,r0,27,31,31
> - mtspr PIR, r0
> -
> - /* Invalidate BATs */
> - li r0, 0
> - mtspr IBAT0U, r0
> - mtspr IBAT1U, r0
> - mtspr IBAT2U, r0
> - mtspr IBAT3U, r0
> - mtspr IBAT4U, r0
> - mtspr IBAT5U, r0
> - mtspr IBAT6U, r0
> - mtspr IBAT7U, r0
> - isync
> - mtspr DBAT0U, r0
> - mtspr DBAT1U, r0
> - mtspr DBAT2U, r0
> - mtspr DBAT3U, r0
> - mtspr DBAT4U, r0
> - mtspr DBAT5U, r0
> - mtspr DBAT6U, r0
> - mtspr DBAT7U, r0
> - isync
> - sync
> -
> - /* enable extended addressing */
> - mfspr r0, HID0
> - lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
> - ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
> - mtspr HID0, r0
> - sync
> - isync
> -
> -#ifdef CONFIG_SYS_L2
> - /* init the L2 cache */
> - addis r3, r0, L2_INIT at h
> - ori r3, r3, L2_INIT at l
> - sync
> - mtspr l2cr, r3
> -#ifdef CONFIG_ALTIVEC
> - dssall
> -#endif
> - /* invalidate the L2 cache */
> - mfspr r3, l2cr
> - rlwinm. r3, r3, 0, 0, 0
> - beq 1f
> -
> - mfspr r3, l2cr
> - rlwinm r3, r3, 0, 1, 31
> -
> -#ifdef CONFIG_ALTIVEC
> - dssall
> -#endif
> - sync
> - mtspr l2cr, r3
> - sync
> -1: mfspr r3, l2cr
> - oris r3, r3, L2CR_L2I at h
> - mtspr l2cr, r3
> -
> -invl2:
> - mfspr r3, l2cr
> - andis. r3, r3, L2CR_L2I at h
> - bne invl2
> - sync
> -#endif
> -
> - /* enable and invalidate the data cache */
> - mfspr r3, HID0
> - li r5, HID0_DCFI|HID0_DLOCK
> - andc r3, r3, r5
> - mtspr HID0, r3 /* no invalidate, unlock */
> - ori r3, r3, HID0_DCE
> - ori r5, r3, HID0_DCFI
> - mtspr HID0, r5 /* enable + invalidate */
> - mtspr HID0, r3 /* enable */
> - sync
> -#ifdef CONFIG_SYS_L2
> - sync
> - lis r3, L2_ENABLE at h
> - ori r3, r3, L2_ENABLE at l
> - mtspr l2cr, r3
> - isync
> - sync
> -#endif
> -
> - /* enable and invalidate the instruction cache*/
> - mfspr r3, HID0
> - li r5, HID0_ICFI|HID0_ILOCK
> - andc r3, r3, r5
> - ori r3, r3, HID0_ICE
> - ori r5, r3, HID0_ICFI
> - mtspr HID0, r5
> - mtspr HID0, r3
> - isync
> - sync
> -
> - /* TBEN in HID0 */
> - mfspr r4, HID0
> - oris r4, r4, 0x0400
> - mtspr HID0, r4
> - sync
> - isync
> -
> - /* MCP|SYNCBE|ABE in HID1 */
> - mfspr r4, HID1
> - oris r4, r4, 0x8000
> - ori r4, r4, 0x0C00
> - mtspr HID1, r4
> - sync
> - isync
> -
> - lis r3, CONFIG_LINUX_RESET_VEC at h
> - ori r3, r3, CONFIG_LINUX_RESET_VEC at l
> - mtlr r3
> - blr
> -
> - /* Never Returns, Running in Linux Now */
> diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
> deleted file mode 100644
> index 86c1709c4ca2..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/speed.c
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2004 Freescale Semiconductor.
> - * Jeff Brown
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - *
> - * (C) Copyright 2000-2002
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - */
> -
> -#include <common.h>
> -#include <clock_legacy.h>
> -#include <mpc86xx.h>
> -#include <asm/global_data.h>
> -#include <asm/processor.h>
> -#include <asm/io.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
> -extern unsigned long get_board_sys_clk(unsigned long dummy);
> -
> -void get_sys_info(sys_info_t *sys_info)
> -{
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> - volatile ccsr_gur_t *gur = &immap->im_gur;
> - uint plat_ratio, e600_ratio;
> -
> - plat_ratio = (gur->porpllsr) & 0x0000003e;
> - plat_ratio >>= 1;
> -
> - switch (plat_ratio) {
> - case 0x0:
> - sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
> - break;
> - case 0x02:
> - case 0x03:
> - case 0x04:
> - case 0x05:
> - case 0x06:
> - case 0x08:
> - case 0x09:
> - case 0x0a:
> - case 0x0c:
> - case 0x10:
> - sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
> - break;
> - default:
> - sys_info->freq_systembus = 0;
> - break;
> - }
> -
> - e600_ratio = (gur->porpllsr) & 0x003f0000;
> - e600_ratio >>= 16;
> -
> - switch (e600_ratio) {
> - case 0x10:
> - sys_info->freq_processor = 2 * sys_info->freq_systembus;
> - break;
> - case 0x19:
> - sys_info->freq_processor = 5 * sys_info->freq_systembus / 2;
> - break;
> - case 0x20:
> - sys_info->freq_processor = 3 * sys_info->freq_systembus;
> - break;
> - case 0x39:
> - sys_info->freq_processor = 7 * sys_info->freq_systembus / 2;
> - break;
> - case 0x28:
> - sys_info->freq_processor = 4 * sys_info->freq_systembus;
> - break;
> - case 0x1d:
> - sys_info->freq_processor = 9 * sys_info->freq_systembus / 2;
> - break;
> - default:
> - sys_info->freq_processor = e600_ratio +
> - sys_info->freq_systembus;
> - break;
> - }
> -
> - sys_info->freq_localbus = sys_info->freq_systembus;
> -}
> -
> -
> -/*
> - * Measure CPU clock speed (core clock GCLK1, GCLK2)
> - * (Approx. GCLK frequency in Hz)
> - */
> -
> -int get_clocks(void)
> -{
> - sys_info_t sys_info;
> -
> - get_sys_info(&sys_info);
> - gd->cpu_clk = sys_info.freq_processor;
> - gd->bus_clk = sys_info.freq_systembus;
> - gd->arch.lbc_clk = sys_info.freq_localbus;
> -
> - /*
> - * The base clock for I2C depends on the actual SOC. Unfortunately,
> - * there is no pattern that can be used to determine the frequency, so
> - * the only choice is to look up the actual SOC number and use the value
> - * for that SOC. This information is taken from application note
> - * AN2919.
> - */
> -#ifdef CONFIG_ARCH_MPC8610
> - gd->arch.i2c1_clk = sys_info.freq_systembus;
> -#else
> - gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
> -#endif
> - gd->arch.i2c2_clk = gd->arch.i2c1_clk;
> -
> - if (gd->cpu_clk != 0)
> - return 0;
> - else
> - return 1;
> -}
> -
> -
> -/*
> - * get_bus_freq
> - * Return system bus freq in Hz
> - */
> -
> -ulong get_bus_freq(ulong dummy)
> -{
> - ulong val;
> - sys_info_t sys_info;
> -
> - get_sys_info(&sys_info);
> - val = sys_info.freq_systembus;
> -
> - return val;
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S
> deleted file mode 100644
> index f4651ce8d46f..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/start.S
> +++ /dev/null
> @@ -1,982 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2004, 2007, 2011 Freescale Semiconductor.
> - * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
> - */
> -
> -/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
> - *
> - *
> - * The processor starts at 0xfff00100 and the code is executed
> - * from flash. The code is organized to be at an other address
> - * in memory, but as long we don't jump around before relocating.
> - * board_init lies at a quite high address and when the cpu has
> - * jumped there, everything is ok.
> - */
> -#include <asm-offsets.h>
> -#include <config.h>
> -#include <mpc86xx.h>
> -#include <version.h>
> -
> -#include <ppc_asm.tmpl>
> -#include <ppc_defs.h>
> -
> -#include <asm/cache.h>
> -#include <asm/mmu.h>
> -#include <asm/u-boot.h>
> -
> -/*
> - * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
> - */
> -
> -/*
> - * Set up GOT: Global Offset Table
> - *
> - * Use r12 to access the GOT
> - */
> - START_GOT
> - GOT_ENTRY(_GOT2_TABLE_)
> - GOT_ENTRY(_FIXUP_TABLE_)
> -
> - GOT_ENTRY(_start)
> - GOT_ENTRY(_start_of_vectors)
> - GOT_ENTRY(_end_of_vectors)
> - GOT_ENTRY(transfer_to_handler)
> -
> - GOT_ENTRY(__init_end)
> - GOT_ENTRY(__bss_end)
> - GOT_ENTRY(__bss_start)
> - END_GOT
> -
> -/*
> - * r3 - 1st arg to board_init(): IMMP pointer
> - * r4 - 2nd arg to board_init(): boot flag
> - */
> - .text
> - .long 0x27051956 /* U-Boot Magic Number */
> - .globl version_string
> -version_string:
> - .ascii U_BOOT_VERSION_STRING, "\0"
> -
> - . = EXC_OFF_SYS_RESET
> - .globl _start
> -_start:
> - b boot_cold
> -
> - /* the boot code is located below the exception table */
> -
> - .globl _start_of_vectors
> -_start_of_vectors:
> -
> -/* Machine check */
> - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
> -
> -/* Data Storage exception. */
> - STD_EXCEPTION(0x300, DataStorage, UnknownException)
> -
> -/* Instruction Storage exception. */
> - STD_EXCEPTION(0x400, InstStorage, UnknownException)
> -
> -/* External Interrupt exception. */
> - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
> -
> -/* Alignment exception. */
> - . = 0x600
> -Alignment:
> - EXCEPTION_PROLOG(SRR0, SRR1)
> - mfspr r4,DAR
> - stw r4,_DAR(r21)
> - mfspr r5,DSISR
> - stw r5,_DSISR(r21)
> - addi r3,r1,STACK_FRAME_OVERHEAD
> - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
> -
> -/* Program check exception */
> - . = 0x700
> -ProgramCheck:
> - EXCEPTION_PROLOG(SRR0, SRR1)
> - addi r3,r1,STACK_FRAME_OVERHEAD
> - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
> - MSR_KERNEL, COPY_EE)
> -
> - STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
> -
> - /* I guess we could implement decrementer, and may have
> - * to someday for timekeeping.
> - */
> - STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
> - STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
> - STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
> - STD_EXCEPTION(0xc00, SystemCall, UnknownException)
> - STD_EXCEPTION(0xd00, SingleStep, UnknownException)
> - STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
> - STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
> - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
> - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
> - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
> - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
> - STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
> - STD_EXCEPTION(0x1500, Reserved5, UnknownException)
> - STD_EXCEPTION(0x1600, Reserved6, UnknownException)
> - STD_EXCEPTION(0x1700, Reserved7, UnknownException)
> - STD_EXCEPTION(0x1800, Reserved8, UnknownException)
> - STD_EXCEPTION(0x1900, Reserved9, UnknownException)
> - STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
> - STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
> - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
> - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
> - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
> - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
> -
> - .globl _end_of_vectors
> -_end_of_vectors:
> -
> - . = 0x2000
> -
> -boot_cold:
> - /*
> - * NOTE: Only Cpu 0 will ever come here. Other cores go to an
> - * address specified by the BPTR
> - */
> -1:
> -#ifdef CONFIG_SYS_RAMBOOT
> - /* disable everything */
> - li r0, 0
> - mtspr HID0, r0
> - sync
> - mtmsr 0
> -#endif
> -
> - /* Invalidate BATs */
> - bl invalidate_bats
> - sync
> - /* Invalidate all of TLB before MMU turn on */
> - bl clear_tlbs
> - sync
> -
> -#ifdef CONFIG_SYS_L2
> - /* init the L2 cache */
> - lis r3, L2_INIT at h
> - ori r3, r3, L2_INIT at l
> - mtspr l2cr, r3
> - /* invalidate the L2 cache */
> - bl l2cache_invalidate
> - sync
> -#endif
> -
> - /*
> - * Calculate absolute address in FLASH and jump there
> - *------------------------------------------------------*/
> - lis r3, CONFIG_SYS_MONITOR_BASE_EARLY at h
> - ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY at l
> - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
> - mtlr r3
> - blr
> -
> -in_flash:
> - /* let the C-code set up the rest */
> - /* */
> - /* Be careful to keep code relocatable ! */
> - /*------------------------------------------------------*/
> - /* perform low-level init */
> -
> - /* enable extended addressing */
> - bl enable_ext_addr
> -
> - /* setup the bats */
> - bl early_bats
> -
> - /*
> - * Cache must be enabled here for stack-in-cache trick.
> - * This means we need to enable the BATS.
> - * Cache should be turned on after BATs, since by default
> - * everything is write-through.
> - */
> -
> - /* enable address translation */
> - mfmsr r5
> - ori r5, r5, (MSR_IR | MSR_DR)
> - lis r3,addr_trans_enabled at h
> - ori r3, r3, addr_trans_enabled at l
> - mtspr SPRN_SRR0,r3
> - mtspr SPRN_SRR1,r5
> - rfi
> -
> -addr_trans_enabled:
> - /* enable and invalidate the data cache */
> -/* bl l1dcache_enable */
> - bl dcache_enable
> - sync
> -
> -#if 1
> - bl icache_enable
> -#endif
> -
> -#ifdef CONFIG_SYS_INIT_RAM_LOCK
> - bl lock_ram_in_cache
> - sync
> -#endif
> -
> -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
> - bl setup_ccsrbar
> -#endif
> -
> - /* set up the stack pointer in our newly created
> - * cache-ram (r1) */
> - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
> - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
> -
> - li r0, 0 /* Make room for stack frame header and */
> - stwu r0, -4(r1) /* clear final stack frame so that */
> - stwu r0, -4(r1) /* stack backtraces terminate cleanly */
> -
> - GET_GOT /* initialize GOT access */
> -
> - /* run low-level CPU init code (from Flash) */
> - bl cpu_init_f
> - sync
> -
> -#ifdef RUN_DIAG
> -
> - /* Load PX_AUX register address in r4 */
> - lis r4, PIXIS_BASE at h
> - ori r4, r4, 0x6
> - /* Load contents of PX_AUX in r3 bits 24 to 31*/
> - lbz r3, 0(r4)
> -
> - /* Mask and obtain the bit in r3 */
> - rlwinm. r3, r3, 0, 24, 24
> - /* If not zero, jump and continue with u-boot */
> - bne diag_done
> -
> - /* Load back contents of PX_AUX in r3 bits 24 to 31 */
> - lbz r3, 0(r4)
> - /* Set the MSB of the register value */
> - ori r3, r3, 0x80
> - /* Write value in r3 back to PX_AUX */
> - stb r3, 0(r4)
> -
> - /* Get the address to jump to in r3*/
> - lis r3, CONFIG_SYS_DIAG_ADDR at h
> - ori r3, r3, CONFIG_SYS_DIAG_ADDR at l
> -
> - /* Load the LR with the branch address */
> - mtlr r3
> -
> - /* Branch to diagnostic */
> - blr
> -
> -diag_done:
> -#endif
> -
> -/* bl l2cache_enable */
> -
> - /* run 1st part of board init code (from Flash) */
> - li r3, 0 /* clear boot_flag for calling board_init_f */
> - bl board_init_f
> - sync
> -
> - /* NOTREACHED - board_init_f() does not return */
> -
> - .globl invalidate_bats
> -invalidate_bats:
> -
> - li r0, 0
> - /* invalidate BATs */
> - mtspr IBAT0U, r0
> - mtspr IBAT1U, r0
> - mtspr IBAT2U, r0
> - mtspr IBAT3U, r0
> - mtspr IBAT4U, r0
> - mtspr IBAT5U, r0
> - mtspr IBAT6U, r0
> - mtspr IBAT7U, r0
> -
> - isync
> - mtspr DBAT0U, r0
> - mtspr DBAT1U, r0
> - mtspr DBAT2U, r0
> - mtspr DBAT3U, r0
> - mtspr DBAT4U, r0
> - mtspr DBAT5U, r0
> - mtspr DBAT6U, r0
> - mtspr DBAT7U, r0
> -
> - isync
> - sync
> - blr
> -
> -#define CONFIG_BAT_PAIR(n) \
> - lis r4, CONFIG_SYS_IBAT##n##L at h; \
> - ori r4, r4, CONFIG_SYS_IBAT##n##L at l; \
> - lis r3, CONFIG_SYS_IBAT##n##U at h; \
> - ori r3, r3, CONFIG_SYS_IBAT##n##U at l; \
> - mtspr IBAT##n##L, r4; \
> - mtspr IBAT##n##U, r3; \
> - lis r4, CONFIG_SYS_DBAT##n##L at h; \
> - ori r4, r4, CONFIG_SYS_DBAT##n##L at l; \
> - lis r3, CONFIG_SYS_DBAT##n##U at h; \
> - ori r3, r3, CONFIG_SYS_DBAT##n##U at l; \
> - mtspr DBAT##n##L, r4; \
> - mtspr DBAT##n##U, r3;
> -
> -/*
> - * setup_bats:
> - *
> - * Set up the final BAT registers now that setup is done.
> - *
> - * Assumes that:
> - * 1) Address translation is enabled upon entry
> - * 2) The boot rom is still accessible via 1:1 translation
> - */
> - .globl setup_bats
> -setup_bats:
> - mflr r5
> - sync
> -
> - /*
> - * When we disable address translation, we will get 1:1 (VA==PA)
> - * translation. The only place we know for sure is safe for that is
> - * the bootrom where we originally started out. Pop back into there.
> - */
> - lis r4, CONFIG_SYS_MONITOR_BASE_EARLY at h
> - ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY at l
> - addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
> -
> - /* disable address translation */
> - mfmsr r3
> - rlwinm r3, r3, 0, 28, 25
> - mtspr SRR0, r4
> - mtspr SRR1, r3
> - rfi
> -
> -trans_disabled:
> -#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
> - && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
> - CONFIG_BAT_PAIR(0)
> -#endif
> - CONFIG_BAT_PAIR(1)
> - CONFIG_BAT_PAIR(2)
> - CONFIG_BAT_PAIR(3)
> - CONFIG_BAT_PAIR(4)
> - CONFIG_BAT_PAIR(5)
> - CONFIG_BAT_PAIR(6)
> - CONFIG_BAT_PAIR(7)
> -
> - sync
> - isync
> -
> - /* Turn translation back on and return */
> - mfmsr r3
> - ori r3, r3, (MSR_IR | MSR_DR)
> - mtspr SPRN_SRR0,r5
> - mtspr SPRN_SRR1,r3
> - rfi
> -
> -/*
> - * early_bats:
> - *
> - * Set up bats needed early on - this is usually the BAT for the
> - * stack-in-cache, the Flash, and CCSR space
> - */
> - .globl early_bats
> -early_bats:
> - /* IBAT 3 */
> - lis r4, CONFIG_SYS_IBAT3L at h
> - ori r4, r4, CONFIG_SYS_IBAT3L at l
> - lis r3, CONFIG_SYS_IBAT3U at h
> - ori r3, r3, CONFIG_SYS_IBAT3U at l
> - mtspr IBAT3L, r4
> - mtspr IBAT3U, r3
> - isync
> -
> - /* DBAT 3 */
> - lis r4, CONFIG_SYS_DBAT3L at h
> - ori r4, r4, CONFIG_SYS_DBAT3L at l
> - lis r3, CONFIG_SYS_DBAT3U at h
> - ori r3, r3, CONFIG_SYS_DBAT3U at l
> - mtspr DBAT3L, r4
> - mtspr DBAT3U, r3
> - isync
> -
> - /* IBAT 5 */
> - lis r4, CONFIG_SYS_IBAT5L at h
> - ori r4, r4, CONFIG_SYS_IBAT5L at l
> - lis r3, CONFIG_SYS_IBAT5U at h
> - ori r3, r3, CONFIG_SYS_IBAT5U at l
> - mtspr IBAT5L, r4
> - mtspr IBAT5U, r3
> - isync
> -
> - /* DBAT 5 */
> - lis r4, CONFIG_SYS_DBAT5L at h
> - ori r4, r4, CONFIG_SYS_DBAT5L at l
> - lis r3, CONFIG_SYS_DBAT5U at h
> - ori r3, r3, CONFIG_SYS_DBAT5U at l
> - mtspr DBAT5L, r4
> - mtspr DBAT5U, r3
> - isync
> -
> - /* IBAT 6 */
> - lis r4, CONFIG_SYS_IBAT6L_EARLY at h
> - ori r4, r4, CONFIG_SYS_IBAT6L_EARLY at l
> - lis r3, CONFIG_SYS_IBAT6U_EARLY at h
> - ori r3, r3, CONFIG_SYS_IBAT6U_EARLY at l
> - mtspr IBAT6L, r4
> - mtspr IBAT6U, r3
> - isync
> -
> - /* DBAT 6 */
> - lis r4, CONFIG_SYS_DBAT6L_EARLY at h
> - ori r4, r4, CONFIG_SYS_DBAT6L_EARLY at l
> - lis r3, CONFIG_SYS_DBAT6U_EARLY at h
> - ori r3, r3, CONFIG_SYS_DBAT6U_EARLY at l
> - mtspr DBAT6L, r4
> - mtspr DBAT6U, r3
> - isync
> -
> -#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
> - /* IBAT 7 */
> - lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at h
> - ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at l
> - lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at h
> - ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at l
> - mtspr IBAT7L, r4
> - mtspr IBAT7U, r3
> - isync
> -
> - /* DBAT 7 */
> - lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at h
> - ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at l
> - lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at h
> - ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at l
> - mtspr DBAT7L, r4
> - mtspr DBAT7U, r3
> - isync
> -#endif
> - blr
> -
> - .globl clear_tlbs
> -clear_tlbs:
> - addis r3, 0, 0x0000
> - addis r5, 0, 0x4
> - isync
> -tlblp:
> - tlbie r3
> - sync
> - addi r3, r3, 0x1000
> - cmp 0, 0, r3, r5
> - blt tlblp
> - blr
> -
> - .globl disable_addr_trans
> -disable_addr_trans:
> - /* disable address translation */
> - mflr r4
> - mfmsr r3
> - andi. r0, r3, (MSR_IR | MSR_DR)
> - beqlr
> - andc r3, r3, r0
> - mtspr SRR0, r4
> - mtspr SRR1, r3
> - rfi
> -
> -/*
> - * This code finishes saving the registers to the exception frame
> - * and jumps to the appropriate handler for the exception.
> - * Register r21 is pointer into trap frame, r1 has new stack pointer.
> - */
> - .globl transfer_to_handler
> -transfer_to_handler:
> - stw r22,_NIP(r21)
> - lis r22,MSR_POW at h
> - andc r23,r23,r22
> - stw r23,_MSR(r21)
> - SAVE_GPR(7, r21)
> - SAVE_4GPRS(8, r21)
> - SAVE_8GPRS(12, r21)
> - SAVE_8GPRS(24, r21)
> - mflr r23
> - andi. r24,r23,0x3f00 /* get vector offset */
> - stw r24,TRAP(r21)
> - li r22,0
> - stw r22,RESULT(r21)
> - mtspr SPRG2,r22 /* r1 is now kernel sp */
> - lwz r24,0(r23) /* virtual address of handler */
> - lwz r23,4(r23) /* where to go when done */
> - mtspr SRR0,r24
> - mtspr SRR1,r20
> - mtlr r23
> - SYNC
> - rfi /* jump to handler, enable MMU */
> -
> -int_return:
> - mfmsr r28 /* Disable interrupts */
> - li r4,0
> - ori r4,r4,MSR_EE
> - andc r28,r28,r4
> - SYNC /* Some chip revs need this... */
> - mtmsr r28
> - SYNC
> - lwz r2,_CTR(r1)
> - lwz r0,_LINK(r1)
> - mtctr r2
> - mtlr r0
> - lwz r2,_XER(r1)
> - lwz r0,_CCR(r1)
> - mtspr XER,r2
> - mtcrf 0xFF,r0
> - REST_10GPRS(3, r1)
> - REST_10GPRS(13, r1)
> - REST_8GPRS(23, r1)
> - REST_GPR(31, r1)
> - lwz r2,_NIP(r1) /* Restore environment */
> - lwz r0,_MSR(r1)
> - mtspr SRR0,r2
> - mtspr SRR1,r0
> - lwz r0,GPR0(r1)
> - lwz r2,GPR2(r1)
> - lwz r1,GPR1(r1)
> - SYNC
> - rfi
> -
> - .globl dc_read
> -dc_read:
> - blr
> -
> -
> -/*
> - * Function: in8
> - * Description: Input 8 bits
> - */
> - .globl in8
> -in8:
> - lbz r3,0x0000(r3)
> - blr
> -
> -/*
> - * Function: out8
> - * Description: Output 8 bits
> - */
> - .globl out8
> -out8:
> - stb r4,0x0000(r3)
> - blr
> -
> -/*
> - * Function: out16
> - * Description: Output 16 bits
> - */
> - .globl out16
> -out16:
> - sth r4,0x0000(r3)
> - blr
> -
> -/*
> - * Function: out16r
> - * Description: Byte reverse and output 16 bits
> - */
> - .globl out16r
> -out16r:
> - sthbrx r4,r0,r3
> - blr
> -
> -/*
> - * Function: out32
> - * Description: Output 32 bits
> - */
> - .globl out32
> -out32:
> - stw r4,0x0000(r3)
> - blr
> -
> -/*
> - * Function: out32r
> - * Description: Byte reverse and output 32 bits
> - */
> - .globl out32r
> -out32r:
> - stwbrx r4,r0,r3
> - blr
> -
> -/*
> - * Function: in16
> - * Description: Input 16 bits
> - */
> - .globl in16
> -in16:
> - lhz r3,0x0000(r3)
> - blr
> -
> -/*
> - * Function: in16r
> - * Description: Input 16 bits and byte reverse
> - */
> - .globl in16r
> -in16r:
> - lhbrx r3,r0,r3
> - blr
> -
> -/*
> - * Function: in32
> - * Description: Input 32 bits
> - */
> - .globl in32
> -in32:
> - lwz 3,0x0000(3)
> - blr
> -
> -/*
> - * Function: in32r
> - * Description: Input 32 bits and byte reverse
> - */
> - .globl in32r
> -in32r:
> - lwbrx r3,r0,r3
> - blr
> -
> -/*
> - * void relocate_code(addr_sp, gd, addr_moni)
> - *
> - * This "function" does not return, instead it continues in RAM
> - * after relocating the monitor code.
> - *
> - * r3 = dest
> - * r4 = src
> - * r5 = length in bytes
> - * r6 = cachelinesize
> - */
> - .globl relocate_code
> -relocate_code:
> -
> - mr r1, r3 /* Set new stack pointer */
> - mr r9, r4 /* Save copy of Global Data pointer */
> - mr r10, r5 /* Save copy of Destination Address */
> -
> - GET_GOT
> - mr r3, r5 /* Destination Address */
> - lis r4, CONFIG_SYS_MONITOR_BASE at h /* Source Address */
> - ori r4, r4, CONFIG_SYS_MONITOR_BASE at l
> - lwz r5, GOT(__init_end)
> - sub r5, r5, r4
> - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
> -
> - /*
> - * Fix GOT pointer:
> - *
> - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
> - *
> - * Offset:
> - */
> - sub r15, r10, r4
> -
> - /* First our own GOT */
> - add r12, r12, r15
> - /* then the one used by the C code */
> - add r30, r30, r15
> -
> - /*
> - * Now relocate code
> - */
> - cmplw cr1,r3,r4
> - addi r0,r5,3
> - srwi. r0,r0,2
> - beq cr1,4f /* In place copy is not necessary */
> - beq 7f /* Protect against 0 count */
> - mtctr r0
> - bge cr1,2f
> -
> - la r8,-4(r4)
> - la r7,-4(r3)
> -1: lwzu r0,4(r8)
> - stwu r0,4(r7)
> - bdnz 1b
> - b 4f
> -
> -2: slwi r0,r0,2
> - add r8,r4,r0
> - add r7,r3,r0
> -3: lwzu r0,-4(r8)
> - stwu r0,-4(r7)
> - bdnz 3b
> -/*
> - * Now flush the cache: note that we must start from a cache aligned
> - * address. Otherwise we might miss one cache line.
> - */
> -4: cmpwi r6,0
> - add r5,r3,r5
> - beq 7f /* Always flush prefetch queue in any case */
> - subi r0,r6,1
> - andc r3,r3,r0
> - mr r4,r3
> -5: dcbst 0,r4
> - add r4,r4,r6
> - cmplw r4,r5
> - blt 5b
> - sync /* Wait for all dcbst to complete on bus */
> - mr r4,r3
> -6: icbi 0,r4
> - add r4,r4,r6
> - cmplw r4,r5
> - blt 6b
> -7: sync /* Wait for all icbi to complete on bus */
> - isync
> -
> -/*
> - * We are done. Do not return, instead branch to second part of board
> - * initialization, now running from RAM.
> - */
> - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
> - mtlr r0
> - blr
> -
> -in_ram:
> - /*
> - * Relocation Function, r12 point to got2+0x8000
> - *
> - * Adjust got2 pointers, no need to check for 0, this code
> - * already puts a few entries in the table.
> - */
> - li r0,__got2_entries at sectoff@l
> - la r3,GOT(_GOT2_TABLE_)
> - lwz r11,GOT(_GOT2_TABLE_)
> - mtctr r0
> - sub r11,r3,r11
> - addi r3,r3,-4
> -1: lwzu r0,4(r3)
> - cmpwi r0,0
> - beq- 2f
> - add r0,r0,r11
> - stw r0,0(r3)
> -2: bdnz 1b
> -
> - /*
> - * Now adjust the fixups and the pointers to the fixups
> - * in case we need to move ourselves again.
> - */
> - li r0,__fixup_entries at sectoff@l
> - lwz r3,GOT(_FIXUP_TABLE_)
> - cmpwi r0,0
> - mtctr r0
> - addi r3,r3,-4
> - beq 4f
> -3: lwzu r4,4(r3)
> - lwzux r0,r4,r11
> - cmpwi r0,0
> - add r0,r0,r11
> - stw r4,0(r3)
> - beq- 5f
> - stw r0,0(r4)
> -5: bdnz 3b
> -4:
> -/* clear_bss: */
> - /*
> - * Now clear BSS segment
> - */
> - lwz r3,GOT(__bss_start)
> - lwz r4,GOT(__bss_end)
> -
> - cmplw 0, r3, r4
> - beq 6f
> -
> - li r0, 0
> -5:
> - stw r0, 0(r3)
> - addi r3, r3, 4
> - cmplw 0, r3, r4
> - bne 5b
> -6:
> - mr r3, r9 /* Init Date pointer */
> - mr r4, r10 /* Destination Address */
> - bl board_init_r
> -
> - /* not reached - end relocate_code */
> -/*-----------------------------------------------------------------------*/
> -
> - /*
> - * Copy exception vector code to low memory
> - *
> - * r3: dest_addr
> - * r7: source address, r8: end address, r9: target address
> - */
> - .globl trap_init
> -trap_init:
> - mflr r4 /* save link register */
> - GET_GOT
> - lwz r7, GOT(_start)
> - lwz r8, GOT(_end_of_vectors)
> -
> - li r9, 0x100 /* reset vector always at 0x100 */
> -
> - cmplw 0, r7, r8
> - bgelr /* return if r7>=r8 - just in case */
> -1:
> - lwz r0, 0(r7)
> - stw r0, 0(r9)
> - addi r7, r7, 4
> - addi r9, r9, 4
> - cmplw 0, r7, r8
> - bne 1b
> -
> - /*
> - * relocate `hdlr' and `int_return' entries
> - */
> - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
> - li r8, Alignment - _start + EXC_OFF_SYS_RESET
> -2:
> - bl trap_reloc
> - addi r7, r7, 0x100 /* next exception vector */
> - cmplw 0, r7, r8
> - blt 2b
> -
> - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
> - bl trap_reloc
> -
> - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
> - bl trap_reloc
> -
> - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
> - li r8, SystemCall - _start + EXC_OFF_SYS_RESET
> -3:
> - bl trap_reloc
> - addi r7, r7, 0x100 /* next exception vector */
> - cmplw 0, r7, r8
> - blt 3b
> -
> - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
> - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
> -4:
> - bl trap_reloc
> - addi r7, r7, 0x100 /* next exception vector */
> - cmplw 0, r7, r8
> - blt 4b
> -
> - /* enable execptions from RAM vectors */
> - mfmsr r7
> - li r8,MSR_IP
> - andc r7,r7,r8
> - ori r7,r7,MSR_ME /* Enable Machine Check */
> - mtmsr r7
> -
> - mtlr r4 /* restore link register */
> - blr
> -
> -.globl enable_ext_addr
> -enable_ext_addr:
> - mfspr r0, HID0
> - lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
> - ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
> - mtspr HID0, r0
> - sync
> - isync
> - blr
> -
> -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
> -.globl setup_ccsrbar
> -setup_ccsrbar:
> - /* Special sequence needed to update CCSRBAR itself */
> - lis r4, CONFIG_SYS_CCSRBAR_DEFAULT at h
> - ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT at l
> -
> - lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at h
> - ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at l
> - srwi r5,r5,12
> - li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l
> - rlwimi r5,r6,20,8,11
> - stw r5, 0(r4) /* Store physical value of CCSR */
> - isync
> -
> - lis r5, CONFIG_SYS_TEXT_BASE at h
> - ori r5,r5,CONFIG_SYS_TEXT_BASE at l
> - lwz r5, 0(r5)
> - isync
> -
> - /* Use VA of CCSR to do read */
> - lis r3, CONFIG_SYS_CCSRBAR at h
> - lwz r5, CONFIG_SYS_CCSRBAR at l(r3)
> - isync
> -
> - blr
> -#endif
> -
> -#ifdef CONFIG_SYS_INIT_RAM_LOCK
> -lock_ram_in_cache:
> - /* Allocate Initial RAM in data cache.
> - */
> - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
> - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
> - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
> - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
> - mtctr r4
> -1:
> - dcbz r0, r3
> - addi r3, r3, 32
> - bdnz 1b
> -#if 1
> -/* Lock the data cache */
> - mfspr r0, HID0
> - ori r0, r0, 0x1000
> - sync
> - mtspr HID0, r0
> - sync
> - blr
> -#endif
> -#if 0
> - /* Lock the first way of the data cache */
> - mfspr r0, LDSTCR
> - ori r0, r0, 0x0080
> -#if defined(CONFIG_ALTIVEC)
> - dssall
> -#endif
> - sync
> - mtspr LDSTCR, r0
> - sync
> - isync
> - blr
> -#endif
> -
> -.globl unlock_ram_in_cache
> -unlock_ram_in_cache:
> - /* invalidate the INIT_RAM section */
> - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
> - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
> - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
> - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
> - mtctr r4
> -1: icbi r0, r3
> - addi r3, r3, 32
> - bdnz 1b
> - sync /* Wait for all icbi to complete on bus */
> - isync
> -#if 1
> -/* Unlock the data cache and invalidate it */
> - mfspr r0, HID0
> - li r3,0x1000
> - andc r0,r0,r3
> - li r3,0x0400
> - or r0,r0,r3
> - sync
> - mtspr HID0, r0
> - sync
> - blr
> -#endif
> -#if 0
> - /* Unlock the first way of the data cache */
> - mfspr r0, LDSTCR
> - li r3,0x0080
> - andc r0,r0,r3
> -#ifdef CONFIG_ALTIVEC
> - dssall
> -#endif
> - sync
> - mtspr LDSTCR, r0
> - sync
> - isync
> - li r3,0x0400
> - or r0,r0,r3
> - sync
> - mtspr HID0, r0
> - sync
> - blr
> -#endif
> -#endif
> diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c
> deleted file mode 100644
> index 46006ece4160..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/traps.c
> +++ /dev/null
> @@ -1,199 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 1995-1996 Gary Thomas (gdt at linuxppc.org)
> - *
> - * Modified by Cort Dougan (cort at cs.nmt.edu)
> - * and Paul Mackerras (paulus at cs.anu.edu.au)
> - *
> - * (C) Copyright 2000
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - */
> -
> -/*
> - * This file handles the architecture-dependent parts of hardware exceptions
> - */
> -
> -#include <common.h>
> -#include <asm/global_data.h>
> -#include <asm/ptrace.h>
> -#include <command.h>
> -#include <init.h>
> -#include <kgdb.h>
> -#include <asm/processor.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/* Returns 0 if exception not found and fixup otherwise. */
> -extern unsigned long search_exception_table(unsigned long);
> -
> -/*
> - * End of addressable memory. This may be less than the actual
> - * amount of memory on the system if we're unable to keep all
> - * the memory mapped in.
> - */
> -#define END_OF_MEM (gd->ram_base + get_effective_memsize())
> -
> -/*
> - * Trap & Exception support
> - */
> -
> -static void print_backtrace(unsigned long *sp)
> -{
> - int cnt = 0;
> - unsigned long i;
> -
> - printf("Call backtrace: ");
> - while (sp) {
> - if ((uint) sp > END_OF_MEM)
> - break;
> -
> - i = sp[1];
> - if (cnt++ % 7 == 0)
> - printf("\n");
> - printf("%08lX ", i);
> - if (cnt > 32)
> - break;
> - sp = (unsigned long *)*sp;
> - }
> - printf("\n");
> -}
> -
> -void show_regs(struct pt_regs *regs)
> -{
> - int i;
> -
> - printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
> - " %p TRAP: %04lx DAR: %08lX\n",
> - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
> - printf("MSR: %08lx EE: %01x PR: %01x FP:"
> - " %01x ME: %01x IR/DR: %01x%01x\n",
> - regs->msr, regs->msr & MSR_EE ? 1 : 0,
> - regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
> - regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
> - regs->msr & MSR_DR ? 1 : 0);
> -
> - printf("\n");
> - for (i = 0; i < 32; i++) {
> - if ((i % 8) == 0) {
> - printf("GPR%02d: ", i);
> - }
> -
> - printf("%08lX ", regs->gpr[i]);
> - if ((i % 8) == 7) {
> - printf("\n");
> - }
> - }
> -}
> -
> -
> -static void _exception(int signr, struct pt_regs *regs)
> -{
> - show_regs(regs);
> - print_backtrace((unsigned long *)regs->gpr[1]);
> - panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
> -}
> -
> -void MachineCheckException(struct pt_regs *regs)
> -{
> - unsigned long fixup;
> -
> - /* Probing PCI using config cycles cause this exception
> - * when a device is not present. Catch it and return to
> - * the PCI exception handler.
> - */
> - if ((fixup = search_exception_table(regs->nip)) != 0) {
> - regs->nip = fixup;
> - return;
> - }
> -
> -#if defined(CONFIG_CMD_KGDB)
> - if (debugger_exception_handler && (*debugger_exception_handler) (regs))
> - return;
> -#endif
> -
> - printf("Machine check in kernel mode.\n");
> - printf("Caused by (from msr): ");
> - printf("regs %p ", regs);
> - switch ( regs->msr & 0x001F0000) {
> - case (0x80000000>>11):
> - printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0));
> - break;
> - case (0x80000000>>12):
> - printf("Machine check signal - probably due to mm fault\n"
> - "with mmu off\n");
> - break;
> - case (0x80000000 >> 13):
> - printf("Transfer error ack signal\n");
> - break;
> - case (0x80000000 >> 14):
> - printf("Data parity signal\n");
> - break;
> - case (0x80000000 >> 15):
> - printf("Address parity signal\n");
> - break;
> - default:
> - printf("Unknown values in msr\n");
> - }
> - show_regs(regs);
> - print_backtrace((unsigned long *)regs->gpr[1]);
> - panic("machine check");
> -}
> -
> -void AlignmentException(struct pt_regs *regs)
> -{
> -#if defined(CONFIG_CMD_KGDB)
> - if (debugger_exception_handler && (*debugger_exception_handler) (regs))
> - return;
> -#endif
> - show_regs(regs);
> - print_backtrace((unsigned long *)regs->gpr[1]);
> - panic("Alignment Exception");
> -}
> -
> -void ProgramCheckException(struct pt_regs *regs)
> -{
> - unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
> - int i, j;
> -
> -#if defined(CONFIG_CMD_KGDB)
> - if (debugger_exception_handler && (*debugger_exception_handler) (regs))
> - return;
> -#endif
> - show_regs(regs);
> -
> - p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0);
> - p -= 32;
> - for (i = 0; i < 256; i += 16) {
> - printf("%08x: ", (unsigned int)p + i);
> - for (j = 0; j < 16; j++) {
> - printf("%02x ", p[i + j]);
> - }
> - printf("\n");
> - }
> -
> - print_backtrace((unsigned long *)regs->gpr[1]);
> - panic("Program Check Exception");
> -}
> -
> -void SoftEmuException(struct pt_regs *regs)
> -{
> -#if defined(CONFIG_CMD_KGDB)
> - if (debugger_exception_handler && (*debugger_exception_handler) (regs))
> - return;
> -#endif
> - show_regs(regs);
> - print_backtrace((unsigned long *)regs->gpr[1]);
> - panic("Software Emulation Exception");
> -}
> -
> -void UnknownException(struct pt_regs *regs)
> -{
> -#if defined(CONFIG_CMD_KGDB)
> - if (debugger_exception_handler && (*debugger_exception_handler) (regs))
> - return;
> -#endif
> - printf("UnknownException regs@%lx\n", (ulong)regs);
> - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
> - regs->nip, regs->msr, regs->trap);
> - _exception(0, regs);
> -}
> diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
> deleted file mode 100644
> index 94f07c6b7dd2..000000000000
> --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds
> +++ /dev/null
> @@ -1,77 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2006, 2007 Freescale Semiconductor, Inc.
> - */
> -
> -OUTPUT_ARCH(powerpc)
> -
> -SECTIONS
> -{
> -
> - /* Read-only sections, merged into text segment: */
> - .text :
> - {
> - arch/powerpc/cpu/mpc86xx/start.o (.text*)
> - arch/powerpc/cpu/mpc86xx/traps.o (.text*)
> - *(.text*)
> - }
> - _etext = .;
> - PROVIDE (etext = .);
> - .rodata :
> - {
> - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
> - }
> -
> - /* Read-write section, merged into data segment: */
> - . = (. + 0x00FF) & 0xFFFFFF00;
> - _erotext = .;
> - PROVIDE (erotext = .);
> - .reloc :
> - {
> - _GOT2_TABLE_ = .;
> - KEEP(*(.got2))
> - KEEP(*(.got))
> - _FIXUP_TABLE_ = .;
> - KEEP(*(.fixup))
> - }
> - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
> - __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
> -
> - .data :
> - {
> - *(.data*)
> - *(.sdata*)
> - }
> - _edata = .;
> - PROVIDE (edata = .);
> -
> - . = .;
> -
> - . = ALIGN(4);
> - .u_boot_list : {
> - KEEP(*(SORT(.u_boot_list*)));
> - }
> -
> - . = .;
> - __start___ex_table = .;
> - __ex_table : { *(__ex_table) }
> - __stop___ex_table = .;
> -
> - . = ALIGN(256);
> - __init_begin = .;
> - .text.init : { *(.text.init) }
> - .data.init : { *(.data.init) }
> - . = ALIGN(256);
> - __init_end = .;
> -
> - __bss_start = .;
> - .bss (NOLOAD) :
> - {
> - *(.bss*)
> - *(.sbss*)
> - *(COMMON)
> - . = ALIGN(4);
> - }
> - __bss_end = . ;
> - PROVIDE (end = .);
> -}
> diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
> index 99b410dc9b09..2c96378efef8 100644
> --- a/arch/powerpc/include/asm/config.h
> +++ b/arch/powerpc/include/asm/config.h
> @@ -10,10 +10,6 @@
> #include <asm/config_mpc85xx.h>
> #endif
>
> -#ifdef CONFIG_MPC86xx
> -#include <asm/config_mpc86xx.h>
> -#endif
> -
> #ifndef HWCONFIG_BUFFER_SIZE
> #define HWCONFIG_BUFFER_SIZE 256
> #endif
> diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
> deleted file mode 100644
> index f19ff7a6a128..000000000000
> --- a/arch/powerpc/include/asm/config_mpc86xx.h
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2011 Freescale Semiconductor, Inc.
> - */
> -
> -#ifndef _ASM_MPC86xx_CONFIG_H_
> -#define _ASM_MPC86xx_CONFIG_H_
> -
> -#endif /* _ASM_MPC85xx_CONFIG_H_ */
> diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
> index 77cdc80fdcd0..39fbc04e4744 100644
> --- a/arch/powerpc/include/asm/fsl_law.h
> +++ b/arch/powerpc/include/asm/fsl_law.h
> @@ -78,9 +78,6 @@ enum law_trgt_if {
> enum law_trgt_if {
> LAW_TRGT_IF_PCI = 0x00,
> LAW_TRGT_IF_PCI_2 = 0x01,
> -#ifndef CONFIG_ARCH_MPC8641
> - LAW_TRGT_IF_PCIE_1 = 0x02,
> -#endif
> #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
> LAW_TRGT_IF_OCN_DSP = 0x03,
> #else
> @@ -116,10 +113,6 @@ enum law_trgt_if {
> #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
> #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
>
> -#ifdef CONFIG_ARCH_MPC8641
> -#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
> -#endif
> -
> #if defined(CONFIG_ARCH_P2020)
> #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
> #endif
> diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
> index 508834829b95..06f9bfb8ac73 100644
> --- a/arch/powerpc/include/asm/fsl_pci.h
> +++ b/arch/powerpc/include/asm/fsl_pci.h
> @@ -30,7 +30,7 @@ void fsl_pci_config_unlock(struct pci_controller *hose);
> void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
>
> /*
> - * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
> + * Common PCI/PCIE Register structure for mpc85xx
> */
>
> /*
> diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
> deleted file mode 100644
> index 1fbc63a5ceb8..000000000000
> --- a/arch/powerpc/include/asm/immap_86xx.h
> +++ /dev/null
> @@ -1,1221 +0,0 @@
> -/*
> - * MPC86xx Internal Memory Map
> - *
> - * Copyright 2004, 2011 Freescale Semiconductor
> - * Jeff Brown (Jeffrey at freescale.com)
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - *
> - */
> -
> -#ifndef __IMMAP_86xx__
> -#define __IMMAP_86xx__
> -
> -#include <fsl_immap.h>
> -#include <asm/types.h>
> -#include <asm/fsl_dma.h>
> -#include <asm/fsl_lbc.h>
> -#include <asm/fsl_i2c.h>
> -
> -/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
> -typedef struct ccsr_local_mcm {
> - uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
> - char res1[4];
> - uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
> - char res2[4];
> - uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
> - char res3[12];
> - uint bptr; /* 0x20 - Boot Page Translation Register */
> - char res4[3044];
> - uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
> - char res5[4];
> - uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
> - char res6[20];
> - uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
> - char res7[4];
> - uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
> - char res8[20];
> - uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
> - char res9[4];
> - uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
> - char res10[20];
> - uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
> - char res11[4];
> - uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
> - char res12[20];
> - uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
> - char res13[4];
> - uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
> - char res14[20];
> - uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
> - char res15[4];
> - uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
> - char res16[20];
> - uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
> - char res17[4];
> - uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
> - char res18[20];
> - uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
> - char res19[4];
> - uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
> - char res20[20];
> - uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
> - char res21[4];
> - uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
> - char res22[20];
> - uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
> - char res23[4];
> - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
> - char res24[716];
> - uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */
> - char res25[4];
> - uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */
> - char res26[4];
> - uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */
> - char res27[44];
> - uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */
> - uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */
> - uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */
> - uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */
> - char res28[16];
> - uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */
> - uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */
> - uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */
> - char res29[3476];
> - uint edr; /* 0x1e00 - MCM Error Detect Register */
> - char res30[4];
> - uint eer; /* 0x1e08 - MCM Error Enable Register */
> - uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */
> - uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */
> - uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */
> - char res31[488];
> -} ccsr_local_mcm_t;
> -
> -/* Daul I2C Registers(0x3000-0x4000) */
> -typedef struct ccsr_i2c {
> - struct fsl_i2c_base i2c[2];
> - u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)];
> -} ccsr_i2c_t;
> -
> -/* DUART Registers(0x4000-0x5000) */
> -typedef struct ccsr_duart {
> - char res1[1280];
> - u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
> - u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
> - u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
> - u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
> - u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
> - u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
> - u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
> - u_char uscr1; /* 0x4507 - UART1 Scratch Register */
> - char res2[8];
> - u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
> - char res3[239];
> - u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
> - u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
> - u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
> - u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
> - u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
> - u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
> - u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
> - u_char uscr2; /* 0x4607 - UART2 Scratch Register */
> - char res4[8];
> - u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
> - char res5[2543];
> -} ccsr_duart_t;
> -
> -/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
> -typedef struct ccsr_pex {
> - uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
> - uint cfg_data; /* 0x8004 - PEX Configuration Data Register */
> - char res1[4];
> - uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */
> - char res2[16];
> - uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */
> - uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */
> - uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */
> - uint pm_command; /* 0x802c - PEX PM Command register */
> - char res3[3016];
> - uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */
> - uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */
> - uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
> - uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
> - char res4[8];
> - uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
> - char res5[12];
> - uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
> - uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
> - uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */
> - char res6[4];
> - uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
> - char res7[12];
> - uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
> - uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
> - uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */
> - char res8[4];
> - uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
> - char res9[12];
> - uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
> - uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
> - uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */
> - char res10[4];
> - uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
> - char res11[12];
> - uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
> - uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
> - uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */
> - char res12[4];
> - uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
> - char res13[12];
> - char res14[256];
> - uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */
> - char res15[4];
> - uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */
> - uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
> - uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
> - char res16[12];
> - uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */
> - char res17[4];
> - uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
> - uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
> - uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
> - char res18[12];
> - uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */
> - char res19[4];
> - uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */
> - uint piwbear1;
> - uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
> - char res20[12];
> - uint pedr; /* 0x8e00 - PEX Error Detect Register */
> - char res21[4];
> - uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */
> - char res22[4];
> - uint pecdr; /* 0x8e10 - PEX Error Disable Register */
> - char res23[12];
> - uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */
> - char res24[4];
> - uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */
> - uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */
> - uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */
> - uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */
> - char res25[452];
> - char res26[4];
> -} ccsr_pex_t;
> -
> -/* Hyper Transport Register Block (0xA000-0xB000) */
> -typedef struct ccsr_ht {
> - uint hcfg_addr; /* 0xa000 - HT Configuration Address register */
> - uint hcfg_data; /* 0xa004 - HT Configuration Data register */
> - char res1[3064];
> - uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */
> - char res2[12];
> - uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */
> - char res3[12];
> - uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */
> - char res4[4];
> - uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */
> - char res5[4];
> - uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */
> - char res6[12];
> - uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */
> - char res7[4];
> - uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */
> - char res8[4];
> - uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */
> - char res9[12];
> - uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */
> - char res10[4];
> - uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */
> - char res11[4];
> - uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */
> - char res12[12];
> - uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */
> - char res13[4];
> - uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */
> - char res14[4];
> - uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */
> - char res15[236];
> - uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */
> - char res16[4];
> - uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */
> - char res17[4];
> - uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */
> - char res18[12];
> - uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */
> - char res19[4];
> - uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */
> - char res20[4];
> - uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */
> - char res21[12];
> - uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */
> - char res22[4];
> - uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */
> - char res23[4];
> - uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */
> - char res24[12];
> - uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */
> - char res25[4];
> - uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */
> - char res26[4];
> - uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */
> - char res27[12];
> - uint hedr; /* 0xae00 - HT Error Detect register */
> - char res28[4];
> - uint heier; /* 0xae08 - HT Error Interrupt Enable register */
> - char res29[4];
> - uint hecdr; /* 0xae10 - HT Error Capture Disbale register */
> - char res30[12];
> - uint hecsr; /* 0xae20 - HT Error Capture Status register */
> - char res31[4];
> - uint hec0; /* 0xae28 - HT Error Capture 0 register */
> - uint hec1; /* 0xae2c - HT Error Capture 1 register */
> - uint hec2; /* 0xae30 - HT Error Capture 2 register */
> - char res32[460];
> -} ccsr_ht_t;
> -
> -/* DMA Registers(0x2_1000-0x2_2000) */
> -typedef struct ccsr_dma {
> - char res1[256];
> - struct fsl_dma dma[4];
> - uint dgsr; /* 0x21300 - DMA General Status Register */
> - char res2[3324];
> -} ccsr_dma_t;
> -
> -/* tsec1-4: 24000-28000 */
> -typedef struct ccsr_tsec {
> - uint id; /* 0x24000 - Controller ID Register */
> - char res1[12];
> - uint ievent; /* 0x24010 - Interrupt Event Register */
> - uint imask; /* 0x24014 - Interrupt Mask Register */
> - uint edis; /* 0x24018 - Error Disabled Register */
> - char res2[4];
> - uint ecntrl; /* 0x24020 - Ethernet Control Register */
> - char res2_1[4];
> - uint ptv; /* 0x24028 - Pause Time Value Register */
> - uint dmactrl; /* 0x2402c - DMA Control Register */
> - uint tbipa; /* 0x24030 - TBI PHY Address Register */
> - char res3[88];
> - uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
> - char res4[8];
> - uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
> - uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
> - char res4_1[4];
> - uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */
> - uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */
> - char res5[84];
> - uint tctrl; /* 0x24100 - Transmit Control Register */
> - uint tstat; /* 0x24104 - Transmit Status Register */
> - uint dfvlan; /* 0x24108 - Default VLAN control word */
> - char res6[4];
> - uint txic; /* 0x24110 - Transmit interrupt coalescing Register */
> - uint tqueue; /* 0x24114 - Transmit Queue Control Register */
> - char res7[40];
> - uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
> - uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
> - char res8[52];
> - uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */
> - char res9[4];
> - uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
> - char res10[4];
> - uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
> - char res11[4];
> - uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
> - char res12[4];
> - uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
> - char res13[4];
> - uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
> - char res14[4];
> - uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
> - char res15[4];
> - uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
> - char res16[4];
> - uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
> - char res17[64];
> - uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
> - uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
> - char res18[4];
> - uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */
> - char res19[4];
> - uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */
> - char res20[4];
> - uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */
> - char res21[4];
> - uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */
> - char res22[4];
> - uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */
> - char res23[4];
> - uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */
> - char res24[4];
> - uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */
> - char res25[192];
> - uint rctrl; /* 0x24300 - Receive Control Register */
> - uint rstat; /* 0x24304 - Receive Status Register */
> - char res26[8];
> - uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */
> - uint rqueue; /* 0x24314 - Receive queue control register */
> - char res27[24];
> - uint rbifx; /* 0x24330 - Receive bit field extract control Register */
> - uint rqfar; /* 0x24334 - Receive queue filing table address Register */
> - uint rqfcr; /* 0x24338 - Receive queue filing table control Register */
> - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */
> - uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
> - char res28[56];
> - uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */
> - char res29[4];
> - uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
> - char res30[4];
> - uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
> - char res31[4];
> - uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
> - char res32[4];
> - uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
> - char res33[4];
> - uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
> - char res34[4];
> - uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
> - char res35[4];
> - uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
> - char res36[4];
> - uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
> - char res37[64];
> - uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
> - uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */
> - char res38[4];
> - uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */
> - char res39[4];
> - uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */
> - char res40[4];
> - uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */
> - char res41[4];
> - uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */
> - char res42[4];
> - uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */
> - char res43[4];
> - uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */
> - char res44[4];
> - uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */
> - char res45[192];
> - uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
> - uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
> - uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
> - uint hafdup; /* 0x2450c - Half Duplex Register */
> - uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
> - char res46[12];
> - uint miimcfg; /* 0x24520 - MII Management Configuration Register */
> - uint miimcom; /* 0x24524 - MII Management Command Register */
> - uint miimadd; /* 0x24528 - MII Management Address Register */
> - uint miimcon; /* 0x2452c - MII Management Control Register */
> - uint miimstat; /* 0x24530 - MII Management Status Register */
> - uint miimind; /* 0x24534 - MII Management Indicator Register */
> - uint ifctrl; /* 0x24538 - Interface Contrl Register */
> - uint ifstat; /* 0x2453c - Interface Status Register */
> - uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
> - uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
> - uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */
> - uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */
> - uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */
> - uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */
> - uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */
> - uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */
> - uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */
> - uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */
> - uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */
> - uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */
> - uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */
> - uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */
> - uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */
> - uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */
> - uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */
> - uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */
> - uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */
> - uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */
> - uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */
> - uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */
> - uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */
> - uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */
> - uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */
> - uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */
> - uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */
> - uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */
> - uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */
> - uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */
> - uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */
> - uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */
> - char res48[192];
> - uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
> - uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
> - uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
> - uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
> - uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
> - uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
> - uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
> - uint rbyt; /* 0x2469c - Receive Byte Counter */
> - uint rpkt; /* 0x246a0 - Receive Packet Counter */
> - uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
> - uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
> - uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
> - uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
> - uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
> - uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
> - uint raln; /* 0x246bc - Receive Alignment Error Counter */
> - uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
> - uint rcde; /* 0x246c4 - Receive Code Error Counter */
> - uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
> - uint rund; /* 0x246cc - Receive Undersize Packet Counter */
> - uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
> - uint rfrg; /* 0x246d4 - Receive Fragments Counter */
> - uint rjbr; /* 0x246d8 - Receive Jabber Counter */
> - uint rdrp; /* 0x246dc - Receive Drop Counter */
> - uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
> - uint tpkt; /* 0x246e4 - Transmit Packet Counter */
> - uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
> - uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
> - uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
> - uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
> - uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
> - uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
> - uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
> - uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
> - uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
> - uint tncl; /* 0x2470c - Transmit Total Collision Counter */
> - char res49[4];
> - uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
> - uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
> - uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
> - uint txcf; /* 0x24720 - Transmit Control Frame Counter */
> - uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
> - uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
> - uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
> - uint car1; /* 0x24730 - Carry Register One */
> - uint car2; /* 0x24734 - Carry Register Two */
> - uint cam1; /* 0x24738 - Carry Mask Register One */
> - uint cam2; /* 0x2473c - Carry Mask Register Two */
> - uint rrej; /* 0x24740 - Receive filer rejected packet counter */
> - char res50[188];
> - uint iaddr0; /* 0x24800 - Indivdual address register 0 */
> - uint iaddr1; /* 0x24804 - Indivdual address register 1 */
> - uint iaddr2; /* 0x24808 - Indivdual address register 2 */
> - uint iaddr3; /* 0x2480c - Indivdual address register 3 */
> - uint iaddr4; /* 0x24810 - Indivdual address register 4 */
> - uint iaddr5; /* 0x24814 - Indivdual address register 5 */
> - uint iaddr6; /* 0x24818 - Indivdual address register 6 */
> - uint iaddr7; /* 0x2481c - Indivdual address register 7 */
> - char res51[96];
> - uint gaddr0; /* 0x24880 - Global address register 0 */
> - uint gaddr1; /* 0x24884 - Global address register 1 */
> - uint gaddr2; /* 0x24888 - Global address register 2 */
> - uint gaddr3; /* 0x2488c - Global address register 3 */
> - uint gaddr4; /* 0x24890 - Global address register 4 */
> - uint gaddr5; /* 0x24894 - Global address register 5 */
> - uint gaddr6; /* 0x24898 - Global address register 6 */
> - uint gaddr7; /* 0x2489c - Global address register 7 */
> - char res52[352];
> - uint fifocfg; /* 0x24A00 - FIFO interface configuration register */
> - char res53[500];
> - uint attr; /* 0x24BF8 - DMA Attribute register */
> - uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */
> - char res54[1024];
> -} ccsr_tsec_t;
> -
> -/* PIC Registers(0x4_0000-0x6_1000) */
> -
> -typedef struct ccsr_pic {
> - char res1[64];
> - uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
> - char res2[12];
> - uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
> - char res3[12];
> - uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
> - char res4[12];
> - uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
> - char res5[12];
> - uint ctpr; /* 0x40080 - Current Task Priority Register */
> - char res6[12];
> - uint whoami; /* 0x40090 - Who Am I Register */
> - char res7[12];
> - uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
> - char res8[12];
> - uint eoi; /* 0x400b0 - End Of Interrupt Register */
> - char res9[3916];
> - uint frr; /* 0x41000 - Feature Reporting Register */
> - char res10[28];
> - uint gcr; /* 0x41020 - Global Configuration Register */
> -#define MPC86xx_PICGCR_RST 0x80000000
> -#define MPC86xx_PICGCR_MODE 0x20000000
> - char res11[92];
> - uint vir; /* 0x41080 - Vendor Identification Register */
> - char res12[12];
> - uint pir; /* 0x41090 - Processor Initialization Register */
> - char res13[12];
> - uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
> - char res14[12];
> - uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
> - char res15[12];
> - uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
> - char res16[12];
> - uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
> - char res17[12];
> - uint svr; /* 0x410e0 - Spurious Vector Register */
> - char res18[12];
> - uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
> - char res19[12];
> - uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
> - char res20[12];
> - uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
> - char res21[12];
> - uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
> - char res22[12];
> - uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
> - char res23[12];
> - uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
> - char res24[12];
> - uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
> - char res25[12];
> - uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
> - char res26[12];
> - uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
> - char res27[12];
> - uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
> - char res28[12];
> - uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
> - char res29[12];
> - uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
> - char res30[12];
> - uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
> - char res31[12];
> - uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
> - char res32[12];
> - uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
> - char res33[12];
> - uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
> - char res34[12];
> - uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
> - char res35[268];
> - uint tcr; /* 0x41300 - Timer Control Register */
> - char res36[12];
> - uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
> - char res37[12];
> - uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
> - char res38[12];
> - uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
> - char res39[12];
> - uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
> - char res40[12];
> - uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */
> - char res41[12];
> - uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */
> - char res42[12];
> - uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */
> - char res43[12];
> - uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */
> - char res44[12];
> - uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */
> - char res45[12];
> - uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */
> - char res46[12];
> - uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */
> - char res47[12];
> - uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */
> - char res48[60];
> - uint msgr0; /* 0x41400 - Message Register 0 */
> - char res49[12];
> - uint msgr1; /* 0x41410 - Message Register 1 */
> - char res50[12];
> - uint msgr2; /* 0x41420 - Message Register 2 */
> - char res51[12];
> - uint msgr3; /* 0x41430 - Message Register 3 */
> - char res52[204];
> - uint mer; /* 0x41500 - Message Enable Register */
> - char res53[12];
> - uint msr; /* 0x41510 - Message Status Register */
> - char res54[60140];
> - uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
> - char res55[12];
> - uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
> - char res56[12];
> - uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
> - char res57[12];
> - uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
> - char res58[12];
> - uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
> - char res59[12];
> - uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
> - char res60[12];
> - uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
> - char res61[12];
> - uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
> - char res62[12];
> - uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
> - char res63[12];
> - uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
> - char res64[12];
> - uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
> - char res65[12];
> - uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
> - char res66[12];
> - uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
> - char res67[12];
> - uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
> - char res68[12];
> - uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
> - char res69[12];
> - uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
> - char res70[12];
> - uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
> - char res71[12];
> - uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
> - char res72[12];
> - uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
> - char res73[12];
> - uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
> - char res74[12];
> - uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
> - char res75[12];
> - uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
> - char res76[12];
> - uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
> - char res77[12];
> - uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
> - char res78[140];
> - uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
> - char res79[12];
> - uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
> - char res80[12];
> - uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
> - char res81[12];
> - uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
> - char res82[12];
> - uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
> - char res83[12];
> - uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
> - char res84[12];
> - uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
> - char res85[12];
> - uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
> - char res86[12];
> - uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
> - char res87[12];
> - uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
> - char res88[12];
> - uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
> - char res89[12];
> - uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
> - char res90[12];
> - uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
> - char res91[12];
> - uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
> - char res92[12];
> - uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
> - char res93[12];
> - uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
> - char res94[12];
> - uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
> - char res95[12];
> - uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
> - char res96[12];
> - uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
> - char res97[12];
> - uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
> - char res98[12];
> - uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
> - char res99[12];
> - uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
> - char res100[12];
> - uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
> - char res101[12];
> - uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
> - char res102[12];
> - uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
> - char res103[12];
> - uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
> - char res104[12];
> - uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
> - char res105[12];
> - uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
> - char res106[12];
> - uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
> - char res107[12];
> - uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
> - char res108[12];
> - uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
> - char res109[12];
> - uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
> - char res110[12];
> - uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
> - char res111[12];
> - uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
> - char res112[12];
> - uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
> - char res113[12];
> - uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
> - char res114[12];
> - uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
> - char res115[12];
> - uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
> - char res116[12];
> - uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
> - char res117[12];
> - uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
> - char res118[12];
> - uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
> - char res119[12];
> - uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
> - char res120[12];
> - uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
> - char res121[12];
> - uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
> - char res122[12];
> - uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
> - char res123[12];
> - uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
> - char res124[12];
> - uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
> - char res125[12];
> - uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
> - char res126[12];
> - uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
> - char res127[12];
> - uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
> - char res128[12];
> - uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
> - char res129[12];
> - uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
> - char res130[12];
> - uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
> - char res131[12];
> - uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
> - char res132[12];
> - uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
> - char res133[12];
> - uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
> - char res134[12];
> - uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
> - char res135[12];
> - uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
> - char res136[12];
> - uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
> - char res137[12];
> - uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
> - char res138[12];
> - uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
> - char res139[12];
> - uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
> - char res140[12];
> - uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
> - char res141[12];
> - uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
> - char res142[4108];
> - uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
> - char res143[12];
> - uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
> - char res144[12];
> - uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
> - char res145[12];
> - uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
> - char res146[12];
> - uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
> - char res147[12];
> - uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
> - char res148[12];
> - uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
> - char res149[12];
> - uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
> - char res150[59852];
> - uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
> - char res151[12];
> - uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
> - char res152[12];
> - uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
> - char res153[12];
> - uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
> - char res154[12];
> - uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
> - char res155[12];
> - uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
> - char res156[12];
> - uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
> - char res157[12];
> - uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
> - char res158[3916];
> -} ccsr_pic_t;
> -
> -/* RapidIO Registers(0xc_0000-0xe_0000) */
> -
> -typedef struct ccsr_rio {
> - uint didcar; /* 0xc0000 - Device Identity Capability Register */
> - uint dicar; /* 0xc0004 - Device Information Capability Register */
> - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
> - uint aicar; /* 0xc000c - Assembly Information Capability Register */
> - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
> - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
> - uint socar; /* 0xc0018 - Source Operations Capability Register */
> - uint docar; /* 0xc001c - Destination Operations Capability Register */
> - char res1[32];
> - uint msr; /* 0xc0040 - Mailbox Command And Status Register */
> - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
> - char res2[4];
> - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
> - char res3[12];
> - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
> - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
> - char res4[4];
> - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
> - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
> - char res5[144];
> - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
> - char res6[28];
> - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
> - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
> - char res7[20];
> - uint pgccsr; /* 0xc013c - Port General Command and Status Register */
> - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
> - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
> - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
> - char res8[12];
> - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
> - uint pccsr; /* 0xc015c - Port Control Command and Status Register */
> - char res9[1184];
> - uint erbh; /* 0xc0600 - Error Reporting Block Header Register */
> - char res10[4];
> - uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */
> - uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */
> - char res11[4];
> - uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */
> - uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */
> - uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */
> - char res12[32];
> - uint edcsr; /* 0xc0640 - Port 0 error detect status register */
> - uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */
> - uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */
> - uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */
> - uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */
> - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */
> - uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */
> - char res13[12];
> - uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */
> - uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/
> - char res14[63892];
> - uint llcr; /* 0xd0004 - Logical Layer Configuration Register */
> - char res15[12];
> - uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */
> - char res16[12];
> - uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */
> - char res17[92];
> - uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
> - char res18[124];
> - uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
> - char res19[28];
> - uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
> - char res20[12];
> - uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */
> - char res21[12];
> - uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
> - char res22[20];
> - uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */
> - char res23[4];
> - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */
> - char res24[2716];
> - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
> - uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
> - char res25[8];
> - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
> - char res26[12];
> - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
> - uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
> - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
> - char res27[4];
> - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
> - uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
> - uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
> - uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
> - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
> - uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
> - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
> - char res28[4];
> - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
> - uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
> - uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
> - uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
> - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
> - uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
> - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
> - char res29[4];
> - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
> - uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
> - uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
> - uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
> - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
> - uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
> - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
> - char res30[4];
> - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
> - uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
> - uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
> - uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
> - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
> - uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
> - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
> - char res31[4];
> - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
> - uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
> - uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
> - uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
> - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
> - uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
> - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
> - char res32[4];
> - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
> - uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
> - uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
> - uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
> - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
> - uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
> - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
> - char res33[4];
> - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
> - uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
> - uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
> - uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
> - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
> - uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
> - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
> - char res34[4];
> - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
> - uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
> - uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
> - uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
> - char res35[64];
> - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
> - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
> - char res36[4];
> - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
> - char res37[12];
> - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
> - char res38[4];
> - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
> - char res39[4];
> - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
> - char res40[12];
> - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
> - char res41[4];
> - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
> - char res42[4];
> - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
> - char res43[12];
> - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
> - char res44[4];
> - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
> - char res45[4];
> - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
> - char res46[12];
> - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
> - char res47[12];
> - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
> - char res48[12];
> - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
> - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
> - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
> - uint pecr; /* 0xd0e0c - Port Error Control Register */
> - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
> - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
> - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
> - char res49[4];
> - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
> - char res50[4];
> - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
> - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
> - char res51[8656];
> - uint omr; /* 0xd3000 - Outbound Mode Register */
> - uint osr; /* 0xd3004 - Outbound Status Register */
> - uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
> - uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
> - uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */
> - uint osar; /* 0xd3014 - Outbound Unit Source Address Register */
> - uint odpr; /* 0xd3018 - Outbound Destination Port Register */
> - uint odatr; /* 0xd301c - Outbound Destination Attributes Register */
> - uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */
> - uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
> - uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
> - uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
> - uint omgr; /* 0xd3030 - Outbound Multicast Group Register */
> - uint omlr; /* 0xd3034 - Outbound Multicast List Register */
> - char res52[40];
> - uint imr; /* 0xd3060 - Outbound Mode Register */
> - uint isr; /* 0xd3064 - Inbound Status Register */
> - uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
> - uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
> - uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
> - uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
> - uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
> - char res53[900];
> - uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
> - uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
> - char res54[16];
> - uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */
> - uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */
> - char res55[12];
> - uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
> - char res56[48];
> - uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
> - uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */
> - uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
> - uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
> - uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
> - uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
> - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
> - char res57[100];
> - uint pwmr; /* 0xd34e0 - Port-Write Mode Register */
> - uint pwsr; /* 0xd34e4 - Port-Write Status Register */
> - uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */
> - uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
> - char res58[51984];
> -} ccsr_rio_t;
> -
> -/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
> -typedef struct ccsr_gur {
> - uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
> - uint porbmsr; /* 0xe0004 - POR boot mode status register */
> - uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
> - uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
> - uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
> - char res1[12];
> - uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
> - char res2[12];
> - uint gpiocr; /* 0xe0030 - GPIO control register */
> - char res3[12];
> - uint gpoutdr; /* 0xe0040 - General-purpose output data register */
> - char res4[12];
> - uint gpindr; /* 0xe0050 - General-purpose input data register */
> - char res5[12];
> - uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
> - char res6[12];
> - uint devdisr; /* 0xe0070 - Device disable control */
> - char res7[12];
> - uint powmgtcsr; /* 0xe0080 - Power management status and control register */
> - char res8[12];
> - uint mcpsumr; /* 0xe0090 - Machine check summary register */
> - uint rstrscr; /* 0xe0094 - Reset request status and control register */
> - char res9[8];
> - uint pvr; /* 0xe00a0 - Processor version register */
> - uint svr; /* 0xe00a4 - System version register */
> - char res10a[8];
> - uint rstcr; /* 0xe00b0 - Reset control register */
> - char res10b[1868];
> - uint clkdvdr; /* 0xe0800 - Clock Divide register */
> - char res10c[796];
> - uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
> - char res10d[4];
> - uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
> - char res10e[724];
> - uint clkocr; /* 0xe0e00 - Clock out select register */
> - char res11[12];
> - uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
> - char res12[12];
> - uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
> - char res13a[224];
> - uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
> - char res13b[4];
> - uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
> - char res14[24];
> - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
> - char res15a[24];
> - uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
> - uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
> - char res16[184];
> -} ccsr_gur_t;
> -
> -#define MPC8610_PORBMSR_HA 0x00070000
> -#define MPC8610_PORBMSR_HA_SHIFT 16
> -#define MPC8641_PORBMSR_HA 0x00060000
> -#define MPC8641_PORBMSR_HA_SHIFT 17
> -#define MPC8610_PORDEVSR_IO_SEL 0x00380000
> -#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19
> -#define MPC8641_PORDEVSR_IO_SEL 0x000F0000
> -#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16
> -#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
> -#define MPC86xx_DEVDISR_PCIEX1 0x80000000
> -#define MPC86xx_DEVDISR_PCIEX2 0x40000000
> -#define MPC86xx_DEVDISR_PCI1 0x80000000
> -#define MPC86xx_DEVDISR_PCIE1 0x40000000
> -#define MPC86xx_DEVDISR_PCIE2 0x20000000
> -#define MPC86xx_DEVDISR_SRIO 0x00080000
> -#define MPC86xx_DEVDISR_RMSG 0x00040000
> -#define MPC86xx_DEVDISR_CPU0 0x00008000
> -#define MPC86xx_DEVDISR_CPU1 0x00004000
> -#define MPC86xx_RSTCR_HRST_REQ 0x00000002
> -
> -/*
> - * Watchdog register block(0xe_4000-0xe_4fff)
> - */
> -typedef struct ccsr_wdt {
> - uint res0;
> - uint swcrr; /* System watchdog control register */
> - uint swcnr; /* System watchdog count register */
> - char res1[2];
> - ushort swsrr; /* System watchdog service register */
> - char res2[4080];
> -} ccsr_wdt_t;
> -
> -typedef struct immap {
> - ccsr_local_mcm_t im_local_mcm;
> - struct ccsr_ddr im_ddr1;
> - ccsr_i2c_t im_i2c;
> - ccsr_duart_t im_duart;
> - fsl_lbc_t im_lbc;
> - struct ccsr_ddr im_ddr2;
> - char res1[4096];
> - ccsr_pex_t im_pex1;
> - ccsr_pex_t im_pex2;
> - ccsr_ht_t im_ht;
> - char res2[90112];
> - ccsr_dma_t im_dma;
> - char res3[8192];
> - ccsr_tsec_t im_tsec1;
> - ccsr_tsec_t im_tsec2;
> - ccsr_tsec_t im_tsec3;
> - ccsr_tsec_t im_tsec4;
> - char res4[98304];
> - ccsr_pic_t im_pic;
> - char res5[389120];
> - ccsr_rio_t im_rio;
> - ccsr_gur_t im_gur;
> - char res6[12288];
> - ccsr_wdt_t im_wdt;
> -} immap_t;
> -
> -extern immap_t *immr;
> -
> -#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
> -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
> -#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
> -#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
> -#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
> -#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
> -#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
> -#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
> -
> -
> -#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
> -#ifdef CONFIG_ARCH_MPC8610
> -#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
> -#else
> -#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
> -#endif
> -#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
> -
> -#define CONFIG_SYS_PCI1_ADDR \
> - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
> -#define CONFIG_SYS_PCI2_ADDR \
> - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
> -#define CONFIG_SYS_PCIE1_ADDR \
> - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
> -#define CONFIG_SYS_PCIE2_ADDR \
> - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
> -
> -#define CONFIG_SYS_TSEC1_OFFSET 0x24000
> -#define CONFIG_SYS_MDIO1_OFFSET 0x24000
> -#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
> -
> -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
> -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
> -
> -#endif /*__IMMAP_86xx__*/
> diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
> index 055364c58fd9..2923350bd7b9 100644
> --- a/arch/powerpc/include/asm/ppc.h
> +++ b/arch/powerpc/include/asm/ppc.h
> @@ -15,10 +15,6 @@
> #if defined(CONFIG_MPC8xx)
> #include <asm/immap_8xx.h>
> #endif
> -#ifdef CONFIG_MPC86xx
> -#include <mpc86xx.h>
> -#include <asm/immap_86xx.h>
> -#endif
> #ifdef CONFIG_MPC85xx
> #include <mpc85xx.h>
> #include <asm/immap_85xx.h>
> diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig
> deleted file mode 100644
> index 8dfc90cf8bc9..000000000000
> --- a/board/sbc8641d/Kconfig
> +++ /dev/null
> @@ -1,9 +0,0 @@
> -if TARGET_SBC8641D
> -
> -config SYS_BOARD
> - default "sbc8641d"
> -
> -config SYS_CONFIG_NAME
> - default "sbc8641d"
> -
> -endif
> diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS
> deleted file mode 100644
> index a50b541ffe84..000000000000
> --- a/board/sbc8641d/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -SBC8641D BOARD
> -M: Paul Gortmaker <paul.gortmaker@windriver.com>
> -S: Maintained
> -F: board/sbc8641d/
> -F: include/configs/sbc8641d.h
> -F: configs/sbc8641d_defconfig
> diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
> deleted file mode 100644
> index c48f82d3d931..000000000000
> --- a/board/sbc8641d/Makefile
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# (C) Copyright 2001
> -# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> -
> -obj-y += sbc8641d.o
> -obj-y += law.o
> -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
> diff --git a/board/sbc8641d/README b/board/sbc8641d/README
> deleted file mode 100644
> index 4999b7763c9c..000000000000
> --- a/board/sbc8641d/README
> +++ /dev/null
> @@ -1,49 +0,0 @@
> -Wind River SBC8641D reference board
> -===========================
> -
> -Created 06/14/2007 Joe Hamman
> -Copyright 2007, Embedded Specialties, Inc.
> -Copyright 2007 Wind River Systems, Inc.
> ------------------------------
> -
> -1. Building U-Boot
> -------------------
> -The SBC8641D code is known to build using ELDK 4.1.
> -
> - $ make sbc8641d_config
> - Configuring for sbc8641d board...
> -
> - $ make
> -
> -
> -2. Switch and Jumper Settings
> ------------------------------
> -All Jumpers & Switches are in their default positions. Please refer to
> -the board documentation for details. Some settings control CPU voltages
> -and settings may change with board revisions.
> -
> -3. Known limitations
> ---------------------
> -PCI:
> - The PCI command may hang if no boards are present in either slot.
> -
> -4. Reflashing U-Boot
> ---------------------
> -The board has two independent flash devices which can be used for dual
> -booting, or for U-Boot backup and recovery. A two pin jumper on the
> -three pin JP10 determines which device is attached to /CS0 line.
> -
> -Assuming one device has a functional U-Boot, and the other device has
> -a recently installed non-functional image, to perform a recovery from
> -that non-functional image goes essentially as follows:
> -
> -a) power down the board and jumper JP10 to select the functional image.
> -b) power on the board and let it get to U-Boot prompt.
> -c) while on, using static precautions, move JP10 back to the failed image.
> -d) use "md fff00000" to confirm you are looking at the failed image
> -e) turn off write protect with "prot off all"
> -f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin"
> -g) erase failed image: "erase FFF00000 FFF5FFFF"
> -h) copy in new image: "cp.b 200000 FFF00000 60000"
> -i) ensure new image is written: "md fff00000"
> -k) power cycle the board and confirm new image works.
> diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
> deleted file mode 100644
> index b6c1847b141b..000000000000
> --- a/board/sbc8641d/ddr.c
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright 2008 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -
> -#include <fsl_ddr_sdram.h>
> -#include <fsl_ddr_dimm_params.h>
> -
> -void fsl_ddr_board_options(memctl_options_t *popts,
> - dimm_params_t *pdimm,
> - unsigned int ctrl_num)
> -{
> - /*
> - * Factors to consider for clock adjust:
> - * - number of chips on bus
> - * - position of slot
> - * - DDR1 vs. DDR2?
> - * - ???
> - *
> - * This needs to be determined on a board-by-board basis.
> - * 0110 3/4 cycle late
> - * 0111 7/8 cycle late
> - */
> - popts->clk_adjust = 7;
> -
> - /*
> - * Factors to consider for CPO:
> - * - frequency
> - * - ddr1 vs. ddr2
> - */
> - popts->cpo_override = 10;
> -
> - /*
> - * Factors to consider for write data delay:
> - * - number of DIMMs
> - *
> - * 1 = 1/4 clock delay
> - * 2 = 1/2 clock delay
> - * 3 = 3/4 clock delay
> - * 4 = 1 clock delay
> - * 5 = 5/4 clock delay
> - * 6 = 3/2 clock delay
> - */
> - popts->write_data_delay = 3;
> -
> - /*
> - * Factors to consider for half-strength driver enable:
> - * - number of DIMMs installed
> - */
> - popts->half_strength_driver_enable = 0;
> -}
> diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
> deleted file mode 100644
> index dc4696d123f4..000000000000
> --- a/board/sbc8641d/law.c
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2008 Freescale Semiconductor, Inc.
> - *
> - * (C) Copyright 2000
> - * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> - */
> -
> -#include <common.h>
> -#include <asm/fsl_law.h>
> -#include <asm/mmu.h>
> -
> -/*
> - * LAW (Local Access Window) configuration:
> - *
> - * 0x0000_0000 DDR 256M
> - * 0x1000_0000 DDR2 256M
> - * 0x8000_0000 PCIE1 MEM 512M
> - * 0xa000_0000 PCIE2 MEM 512M
> - * 0xc000_0000 RapidIO 512M
> - * 0xe200_0000 PCIE1 IO 16M
> - * 0xe300_0000 PCIE2 IO 16M
> - * 0xf800_0000 CCSRBAR 2M
> - * 0xfe00_0000 FLASH (boot bank) 32M
> - *
> - */
> -
> -
> -struct law_entry law_table[] = {
> -#if !defined(CONFIG_SPD_EEPROM)
> - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
> - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
> - LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
> -#endif
> - SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
> - SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
> -};
> -
> -int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
> deleted file mode 100644
> index a67092daf47f..000000000000
> --- a/board/sbc8641d/sbc8641d.c
> +++ /dev/null
> @@ -1,268 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
> - * Copyright 2007 Embedded Specialties, Inc.
> - * Joe Hamman joe.hamman at embeddedspecialties.com
> - *
> - * Copyright 2004 Freescale Semiconductor.
> - * Jeff Brown
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - *
> - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <init.h>
> -#include <log.h>
> -#include <pci.h>
> -#include <asm/global_data.h>
> -#include <asm/processor.h>
> -#include <asm/immap_86xx.h>
> -#include <asm/fsl_pci.h>
> -#include <fsl_ddr_sdram.h>
> -#include <asm/fsl_serdes.h>
> -#include <linux/delay.h>
> -#include <linux/libfdt.h>
> -#include <fdt_support.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -long int fixed_sdram (void);
> -
> -int board_early_init_f (void)
> -{
> - return 0;
> -}
> -
> -int checkboard (void)
> -{
> - puts ("Board: Wind River SBC8641D\n");
> -
> - return 0;
> -}
> -
> -int dram_init(void)
> -{
> - long dram_size = 0;
> -
> -#if defined(CONFIG_SPD_EEPROM)
> - dram_size = fsl_ddr_sdram();
> -#else
> - dram_size = fixed_sdram ();
> -#endif
> -
> - debug(" DDR: ");
> - gd->ram_size = dram_size;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_SYS_DRAM_TEST)
> -int testdram(void)
> -{
> - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
> - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
> - uint *p;
> -
> - puts ("SDRAM test phase 1:\n");
> - for (p = pstart; p < pend; p++)
> - *p = 0xaaaaaaaa;
> -
> - for (p = pstart; p < pend; p++) {
> - if (*p != 0xaaaaaaaa) {
> - printf ("SDRAM test fails at: %08x\n", (uint) p);
> - return 1;
> - }
> - }
> -
> - puts ("SDRAM test phase 2:\n");
> - for (p = pstart; p < pend; p++)
> - *p = 0x55555555;
> -
> - for (p = pstart; p < pend; p++) {
> - if (*p != 0x55555555) {
> - printf ("SDRAM test fails at: %08x\n", (uint) p);
> - return 1;
> - }
> - }
> -
> - puts ("SDRAM test passed.\n");
> - return 0;
> -}
> -#endif
> -
> -#if !defined(CONFIG_SPD_EEPROM)
> -/*
> - * Fixed sdram init -- doesn't use serial presence detect.
> - */
> -long int fixed_sdram (void)
> -{
> -#if !defined(CONFIG_SYS_RAMBOOT)
> - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
> - volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
> -
> - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
> - ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
> - ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
> - ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
> - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
> - ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
> - ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
> - ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
> - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
> - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
> - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
> - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
> - ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
> - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
> - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
> - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
> - ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
> - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
> - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
> - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
> -
> - asm ("sync;isync");
> -
> - udelay(500);
> -
> - ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
> - asm ("sync; isync");
> -
> - udelay(500);
> - ddr = &immap->im_ddr2;
> -
> - ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
> - ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
> - ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
> - ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
> - ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
> - ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
> - ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
> - ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
> - ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
> - ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
> - ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
> - ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
> - ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
> - ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
> - ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
> - ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
> - ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
> - ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
> - ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
> - ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
> -
> - asm ("sync;isync");
> -
> - udelay(500);
> -
> - ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
> - asm ("sync; isync");
> -
> - udelay(500);
> -#endif
> - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
> -}
> -#endif /* !defined(CONFIG_SPD_EEPROM) */
> -
> -#if defined(CONFIG_PCI)
> -/*
> - * Initialize PCI Devices, report devices found.
> - */
> -
> -void pci_init_board(void)
> -{
> - fsl_pcie_init_board(0);
> -}
> -#endif /* CONFIG_PCI */
> -
> -
> -#if defined(CONFIG_OF_BOARD_SETUP)
> -int ft_board_setup(void *blob, struct bd_info *bd)
> -{
> - ft_cpu_setup(blob, bd);
> -
> - FT_FSL_PCI_SETUP;
> -
> - return 0;
> -}
> -#endif
> -
> -void sbc8641d_reset_board (void)
> -{
> - puts ("Resetting board....\n");
> -}
> -
> -/*
> - * get_board_sys_clk
> - * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
> - */
> -
> -unsigned long get_board_sys_clk (ulong dummy)
> -{
> - int i;
> - ulong val = 0;
> -
> - i = 5;
> - i &= 0x07;
> -
> - switch (i) {
> - case 0:
> - val = 33000000;
> - break;
> - case 1:
> - val = 40000000;
> - break;
> - case 2:
> - val = 50000000;
> - break;
> - case 3:
> - val = 66000000;
> - break;
> - case 4:
> - val = 83000000;
> - break;
> - case 5:
> - val = 100000000;
> - break;
> - case 6:
> - val = 134000000;
> - break;
> - case 7:
> - val = 166000000;
> - break;
> - }
> -
> - return val;
> -}
> -
> -void board_reset(void)
> -{
> -#ifdef CONFIG_SYS_RESET_ADDRESS
> - ulong addr = CONFIG_SYS_RESET_ADDRESS;
> -
> - /* flush and disable I/D cache */
> - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
> - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
> - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
> - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
> - __asm__ __volatile__ ("sync");
> - __asm__ __volatile__ ("mtspr 1008, 4");
> - __asm__ __volatile__ ("isync");
> - __asm__ __volatile__ ("sync");
> - __asm__ __volatile__ ("mtspr 1008, 5");
> - __asm__ __volatile__ ("isync");
> - __asm__ __volatile__ ("sync");
> -
> - /*
> - * SRR0 has system reset vector, SRR1 has default MSR value
> - * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
> - */
> - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
> - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
> - __asm__ __volatile__ ("mtspr 27, 4");
> - __asm__ __volatile__ ("rfi");
> -#endif
> -}
> diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
> deleted file mode 100644
> index ea601dea6f40..000000000000
> --- a/configs/sbc8641d_defconfig
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -CONFIG_PPC=y
> -CONFIG_SYS_TEXT_BASE=0xfff00000
> -CONFIG_ENV_SIZE=0x2000
> -CONFIG_ENV_SECT_SIZE=0x20000
> -CONFIG_MPC86xx=y
> -CONFIG_HIGH_BATS=y
> -CONFIG_TARGET_SBC8641D=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_OF_STDOUT_VIA_ALIAS=y
> -CONFIG_BOOTDELAY=10
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_HUSH_PARSER=y
> -# CONFIG_AUTO_COMPLETE is not set
> -CONFIG_CMD_IMLS=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_PCI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_PING=y
> -CONFIG_MP=y
> -CONFIG_DOS_PARTITION=y
> -CONFIG_ENV_OVERWRITE=y
> -CONFIG_ENV_ADDR=0xFFF60000
> -# CONFIG_MMC is not set
> -CONFIG_MTD_NOR_FLASH=y
> -CONFIG_FLASH_CFI_DRIVER=y
> -CONFIG_SYS_FLASH_PROTECTION=y
> -CONFIG_SYS_FLASH_CFI=y
> -CONFIG_PHY_ATHEROS=y
> -CONFIG_PHY_BROADCOM=y
> -CONFIG_PHY_DAVICOM=y
> -CONFIG_PHY_LXT=y
> -CONFIG_PHY_MARVELL=y
> -CONFIG_PHY_NATSEMI=y
> -CONFIG_PHY_REALTEK=y
> -CONFIG_PHY_SMSC=y
> -CONFIG_PHY_VITESSE=y
> -CONFIG_TSEC_ENET=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OF_LIBFDT=y
> diff --git a/doc/git-mailrc b/doc/git-mailrc
> index f520ff89b390..b8299a1a6c30 100644
> --- a/doc/git-mailrc
> +++ b/doc/git-mailrc
> @@ -99,7 +99,6 @@ alias ppc powerpc
> alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@c-s.fr>
> alias mpc83xx uboot, mariosix
> alias mpc85xx uboot, afleming, priyankajain
> -alias mpc86xx uboot, afleming, priyankajain
>
> alias sandbox sjg
> alias sb sandbox
> diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
> index 890e62190b1a..e6a51f560978 100644
> --- a/drivers/ddr/fsl/Kconfig
> +++ b/drivers/ddr/fsl/Kconfig
> @@ -2,8 +2,8 @@ config SYS_FSL_DDR
> bool
> help
> Select Freescale General DDR driver, shared between most Freescale
> - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
> - based Layerscape SoCs (such as ls2080a).
> + PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
> + Layerscape SoCs (such as ls2080a).
>
> config SYS_FSL_MMDC
> bool
> @@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS
> ARCH_T4240
> default 2 if ARCH_B4860 || \
> ARCH_BSC9132 || \
> - ARCH_MPC8641 || \
> ARCH_P4080 || \
> ARCH_P5040 || \
> ARCH_LX2160A || \
> @@ -79,12 +78,6 @@ config SYS_FSL_DDRC_GEN2
> help
> Enable Freescale DDR2 controller.
>
> -config SYS_FSL_DDRC_86XX_GEN2
> - bool
> - depends on MPC86xx
> - help
> - Enable Freescale DDR2 controller for MPC86xx SoCs.
> -
> config SYS_FSL_DDRC_GEN3
> bool
> depends on PPC
> @@ -136,7 +129,6 @@ config SYS_FSL_DDR2
> bool "Freescale DDR2 controller"
> depends on SYS_FSL_HAS_DDR2
> select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
> - select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
>
> config SYS_FSL_DDR1
> bool "Freescale DDR1 controller"
> diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
> index c675f44ab00c..8081d0cd82f3 100644
> --- a/drivers/ddr/fsl/Makefile
> +++ b/drivers/ddr/fsl/Makefile
> @@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
> obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
> obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
> obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
> -obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
> obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
> obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
> obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
> diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c
> deleted file mode 100644
> index 43ed1ba432de..000000000000
> --- a/drivers/ddr/fsl/mpc86xx_ddr.c
> +++ /dev/null
> @@ -1,84 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Copyright 2008 Freescale Semiconductor, Inc.
> - */
> -
> -#include <common.h>
> -#include <log.h>
> -#include <asm/io.h>
> -#include <fsl_ddr_sdram.h>
> -#include <linux/delay.h>
> -
> -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
> -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
> -#endif
> -
> -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
> - unsigned int ctrl_num, int step)
> -{
> - unsigned int i;
> - struct ccsr_ddr __iomem *ddr;
> -
> - switch (ctrl_num) {
> - case 0:
> - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
> - break;
> - case 1:
> - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
> - break;
> - default:
> - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
> - return;
> - }
> -
> - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
> - if (i == 0) {
> - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
> - out_be32(&ddr->cs0_config, regs->cs[i].config);
> -
> - } else if (i == 1) {
> - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
> - out_be32(&ddr->cs1_config, regs->cs[i].config);
> -
> - } else if (i == 2) {
> - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
> - out_be32(&ddr->cs2_config, regs->cs[i].config);
> -
> - } else if (i == 3) {
> - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
> - out_be32(&ddr->cs3_config, regs->cs[i].config);
> - }
> - }
> -
> - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
> - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
> - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
> - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
> - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
> - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
> - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
> - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
> - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
> - out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
> - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
> - out_be32(&ddr->init_addr, regs->ddr_init_addr);
> - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
> -
> - debug("before go\n");
> -
> - /*
> - * 200 painful micro-seconds must elapse between
> - * the DDR clock setup and the DDR config enable.
> - */
> - udelay(200);
> - asm volatile("sync;isync");
> -
> - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
> -
> - /*
> - * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
> - */
> - while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
> - udelay(10000); /* throttle polling rate */
> - }
> -}
> diff --git a/env/Kconfig b/env/Kconfig
> index c06b8ba8cb7e..691f4d480cc4 100644
> --- a/env/Kconfig
> +++ b/env/Kconfig
> @@ -85,7 +85,7 @@ config ENV_IS_IN_FLASH
> default y if M548x || M547x || M5282
> default y if MCF532x || MCF52x2
> default y if MPC86xx || MPC83xx
> - default y if ARCH_MPC8548 || ARCH_MPC8641
> + default y if ARCH_MPC8548
> default y if SH && !CPU_SH4
> help
> Define this if you have a flash device which you want to use for the
> diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
> deleted file mode 100644
> index 3d5aee0dd58a..000000000000
> --- a/include/configs/sbc8641d.h
> +++ /dev/null
> @@ -1,509 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright 2007 Wind River Systems <www.windriver.com>
> - * Copyright 2007 Embedded Specialties, Inc.
> - * Joe Hamman <joe.hamman@embeddedspecialties.com>
> - *
> - * Copyright 2006 Freescale Semiconductor.
> - *
> - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com)
> - */
> -
> -/*
> - * SBC8641D board configuration file
> - *
> - * Make sure you change the MAC address and other network params first,
> - * search for CONFIG_SERVERIP, etc in this file.
> - */
> -
> -#ifndef __CONFIG_H
> -#define __CONFIG_H
> -
> -/* High Level Configuration Options */
> -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
> -
> -#ifdef RUN_DIAG
> -#define CONFIG_SYS_DIAG_ADDR 0xff800000
> -#endif
> -
> -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
> -
> -/*
> - * virtual address to be used for temporary mappings. There
> - * should be 128k free at this VA.
> - */
> -#define CONFIG_SYS_SCRATCH_VA 0xe8000000
> -
> -#define CONFIG_SYS_SRIO
> -#define CONFIG_SRIO1 /* SRIO port 1 */
> -
> -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
> -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
> -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
> -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
> -
> -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
> -
> -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
> -#undef CONFIG_DDR_ECC /* only for ECC DDR module */
> -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
> -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
> -#define CACHE_LINE_INTERLEAVING 0x20000000
> -#define PAGE_INTERLEAVING 0x21000000
> -#define BANK_INTERLEAVING 0x22000000
> -#define SUPER_BANK_INTERLEAVING 0x23000000
> -
> -#define CONFIG_ALTIVEC 1
> -
> -/*
> - * L2CR setup -- make sure this is right for your board!
> - */
> -#define CONFIG_SYS_L2
> -#define L2_INIT 0
> -#define L2_ENABLE (L2CR_L2E)
> -
> -#ifndef CONFIG_SYS_CLK_FREQ
> -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
> -#endif
> -
> -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
> -
> -/*
> - * Base addresses -- Note these are effective addresses where the
> - * actual resources get mapped (not physical addresses)
> - */
> -#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
> -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
> -
> -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
> -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
> -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
> -
> -/*
> - * DDR Setup
> - */
> -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
> -#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
> -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
> -#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
> -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
> -#define CONFIG_VERY_BIG_RAM
> -
> -#define CONFIG_DIMM_SLOTS_PER_CTLR 2
> -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
> -
> -#if defined(CONFIG_SPD_EEPROM)
> - /*
> - * Determine DDR configuration from I2C interface.
> - */
> - #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
> - #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
> - #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
> - #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
> -
> -#else
> - /*
> - * Manually set up DDR1 & DDR2 parameters
> - */
> -
> - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
> -
> - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
> - #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
> - #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
> - #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
> - #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
> - #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
> - #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
> - #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
> - #define CONFIG_SYS_DDR_TIMING_3 0x00000000
> - #define CONFIG_SYS_DDR_TIMING_0 0x00220802
> - #define CONFIG_SYS_DDR_TIMING_1 0x38377322
> - #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
> - #define CONFIG_SYS_DDR_CFG_1A 0x43008008
> - #define CONFIG_SYS_DDR_CFG_2 0x24401000
> - #define CONFIG_SYS_DDR_MODE_1 0x23c00542
> - #define CONFIG_SYS_DDR_MODE_2 0x00000000
> - #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
> - #define CONFIG_SYS_DDR_INTERVAL 0x05080100
> - #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
> - #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
> - #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
> -
> - #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
> - #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
> - #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
> - #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
> - #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
> - #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
> - #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
> - #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
> - #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
> - #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
> - #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
> - #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
> - #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
> - #define CONFIG_SYS_DDR2_CFG_2 0x24401000
> - #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
> - #define CONFIG_SYS_DDR2_MODE_2 0x00000000
> - #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
> - #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
> - #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
> - #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
> - #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
> -
> -#endif
> -
> -/* #define CONFIG_ID_EEPROM 1
> -#define ID_EEPROM_ADDR 0x57 */
> -
> -/*
> - * The SBC8641D contains 16MB flash space at ff000000.
> - */
> -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
> -
> -/* Flash */
> -#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
> -#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
> -
> -/* 64KB EEPROM */
> -#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
> -#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
> -
> -/* EPLD - User switches, board id, LEDs */
> -#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
> -#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
> -
> -/* Local bus SDRAM 128MB */
> -#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
> -#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
> -#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
> -#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
> -
> -/* Disk on Chip (DOC) 128MB */
> -#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
> -#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
> -
> -/* LCD */
> -#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
> -#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
> -
> -/* Control logic & misc peripherals */
> -#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
> -#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
> -
> -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
> -#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
> -
> -#undef CONFIG_SYS_FLASH_CHECKSUM
> -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
> -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
> -
> -#define CONFIG_SYS_WRITE_SWAPPED_DATA
> -#define CONFIG_SYS_FLASH_EMPTY_INFO
> -
> -#define CONFIG_SYS_INIT_RAM_LOCK 1
> -#ifndef CONFIG_SYS_INIT_RAM_LOCK
> -#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
> -#else
> -#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
> -#endif
> -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
> -
> -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
> -
> -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
> -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
> -
> -/* Serial Port */
> -#define CONFIG_SYS_NS16550_SERIAL
> -#define CONFIG_SYS_NS16550_REG_SIZE 1
> -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
> -
> -#define CONFIG_SYS_BAUDRATE_TABLE \
> - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
> -
> -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
> -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
> -
> -/*
> - * I2C
> - */
> -#define CONFIG_SYS_I2C
> -#define CONFIG_SYS_I2C_FSL
> -#define CONFIG_SYS_FSL_I2C_SPEED 400000
> -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
> -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
> -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
> -
> -/*
> - * RapidIO MMU
> - */
> -#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
> -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
> -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
> -
> -/*
> - * General PCI
> - * Addresses are mapped 1-1.
> - */
> -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
> -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
> -#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
> -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
> -#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
> -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
> -#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
> -#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
> -
> -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
> -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
> -#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
> -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
> -#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
> -#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
> -#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
> -#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
> -
> -#if defined(CONFIG_PCI)
> -
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -
> -
> -#if !defined(CONFIG_PCI_PNP)
> - #define PCI_ENET0_IOADDR 0xe0000000
> - #define PCI_ENET0_MEMADDR 0xe0000000
> - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
> -#endif
> -
> -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
> -
> -#ifdef CONFIG_SCSI_AHCI
> -#define CONFIG_SATA_ULI5288
> -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
> -#define CONFIG_SYS_SCSI_MAX_LUN 1
> -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
> -#endif
> -
> -#endif /* CONFIG_PCI */
> -
> -#if defined(CONFIG_TSEC_ENET)
> -#define CONFIG_TSEC1 1
> -#define CONFIG_TSEC1_NAME "eTSEC1"
> -#define CONFIG_TSEC2 1
> -#define CONFIG_TSEC2_NAME "eTSEC2"
> -#define CONFIG_TSEC3 1
> -#define CONFIG_TSEC3_NAME "eTSEC3"
> -#define CONFIG_TSEC4 1
> -#define CONFIG_TSEC4_NAME "eTSEC4"
> -
> -#define TSEC1_PHY_ADDR 0x1F
> -#define TSEC2_PHY_ADDR 0x00
> -#define TSEC3_PHY_ADDR 0x01
> -#define TSEC4_PHY_ADDR 0x02
> -#define TSEC1_PHYIDX 0
> -#define TSEC2_PHYIDX 0
> -#define TSEC3_PHYIDX 0
> -#define TSEC4_PHYIDX 0
> -#define TSEC1_FLAGS TSEC_GIGABIT
> -#define TSEC2_FLAGS TSEC_GIGABIT
> -#define TSEC3_FLAGS TSEC_GIGABIT
> -#define TSEC4_FLAGS TSEC_GIGABIT
> -
> -#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
> -
> -#define CONFIG_ETHPRIME "eTSEC1"
> -
> -#endif /* CONFIG_TSEC_ENET */
> -
> -/*
> - * BAT0 2G Cacheable, non-guarded
> - * 0x0000_0000 2G DDR
> - */
> -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
> -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
> -
> -/*
> - * BAT1 1G Cache-inhibited, guarded
> - * 0x8000_0000 512M PCI-Express 1 Memory
> - * 0xa000_0000 512M PCI-Express 2 Memory
> - * Changed it for operating from 0xd0000000
> - */
> -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
> - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
> -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
> -
> -/*
> - * BAT2 512M Cache-inhibited, guarded
> - * 0xc000_0000 512M RapidIO Memory
> - */
> -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
> - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
> -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
> -
> -/*
> - * BAT3 4M Cache-inhibited, guarded
> - * 0xf800_0000 4M CCSR
> - */
> -#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
> - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
> -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
> -
> -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
> -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
> - | BATL_PP_RW | BATL_CACHEINHIBIT \
> - | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
> - | BATU_BL_1M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
> - | BATL_PP_RW | BATL_CACHEINHIBIT)
> -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
> -#endif
> -
> -/*
> - * BAT4 32M Cache-inhibited, guarded
> - * 0xe200_0000 16M PCI-Express 1 I/O
> - * 0xe300_0000 16M PCI-Express 2 I/0
> - * Note that this is at 0xe0000000
> - */
> -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
> - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
> -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
> -
> -/*
> - * BAT5 128K Cacheable, non-guarded
> - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
> - */
> -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
> -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
> -
> -/*
> - * BAT6 32M Cache-inhibited, guarded
> - * 0xfe00_0000 32M FLASH
> - */
> -#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
> - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
> -
> -/* Map the last 1M of flash where we're running from reset */
> -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
> - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
> - | BATL_MEMCOHERENCE)
> -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
> -
> -#define CONFIG_SYS_DBAT7L 0x00000000
> -#define CONFIG_SYS_DBAT7U 0x00000000
> -#define CONFIG_SYS_IBAT7L 0x00000000
> -#define CONFIG_SYS_IBAT7U 0x00000000
> -
> -/*
> - * Environment
> - */
> -
> -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
> -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
> -
> -#undef CONFIG_WATCHDOG /* watchdog disabled */
> -
> -/*
> - * Miscellaneous configurable options
> - */
> -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
> -
> -/*
> - * For booting Linux, the board info and command line data
> - * have to be in the first 8 MB of memory, since this is
> - * the maximum mapped by the Linux kernel during initialization.
> - */
> -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
> -
> -/* Cache Configuration */
> -#define CONFIG_SYS_DCACHE_SIZE 32768
> -#define CONFIG_SYS_CACHELINE_SIZE 32
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
> -#endif
> -
> -#if defined(CONFIG_CMD_KGDB)
> -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
> -#endif
> -
> -/*
> - * Environment Configuration
> - */
> -
> -#define CONFIG_HAS_ETH0 1
> -#define CONFIG_HAS_ETH1 1
> -#define CONFIG_HAS_ETH2 1
> -#define CONFIG_HAS_ETH3 1
> -
> -#define CONFIG_IPADDR 192.168.0.50
> -
> -#define CONFIG_HOSTNAME "sbc8641d"
> -#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
> -#define CONFIG_BOOTFILE "uImage"
> -
> -#define CONFIG_SERVERIP 192.168.0.2
> -#define CONFIG_GATEWAYIP 192.168.0.1
> -#define CONFIG_NETMASK 255.255.255.0
> -
> -/* default location for tftp and bootm */
> -#define CONFIG_LOADADDR 1000000
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "netdev=eth0\0" \
> - "consoledev=ttyS0\0" \
> - "ramdiskaddr=2000000\0" \
> - "ramdiskfile=uRamdisk\0" \
> - "dtbaddr=400000\0" \
> - "dtbfile=sbc8641d.dtb\0" \
> - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
> - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
> - "maxcpus=1"
> -
> -#define CONFIG_NFSBOOTCOMMAND \
> - "setenv bootargs root=/dev/nfs rw " \
> - "nfsroot=$serverip:$rootpath " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $dtbaddr $dtbfile;" \
> - "bootm $loadaddr - $dtbaddr"
> -
> -#define CONFIG_RAMBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "tftp $ramdiskaddr $ramdiskfile;" \
> - "tftp $loadaddr $bootfile;" \
> - "tftp $dtbaddr $dtbfile;" \
> - "bootm $loadaddr $ramdiskaddr $dtbaddr"
> -
> -#define CONFIG_FLASHBOOTCOMMAND \
> - "setenv bootargs root=/dev/ram rw " \
> - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
> - "console=$consoledev,$baudrate $othbootargs;" \
> - "bootm ffd00000 ffb00000 ffa00000"
> -
> -#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
> -
> -#endif /* __CONFIG_H */
> diff --git a/include/post.h b/include/post.h
> index 5695e2b5334f..a07a6bc5e252 100644
> --- a/include/post.h
> +++ b/include/post.h
> @@ -29,11 +29,6 @@
> #include <asm/immap_85xx.h>
> #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
> offsetof(ccsr_pic_t, tfrr))
> -
> -#elif defined (CONFIG_MPC86xx)
> -#include <asm/immap_86xx.h>
> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
> - offsetof(ccsr_pic_t, tfrr))
> #endif
>
> #ifndef _POST_WORD_ADDR
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread* Re: [PATCH 21/27] ppc: Remove sbc8641d board
2021-05-15 1:34 ` [PATCH 21/27] ppc: Remove sbc8641d board Tom Rini
2021-05-15 15:20 ` Simon Glass
2021-05-15 19:15 ` Paul Gortmaker
@ 2021-07-08 2:53 ` Tom Rini
2 siblings, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:53 UTC (permalink / raw)
To: u-boot; +Cc: Paul Gortmaker, Priyanka Jain
[-- Attachment #1: Type: text/plain, Size: 534 bytes --]
On Fri, May 14, 2021 at 09:34:26PM -0400, Tom Rini wrote:
> This board has not been converted to CONFIG_DM_PCI by the deadline and is
> also missing conversion to CONFIG_DM. Remove it. This is also the last
> of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
>
> Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
> Cc: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH 22/27] ppc: Remove MPC8315ERDB board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (19 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 21/27] ppc: Remove sbc8641d board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:53 ` Tom Rini
2021-05-15 1:34 ` [PATCH 23/27] ppc: Remove MPC8323ERDB board Tom Rini
` (5 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_MPC8315 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 14 -
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 3 +-
arch/powerpc/cpu/mpc83xx/speed.c | 41 +-
arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 3 +-
arch/powerpc/include/asm/global_data.h | 5 +-
arch/powerpc/include/asm/immap_83xx.h | 45 ---
arch/powerpc/include/asm/mpc8xxx_spi.h | 1 -
board/freescale/mpc8315erdb/Kconfig | 12 -
board/freescale/mpc8315erdb/MAINTAINERS | 7 -
board/freescale/mpc8315erdb/Makefile | 6 -
board/freescale/mpc8315erdb/README | 105 ------
board/freescale/mpc8315erdb/mpc8315erdb.c | 249 -------------
board/freescale/mpc8315erdb/sdram.c | 115 ------
configs/MPC8315ERDB_defconfig | 156 --------
include/configs/MPC8315ERDB.h | 370 -------------------
include/mpc83xx.h | 39 +-
16 files changed, 11 insertions(+), 1160 deletions(-)
delete mode 100644 board/freescale/mpc8315erdb/Kconfig
delete mode 100644 board/freescale/mpc8315erdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8315erdb/Makefile
delete mode 100644 board/freescale/mpc8315erdb/README
delete mode 100644 board/freescale/mpc8315erdb/mpc8315erdb.c
delete mode 100644 board/freescale/mpc8315erdb/sdram.c
delete mode 100644 configs/MPC8315ERDB_defconfig
delete mode 100644 include/configs/MPC8315ERDB.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index a67216a2f460..d1b774f8d55f 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -8,11 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_MPC8315ERDB
- bool "Support MPC8315ERDB"
- select ARCH_MPC8315
- select BOARD_EARLY_INIT_F
-
config TARGET_MPC8323ERDB
bool "Support MPC8323ERDB"
select ARCH_MPC832X
@@ -175,14 +170,6 @@ config ARCH_MPC8313
select MPC83XX_SECOND_I2C_SUPPORT
select FSL_ELBC
-config ARCH_MPC8315
- bool
- select ARCH_MPC831X
- select MPC83XX_PCIE1_SUPPORT
- select MPC83XX_PCIE2_SUPPORT
- select MPC83XX_SATA_SUPPORT
- select FSL_ELBC
-
config ARCH_MPC832X
bool
select MPC83XX_QUICC_ENGINE
@@ -265,7 +252,6 @@ endmenu
config FSL_ELBC
bool
-source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index c657a47b1143..75ec9c9a3464 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -19,7 +19,7 @@ config DDR_MC_CLOCK_MODE_1_2
bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1
- depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
+ depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X
bool "1 : 1"
endchoice
@@ -143,7 +143,6 @@ config CORE_PLL_VCO_DIVIDER_4
bool "4"
config CORE_PLL_VCO_DIVIDER_8
- depends on !ARCH_MPC8315
bool "8"
endchoice
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 58e197f12082..e5db96b328d5 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -104,9 +104,6 @@ int get_clocks(void)
#if !defined(CONFIG_ARCH_MPC832X)
u32 i2c2_clk;
#endif
-#if defined(CONFIG_ARCH_MPC8315)
- u32 tdm_clk;
-#endif
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
@@ -130,7 +127,7 @@ int get_clocks(void)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
-#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X)
u32 sata_clk;
#endif
@@ -200,8 +197,8 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
- defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
+ defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@@ -294,25 +291,6 @@ int get_clocks(void)
return -8;
}
#endif
-#if defined(CONFIG_ARCH_MPC8315)
- switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
- case 0:
- tdm_clk = 0;
- break;
- case 1:
- tdm_clk = csb_clk;
- break;
- case 2:
- tdm_clk = csb_clk / 2;
- break;
- case 3:
- tdm_clk = csb_clk / 3;
- break;
- default:
- /* unknown SCCR_TDMCM value */
- return -8;
- }
-#endif
#if defined(CONFIG_ARCH_MPC834X)
i2c1_clk = tsec2_clk;
@@ -372,7 +350,7 @@ int get_clocks(void)
}
#endif
-#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
@@ -462,9 +440,6 @@ int get_clocks(void)
#if defined(CONFIG_ARCH_MPC834X)
gd->arch.usbmph_clk = usbmph_clk;
#endif
-#if defined(CONFIG_ARCH_MPC8315)
- gd->arch.tdm_clk = tdm_clk;
-#endif
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = sdhc_clk;
#endif
@@ -491,7 +466,7 @@ int get_clocks(void)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
-#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X)
gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
@@ -559,10 +534,6 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" I2C2: %-4s MHz\n",
strmhz(buf, gd->arch.i2c2_clk));
#endif
-#if defined(CONFIG_ARCH_MPC8315)
- printf(" TDM: %-4s MHz\n",
- strmhz(buf, gd->arch.tdm_clk));
-#endif
#if defined(CONFIG_FSL_ESDHC)
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
@@ -590,7 +561,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
#endif
-#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC837X)
printf(" SATA: %-4s MHz\n",
strmhz(buf, gd->arch.sata_clk));
#endif
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index 8a6896e6229c..b7406751838a 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -6,8 +6,7 @@
/*
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
*/
-#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
- defined(CONFIG_ARCH_MPC8315)
+#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308)
#define MPC83XX_GPIO_CTRLRS 1
#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \
defined(CONFIG_ARCH_MPC8309)
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 192a02d347e7..5c3de48cc808 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -45,9 +45,6 @@ struct arch_global_data {
# if defined(CONFIG_ARCH_MPC834X)
u32 usbmph_clk;
# endif /* CONFIG_ARCH_MPC834X */
-# if defined(CONFIG_ARCH_MPC8315)
- u32 tdm_clk;
-# endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
@@ -57,7 +54,7 @@ struct arch_global_data {
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
-# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+# if defined(CONFIG_ARCH_MPC837X)
u32 sata_clk;
# endif
# if defined(CONFIG_ARCH_MPC8360)
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index a03f938d9f49..d2443dc90d50 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -714,51 +714,6 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
-#elif defined(CONFIG_ARCH_MPC8315)
-typedef struct immap {
- sysconf83xx_t sysconf; /* System configuration */
- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk83xx_t rtc; /* Real Time Clock Module Registers */
- rtclk83xx_t pit; /* Periodic Interval Timer */
- gtm83xx_t gtm[2]; /* Global Timers Module */
- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter83xx_t arbiter; /* System Arbiter Registers */
- reset83xx_t reset; /* Reset Module */
- clk83xx_t clk; /* System Clock Module */
- pmc83xx_t pmc; /* Power Management Control Module */
- gpio83xx_t gpio[1]; /* General purpose I/O module */
- u8 res0[0x1300];
- ddr83xx_t ddr; /* DDR Memory Controller Memory */
- fsl_i2c_t i2c[1]; /* I2C Controllers */
- u8 res1[0x1400];
- duart83xx_t duart[2]; /* DUART */
- u8 res2[0x900];
- fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
- u8 res3[0x1000];
- spi8xxx_t spi; /* Serial Peripheral Interface */
- dma83xx_t dma; /* DMA */
- pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
- u8 res4[0x80];
- ios83xx_t ios; /* Sequencer */
- pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
- u8 res5[0xa00];
- pex83xx_t pciexp[2]; /* PCI Express Controller */
- u8 res6[0xb000];
- tdm83xx_t tdm; /* TDM Controller */
- u8 res7[0x1e00];
- sata83xx_t sata[2]; /* SATA Controller */
- u8 res8[0x9000];
- usb83xx_t usb[1]; /* USB DR Controller */
- tsec83xx_t tsec[2];
- u8 res9[0x6000];
- tdmdmac83xx_t tdmdmac; /* TDM DMAC */
- u8 res10[0x2000];
- security83xx_t security;
- u8 res11[0xA3000];
- serdes83xx_t serdes[1]; /* SerDes Registers */
- u8 res12[0x1CF00];
-} immap_t;
-
#elif defined(CONFIG_ARCH_MPC8308)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 470ee955f303..f2210a14aeae 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -13,7 +13,6 @@
#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC8309) || \
defined(CONFIG_ARCH_MPC8313) || \
- defined(CONFIG_ARCH_MPC8315) || \
defined(CONFIG_ARCH_MPC834X) || \
defined(CONFIG_ARCH_MPC837X)
diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
deleted file mode 100644
index f76b0d1d6dbc..000000000000
--- a/board/freescale/mpc8315erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8315ERDB
-
-config SYS_BOARD
- default "mpc8315erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8315ERDB"
-
-endif
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
deleted file mode 100644
index cdac1ac2eed4..000000000000
--- a/board/freescale/mpc8315erdb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8315ERDB BOARD
-#M: Dave Liu <daveliu@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/mpc8315erdb/
-F: include/configs/MPC8315ERDB.h
-F: configs/MPC8315ERDB_defconfig
-F: configs/MPC8315ERDB_NANDSPL_defconfig
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
deleted file mode 100644
index 579181999d42..000000000000
--- a/board/freescale/mpc8315erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
deleted file mode 100644
index 8ad6d810c79e..000000000000
--- a/board/freescale/mpc8315erdb/README
+++ /dev/null
@@ -1,105 +0,0 @@
-Freescale MPC8315ERDB Board
------------------------------------------
-
-1. Board Switches and Jumpers
-
- S3 is used to set CONFIG_SYS_RESET_SOURCE.
-
- To boot the image at 0xFE000000 in NOR flash, use these DIP
- switch settings for S3 S4:
-
- +------+ +------+
- | | | **** |
- | **** | | |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- To boot the image at the beginning of NAND flash, use these
- DIP switch settings for S3 S4:
-
- +------+ +------+
- | * | | *** |
- | *** | | * |
- +------+ ON +------+ ON
- 4321 4321
- (where the '*' indicates the position of the tab of the switch.)
-
- When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
-
-2. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x07ff_ffff DDR 128M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
- 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
-
- When booting from NAND, NAND flash is CS0 and NOR flash
- is CS1.
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8315ERDB.h
-
- CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC831x MPC831x specific
- CONFIG_MPC8315 MPC8315 specific
- CONFIG_MPC8315ERDB MPC8315ERDB board specific
-
-4. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
- make all
-
-5. Downloading and Flashing Images
-
-5.1 Reflash U-Boot Image using U-Boot
-
- NOR flash:
-
- tftp 40000 u-boot.bin
- protect off all
- erase fe000000 fe1fffff
-
- cp.b 40000 fe000000 xxxx
- protect on all
-
- You have to supply the correct byte count with 'xxxx'
- from the TFTP result log.
-
- NAND flash:
-
- =>tftpboot $loadaddr <filename>
- =>nand erase 0 0x80000
- =>nand write $loadaddr 0 0x80000
-
- ...where 0x80000 is the filesize rounded up to
- the next 0x20000 increment.
-
-5.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, rootpath (if using NFS root),
- fdtfile, and bootfile).
-
- Then, do one of the following, depending on whether you
- want an NFS root or a ramdisk root:
-
- =>run nfsboot
- or
- =>run ramboot
-
-6 Notes
-
- The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
deleted file mode 100644
index e89d5d495595..000000000000
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ /dev/null
@@ -1,249 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Author: Scott Wood <scottwood@freescale.com>
- * Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- gd->flags |= GD_FLG_SILENT;
-
- return 0;
-}
-
-#ifndef CONFIG_NAND_SPL
-
-static u8 read_board_info(void)
-{
- u8 val8;
- i2c_set_bus_num(0);
-
- if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
- return val8;
- else
- return 0;
-}
-
-int checkboard(void)
-{
- static const char * const rev_str[] = {
- "0.0",
- "0.1",
- "1.0",
- "1.1",
- "<unknown>",
- };
- u8 info;
- int i;
-
- info = read_board_info();
- i = (!info) ? 4: info & 0x03;
-
- printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
-
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI_MEM_BASE,
- phys_start: CONFIG_SYS_PCI_MEM_PHYS,
- size: CONFIG_SYS_PCI_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
- size: CONFIG_SYS_PCI_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI_IO_BASE,
- phys_start: CONFIG_SYS_PCI_IO_PHYS,
- size: CONFIG_SYS_PCI_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-static struct pci_region pcie_regions_0[] = {
- {
- .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
- .size = CONFIG_SYS_PCIE1_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
- .size = CONFIG_SYS_PCIE1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-static struct pci_region pcie_regions_1[] = {
- {
- .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
- .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
- .size = CONFIG_SYS_PCIE2_MEM_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
- .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
- .size = CONFIG_SYS_PCIE2_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile sysconf83xx_t *sysconf = &immr->sysconf;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile law83xx_t *pcie_law = sysconf->pcielaw;
- struct pci_region *reg[] = { pci_regions };
- struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-
- /* Configure the clock for PCIE controller */
- clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
- SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
- /* Deassert the resets in the control register */
- out_be32(&sysconf->pecr1, 0xE0008000);
- out_be32(&sysconf->pecr2, 0xE0008000);
- udelay(2000);
-
- /* Configure PCI Express Local Access Windows */
- out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
- out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
- mpc83xx_pcie_init(2, pcie_reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
-{
- const char disabled[] = "disabled";
- const char *path;
- int ret;
-
- if (hwconfig_arg_cmp("board_type", "tsec1")) {
- return;
- } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
- printf("NOTICE: No or unknown board_type hwconfig specified.\n"
- " Assuming board with TSEC1.\n");
- return;
- }
-
- ret = fdt_path_offset(fdt, "/aliases");
- if (ret < 0) {
- printf("WARNING: can't find /aliases node\n");
- return;
- }
-
- path = fdt_getprop(fdt, ret, "ethernet0", NULL);
- if (!path) {
- printf("WARNING: can't find ethernet0 alias\n");
- return;
- }
-
- do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- fsl_fdt_fixup_dr_usb(blob, bd);
- fdt_tsec1_fixup(blob, bd);
-
- return 0;
-}
-#endif
-
-int board_eth_init(struct bd_info *bis)
-{
- cpu_eth_init(bis); /* Initialize TSECs first */
- return pci_eth_init(bis);
-}
-
-#else /* CONFIG_NAND_SPL */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8315ERDB\n");
- return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
- board_early_init_f();
- ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
- puts("NAND boot... ");
- timer_init();
- dram_init();
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (gd->flags & GD_FLG_SILENT)
- return;
-
- if (c == '\n')
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
- ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-
-#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
deleted file mode 100644
index ffbb79aaec14..000000000000
--- a/board/freescale/mpc8315erdb/sdram.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Authors: Nick.Spence at freescale.com
- * Wilson.Lo at freescale.com
- * scottwood at freescale.com
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/bitops.h>
-#include <asm/io.h>
-
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void resume_from_sleep(void)
-{
- u32 magic = *(u32 *)0;
-
- typedef void (*func_t)(void);
- func_t resume = *(func_t *)4;
-
- if (magic == 0xf5153ae5)
- resume();
-
- gd->flags &= ~GD_FLG_SILENT;
- puts("\nResume from sleep failed: bad magic word\n");
-}
-
-/* Fixed sdram init -- doesn't use serial presence detect.
- *
- * This is useful for faster booting in configs where the RAM is unlikely
- * to be changed, or for things like NAND booting where space is tight.
- */
-#ifndef CONFIG_SYS_RAMBOOT
-static long fixed_sdram(void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
- u32 msize_log2 = __ilog2(msize);
-
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
-
- /*
- * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
- * or the DDR2 controller may fail to initialize correctly.
- */
- __udelay(50000);
-
- im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
-
- /* Currently we use only one CS, so disable the other bank. */
- im->ddr.cs_config[1] = 0;
-
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
- else
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- sync();
-
- /* enable DDR controller */
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- sync();
-
- return msize;
-}
-#else
-static long fixed_sdram(void)
-{
- return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-int dram_init(void)
-{
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- u32 msize;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -ENXIO;
-
- /* DDR SDRAM */
- msize = fixed_sdram();
-
- if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
- resume_from_sleep();
-
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize;
-
- return 0;
-}
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
deleted file mode 100644
index fa22196526c0..000000000000
--- a/configs/MPC8315ERDB_defconfig
+++ /dev/null
@@ -1,156 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8315ERDB=y
-CONFIG_SYSTEM_PLL_VCO_DIV_2=y
-CONFIG_CORE_PLL_RATIO_3_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_128_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMRBAR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_8_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="FLASH"
-CONFIG_BAT2_BASE=0xFE000000
-CONFIG_BAT2_LENGTH_32_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="STACK_IN_DCACHE"
-CONFIG_BAT3_BASE=0xE6000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="PCI_MEM_PHYS"
-CONFIG_BAT4_BASE=0x80000000
-CONFIG_BAT4_LENGTH_256_MBYTES=y
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT4_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="PCI_MMIO_PHYS"
-CONFIG_BAT5_BASE=0x90000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_1=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=e0600000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m at 1m(kernel),-(fs)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_EEPRO100=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
deleted file mode 100644
index 688aa5ea9867..000000000000
--- a/include/configs/MPC8315ERDB.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
-
-#define CONFIG_HWCONFIG
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
- | DDRCDR_PZ_LOZ \
- | DDRCDR_NZ_LOZ \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of two chips HY5PS12621BFP-C4 from HYNIX
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ODT_RD_NEVER \
- | CSCONFIG_ODT_WR_ONLY_CURRENT \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (6 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x27256222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (4 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x121048c5 */
-#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03600100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_DBW_32)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* ODT 150ohm CL=3, AL=1 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2 0x00000000
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-/* 127 64KB sectors and 8 8KB top sectors per device */
-#define CONFIG_SYS_MAX_FLASH_SECT 135
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-/*
- * NAND Flash on the Local Bus
- */
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE0600000
-#endif
-
-#define CONFIG_MTD_PARTITION
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
-#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-
-
-
-/* Still needed for spl_minimal.c */
-#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
-#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
- !defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Board info - revision and where boot from
- */
-#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-#define CONFIG_SYS_PCIE1_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
-
-#define CONFIG_SYS_PCIE2_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
-#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#define CONFIG_HAS_FSL_DR_USB
-#define CONFIG_SYS_SCCR_USBDRCM 3
-
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_USB_PHY_TYPE "utmi"
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
-/*
- * TSEC
- */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME "eTSEC1"
-
-/*
- * SATA
- */
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1_OFFSET 0x18000
-#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2_OFFSET 0x19000
-#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#ifdef CONFIG_FSL_SATA
-#define CONFIG_LBA48
-#endif
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-/*
- * MMU Setup
- */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc8315erdb.dtb\0" \
- "usb_phy_type=utmi\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index ea67868ea012..71cffa1b0fc8 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -243,41 +243,6 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_ARCH_MPC8315)
-/* SICRL bits - MPC8315 specific */
-#define SICRL_DMA_CH0 0xc0000000
-#define SICRL_DMA_SPI 0x30000000
-#define SICRL_UART 0x0c000000
-#define SICRL_IRQ4 0x02000000
-#define SICRL_IRQ5 0x01800000
-#define SICRL_IRQ6_7 0x00400000
-#define SICRL_IIC1 0x00300000
-#define SICRL_TDM 0x000c0000
-#define SICRL_TDM_SHARED 0x00030000
-#define SICRL_PCI_A 0x0000c000
-#define SICRL_ELBC_A 0x00003000
-#define SICRL_ETSEC1_A 0x000000c0
-#define SICRL_ETSEC1_B 0x00000030
-#define SICRL_ETSEC1_C 0x0000000c
-#define SICRL_TSEXPOBI 0x00000001
-
-/* SICRH bits - MPC8315 specific */
-#define SICRH_GPIO_0 0xc0000000
-#define SICRH_GPIO_1 0x30000000
-#define SICRH_GPIO_2 0x0c000000
-#define SICRH_GPIO_3 0x03000000
-#define SICRH_GPIO_4 0x00c00000
-#define SICRH_GPIO_5 0x00300000
-#define SICRH_GPIO_6 0x000c0000
-#define SICRH_GPIO_7 0x00030000
-#define SICRH_GPIO_8 0x0000c000
-#define SICRH_GPIO_9 0x00003000
-#define SICRH_GPIO_10 0x00000c00
-#define SICRH_GPIO_11 0x00000300
-#define SICRH_ETSEC2_A 0x000000c0
-#define SICRH_TSOBI1 0x00000002
-#define SICRH_TSOBI2 0x00000001
-
#elif defined(CONFIG_ARCH_MPC837X)
/* SICRL bits - MPC837X specific */
#define SICRL_USB_A 0xC0000000
@@ -634,7 +599,7 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
@@ -981,7 +946,7 @@
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
+#elif defined(CONFIG_ARCH_MPC8308)
/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 23/27] ppc: Remove MPC8323ERDB board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (20 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 22/27] ppc: Remove MPC8315ERDB board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:53 ` Tom Rini
2021-05-15 1:34 ` [PATCH 24/27] ppc: Remove MPC832XEMDS boards Tom Rini
` (4 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 5 -
board/freescale/mpc8323erdb/Kconfig | 12 -
board/freescale/mpc8323erdb/MAINTAINERS | 6 -
board/freescale/mpc8323erdb/Makefile | 6 -
board/freescale/mpc8323erdb/README | 71 -----
board/freescale/mpc8323erdb/mpc8323erdb.c | 233 ----------------
configs/MPC8323ERDB_defconfig | 115 --------
include/configs/MPC8323ERDB.h | 309 ----------------------
8 files changed, 757 deletions(-)
delete mode 100644 board/freescale/mpc8323erdb/Kconfig
delete mode 100644 board/freescale/mpc8323erdb/MAINTAINERS
delete mode 100644 board/freescale/mpc8323erdb/Makefile
delete mode 100644 board/freescale/mpc8323erdb/README
delete mode 100644 board/freescale/mpc8323erdb/mpc8323erdb.c
delete mode 100644 configs/MPC8323ERDB_defconfig
delete mode 100644 include/configs/MPC8323ERDB.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index d1b774f8d55f..8ae6d080c8a9 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -8,10 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_MPC8323ERDB
- bool "Support MPC8323ERDB"
- select ARCH_MPC832X
-
config TARGET_MPC832XEMDS
bool "Support MPC832XEMDS"
select ARCH_MPC832X
@@ -252,7 +248,6 @@ endmenu
config FSL_ELBC
bool
-source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
deleted file mode 100644
index acf812219662..000000000000
--- a/board/freescale/mpc8323erdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8323ERDB
-
-config SYS_BOARD
- default "mpc8323erdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8323ERDB"
-
-endif
diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS
deleted file mode 100644
index 496ab2af271f..000000000000
--- a/board/freescale/mpc8323erdb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8323ERDB BOARD
-#M: Michael Barkowski <michael.barkowski@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/mpc8323erdb/
-F: include/configs/MPC8323ERDB.h
-F: configs/MPC8323ERDB_defconfig
diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
deleted file mode 100644
index e6f61891d9c1..000000000000
--- a/board/freescale/mpc8323erdb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y := mpc8323erdb.o
diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
deleted file mode 100644
index 9a46da078187..000000000000
--- a/board/freescale/mpc8323erdb/README
+++ /dev/null
@@ -1,71 +0,0 @@
-Freescale MPC8323ERDB Board
------------------------------------------
-
-1. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x03ff_ffff DDR 64M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xd000_0000 0xd3ff_ffff PCI IO 64M
- 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M
-
-2. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make MPC8323ERDB_config
- make
-
-3. Downloading and Flashing Images
-
-3.1 Reflash U-Boot Image using U-Boot
-
- N.b, have an alternate means of programming
- the flash available if the new U-Boot doesn't boot.
-
- First try a:
-
- tftpboot $loadaddr $uboot
-
- to make sure that the TFTP load will succeed before
- an erase goes ahead and wipes out your current firmware.
- Then do a:
-
- run tftpflash
-
- which is a shorter version of the manual sequence:
-
- tftp $loadaddr u-boot.bin
- protect off fe000000 +$filesize
- erase fe000000 +$filesize
- cp.b $loadaddr fe000000 $filesize
-
- To keep your old U-Boot's environment variables, do a:
-
- saveenv
-
- prior to resetting the board.
-
-3.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, rootpath (if using NFS root),
- fdtfile, and bootfile).
-
- Then, do one of the following, depending on whether you
- want an NFS root or a ramdisk root:
-
- run nfsboot
-
- or
-
- run ramboot
-
-4 Notes
-
- The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
deleted file mode 100644
index cef3216a6fe5..000000000000
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * Michael Barkowski <michael.barkowski@freescale.com>
- * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <eeprom.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <u-boot/crc.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* UCC3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
-
- /* UCC2 */
- {0, 18, 1, 0, 1}, /* TxD0 */
- {0, 19, 1, 0, 1}, /* TxD1 */
- {0, 20, 1, 0, 1}, /* TxD2 */
- {0, 21, 1, 0, 1}, /* TxD3 */
- {0, 27, 1, 0, 1}, /* TxER */
- {0, 30, 1, 0, 1}, /* TxEN */
- {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
-
- {0, 22, 2, 0, 1}, /* RxD0 */
- {0, 23, 2, 0, 1}, /* RxD1 */
- {0, 24, 2, 0, 1}, /* RxD2 */
- {0, 25, 2, 0, 1}, /* RxD3 */
- {0, 26, 1, 0, 1}, /* RxER */
- {0, 28, 2, 0, 1}, /* Rx_DV */
- {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
- {0, 29, 2, 0, 1}, /* COL */
- {0, 31, 2, 0, 1}, /* CRS */
-
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int fixed_sdram(void);
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -ENXIO;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
- msize = fixed_sdram();
-
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__ ("sync");
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- __asm__ __volatile__ ("sync");
- return msize;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8323ERDB\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
-int mac_read_from_eeprom(void)
-{
- uchar buf[28];
- char str[18];
- int i = 0;
- unsigned int crc = 0;
- unsigned char enetvar[32];
-
- /* Read MAC addresses from EEPROM */
- if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
- printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
- } else {
- uint32_t crc_buf;
-
- memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
-
- if (crc32(crc, buf, 24) == crc_buf) {
- printf("Reading MAC from EEPROM\n");
- for (i = 0; i < 4; i++) {
- if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
- sprintf(str,
- "%02X:%02X:%02X:%02X:%02X:%02X",
- buf[i * 6], buf[i * 6 + 1],
- buf[i * 6 + 2], buf[i * 6 + 3],
- buf[i * 6 + 4], buf[i * 6 + 5]);
- sprintf((char *)enetvar,
- i ? "eth%daddr" : "ethaddr", i);
- env_set((char *)enetvar, str);
- }
- }
- }
- }
- return 0;
-}
-#endif /* CONFIG_I2C_MAC_OFFSET */
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
deleted file mode 100644
index 1c85e6081401..000000000000
--- a/configs/MPC8323ERDB_defconfig
+++ /dev/null
@@ -1,115 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66666667
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC8323ERDB=y
-CONFIG_CORE_PLL_RATIO_25_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="FLASH"
-CONFIG_BAT2_BASE=0xFE000000
-CONFIG_BAT2_LENGTH_32_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT4=y
-CONFIG_BAT4_NAME="STACK_IN_DCACHE"
-CONFIG_BAT4_BASE=0xE6000000
-CONFIG_BAT4_ACCESS_RW=y
-CONFIG_BAT4_USER_MODE_VALID=y
-CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="PCI_MEM_PHYS"
-CONFIG_BAT5_BASE=0x80000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT5_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT6_BASE=0x90000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_INHIBITED=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_INHIBITED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_OPT_SPEC_READ=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
deleted file mode 100644
index 6effaeaa981d..000000000000
--- a/include/configs/MPC8323ERDB.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 64 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_9)
- /* 0x80010101 */
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (3 << TIMING_CFG1_REFREC_SHIFT) \
- | (2 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x26253222 */
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (31 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x1f9048c7 */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* 0x44480232 */
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board EEPROM
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
-#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_SKIP_HOST_BRIDGE
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 4
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-#define CONFIG_UEC_ETH2 /* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if (CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
-#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
-
-/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
- * (see CONFIG_SYS_I2C_EEPROM) */
- /* MAC address offset in I2C EEPROM */
-#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME "mpc8323erdb"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot.bin"
-#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
-#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftp $loadaddr $uboot;" \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=780000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
- "$netdev:off "\
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 24/27] ppc: Remove MPC832XEMDS boards
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (21 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 23/27] ppc: Remove MPC8323ERDB board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:53 ` Tom Rini
2021-05-15 1:34 ` [PATCH 25/27] ppc: Remove T4160RDB board Tom Rini
` (3 subsequent siblings)
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc83xx/Kconfig | 6 -
board/freescale/common/pq-mds-pib.c | 29 ---
board/freescale/mpc832xemds/Kconfig | 12 -
board/freescale/mpc832xemds/MAINTAINERS | 10 -
board/freescale/mpc832xemds/Makefile | 7 -
board/freescale/mpc832xemds/README | 128 ---------
board/freescale/mpc832xemds/mpc832xemds.c | 173 -------------
board/freescale/mpc832xemds/pci.c | 145 -----------
configs/MPC832XEMDS_ATM_defconfig | 141 ----------
configs/MPC832XEMDS_HOST_33_defconfig | 161 ------------
configs/MPC832XEMDS_HOST_66_defconfig | 161 ------------
configs/MPC832XEMDS_SLAVE_defconfig | 158 -----------
configs/MPC832XEMDS_defconfig | 140 ----------
include/configs/MPC832XEMDS.h | 302 ----------------------
14 files changed, 1573 deletions(-)
delete mode 100644 board/freescale/mpc832xemds/Kconfig
delete mode 100644 board/freescale/mpc832xemds/MAINTAINERS
delete mode 100644 board/freescale/mpc832xemds/Makefile
delete mode 100644 board/freescale/mpc832xemds/README
delete mode 100644 board/freescale/mpc832xemds/mpc832xemds.c
delete mode 100644 board/freescale/mpc832xemds/pci.c
delete mode 100644 configs/MPC832XEMDS_ATM_defconfig
delete mode 100644 configs/MPC832XEMDS_HOST_33_defconfig
delete mode 100644 configs/MPC832XEMDS_HOST_66_defconfig
delete mode 100644 configs/MPC832XEMDS_SLAVE_defconfig
delete mode 100644 configs/MPC832XEMDS_defconfig
delete mode 100644 include/configs/MPC832XEMDS.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 8ae6d080c8a9..1d5704848aee 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -8,11 +8,6 @@ choice
prompt "Target select"
optional
-config TARGET_MPC832XEMDS
- bool "Support MPC832XEMDS"
- select ARCH_MPC832X
- select BOARD_EARLY_INIT_F
-
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
select ARCH_MPC8349
@@ -248,7 +243,6 @@ endmenu
config FSL_ELBC
bool
-source "board/freescale/mpc832xemds/Kconfig"
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig"
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 596cd0018c53..162c8a954f07 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -36,11 +36,7 @@ int pib_init(void)
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(CONFIG_TARGET_MPC832XEMDS)
- val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
-#else
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
-#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
@@ -55,34 +51,9 @@ int pib_init(void)
eieio();
-#if defined(CONFIG_TARGET_MPC832XEMDS)
- printf("PCI 32bit bus on PMC2 &PMC3\n");
-#else
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
#endif
-#endif
-
-#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_TARGET_MPC832XEMDS)
- val8 = 0;
- i2c_write(0x26, 0x7, 1, &val8, 1);
- val8 = 0xf7;
- i2c_write(0x26, 0x3, 1, &val8, 1);
-
- val8 = 0;
- i2c_write(0x21, 0x6, 1, &val8, 1);
- i2c_write(0x21, 0x7, 1, &val8, 1);
-
- val8 = 0xdf;
- i2c_write(0x21, 0x2, 1, &val8, 1);
- val8 = 0xef;
- i2c_write(0x21, 0x3, 1, &val8, 1);
- eieio();
-
- printf("QOC3 ATM card on PMC1\n");
-#endif
-#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
return 0;
diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
deleted file mode 100644
index e4cfa15a6f23..000000000000
--- a/board/freescale/mpc832xemds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC832XEMDS
-
-config SYS_BOARD
- default "mpc832xemds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC832XEMDS"
-
-endif
diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS
deleted file mode 100644
index 232658a203c2..000000000000
--- a/board/freescale/mpc832xemds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-MPC832XEMDS BOARD
-#M: Dave Liu <daveliu@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/mpc832xemds/
-F: include/configs/MPC832XEMDS.h
-F: configs/MPC832XEMDS_defconfig
-F: configs/MPC832XEMDS_ATM_defconfig
-F: configs/MPC832XEMDS_HOST_33_defconfig
-F: configs/MPC832XEMDS_HOST_66_defconfig
-F: configs/MPC832XEMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
deleted file mode 100644
index b1551bf47863..000000000000
--- a/board/freescale/mpc832xemds/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y += mpc832xemds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
deleted file mode 100644
index d141cd33e782..000000000000
--- a/board/freescale/mpc832xemds/README
+++ /dev/null
@@ -1,128 +0,0 @@
-Freescale MPC832XEMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW3 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labeled 8 on Switch 4.
- SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
- SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
- SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 For the MPC832XEMDS PROTO Board
-
- First, make sure the board default setting is consistent with the document
- shipped with your board. Then apply the following setting:
- SW3[1-8]= 0000_1000 (core PLL setting, core enable)
- SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
- SW5[1-8]= 0010_0110 (Boot from high end)
- SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
- SW7[1-8]= 1000_0011 (QE PLL setting)
-
- ENET3/4 MII mode settings:
- J1 1-2 (ETH3_TXER)
- J2 2-3 (MII mode)
- J3 2-3 (MII mode)
- J4 2-3 (ADSL clockOscillator)
- J5 1-2 (ETH4_TXER)
- J6 2-3 (ClockOscillator)
- JP1 removed (don't force PORESET)
- JP2 mounted (ETH4/2 MII)
- JP3 mounted (ETH3 MII)
- JP4 mounted (HRCW from BCSR)
-
- ENET3/4 RMII mode settings:
- J1 1-2 (ETH3_TXER)
- J2 1-2 (RMII mode)
- J3 1-2 (RMII mode)
- J4 2-3 (ADSL clockOscillator)
- J5 1-2 (ETH4_TXER)
- J6 2-3 (ClockOscillator)
- JP1 removed (don't force PORESET)
- JP2 removed (ETH4/2 RMII)
- JP3 removed (ETH3 RMII)
- JP4 removed (HRCW from FLASH)
-
- on board Oscillator: 66M
-
-
-2. Memory Map
-
-2.1 The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
- 0xe020_0000 0xe02f_ffff Empty 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xefff_ffff Empty 252M
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xf800_8000 0xf800_ffff PIB CS2 32K
- 0xf801_0000 0xf801_7fff PIB CS3 32K
- 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC832XEPB.h
-
- CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
- CONFIG_MPC832x MPC832x specific
- CONFIG_MPC832XEMDS MPC832XEMDS board specific
-
-4. Compilation
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC832XEMDS_config
- make
-
- MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI:
-
- 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
-
- 2)To Make U-Boot image support PCI 33MHz, use
- Make MPC832XEMDS_HOST_33_config
-
- 3)To Make U-Boot image support PCI 66MHz, use
- Make MPC832XEMDS_HOST_66M_config
-
-5. Downloading and Flashing Images
-
-5.0 Download over network:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-Boot Image using U-Boot
-
- tftp 20000 u-boot.bin
- protect off fe000000 fe0fffff
- erase fe000000 fe0fffff
- cp.b 20000 fe000000 xxxx
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
- 1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
deleted file mode 100644
index f34758a9470a..000000000000
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ /dev/null
@@ -1,173 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* ETH3 */
- {1, 0, 1, 0, 1}, /* TxD0 */
- {1, 1, 1, 0, 1}, /* TxD1 */
- {1, 2, 1, 0, 1}, /* TxD2 */
- {1, 3, 1, 0, 1}, /* TxD3 */
- {1, 9, 1, 0, 1}, /* TxER */
- {1, 12, 1, 0, 1}, /* TxEN */
- {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-
- {1, 4, 2, 0, 1}, /* RxD0 */
- {1, 5, 2, 0, 1}, /* RxD1 */
- {1, 6, 2, 0, 1}, /* RxD2 */
- {1, 7, 2, 0, 1}, /* RxD3 */
- {1, 8, 2, 0, 1}, /* RxER */
- {1, 10, 2, 0, 1}, /* RxDV */
- {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
- {1, 11, 2, 0, 1}, /* COL */
- {1, 13, 2, 0, 1}, /* CRS */
-
- /* ETH4 */
- {1, 18, 1, 0, 1}, /* TxD0 */
- {1, 19, 1, 0, 1}, /* TxD1 */
- {1, 20, 1, 0, 1}, /* TxD2 */
- {1, 21, 1, 0, 1}, /* TxD3 */
- {1, 27, 1, 0, 1}, /* TxER */
- {1, 30, 1, 0, 1}, /* TxEN */
- {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
-
- {1, 22, 2, 0, 1}, /* RxD0 */
- {1, 23, 2, 0, 1}, /* RxD1 */
- {1, 24, 2, 0, 1}, /* RxD2 */
- {1, 25, 2, 0, 1}, /* RxD3 */
- {1, 26, 1, 0, 1}, /* RxER */
- {1, 28, 2, 0, 1}, /* Rx_DV */
- {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
- {1, 29, 2, 0, 1}, /* COL */
- {1, 31, 2, 0, 1}, /* CRS */
-
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-int board_early_init_f(void)
-{
- volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[9] &= ~0x08;
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- return 0;
-}
-
-int fixed_sdram(void);
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -ENXIO;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
- msize = fixed_sdram();
-
- /* set total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 128)
-#warning Currenly any ddr size other than 128 is not supported
-#endif
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- __asm__ __volatile__ ("sync");
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
- __asm__ __volatile__ ("sync");
- return msize;
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC832XEMDS\n");
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
deleted file mode 100644
index 944108f6319d..000000000000
--- a/board/freescale/mpc832xemds/pci.c
+++ /dev/null
@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-#include "../common/pq-mds-pib.h"
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- mpc83xx_pci_init(1, reg);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar0 = 0x0;
- pci_ctrl[0].pibar0 = 0x0;
- pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
- pci_ctrl[0].pitar2 = 0x0;
- pci_ctrl[0].pibar2 = 0x0;
- pci_ctrl[0].piebar2 = 0x0;
- pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#else
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
-#if defined(CONFIG_PCI_66M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
deleted file mode 100644
index 42ef80a64708..000000000000
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ /dev/null
@@ -1,141 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-# CONFIG_PCI is not set
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
deleted file mode 100644
index 262641023906..000000000000
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ /dev/null
@@ -1,161 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM_PHYS"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
deleted file mode 100644
index 6a35a9cd8650..000000000000
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ /dev/null
@@ -1,161 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM_PHYS"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
deleted file mode 100644
index 2fed65ad19d9..000000000000
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="PCI_MEM_PHYS"
-CONFIG_BAT6_BASE=0x80000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT7=y
-CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
-CONFIG_BAT7_BASE=0x90000000
-CONFIG_BAT7_LENGTH_256_MBYTES=y
-CONFIG_BAT7_ACCESS_RW=y
-CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
-CONFIG_BAT7_DCACHE_INHIBITED=y
-CONFIG_BAT7_DCACHE_GUARDED=y
-CONFIG_BAT7_USER_MODE_VALID=y
-CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
deleted file mode 100644
index 9554c3f9dfa9..000000000000
--- a/configs/MPC832XEMDS_defconfig
+++ /dev/null
@@ -1,140 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_MPC832XEMDS=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_QUICC_MULT_FACTOR_3=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_4_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="BCSR"
-CONFIG_BAT2_BASE=0xF8000000
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="FLASH"
-CONFIG_BAT3_BASE=0xFE000000
-CONFIG_BAT3_LENGTH_32_MBYTES=y
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT3_DCACHE_INHIBITED=y
-CONFIG_BAT3_DCACHE_GUARDED=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="STACK_IN_DCACHE"
-CONFIG_BAT5_BASE=0xE6000000
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_32_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF8000000
-CONFIG_LBLAW1_NAME="BCSR"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xF8008000
-CONFIG_LBLAW3_NAME="PIB"
-CONFIG_LBLAW3_LENGTH_64_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_16_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="BCSR"
-CONFIG_BR1_OR1_BASE=0xF8000000
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_OR1_EAD_EXTRA=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="PIB1"
-CONFIG_BR2_OR2_BASE=0xF8008000
-CONFIG_OR2_XAM_SET=y
-CONFIG_OR2_SCY_15=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_XACS_EXTENDED=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_OR2_EHTR_8_CYCLE=y
-CONFIG_OR2_EAD_EXTRA=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="PIB2"
-CONFIG_BR3_OR3_BASE=0xF8010000
-CONFIG_OR3_XAM_SET=y
-CONFIG_OR3_SCY_15=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_XACS_EXTENDED=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_OR3_EHTR_8_CYCLE=y
-CONFIG_OR3_EAD_EXTRA=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_ADDR=0xFE080000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-# CONFIG_PCI is not set
-CONFIG_QE=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
deleted file mode 100644
index 94d73295de85..000000000000
--- a/include/configs/MPC832XEMDS.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 family */
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRL 0x00000000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
-
-#undef CONFIG_SPD_EEPROM
-#if defined(CONFIG_SPD_EEPROM)
-/* Determine DDR configuration from I2C interface
- */
-#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
-#else
-/* Manually set up DDR parameters
- */
-#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
- | CSCONFIG_AP \
- | CSCONFIG_ODT_WR_CFG \
- | CSCONFIG_ROW_BIT_13 \
- | CSCONFIG_COL_BIT_10)
- /* 0x80840102 */
-#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
- | (0 << TIMING_CFG0_WRT_SHIFT) \
- | (0 << TIMING_CFG0_RRT_SHIFT) \
- | (0 << TIMING_CFG0_WWT_SHIFT) \
- | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
- | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
- | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
- /* 0x00220802 */
-#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
- | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
- | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
- | (5 << TIMING_CFG1_CASLAT_SHIFT) \
- | (13 << TIMING_CFG1_REFREC_SHIFT) \
- | (3 << TIMING_CFG1_WRREC_SHIFT) \
- | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
- | (2 << TIMING_CFG1_WRTORD_SHIFT))
- /* 0x3935D322 */
-#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
- | (31 << TIMING_CFG2_CPO_SHIFT) \
- | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
- | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
- | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
- | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
- | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
- /* 0x0F9048CA */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
- /* 0x02000000 */
-#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
- | (0x0232 << SDRAM_MODE_SD_SHIFT))
- /* 0x44400232 */
-#define CONFIG_SYS_DDR_MODE2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
- | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
- /* 0x03200064 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
-#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
- | SDRAM_CFG_SDRAM_TYPE_DDR2 \
- | SDRAM_CFG_32_BE)
- /* 0x43080000 */
-#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
-#endif
-
-/*
- * Memory test
- */
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * BCSR on the Local Bus
- */
-#define CONFIG_SYS_BCSR 0xF8000000
- /* Access window base at BCSR base */
-
-
-/*
- * Windows to access PIB via local bus
- */
- /* PIB window base 0xF8008000 */
-#define CONFIG_SYS_PIB_BASE 0xF8008000
-#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
-
-/*
- * CS2 on Local Bus, to PIB
- */
-
-
-/*
- * CS3 on Local Bus, to PIB
- */
-
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
-
-/*
- * Config on-board RTC
- */
-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /*@address 0x68 */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
-
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
-#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_83XX_PCI_STREAMING
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-
-#define CONFIG_UEC_ETH1 /* ETH3 */
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 3
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif
-
-#define CONFIG_UEC_ETH2 /* ETH4 */
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 4
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-#if defined(CONFIG_UEC_ETH)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=1000000\0" \
- "ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=780000\0" \
- "fdtfile=mpc832x_mds.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 25/27] ppc: Remove T4160RDB board
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (22 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 24/27] ppc: Remove MPC832XEMDS boards Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-05-21 16:10 ` Camelia Alexandra Groza (OSS)
2021-05-23 14:58 ` [PATCHv2 " Tom Rini
2021-05-15 1:34 ` [PATCH 26/27] configs: Remove unnecessary CONFIG_DM_PCI_COMPAT=y Tom Rini
` (2 subsequent siblings)
26 siblings, 2 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_T4160 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 37 +-
arch/powerpc/cpu/mpc85xx/Makefile | 2 -
arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -------
arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
arch/powerpc/include/asm/immap_85xx.h | 4 +-
board/freescale/t4rdb/Kconfig | 14 -
board/freescale/t4rdb/MAINTAINERS | 8 -
board/freescale/t4rdb/Makefile | 19 -
board/freescale/t4rdb/cpld.c | 129 -----
board/freescale/t4rdb/cpld.h | 48 --
board/freescale/t4rdb/ddr.c | 128 -----
board/freescale/t4rdb/ddr.h | 77 ---
board/freescale/t4rdb/eth.c | 152 -----
board/freescale/t4rdb/law.c | 30 -
board/freescale/t4rdb/pci.c | 25 -
board/freescale/t4rdb/spl.c | 98 ----
board/freescale/t4rdb/t4240rdb.c | 153 -----
board/freescale/t4rdb/t4_pbi.cfg | 27 -
board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
board/freescale/t4rdb/t4rdb.h | 17 -
board/freescale/t4rdb/tlb.c | 123 ----
configs/T4160RDB_defconfig | 57 --
configs/T4240RDB_SDCARD_defconfig | 80 ---
configs/T4240RDB_defconfig | 68 ---
drivers/ddr/fsl/Kconfig | 3 +-
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 1 -
include/configs/T4240RDB.h | 667 ----------------------
30 files changed, 8 insertions(+), 2182 deletions(-)
delete mode 100644 board/freescale/t4rdb/Kconfig
delete mode 100644 board/freescale/t4rdb/MAINTAINERS
delete mode 100644 board/freescale/t4rdb/Makefile
delete mode 100644 board/freescale/t4rdb/cpld.c
delete mode 100644 board/freescale/t4rdb/cpld.h
delete mode 100644 board/freescale/t4rdb/ddr.c
delete mode 100644 board/freescale/t4rdb/ddr.h
delete mode 100644 board/freescale/t4rdb/eth.c
delete mode 100644 board/freescale/t4rdb/law.c
delete mode 100644 board/freescale/t4rdb/pci.c
delete mode 100644 board/freescale/t4rdb/spl.c
delete mode 100644 board/freescale/t4rdb/t4240rdb.c
delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
delete mode 100644 board/freescale/t4rdb/t4rdb.h
delete mode 100644 board/freescale/t4rdb/tlb.c
delete mode 100644 configs/T4160RDB_defconfig
delete mode 100644 configs/T4240RDB_SDCARD_defconfig
delete mode 100644 configs/T4240RDB_defconfig
delete mode 100644 include/configs/T4240RDB.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 876f768e8601..5c6806901bea 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -161,13 +161,6 @@ config TARGET_T2080RDB
imply CMD_SATA
imply PANIC_HANG
-config TARGET_T4160RDB
- bool "Support T4160RDB"
- select ARCH_T4160
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
config TARGET_T4240RDB
bool "Support T4240RDB"
select ARCH_T4240
@@ -732,29 +725,6 @@ config ARCH_T2080
imply CMD_REGINFO
imply FSL_SATA
-config ARCH_T4160
- bool
- select E500MC
- select E6500
- select FSL_LAW
- select SYS_FSL_DDR_VER_47
- select SYS_FSL_ERRATUM_A004468
- select SYS_FSL_ERRATUM_A005871
- select SYS_FSL_ERRATUM_A006379
- select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
- select SYS_FSL_ERRATUM_A007798
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS2
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_PPC64
- select FSL_IFC
- imply CMD_NAND
- imply CMD_REGINFO
-
config ARCH_T4240
bool
select E500MC
@@ -823,8 +793,7 @@ config NXP_ESBC
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
default 12 if ARCH_T4240
- default 8 if ARCH_P4080 || \
- ARCH_T4160
+ default 8 if ARCH_P4080
default 4 if ARCH_B4860 || \
ARCH_P2041 || \
ARCH_P3041 || \
@@ -877,7 +846,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
- ARCH_T4160 || \
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
help
@@ -1062,7 +1030,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T2080 || \
- ARCH_T4160 || \
ARCH_T4240
default 16 if ARCH_T1024 || \
ARCH_T1040 || \
@@ -1142,7 +1109,6 @@ config SYS_FSL_IFC_CLK_DIV
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
- ARCH_T4160 || \
ARCH_T4240
default 1
help
@@ -1178,7 +1144,6 @@ source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
-source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
source "board/socrates/Kconfig"
source "board/Arcturus/ucp1020/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index bbaae0d8454f..993e4873184f 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
-obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
@@ -74,7 +73,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
-obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7d168e3c9a0e..3f2fc062b2b0 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -527,8 +527,7 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
- defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -545,7 +544,7 @@ void fdt_fixup_dma3(void *blob)
case 0x29:
case 0x2d:
case 0x2e:
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e6e3f17bb272..e229a5c5a7e0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -126,8 +126,7 @@ void get_sys_info(sys_info_t *sys_info)
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
- defined(CONFIG_ARCH_T2080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index a8c0c47f4af1..61402e84ef62 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_ARCH_T4160)
-static const struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {1, {NONE, NONE, NONE, NONE,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
- {2, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {4, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {27, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {28, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {35, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {36, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {37, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {38, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {}
-};
-static const struct serdes_config serdes2_cfg_tbl[] = {
- /* SerDes 2 */
- {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {37, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {55, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {56, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {57, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {}
-};
-static const struct serdes_config serdes3_cfg_tbl[] = {
- /* SerDes 3 */
- {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {11, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {12, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {15, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {16, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {17, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {}
-};
-static const struct serdes_config serdes4_cfg_tbl[] = {
- /* SerDes 4 */
- {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
- {}
-}
-;
#else
#error "Need to define SerDes protocol"
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 33a3b3a13db7..cfe74bcb84a2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -184,7 +184,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
@@ -199,9 +199,6 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#if defined(CONFIG_ARCH_T4160)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_SRDS_1
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 70112c91fc51..f539c0be71ed 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1757,7 +1757,7 @@ typedef struct ccsr_gur {
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1869,7 +1869,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
deleted file mode 100644
index a94a57e7feeb..000000000000
--- a/board/freescale/t4rdb/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_T4160RDB || TARGET_T4240RDB
-
-config SYS_BOARD
- default "t4rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "T4240RDB"
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
deleted file mode 100644
index 4ba5c3a546a3..000000000000
--- a/board/freescale/t4rdb/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-T4RDB BOARD
-#M: Chunhe Lan <Chunhe.Lan@freescale.com>
-S: Orphan (since 2018-05)
-F: board/freescale/t4rdb/
-F: include/configs/T4240RDB.h
-F: configs/T4160RDB_defconfig
-F: configs/T4240RDB_defconfig
-F: configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
deleted file mode 100644
index 209983a24bd1..000000000000
--- a/board/freescale/t4rdb/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o
-obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
-obj-y += cpld.o
-obj-y += eth.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
deleted file mode 100644
index d484509bc20a..000000000000
--- a/board/freescale/t4rdb/cpld.c
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
- *
- * This file provides support for the board-specific CPLD used on some Freescale
- * reference boards.
- *
- * The following macros need to be defined:
- *
- * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
- * CPLD register map
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/**
- * Set the boot bank to the alternate bank
- */
-void cpld_set_altbank(void)
-{
- u8 val, curbank, altbank, override;
-
- val = CPLD_READ(vbank);
- curbank = val & CPLD_BANK_SEL_MASK;
-
- switch (curbank) {
- case CPLD_SELECT_BANK0:
- case CPLD_SELECT_BANK4:
- altbank = CPLD_SELECT_BANK4;
- CPLD_WRITE(vbank, altbank);
- override = CPLD_READ(software_on);
- CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
- CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
- break;
- default:
- printf("CPLD Altbank Fail: Invalid value!\n");
- return;
- }
-}
-
-/**
- * Set the boot bank to the default bank
- */
-void cpld_set_defbank(void)
-{
- u8 val;
-
- val = CPLD_DEFAULT_BANK;
-
- CPLD_WRITE(global_reset, val);
-}
-
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1));
- printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2));
- printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver));
- printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver));
- printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
- printf("software_on = 0x%02x\n", CPLD_READ(software_on));
- printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src));
- printf("res0 = 0x%02x\n", CPLD_READ(res0));
- printf("vbank = 0x%02x\n", CPLD_READ(vbank));
- printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk));
- printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status));
- printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status));
- printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status));
- printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset));
- printf("global_reset = 0x%02x\n", CPLD_READ(global_reset));
- printf("res1 = 0x%02x\n", CPLD_READ(res1));
- putc('\n');
-}
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else
- rc = cmd_usage(cmdtp);
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset - reset to default bank\n"
- "cpld reset altbank - reset to alternate bank\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
- );
-#endif
diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h
deleted file mode 100644
index dc3f9f3c26ca..000000000000
--- a/board/freescale/t4rdb/cpld.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/**
- * Copyright 2014 Freescale Semiconductor
- *
- * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
- *
- * This file provides support for the ngPIXIS, a board-specific FPGA used on
- * some Freescale reference boards.
- */
-
-/*
- * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
- */
-struct cpld_data {
- u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
- u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
- u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
- u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
- u8 hw_ver; /* 0x04 - PCBA Version Register */
- u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
- u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
- u8 res0; /* 0x07 - not used */
- u8 vbank; /* 0x08 - Flash Bank Selection Control Register */
- u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */
- u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */
- u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */
- u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */
- u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/
- u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
- u8 res1; /* 0x0f - not used */
-};
-
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_SEL_EN 0x04
-#define CPLD_SYSTEM_RESET 0x01
-#define CPLD_SELECT_BANK0 0x00
-#define CPLD_SELECT_BANK4 0x04
-#define CPLD_DEFAULT_BANK 0x01
-
-/* Pointer to the CPLD register set */
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \
- cpld_write(offsetof(struct cpld_data, reg), value)
-
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
deleted file mode 100644
index 57cbde154f0e..000000000000
--- a/board/freescale/t4rdb/ddr.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/mmu.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-#include "ddr.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 2) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * we use identical timing for all slots. If needed, change the code
- * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
- */
- if (popts->registered_dimm_en)
- pbsp = rdimms[0];
- else
- pbsp = udimms[0];
-
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks &&
- (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for data\n"
- "rate %lu MT/s\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
- "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
- "wrlvl_ctrl_3 0x%x\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
- pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
- pbsp->wrlvl_ctl_3);
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* DHC_EN =1, ODT = 75 Ohm */
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x64;
-}
-
-int dram_init(void)
-{
- phys_size_t dram_size;
-
- puts("Initializing....using SPD\n");
-
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
- dram_size = fsl_ddr_sdram();
-#else
- /* DDR has been initialised by first stage boot loader */
- dram_size = fsl_ddr_sdram_size();
-#endif
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
deleted file mode 100644
index 74a277961144..000000000000
--- a/board/freescale/t4rdb/ddr.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a},
- {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09},
- {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b},
- {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a},
- {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
- {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c},
- {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a},
- {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a},
- {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b},
- {}
-};
-
-static const struct board_specific_parameters rdimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3
- */
- {4, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906},
- {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
- {2, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
- {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07},
- {1, 1350, 0, 10, 9, 0x08070605, 0x06070806},
- {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06},
- {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07},
- {}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
- rdimm0,
-};
-
-
-#endif
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
deleted file mode 100644
index c815a3a4fa52..000000000000
--- a/board/freescale/t4rdb/eth.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <fdt_support.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_dtsec.h>
-#include <asm/fsl_serdes.h>
-#include <hwconfig.h>
-
-#include "../common/fman.h"
-#include "t4rdb.h"
-
-void fdt_fixup_board_enet(void *fdt)
-{
- return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_FMAN_ENET)
- int i, interface;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
-
- srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
- srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
- FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
- srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
- /* SGMII */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
- } else {
- puts("Invalid SerDes1 protocol for T4240RDB\n");
- }
-
- fm_disable_port(FM1_DTSEC5);
- fm_disable_port(FM1_DTSEC6);
-
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
- if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
- /* SGMII && XFI */
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
- } else {
- puts("Invalid SerDes2 protocol for T4240RDB\n");
- }
-
- fm_disable_port(FM2_DTSEC5);
- fm_disable_port(FM2_DTSEC6);
- for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- interface = fm_info_get_enet_if(i);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-
- for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
- switch (fm_info_get_enet_if(i)) {
- case PHY_INTERFACE_MODE_XGMII:
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(i, dev);
- break;
- default:
- break;
- }
- }
-#endif /* CONFIG_SYS_NUM_FMAN */
-
- cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
deleted file mode 100644
index 038f60565f7e..000000000000
--- a/board/freescale/t4rdb/law.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE_PHYS
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- /* Limit DCSR to 32M to access NPC Trace Buffer */
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
deleted file mode 100644
index c2bc05164dd1..000000000000
--- a/board/freescale/t4rdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
deleted file mode 100644
index e2f9c9b3de29..000000000000
--- a/board/freescale/t4rdb/spl.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <console.h>
-#include <env_internal.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/spl.h>
-#include <malloc.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-
-#include "t4rdb.h"
-
-#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L3_SIZE;
-}
-
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-unsigned long get_board_ddr_clk(void)
-{
- return CONFIG_DDR_CLK_FREQ;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, sys_clk, ccb_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
- memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
-
- /* Update GD pointer */
- gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
-
- /* compiler optimization barrier needed for GCC >= 3.4 */
- __asm__ __volatile__("" : : : "memory");
-
- console_init_f();
-
- /* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
- plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- ccb_clk = sys_clk * plat_ratio / 2;
-
- ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
- ccb_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nSD boot...\n");
-
- relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- struct bd_info *bd;
-
- bd = (struct bd_info *)(gd + sizeof(gd_t));
- memset(bd, 0, sizeof(struct bd_info));
- gd->bd = bd;
-
- arch_cpu_init();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-
- mmc_initialize(bd);
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)SPL_ENV_ADDR);
-
- gd->env_addr = (ulong)(SPL_ENV_ADDR);
- gd->env_valid = ENV_VALID;
-
- i2c_init_all();
-
- dram_init();
-
- mmc_boot();
-}
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
deleted file mode 100644
index 6ab35ca9185b..000000000000
--- a/board/freescale/t4rdb/t4240rdb.c
+++ /dev/null
@@ -1,153 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <image.h>
-#include <init.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-
-#include "t4rdb.h"
-#include "cpld.h"
-#include "../common/vid.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- struct cpu_type *cpu = gd->arch.cpu;
- u8 sw;
-
- printf("Board: %sRDB, ", cpu->name);
- printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
- CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
-
- sw = CPLD_READ(vbank);
- sw = sw & CPLD_BANK_SEL_MASK;
-
- if (sw <= 7)
- printf("vBank: %d\n", sw);
- else
- printf("Unsupported Bank=%x\n", sw);
-
- puts("SERDES Reference Clocks:\n");
- printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
- " SERDES3=100MHz SERDES4=100MHz\n");
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- /*
- * Adjust core voltage according to voltage ID
- * This function changes I2C mux to channel 2.
- */
- if (adjust_vdd(0))
- printf("Warning: Adjusting core voltage failed.\n");
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = env_get_bootm_low();
- size = env_get_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_PCI
- pci_of_setup(blob, bd);
-#endif
-
- fdt_fixup_liodn(blob);
- fsl_fdt_fixup_dr_usb(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_DM_ETH
- fdt_fixup_fman_ethernet(blob);
-#endif
- fdt_fixup_board_enet(blob);
-#endif
-
- return 0;
-}
-
-/*
- * This function is called by bdinfo to print detail board information.
- * As an exmaple for future board, we organize the messages into
- * several sections. If applicable, the message is in the format of
- * <name> = <value>
- * It should aligned with normal output of bdinfo command.
- *
- * Voltage: Core, DDR and another configurable voltages
- * Clock : Critical clocks which are not printed already
- * RCW : RCW source if not printed already
- * Misc : Other important information not in above catagories
- */
-void board_detail(void)
-{
- int rcwsrc;
-
- /* RCW section SW3[4] */
- rcwsrc = 0x0;
- puts("RCW source = ");
- switch (rcwsrc & 0x1) {
- case 0x1:
- puts("SDHC/eMMC\n");
- break;
- default:
- puts("I2C normal addressing\n");
- break;
- }
-}
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
deleted file mode 100644
index 0b326fa1635a..000000000000
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#PBI commands
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#512KB SRAM
-09010100 00000000
-09010104 fff80009
-09010f00 08000000
-#enable CPC1
-09010000 80000000
-#Configure LAW for CPC1
-09000d00 00000000
-09000d04 fff80000
-09000d08 81000012
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Flush PBL data
-091380c0 00100000
diff --git a/board/freescale/t4rdb/t4_sd_rcw.cfg b/board/freescale/t4rdb/t4_sd_rcw.cfg
deleted file mode 100644
index cc2bff68269c..000000000000
--- a/board/freescale/t4rdb/t4_sd_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol 27_55_1_9
-16070019 18101916 00000000 00000000
-6c6e0848 00448c00 6c020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h
deleted file mode 100644
index 3f1fa7bbd24e..000000000000
--- a/board/freescale/t4rdb/t4rdb.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __T4RDB_H__
-#define __T4RDB_H__
-
-#undef CONFIG_SYS_NUM_FM1_DTSEC
-#undef CONFIG_SYS_NUM_FM2_DTSEC
-#define CONFIG_SYS_NUM_FM1_DTSEC 4
-#define CONFIG_SYS_NUM_FM2_DTSEC 4
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, struct bd_info *bd);
-
-#endif
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
deleted file mode 100644
index b927dd8484f8..000000000000
--- a/board/freescale/t4rdb/tlb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
- /*
- * *I*G - L3SRAM. When L3 is used as 512K SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_512K, 1),
-#else
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
-
- /* *I*G* - Flash, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 9, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_16M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 11, BOOKE_PAGESZ_16M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
- CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_16M, 1),
-#endif
-#endif
-
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_32M, 1),
-#endif
-#ifdef CONFIG_SYS_NAND_BASE
- /*
- * *I*G - NAND
- * entry 14 and 15 has been used hard coded, they will be disabled
- * in cpu_init_f, so we use entry 16 for nand.
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_64K, 1),
-#endif
-#ifdef CONFIG_SYS_CPLD_BASE
- SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
- MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 17, BOOKE_PAGESZ_4K, 1),
-#endif
-#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 18, BOOKE_PAGESZ_2G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
deleted file mode 100644
index 706d6a2367d5..000000000000
--- a/configs/T4160RDB_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
deleted file mode 100644
index 73b90c210962..000000000000
--- a/configs/T4240RDB_SDCARD_defconfig
+++ /dev/null
@@ -1,80 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x00201000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_MMC_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
deleted file mode 100644
index b931eb025f5f..000000000000
--- a/configs/T4240RDB_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4240RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_I2C=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_FSL=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index e6a51f560978..8246f627982c 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -44,8 +44,7 @@ config SYS_NUM_DDR_CTLRS
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_LX2160A || \
- ARCH_LX2162A || \
- ARCH_T4160
+ ARCH_LX2162A
default 1
config SYS_FSL_DDR_VER
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0220dd2a5f2d..e95041447779 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -737,7 +737,6 @@ config SYS_DPAA_QBMAN
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T4240 || \
- ARCH_T4160 || \
ARCH_P4080 || \
ARCH_P3041 || \
ARCH_P5040 || \
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index c988e4e9257f..ae3841217663 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T4240) += t4240.o
-obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o
obj-$(CONFIG_ARCH_B4860) += b4860.o
obj-$(CONFIG_ARCH_LS1043A) += ls1043.o
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
deleted file mode 100644
index a04d9137b32d..000000000000
--- a/include/configs/T4240RDB.h
+++ /dev/null
@@ -1,667 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
- */
-
-/*
- * T4240 RDB board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-#define CONFIG_FSL_SATA_V2
-#define CONFIG_PCIE4
-
-#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
-#ifndef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#else
-#define CONFIG_SPL_FLUSH_IMAGE
-#define CONFIG_SPL_PAD_TO 0x40000
-#define CONFIG_SPL_MAX_SIZE 0x28000
-#define RESET_VECTOR_OFFSET 0x27FFC
-#define BOOT_PAGE_OFFSET 0x27000
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
-#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_SKIP_RELOCATE
-#define CONFIG_SPL_COMMON_INIT_DDR
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-#endif
-#endif /* CONFIG_RAMBOOT_PBL */
-
-#define CONFIG_DDR_ECC
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB /* toggle branch predition */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-/*
- * Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
-#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
-#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR 0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_DDR_SPD
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE 0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
- ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
- CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-
-#define CONFIG_SYS_I2C_FSL
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
-#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
-#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
-#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-
-#ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1@DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ 133333333
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SPD_BUS_NUM 0
-#define SPD_EEPROM_ADDRESS1 0x52
-#define SPD_EEPROM_ADDRESS2 0x54
-#define SPD_EEPROM_ADDRESS3 0x56
-#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
-#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
-#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
- FTIM0_NOR_TEADC(0x5) | \
- FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
- FTIM1_NOR_TRAD_NOR(0x1A) |\
- FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x0E) | \
- FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3 0x0
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
- + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
-
-/* NAND Flash on IFC */
-#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_NAND_MAX_ECCPOS 256
-#define CONFIG_SYS_NAND_MAX_OOBFREE 2
-#define CONFIG_SYS_NAND_BASE 0xff800000
-#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
- | CSPR_MSEL_NAND /* MSEL = NAND */ \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
- | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
- | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
- | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x07) | \
- FTIM0_NAND_TWH(0x0a))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0x0e) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
- FTIM2_NAND_TREH(0x0a) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_DDR_LAW 11
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
-#if defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-/* CPLD on IFC */
-#define CONFIG_SYS_CPLD_BASE 0xffdf0000
-#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
-#define CONFIG_SYS_CSPR3_EXT (0xf)
-#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_GPCM \
- | CSPR_V)
-
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR3 0x0
-
-/* CPLD Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
- FTIM0_GPCM_TEADC(0x0e) | \
- FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
- FTIM1_GPCM_TRAD(0x1f))
-#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
- FTIM2_GPCM_TCH(0x8) | \
- FTIM2_GPCM_TWP(0x1f))
-#define CONFIG_SYS_CS3_FTIM3 0x0
-
-#if defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-/* I2C */
-#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
-#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
-
-#define I2C_MUX_CH_DEFAULT 0x8
-#define I2C_MUX_CH_VOL_MONITOR 0xa
-#define I2C_MUX_CH_VSC3316_FS 0xc
-#define I2C_MUX_CH_VSC3316_BS 0xd
-
-/* Voltage monitor on channel 2*/
-#define I2C_VOL_MONITOR_ADDR 0x40
-#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
-#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
-#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
-
-#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_VID
-#endif
-#define CONFIG_VOL_MONITOR_IR36021_SET
-#define CONFIG_VOL_MONITOR_IR36021_READ
-/* The lowest and highest voltage allowed for T4240RDB */
-#define VDD_MV_MIN 819
-#define VDD_MV_MAX 1212
-
-/*
- * eSPI - Enhanced SPI
- */
-
-/* Qman/Bman */
-#ifndef CONFIG_NOBQFMAN
-#define CONFIG_SYS_BMAN_NUM_PORTALS 50
-#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
-#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
-#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
-#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
- CONFIG_SYS_BMAN_CENA_SIZE)
-#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
-#define CONFIG_SYS_QMAN_NUM_PORTALS 50
-#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
-#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
-#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
-#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
-#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
-#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
-#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
- CONFIG_SYS_QMAN_CENA_SIZE)
-#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
-#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
-
-#define CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_PMAN
-#define CONFIG_SYS_DPAA_DCE
-#define CONFIG_SYS_DPAA_RMAN
-#define CONFIG_SYS_INTERLAKEN
-
-/* Default address of microcode for the Linux Fman driver */
-#if defined(CONFIG_SPIFLASH)
-/*
- * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
- * env, so we got 0x110000.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
-#elif defined(CONFIG_SDCARD)
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-#endif /* CONFIG_NOBQFMAN */
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_CORTINA_FW_ADDR 0xefe00000
-#define CONFIG_CORTINA_FW_LENGTH 0x40000
-#define SGMII_PHY_ADDR1 0x0
-#define SGMII_PHY_ADDR2 0x1
-#define SGMII_PHY_ADDR3 0x2
-#define SGMII_PHY_ADDR4 0x3
-#define SGMII_PHY_ADDR5 0x4
-#define SGMII_PHY_ADDR6 0x5
-#define SGMII_PHY_ADDR7 0x6
-#define SGMII_PHY_ADDR8 0x7
-#define FM1_10GEC1_PHY_ADDR 0x10
-#define FM1_10GEC2_PHY_ADDR 0x11
-#define FM2_10GEC1_PHY_ADDR 0x12
-#define FM2_10GEC2_PHY_ADDR 0x13
-#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
-#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
-#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
-#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
-#endif
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME "FM1 at DTSEC1"
-#endif
-
-/*
-* USB
-*/
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_HAS_FSL_DR_USB
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-
-#define __USB_PHY_TYPE utmi
-
-/*
- * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
- * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
- * interleaving. It can be cacheline, page, bank, superbank.
- * See doc/README.fsl-ddr for details.
- */
-#ifdef CONFIG_ARCH_T4240
-#define CTRL_INTLV_PREFERED 3way_4KB
-#else
-#define CTRL_INTLV_PREFERED cacheline
-#endif
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:" \
- "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
- "bank_intlv=auto;" \
- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot && " \
- "protect off $ubootaddr +$filesize && " \
- "erase $ubootaddr +$filesize && " \
- "cp.b $loadaddr $ubootaddr $filesize && " \
- "protect on $ubootaddr +$filesize && " \
- "cmp.b $loadaddr $ubootaddr $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
- "fdtaddr=1e00000\0" \
- "fdtfile=t4240rdb/t4240rdb.dtb\0" \
- "bdev=sda3\0"
-
-#define CONFIG_HVBOOT \
- "setenv bootargs config-addr=0x60000000; " \
- "bootm 0x01000000 - 0x00f00000"
-
-#define CONFIG_LINUX \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "setenv ramdiskaddr 0x02000000;" \
- "setenv fdtaddr 0x00c00000;" \
- "setenv loadaddr 0x1000000;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_HDBOOT \
- "setenv bootargs root=/dev/$bdev rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_LINUX
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __CONFIG_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* RE: [PATCH 25/27] ppc: Remove T4160RDB board
2021-05-15 1:34 ` [PATCH 25/27] ppc: Remove T4160RDB board Tom Rini
@ 2021-05-21 16:10 ` Camelia Alexandra Groza (OSS)
2021-05-21 16:18 ` Tom Rini
2021-05-21 17:39 ` Tom Rini
2021-05-23 14:58 ` [PATCHv2 " Tom Rini
1 sibling, 2 replies; 71+ messages in thread
From: Camelia Alexandra Groza (OSS) @ 2021-05-21 16:10 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot, Priyanka Jain
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
> Sent: Saturday, May 15, 2021 4:35
> To: u-boot@lists.denx.de
> Subject: [PATCH 25/27] ppc: Remove T4160RDB board
>
> This board has not been converted to CONFIG_DM_PCI by the deadline and
> is
> also missing conversion to CONFIG_DM. Remove it. As this is the last
> ARCH_T4160 platform, remove that support as well.
>
> Signed-off-by: Tom Rini <trini@konsulko.com>
> ---
> arch/powerpc/cpu/mpc85xx/Kconfig | 37 +-
> arch/powerpc/cpu/mpc85xx/Makefile | 2 -
> arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
> arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
> arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -------
> arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
> arch/powerpc/include/asm/immap_85xx.h | 4 +-
> board/freescale/t4rdb/Kconfig | 14 -
> board/freescale/t4rdb/MAINTAINERS | 8 -
> board/freescale/t4rdb/Makefile | 19 -
> board/freescale/t4rdb/cpld.c | 129 -----
> board/freescale/t4rdb/cpld.h | 48 --
> board/freescale/t4rdb/ddr.c | 128 -----
> board/freescale/t4rdb/ddr.h | 77 ---
> board/freescale/t4rdb/eth.c | 152 -----
> board/freescale/t4rdb/law.c | 30 -
> board/freescale/t4rdb/pci.c | 25 -
> board/freescale/t4rdb/spl.c | 98 ----
> board/freescale/t4rdb/t4240rdb.c | 153 -----
> board/freescale/t4rdb/t4_pbi.cfg | 27 -
> board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
> board/freescale/t4rdb/t4rdb.h | 17 -
> board/freescale/t4rdb/tlb.c | 123 ----
> configs/T4160RDB_defconfig | 57 --
> configs/T4240RDB_SDCARD_defconfig | 80 ---
> configs/T4240RDB_defconfig | 68 ---
> drivers/ddr/fsl/Kconfig | 3 +-
> drivers/net/Kconfig | 1 -
> drivers/net/fm/Makefile | 1 -
> include/configs/T4240RDB.h | 667 ----------------------
> 30 files changed, 8 insertions(+), 2182 deletions(-)
> delete mode 100644 board/freescale/t4rdb/Kconfig
> delete mode 100644 board/freescale/t4rdb/MAINTAINERS
> delete mode 100644 board/freescale/t4rdb/Makefile
> delete mode 100644 board/freescale/t4rdb/cpld.c
> delete mode 100644 board/freescale/t4rdb/cpld.h
> delete mode 100644 board/freescale/t4rdb/ddr.c
> delete mode 100644 board/freescale/t4rdb/ddr.h
> delete mode 100644 board/freescale/t4rdb/eth.c
> delete mode 100644 board/freescale/t4rdb/law.c
> delete mode 100644 board/freescale/t4rdb/pci.c
> delete mode 100644 board/freescale/t4rdb/spl.c
> delete mode 100644 board/freescale/t4rdb/t4240rdb.c
> delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
> delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
> delete mode 100644 board/freescale/t4rdb/t4rdb.h
> delete mode 100644 board/freescale/t4rdb/tlb.c
> delete mode 100644 configs/T4160RDB_defconfig
> delete mode 100644 configs/T4240RDB_SDCARD_defconfig
> delete mode 100644 configs/T4240RDB_defconfig
> delete mode 100644 include/configs/T4240RDB.h
Hi Tom
The T4240RDB has DM_PCI enabled. Why is it also getting removed?
Am I missing something?
Thanks,
Camelia
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 25/27] ppc: Remove T4160RDB board
2021-05-21 16:10 ` Camelia Alexandra Groza (OSS)
@ 2021-05-21 16:18 ` Tom Rini
2021-05-21 17:39 ` Tom Rini
1 sibling, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-05-21 16:18 UTC (permalink / raw)
To: Camelia Alexandra Groza (OSS); +Cc: u-boot, Priyanka Jain
[-- Attachment #1: Type: text/plain, Size: 3730 bytes --]
On Fri, May 21, 2021 at 04:10:12PM +0000, Camelia Alexandra Groza (OSS) wrote:
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
> > Sent: Saturday, May 15, 2021 4:35
> > To: u-boot@lists.denx.de
> > Subject: [PATCH 25/27] ppc: Remove T4160RDB board
> >
> > This board has not been converted to CONFIG_DM_PCI by the deadline and
> > is
> > also missing conversion to CONFIG_DM. Remove it. As this is the last
> > ARCH_T4160 platform, remove that support as well.
> >
> > Signed-off-by: Tom Rini <trini@konsulko.com>
> > ---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 37 +-
> > arch/powerpc/cpu/mpc85xx/Makefile | 2 -
> > arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
> > arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
> > arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -------
> > arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
> > arch/powerpc/include/asm/immap_85xx.h | 4 +-
> > board/freescale/t4rdb/Kconfig | 14 -
> > board/freescale/t4rdb/MAINTAINERS | 8 -
> > board/freescale/t4rdb/Makefile | 19 -
> > board/freescale/t4rdb/cpld.c | 129 -----
> > board/freescale/t4rdb/cpld.h | 48 --
> > board/freescale/t4rdb/ddr.c | 128 -----
> > board/freescale/t4rdb/ddr.h | 77 ---
> > board/freescale/t4rdb/eth.c | 152 -----
> > board/freescale/t4rdb/law.c | 30 -
> > board/freescale/t4rdb/pci.c | 25 -
> > board/freescale/t4rdb/spl.c | 98 ----
> > board/freescale/t4rdb/t4240rdb.c | 153 -----
> > board/freescale/t4rdb/t4_pbi.cfg | 27 -
> > board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
> > board/freescale/t4rdb/t4rdb.h | 17 -
> > board/freescale/t4rdb/tlb.c | 123 ----
> > configs/T4160RDB_defconfig | 57 --
> > configs/T4240RDB_SDCARD_defconfig | 80 ---
> > configs/T4240RDB_defconfig | 68 ---
> > drivers/ddr/fsl/Kconfig | 3 +-
> > drivers/net/Kconfig | 1 -
> > drivers/net/fm/Makefile | 1 -
> > include/configs/T4240RDB.h | 667 ----------------------
> > 30 files changed, 8 insertions(+), 2182 deletions(-)
> > delete mode 100644 board/freescale/t4rdb/Kconfig
> > delete mode 100644 board/freescale/t4rdb/MAINTAINERS
> > delete mode 100644 board/freescale/t4rdb/Makefile
> > delete mode 100644 board/freescale/t4rdb/cpld.c
> > delete mode 100644 board/freescale/t4rdb/cpld.h
> > delete mode 100644 board/freescale/t4rdb/ddr.c
> > delete mode 100644 board/freescale/t4rdb/ddr.h
> > delete mode 100644 board/freescale/t4rdb/eth.c
> > delete mode 100644 board/freescale/t4rdb/law.c
> > delete mode 100644 board/freescale/t4rdb/pci.c
> > delete mode 100644 board/freescale/t4rdb/spl.c
> > delete mode 100644 board/freescale/t4rdb/t4240rdb.c
> > delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
> > delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
> > delete mode 100644 board/freescale/t4rdb/t4rdb.h
> > delete mode 100644 board/freescale/t4rdb/tlb.c
> > delete mode 100644 configs/T4160RDB_defconfig
> > delete mode 100644 configs/T4240RDB_SDCARD_defconfig
> > delete mode 100644 configs/T4240RDB_defconfig
> > delete mode 100644 include/configs/T4240RDB.h
>
> Hi Tom
>
> The T4240RDB has DM_PCI enabled. Why is it also getting removed?
> Am I missing something?
Because of how they're done in Kconfig, etc, that got pulled in. I'll
rework dropping just T4160RDB, thanks.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 25/27] ppc: Remove T4160RDB board
2021-05-21 16:10 ` Camelia Alexandra Groza (OSS)
2021-05-21 16:18 ` Tom Rini
@ 2021-05-21 17:39 ` Tom Rini
2021-06-08 7:36 ` Priyanka Jain
1 sibling, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-21 17:39 UTC (permalink / raw)
To: Camelia Alexandra Groza (OSS); +Cc: u-boot, Priyanka Jain
[-- Attachment #1: Type: text/plain, Size: 3730 bytes --]
On Fri, May 21, 2021 at 04:10:12PM +0000, Camelia Alexandra Groza (OSS) wrote:
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
> > Sent: Saturday, May 15, 2021 4:35
> > To: u-boot@lists.denx.de
> > Subject: [PATCH 25/27] ppc: Remove T4160RDB board
> >
> > This board has not been converted to CONFIG_DM_PCI by the deadline and
> > is
> > also missing conversion to CONFIG_DM. Remove it. As this is the last
> > ARCH_T4160 platform, remove that support as well.
> >
> > Signed-off-by: Tom Rini <trini@konsulko.com>
> > ---
> > arch/powerpc/cpu/mpc85xx/Kconfig | 37 +-
> > arch/powerpc/cpu/mpc85xx/Makefile | 2 -
> > arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
> > arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
> > arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -------
> > arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
> > arch/powerpc/include/asm/immap_85xx.h | 4 +-
> > board/freescale/t4rdb/Kconfig | 14 -
> > board/freescale/t4rdb/MAINTAINERS | 8 -
> > board/freescale/t4rdb/Makefile | 19 -
> > board/freescale/t4rdb/cpld.c | 129 -----
> > board/freescale/t4rdb/cpld.h | 48 --
> > board/freescale/t4rdb/ddr.c | 128 -----
> > board/freescale/t4rdb/ddr.h | 77 ---
> > board/freescale/t4rdb/eth.c | 152 -----
> > board/freescale/t4rdb/law.c | 30 -
> > board/freescale/t4rdb/pci.c | 25 -
> > board/freescale/t4rdb/spl.c | 98 ----
> > board/freescale/t4rdb/t4240rdb.c | 153 -----
> > board/freescale/t4rdb/t4_pbi.cfg | 27 -
> > board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
> > board/freescale/t4rdb/t4rdb.h | 17 -
> > board/freescale/t4rdb/tlb.c | 123 ----
> > configs/T4160RDB_defconfig | 57 --
> > configs/T4240RDB_SDCARD_defconfig | 80 ---
> > configs/T4240RDB_defconfig | 68 ---
> > drivers/ddr/fsl/Kconfig | 3 +-
> > drivers/net/Kconfig | 1 -
> > drivers/net/fm/Makefile | 1 -
> > include/configs/T4240RDB.h | 667 ----------------------
> > 30 files changed, 8 insertions(+), 2182 deletions(-)
> > delete mode 100644 board/freescale/t4rdb/Kconfig
> > delete mode 100644 board/freescale/t4rdb/MAINTAINERS
> > delete mode 100644 board/freescale/t4rdb/Makefile
> > delete mode 100644 board/freescale/t4rdb/cpld.c
> > delete mode 100644 board/freescale/t4rdb/cpld.h
> > delete mode 100644 board/freescale/t4rdb/ddr.c
> > delete mode 100644 board/freescale/t4rdb/ddr.h
> > delete mode 100644 board/freescale/t4rdb/eth.c
> > delete mode 100644 board/freescale/t4rdb/law.c
> > delete mode 100644 board/freescale/t4rdb/pci.c
> > delete mode 100644 board/freescale/t4rdb/spl.c
> > delete mode 100644 board/freescale/t4rdb/t4240rdb.c
> > delete mode 100644 board/freescale/t4rdb/t4_pbi.cfg
> > delete mode 100644 board/freescale/t4rdb/t4_sd_rcw.cfg
> > delete mode 100644 board/freescale/t4rdb/t4rdb.h
> > delete mode 100644 board/freescale/t4rdb/tlb.c
> > delete mode 100644 configs/T4160RDB_defconfig
> > delete mode 100644 configs/T4240RDB_SDCARD_defconfig
> > delete mode 100644 configs/T4240RDB_defconfig
> > delete mode 100644 include/configs/T4240RDB.h
>
> Hi Tom
>
> The T4240RDB has DM_PCI enabled. Why is it also getting removed?
> Am I missing something?
Please note that board/freescale/t4rdb/MAINTAINERS needs to be updated
with a responsible maintainer, thanks.
--
Tom
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^ permalink raw reply [flat|nested] 71+ messages in thread
* RE: [PATCH 25/27] ppc: Remove T4160RDB board
2021-05-21 17:39 ` Tom Rini
@ 2021-06-08 7:36 ` Priyanka Jain
2021-06-08 12:06 ` Tom Rini
0 siblings, 1 reply; 71+ messages in thread
From: Priyanka Jain @ 2021-06-08 7:36 UTC (permalink / raw)
To: Tom Rini, Camelia Alexandra Groza (OSS); +Cc: u-boot
>-----Original Message-----
>From: Tom Rini <trini@konsulko.com>
>Sent: Friday, May 21, 2021 11:09 PM
>To: Camelia Alexandra Groza (OSS) <camelia.groza@oss.nxp.com>
>Cc: u-boot@lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>
>Subject: Re: [PATCH 25/27] ppc: Remove T4160RDB board
>
>On Fri, May 21, 2021 at 04:10:12PM +0000, Camelia Alexandra Groza (OSS) wrote:
>> > -----Original Message-----
>> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
>> > Sent: Saturday, May 15, 2021 4:35
>> > To: u-boot@lists.denx.de
>> > Subject: [PATCH 25/27] ppc: Remove T4160RDB board
>> >
>> > This board has not been converted to CONFIG_DM_PCI by the deadline
>> > and is also missing conversion to CONFIG_DM. Remove it. As this is
>> > the last
>> > ARCH_T4160 platform, remove that support as well.
>> >
>> > Signed-off-by: Tom Rini <trini@konsulko.com>
>> > ---
>> > arch/powerpc/cpu/mpc85xx/Kconfig | 37 +-
>> > arch/powerpc/cpu/mpc85xx/Makefile | 2 -
>> > arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
>> > arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
>> > arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -------
>> > arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
>> > arch/powerpc/include/asm/immap_85xx.h | 4 +-
>> > board/freescale/t4rdb/Kconfig | 14 -
>> > board/freescale/t4rdb/MAINTAINERS | 8 -
>> > board/freescale/t4rdb/Makefile | 19 -
>> > board/freescale/t4rdb/cpld.c | 129 -----
>> > board/freescale/t4rdb/cpld.h | 48 --
>> > board/freescale/t4rdb/ddr.c | 128 -----
>> > board/freescale/t4rdb/ddr.h | 77 ---
>> > board/freescale/t4rdb/eth.c | 152 -----
>> > board/freescale/t4rdb/law.c | 30 -
>> > board/freescale/t4rdb/pci.c | 25 -
>> > board/freescale/t4rdb/spl.c | 98 ----
>> > board/freescale/t4rdb/t4240rdb.c | 153 -----
>> > board/freescale/t4rdb/t4_pbi.cfg | 27 -
>> > board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
>> > board/freescale/t4rdb/t4rdb.h | 17 -
>> > board/freescale/t4rdb/tlb.c | 123 ----
>> > configs/T4160RDB_defconfig | 57 --
>> > configs/T4240RDB_SDCARD_defconfig | 80 ---
>> > configs/T4240RDB_defconfig | 68 ---
>> > drivers/ddr/fsl/Kconfig | 3 +-
>> > drivers/net/Kconfig | 1 -
>> > drivers/net/fm/Makefile | 1 -
>> > include/configs/T4240RDB.h | 667 ----------------------
>> > 30 files changed, 8 insertions(+), 2182 deletions(-) delete mode
>> > 100644 board/freescale/t4rdb/Kconfig delete mode 100644
>> > board/freescale/t4rdb/MAINTAINERS delete mode 100644
>> > board/freescale/t4rdb/Makefile delete mode 100644
>> > board/freescale/t4rdb/cpld.c delete mode 100644
>> > board/freescale/t4rdb/cpld.h delete mode 100644
>> > board/freescale/t4rdb/ddr.c delete mode 100644
>> > board/freescale/t4rdb/ddr.h delete mode 100644
>> > board/freescale/t4rdb/eth.c delete mode 100644
>> > board/freescale/t4rdb/law.c delete mode 100644
>> > board/freescale/t4rdb/pci.c delete mode 100644
>> > board/freescale/t4rdb/spl.c delete mode 100644
>> > board/freescale/t4rdb/t4240rdb.c delete mode 100644
>> > board/freescale/t4rdb/t4_pbi.cfg delete mode 100644
>> > board/freescale/t4rdb/t4_sd_rcw.cfg
>> > delete mode 100644 board/freescale/t4rdb/t4rdb.h delete mode
>> > 100644 board/freescale/t4rdb/tlb.c delete mode 100644
>> > configs/T4160RDB_defconfig delete mode 100644
>> > configs/T4240RDB_SDCARD_defconfig delete mode 100644
>> > configs/T4240RDB_defconfig delete mode 100644
>> > include/configs/T4240RDB.h
>>
>> Hi Tom
>>
>> The T4240RDB has DM_PCI enabled. Why is it also getting removed?
>> Am I missing something?
>
>Please note that board/freescale/t4rdb/MAINTAINERS needs to be updated with
>a responsible maintainer, thanks.
>
>--
>Tom
Hello Tom,
I will submit patch to add myself as MAINTAINER in board/freescale/t4rdb/MAINTAINERS.
Kindly don't remove the board support.
Thanks
Priyanka
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH 25/27] ppc: Remove T4160RDB board
2021-06-08 7:36 ` Priyanka Jain
@ 2021-06-08 12:06 ` Tom Rini
0 siblings, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-06-08 12:06 UTC (permalink / raw)
To: Priyanka Jain; +Cc: Camelia Alexandra Groza (OSS), u-boot
[-- Attachment #1: Type: text/plain, Size: 4878 bytes --]
On Tue, Jun 08, 2021 at 07:36:31AM +0000, Priyanka Jain wrote:
>
>
> >-----Original Message-----
> >From: Tom Rini <trini@konsulko.com>
> >Sent: Friday, May 21, 2021 11:09 PM
> >To: Camelia Alexandra Groza (OSS) <camelia.groza@oss.nxp.com>
> >Cc: u-boot@lists.denx.de; Priyanka Jain <priyanka.jain@nxp.com>
> >Subject: Re: [PATCH 25/27] ppc: Remove T4160RDB board
> >
> >On Fri, May 21, 2021 at 04:10:12PM +0000, Camelia Alexandra Groza (OSS) wrote:
> >> > -----Original Message-----
> >> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tom Rini
> >> > Sent: Saturday, May 15, 2021 4:35
> >> > To: u-boot@lists.denx.de
> >> > Subject: [PATCH 25/27] ppc: Remove T4160RDB board
> >> >
> >> > This board has not been converted to CONFIG_DM_PCI by the deadline
> >> > and is also missing conversion to CONFIG_DM. Remove it. As this is
> >> > the last
> >> > ARCH_T4160 platform, remove that support as well.
> >> >
> >> > Signed-off-by: Tom Rini <trini@konsulko.com>
> >> > ---
> >> > arch/powerpc/cpu/mpc85xx/Kconfig | 37 +-
> >> > arch/powerpc/cpu/mpc85xx/Makefile | 2 -
> >> > arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
> >> > arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
> >> > arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 -------
> >> > arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
> >> > arch/powerpc/include/asm/immap_85xx.h | 4 +-
> >> > board/freescale/t4rdb/Kconfig | 14 -
> >> > board/freescale/t4rdb/MAINTAINERS | 8 -
> >> > board/freescale/t4rdb/Makefile | 19 -
> >> > board/freescale/t4rdb/cpld.c | 129 -----
> >> > board/freescale/t4rdb/cpld.h | 48 --
> >> > board/freescale/t4rdb/ddr.c | 128 -----
> >> > board/freescale/t4rdb/ddr.h | 77 ---
> >> > board/freescale/t4rdb/eth.c | 152 -----
> >> > board/freescale/t4rdb/law.c | 30 -
> >> > board/freescale/t4rdb/pci.c | 25 -
> >> > board/freescale/t4rdb/spl.c | 98 ----
> >> > board/freescale/t4rdb/t4240rdb.c | 153 -----
> >> > board/freescale/t4rdb/t4_pbi.cfg | 27 -
> >> > board/freescale/t4rdb/t4_sd_rcw.cfg | 7 -
> >> > board/freescale/t4rdb/t4rdb.h | 17 -
> >> > board/freescale/t4rdb/tlb.c | 123 ----
> >> > configs/T4160RDB_defconfig | 57 --
> >> > configs/T4240RDB_SDCARD_defconfig | 80 ---
> >> > configs/T4240RDB_defconfig | 68 ---
> >> > drivers/ddr/fsl/Kconfig | 3 +-
> >> > drivers/net/Kconfig | 1 -
> >> > drivers/net/fm/Makefile | 1 -
> >> > include/configs/T4240RDB.h | 667 ----------------------
> >> > 30 files changed, 8 insertions(+), 2182 deletions(-) delete mode
> >> > 100644 board/freescale/t4rdb/Kconfig delete mode 100644
> >> > board/freescale/t4rdb/MAINTAINERS delete mode 100644
> >> > board/freescale/t4rdb/Makefile delete mode 100644
> >> > board/freescale/t4rdb/cpld.c delete mode 100644
> >> > board/freescale/t4rdb/cpld.h delete mode 100644
> >> > board/freescale/t4rdb/ddr.c delete mode 100644
> >> > board/freescale/t4rdb/ddr.h delete mode 100644
> >> > board/freescale/t4rdb/eth.c delete mode 100644
> >> > board/freescale/t4rdb/law.c delete mode 100644
> >> > board/freescale/t4rdb/pci.c delete mode 100644
> >> > board/freescale/t4rdb/spl.c delete mode 100644
> >> > board/freescale/t4rdb/t4240rdb.c delete mode 100644
> >> > board/freescale/t4rdb/t4_pbi.cfg delete mode 100644
> >> > board/freescale/t4rdb/t4_sd_rcw.cfg
> >> > delete mode 100644 board/freescale/t4rdb/t4rdb.h delete mode
> >> > 100644 board/freescale/t4rdb/tlb.c delete mode 100644
> >> > configs/T4160RDB_defconfig delete mode 100644
> >> > configs/T4240RDB_SDCARD_defconfig delete mode 100644
> >> > configs/T4240RDB_defconfig delete mode 100644
> >> > include/configs/T4240RDB.h
> >>
> >> Hi Tom
> >>
> >> The T4240RDB has DM_PCI enabled. Why is it also getting removed?
> >> Am I missing something?
> >
> >Please note that board/freescale/t4rdb/MAINTAINERS needs to be updated with
> >a responsible maintainer, thanks.
>
> Hello Tom,
>
> I will submit patch to add myself as MAINTAINER in board/freescale/t4rdb/MAINTAINERS.
> Kindly don't remove the board support.
OK, but note that there's two things going on here. There's (1) the
boards with an orphaned maintainer setting and (2) boards without DM_PCI
migration. I'm not (intentionally) removing boards that hit problem #1
but I am removing boards that hit problem #2. Since you posted a series
to update MAINTAINERS only, I assume that nothing in that second
category is something you want to keep.
--
Tom
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[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCHv2 25/27] ppc: Remove T4160RDB board
2021-05-15 1:34 ` [PATCH 25/27] ppc: Remove T4160RDB board Tom Rini
2021-05-21 16:10 ` Camelia Alexandra Groza (OSS)
@ 2021-05-23 14:58 ` Tom Rini
2021-07-08 2:53 ` Tom Rini
1 sibling, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-23 14:58 UTC (permalink / raw)
To: u-boot; +Cc: camelia.groza
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_T4160 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Changes in v2:
- Only remove T4160 support and not T4240RDB as well.
---
arch/powerpc/cpu/mpc85xx/Kconfig | 36 +---
arch/powerpc/cpu/mpc85xx/Makefile | 2 -
arch/powerpc/cpu/mpc85xx/fdt.c | 5 +-
.../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +-
arch/powerpc/cpu/mpc85xx/speed.c | 3 +-
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 ------------------
arch/powerpc/include/asm/config_mpc85xx.h | 5 +-
arch/powerpc/include/asm/fsl_secure_boot.h | 1 -
arch/powerpc/include/asm/immap_85xx.h | 4 +-
board/freescale/t4rdb/Kconfig | 2 +-
board/freescale/t4rdb/MAINTAINERS | 1 -
board/freescale/t4rdb/Makefile | 1 -
configs/T4160RDB_defconfig | 57 -----
drivers/ddr/fsl/Kconfig | 3 +-
drivers/net/Kconfig | 1 -
drivers/net/fm/Makefile | 1 -
16 files changed, 10 insertions(+), 316 deletions(-)
delete mode 100644 configs/T4160RDB_defconfig
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 876f768e8601..395423582a8e 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -161,13 +161,6 @@ config TARGET_T2080RDB
imply CMD_SATA
imply PANIC_HANG
-config TARGET_T4160RDB
- bool "Support T4160RDB"
- select ARCH_T4160
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
config TARGET_T4240RDB
bool "Support T4240RDB"
select ARCH_T4240
@@ -732,29 +725,6 @@ config ARCH_T2080
imply CMD_REGINFO
imply FSL_SATA
-config ARCH_T4160
- bool
- select E500MC
- select E6500
- select FSL_LAW
- select SYS_FSL_DDR_VER_47
- select SYS_FSL_ERRATUM_A004468
- select SYS_FSL_ERRATUM_A005871
- select SYS_FSL_ERRATUM_A006379
- select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
- select SYS_FSL_ERRATUM_A007798
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS2
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_PPC64
- select FSL_IFC
- imply CMD_NAND
- imply CMD_REGINFO
-
config ARCH_T4240
bool
select E500MC
@@ -823,8 +793,7 @@ config NXP_ESBC
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
default 12 if ARCH_T4240
- default 8 if ARCH_P4080 || \
- ARCH_T4160
+ default 8 if ARCH_P4080
default 4 if ARCH_B4860 || \
ARCH_P2041 || \
ARCH_P3041 || \
@@ -877,7 +846,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
- ARCH_T4160 || \
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
help
@@ -1062,7 +1030,6 @@ config SYS_FSL_NUM_LAWS
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T2080 || \
- ARCH_T4160 || \
ARCH_T4240
default 16 if ARCH_T1024 || \
ARCH_T1040 || \
@@ -1142,7 +1109,6 @@ config SYS_FSL_IFC_CLK_DIV
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
- ARCH_T4160 || \
ARCH_T4240
default 1
help
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index bbaae0d8454f..993e4873184f 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -42,7 +42,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
-obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
@@ -74,7 +73,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
-obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7d168e3c9a0e..3f2fc062b2b0 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -527,8 +527,7 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
- defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -545,7 +544,7 @@ void fdt_fixup_dma3(void *blob)
case 0x29:
case 0x2d:
case 0x2e:
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index ee5015ec8f3e..5bf0047930fe 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -392,7 +392,7 @@ const char *serdes_clock_to_string(u32 clock)
case SRDS_PLLCR0_RFCK_SEL_161_13:
return "161.1328123";
default:
-#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
+#if defined(CONFIG_TARGET_T4240QDS)
return "???";
#else
return "122.88";
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e6e3f17bb272..e229a5c5a7e0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -126,8 +126,7 @@ void get_sys_info(sys_info_t *sys_info)
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
- defined(CONFIG_ARCH_T2080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index a8c0c47f4af1..61402e84ef62 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_ARCH_T4160)
-static const struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {1, {NONE, NONE, NONE, NONE,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
- {2, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {4, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {27, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {28, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {35, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {36, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {37, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {38, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {}
-};
-static const struct serdes_config serdes2_cfg_tbl[] = {
- /* SerDes 2 */
- {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {37, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {55, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {56, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {57, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {}
-};
-static const struct serdes_config serdes3_cfg_tbl[] = {
- /* SerDes 3 */
- {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {11, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {12, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {15, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {16, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {17, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {}
-};
-static const struct serdes_config serdes4_cfg_tbl[] = {
- /* SerDes 4 */
- {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
- {}
-}
-;
#else
#error "Need to define SerDes protocol"
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 33a3b3a13db7..cfe74bcb84a2 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -184,7 +184,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
@@ -199,9 +199,6 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#if defined(CONFIG_ARCH_T4160)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_SRDS_1
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 991d75312a34..3a1d858ec645 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -21,7 +21,6 @@
#if defined(CONFIG_TARGET_B4860QDS) || \
defined(CONFIG_TARGET_B4420QDS) || \
- defined(CONFIG_TARGET_T4160QDS) || \
defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_TARGET_T2080QDS) || \
defined(CONFIG_TARGET_T2080RDB) || \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 70112c91fc51..f539c0be71ed 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1757,7 +1757,7 @@ typedef struct ccsr_gur {
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1869,7 +1869,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T4240)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index a94a57e7feeb..542e574fed14 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4160RDB || TARGET_T4240RDB
+if TARGET_T4240RDB
config SYS_BOARD
default "t4rdb"
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
index 4ba5c3a546a3..85d8a7ea4cc1 100644
--- a/board/freescale/t4rdb/MAINTAINERS
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -3,6 +3,5 @@ T4RDB BOARD
S: Orphan (since 2018-05)
F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
-F: configs/T4160RDB_defconfig
F: configs/T4240RDB_defconfig
F: configs/T4240RDB_SDCARD_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 209983a24bd1..f1fd623339cb 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -7,7 +7,6 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_TARGET_T4160RDB) += t4240rdb.o
obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o
obj-y += cpld.o
obj-y += eth.o
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
deleted file mode 100644
index 706d6a2367d5..000000000000
--- a/configs/T4160RDB_defconfig
+++ /dev/null
@@ -1,57 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T4160RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xEFF20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SST=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index e6a51f560978..8246f627982c 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -44,8 +44,7 @@ config SYS_NUM_DDR_CTLRS
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_LX2160A || \
- ARCH_LX2162A || \
- ARCH_T4160
+ ARCH_LX2162A
default 1
config SYS_FSL_DDR_VER
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0220dd2a5f2d..e95041447779 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -737,7 +737,6 @@ config SYS_DPAA_QBMAN
ARCH_T1042 || \
ARCH_T2080 || \
ARCH_T4240 || \
- ARCH_T4160 || \
ARCH_P4080 || \
ARCH_P3041 || \
ARCH_P5040 || \
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index c988e4e9257f..ae3841217663 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040.o
obj-$(CONFIG_ARCH_T1024) += t1024.o
obj-$(CONFIG_ARCH_T2080) += t2080.o
obj-$(CONFIG_ARCH_T4240) += t4240.o
-obj-$(CONFIG_ARCH_T4160) += t4240.o
obj-$(CONFIG_ARCH_B4420) += b4860.o
obj-$(CONFIG_ARCH_B4860) += b4860.o
obj-$(CONFIG_ARCH_LS1043A) += ls1043.o
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH 26/27] configs: Remove unnecessary CONFIG_DM_PCI_COMPAT=y
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (23 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 25/27] ppc: Remove T4160RDB board Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-08 2:53 ` Tom Rini
2021-05-15 1:34 ` [PATCH 27/27] pci: Require DM_PCI Tom Rini
2021-07-08 2:51 ` [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
The following boards no longer need CONFIG_DM_PCI_COMPAT enabled, so
remove that.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 -
configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 -
configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 -
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 -
configs/P1010RDB-PA_NAND_defconfig | 1 -
configs/P1010RDB-PA_NOR_defconfig | 1 -
configs/P1010RDB-PA_SDCARD_defconfig | 1 -
configs/P1010RDB-PA_SPIFLASH_defconfig | 1 -
configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 -
configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 -
configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 -
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 -
configs/P1010RDB-PB_NAND_defconfig | 1 -
configs/P1010RDB-PB_NOR_defconfig | 1 -
configs/P1010RDB-PB_SDCARD_defconfig | 1 -
configs/P1010RDB-PB_SPIFLASH_defconfig | 1 -
configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 -
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 -
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 -
configs/P1020RDB-PC_36BIT_defconfig | 1 -
configs/P1020RDB-PC_NAND_defconfig | 1 -
configs/P1020RDB-PC_SDCARD_defconfig | 1 -
configs/P1020RDB-PC_SPIFLASH_defconfig | 1 -
configs/P1020RDB-PC_defconfig | 1 -
configs/P1020RDB-PD_NAND_defconfig | 1 -
configs/P1020RDB-PD_SDCARD_defconfig | 1 -
configs/P1020RDB-PD_SPIFLASH_defconfig | 1 -
configs/P1020RDB-PD_defconfig | 1 -
configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 -
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 -
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 -
configs/P2020RDB-PC_36BIT_defconfig | 1 -
configs/P2020RDB-PC_NAND_defconfig | 1 -
configs/P2020RDB-PC_SDCARD_defconfig | 1 -
configs/P2020RDB-PC_SPIFLASH_defconfig | 1 -
configs/P2020RDB-PC_defconfig | 1 -
configs/P2041RDB_NAND_defconfig | 1 -
configs/P2041RDB_SDCARD_defconfig | 1 -
configs/P2041RDB_SPIFLASH_defconfig | 1 -
configs/P2041RDB_defconfig | 1 -
configs/T1024RDB_NAND_defconfig | 1 -
configs/T1024RDB_SDCARD_defconfig | 1 -
configs/T1024RDB_SPIFLASH_defconfig | 1 -
configs/T1024RDB_defconfig | 1 -
configs/T1042D4RDB_NAND_defconfig | 1 -
configs/T1042D4RDB_SDCARD_defconfig | 1 -
configs/T1042D4RDB_SPIFLASH_defconfig | 1 -
configs/T1042D4RDB_defconfig | 1 -
configs/T2080RDB_NAND_defconfig | 1 -
configs/T2080RDB_SDCARD_defconfig | 1 -
configs/T2080RDB_SPIFLASH_defconfig | 1 -
configs/T2080RDB_defconfig | 1 -
configs/apalis-tk1_defconfig | 1 -
configs/apalis_t30_defconfig | 1 -
configs/beaver_defconfig | 1 -
configs/cardhu_defconfig | 1 -
configs/cei-tk1-som_defconfig | 1 -
configs/durian_defconfig | 1 -
configs/harmony_defconfig | 1 -
configs/jetson-tk1_defconfig | 1 -
configs/kmcent2_defconfig | 1 -
configs/ls1012afrdm_qspi_defconfig | 1 -
configs/ls1012afrdm_tfa_defconfig | 1 -
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 1 -
configs/ls1012afrwy_qspi_defconfig | 1 -
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1012afrwy_tfa_defconfig | 1 -
configs/ls1012aqds_qspi_defconfig | 1 -
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1012aqds_tfa_defconfig | 1 -
configs/ls1012ardb_qspi_defconfig | 1 -
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1012ardb_tfa_defconfig | 1 -
configs/ls1021atsn_qspi_defconfig | 1 -
configs/ls1021atsn_sdcard_defconfig | 1 -
configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 -
configs/ls1021atwr_nor_defconfig | 1 -
configs/ls1021atwr_nor_lpuart_defconfig | 1 -
configs/ls1021atwr_qspi_defconfig | 1 -
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 -
configs/ls1021atwr_sdcard_ifc_defconfig | 1 -
configs/ls1021atwr_sdcard_qspi_defconfig | 1 -
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1028aqds_tfa_defconfig | 1 -
configs/ls1028aqds_tfa_lpuart_defconfig | 1 -
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1028ardb_tfa_defconfig | 1 -
configs/ls1043ardb_SECURE_BOOT_defconfig | 1 -
configs/ls1043ardb_defconfig | 1 -
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 -
configs/ls1043ardb_nand_defconfig | 1 -
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 -
configs/ls1043ardb_sdcard_defconfig | 1 -
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1043ardb_tfa_defconfig | 1 -
configs/ls1046ardb_emmc_defconfig | 1 -
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 -
configs/ls1046ardb_qspi_defconfig | 1 -
configs/ls1046ardb_qspi_spl_defconfig | 1 -
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 -
configs/ls1046ardb_sdcard_defconfig | 1 -
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1046ardb_tfa_defconfig | 1 -
configs/ls1088aqds_tfa_defconfig | 1 -
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 -
configs/ls1088ardb_qspi_defconfig | 1 -
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 -
configs/ls1088ardb_sdcard_qspi_defconfig | 1 -
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1088ardb_tfa_defconfig | 1 -
configs/ls2088aqds_tfa_defconfig | 1 -
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 -
configs/ls2088ardb_qspi_defconfig | 1 -
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls2088ardb_tfa_defconfig | 1 -
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/lx2160aqds_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/lx2160ardb_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_stmm_defconfig | 1 -
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/lx2162aqds_tfa_defconfig | 1 -
configs/lx2162aqds_tfa_verified_boot_defconfig | 1 -
configs/octeontx2_95xx_defconfig | 1 -
configs/octeontx2_96xx_defconfig | 1 -
configs/octeontx_81xx_defconfig | 1 -
configs/octeontx_83xx_defconfig | 1 -
configs/p2371-2180_defconfig | 1 -
configs/p2771-0000-000_defconfig | 1 -
configs/p2771-0000-500_defconfig | 1 -
configs/p3450-0000_defconfig | 1 -
configs/sandbox64_defconfig | 1 -
configs/sandbox_defconfig | 1 -
configs/sandbox_flattree_defconfig | 1 -
configs/sandbox_noinst_defconfig | 1 -
configs/sandbox_spl_defconfig | 1 -
configs/trimslice_defconfig | 1 -
configs/vexpress_aemv8a_juno_defconfig | 1 -
configs/x530_defconfig | 1 -
139 files changed, 139 deletions(-)
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 269a4453b95b..c9b7ea59a197 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -77,7 +77,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 3ac1db0e888c..1e9d40994adc 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -59,7 +59,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index e44e91b1b7c0..1b0364f240be 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -71,7 +71,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index bf612065d608..2fb15d53e118 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -73,7 +73,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 5809b1cd720b..3301008c69c7 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -76,7 +76,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index b8773e0887a1..98c7d032c077 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -58,7 +58,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index e1e7daf62cc2..4333c9492a03 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -70,7 +70,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index 4863d608603b..98611f6ba519 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -72,7 +72,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 1f3f47511638..ca8409dfb5b9 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -77,7 +77,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index db3ee245f461..5749acc4fbc3 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -59,7 +59,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 329bd4b0e4c7..4ff5aa988ca8 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -71,7 +71,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index d639f459e668..eb831086eb46 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -73,7 +73,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index a2bc41c3260f..65e36b10c8dc 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -76,7 +76,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index e8dd323a267b..bc0ab873f5b3 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -58,7 +58,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 709e4ac196e1..fdf03a90efc0 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -70,7 +70,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index e8abb67231ce..8b67fcaf9b60 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -72,7 +72,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 32efb87aa057..5076e5027550 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -77,7 +77,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index c73c9dbedd70..117b267ef719 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -72,7 +72,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index d02bd7562e28..da44c246ac1f 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -74,7 +74,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index fb5285f0ccf4..052b5330480b 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -61,7 +61,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 542805798c3d..969d9063cad8 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -76,7 +76,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 591c2785c39d..d24f70eda165 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -71,7 +71,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 6bccd7c2d088..c44537ecb2f9 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -73,7 +73,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index b59190379e64..2e1b3003fb58 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -60,7 +60,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 8ec246d0f127..cd61f96674aa 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -80,7 +80,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index c9e2f59dfb0c..938616057261 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -75,7 +75,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 2791eefa87d4..b2f3f0d05e26 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -77,7 +77,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index 0e5ce3854827..55357cd76b91 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -64,7 +64,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index f97742830ac3..2166ca8dc04f 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -82,7 +82,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 0e7be2bb9c7b..7e4158e1fb08 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -77,7 +77,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 5c53a702f753..3228a04e9cde 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -79,7 +79,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index 565a537a2b57..fc3ac6b47d13 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -66,7 +66,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index aca3e28da6ea..71105e3bee32 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -81,7 +81,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 3f317fda68a6..fe60c0800f69 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -76,7 +76,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 755674d532c5..ae85403ee27a 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -78,7 +78,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index e49bc114520d..dd344e56e141 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -65,7 +65,6 @@ CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index c434ebd193cb..1eda09747d16 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -56,7 +56,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index e259780d6c0f..171859fe840f 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -55,7 +55,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index a9682df1ca93..1fb6b4346176 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -56,7 +56,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 7b6c0ed756ed..c6cf2d5b8dc6 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -54,7 +54,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index a298779f9743..7f8302655282 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -77,7 +77,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index e4ad73871253..a7edf600c66c 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -74,7 +74,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index c2cda977d910..e3ed6b726b4e 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -76,7 +76,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 05cd138bdcbb..087ea28c8857 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -62,7 +62,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 473b029b8113..fcef59226168 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -73,7 +73,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index cf1f14557fb1..0ad71a54765a 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -70,7 +70,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 15b97a9f988f..2d48370a0abf 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -72,7 +72,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 50713e6ba228..16bc071e3d47 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -58,7 +58,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 2b95637f2c20..ef2dad5e3a00 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -76,7 +76,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_RTC=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index e47234d4d776..5431143d6399 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -73,7 +73,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_RTC=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index d4431d69c737..8a92ddbdb1cb 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -75,7 +75,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_RTC=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 39adbcfefe11..b7facfea5a96 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -60,7 +60,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 5da83e9d1fb6..b651e915df70 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -45,7 +45,6 @@ CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 85f9ce9793b4..b7f588b9d698 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -38,7 +38,6 @@ CONFIG_SYS_I2C_TEGRA=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 4c892443b970..0b73f9b295e7 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -41,7 +41,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index a17ac2b8f459..097ef885fe96 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -35,7 +35,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 987e3ac8e95f..f07470c0933c 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -41,7 +41,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
diff --git a/configs/durian_defconfig b/configs/durian_defconfig
index 171abbfd7cda..e0f90a91bc74 100644
--- a/configs/durian_defconfig
+++ b/configs/durian_defconfig
@@ -27,7 +27,6 @@ CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_PHYTIUM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index bd9201b0f366..72074fe3983a 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -39,7 +39,6 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 74d315d14359..5b99d13c43b2 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -41,7 +41,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_AS3722=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 0c09e2f18869..2480a98be8a0 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -70,7 +70,6 @@ CONFIG_FMAN_ENET=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_FSL=y
CONFIG_U_QE=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 27a73931b550..2690c0b9fd18 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -51,7 +51,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig
index d17f1e28edf6..6539e81909e0 100644
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -51,7 +51,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index eea33d3dcfbd..c1771f2e91bd 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -49,7 +49,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 2d0548b04ea5..06d5c59d9c0f 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -53,7 +53,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 1a8343e67c6b..48ec7f0190a3 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -49,7 +49,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index 64200daec4aa..76d62a99937f 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -53,7 +53,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index cafd0dc58a56..291f48665496 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -69,7 +69,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 7a0e80025ccc..cf8b8885540d 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -57,7 +57,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index ac03940ac9d7..27a98e9e5be8 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -69,7 +69,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF8563=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 20b37ffba03e..694c6935d8a8 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -56,7 +56,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index c8902defe570..e38b4af8082f 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -53,7 +53,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index c460e39d0aa4..b27fbac37198 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -55,7 +55,6 @@ CONFIG_E1000=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 5e0a51c0360c..f0574c05300e 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -50,7 +50,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 47d8781a0f40..1b4a3b09660c 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -61,7 +61,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 38fe10b3319d..bc3b1f927f40 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -52,7 +52,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index e39949999628..adf43eed2284 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -54,7 +54,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 22754f0403dc..4791cb0e8201 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -56,7 +56,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index f3877ed645b4..bcc76a4423f0 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -55,7 +55,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 11d33fd8271f..81a1a9eea315 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -70,7 +70,6 @@ CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index e08fa9caa2c4..f4c4832dd3a5 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -69,7 +69,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 80997a7b6347..16198906565a 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -66,7 +66,6 @@ CONFIG_TSEC_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index b576806b9dd1..a700a976eead 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -67,7 +67,6 @@ CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index bcdb96d0bbe1..2149ffec12d0 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -73,7 +73,6 @@ CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
index e310cfee1d86..30e36162d554 100644
--- a/configs/ls1028aqds_tfa_lpuart_defconfig
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -71,7 +71,6 @@ CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 34cd6fbaab20..64d7cdcaa0bb 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -62,7 +62,6 @@ CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 6ffc3bd39936..c21894bfee6c 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -68,7 +68,6 @@ CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 5e1cfc6f31ed..bbb3d6a48f1f 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -48,7 +48,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index bd7b2db13a7e..80633f4eae53 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -51,7 +51,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 04633bc7b7e4..280313181d6c 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -68,7 +68,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 5c993f3a017a..b2a16f7cfec2 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -69,7 +69,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 1f6087ccd614..3b16d6606e1b 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -70,7 +70,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index c66ec3ba5391..0a98aef4cfc6 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -69,7 +69,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 44cbd76abf44..5572eaa2f741 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -50,7 +50,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 7e53bc4b6536..c6bc154ef8f0 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -56,7 +56,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 68efb1be923d..936ff78b1801 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -68,7 +68,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 3b43fd0ae6dc..1368796a856e 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -50,7 +50,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index a9036dd11ff7..8922b065dcaf 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -54,7 +54,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index a6e464b5c149..390c51edd67a 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -72,7 +72,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 3514f29bfe32..998affe091e1 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -67,7 +67,6 @@ CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index e5a8ad15a879..3e49b2f4609d 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -67,7 +67,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index faa08b2fed49..37634806129d 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -50,7 +50,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 53f13147fa98..ecc6596cfed5 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -56,7 +56,6 @@ CONFIG_FMAN_ENET=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index 5229a351e1a1..b59029d336bd 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -83,7 +83,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index de3759951e19..db409e3ab132 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -60,7 +60,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 0e32aeb6349e..f81a3b9ed9c3 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -63,7 +63,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 7b85bf6174d4..fdcf2b7b6815 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -74,7 +74,6 @@ CONFIG_MII=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index 59469d3b7e72..4ca87b601a26 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -73,7 +73,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 84fbab0f4288..7fb93ad4c64f 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -66,7 +66,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 007a80c2c661..85c9032084e8 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -71,7 +71,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 5620e8a786b5..11de6ab5869f 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -77,7 +77,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 10c139c98ea3..e56f7c0128cc 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -51,7 +51,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 58fc6b238449..e34aada0dd65 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -58,7 +58,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index eed26fa8983a..75d4027ecf20 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -65,7 +65,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index 56cd02418cde..cd4be482e63a 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -73,7 +73,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 54d88c88d59d..f91ec8d0a7d7 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -67,7 +67,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index d25d3e8b98ce..4fb79cd5d2d3 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -74,7 +74,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 1d61807c11ea..b1674724b28c 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -59,7 +59,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index a160cfe21e3e..c60cbe84ef3a 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -68,7 +68,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index 8b69a36dd9d2..7d2ee6c83f4b 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -68,7 +68,6 @@ CONFIG_FSL_LS_MDIO=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_DM_RTC=y
diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
index fcc78c6fe5c4..300168a4d877 100644
--- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -69,7 +69,6 @@ CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index 42a3a3af4466..e000b21ad974 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -77,7 +77,6 @@ CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
index bf0ac38ff232..2b16788838ff 100644
--- a/configs/lx2162aqds_tfa_verified_boot_defconfig
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -78,7 +78,6 @@ CONFIG_MDIO_MUX_I2CREG=y
CONFIG_FSL_LS_MDIO=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index 2402a34dbe81..7be98b936930 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -89,7 +89,6 @@ CONFIG_NET_OCTEONTX2=y
CONFIG_OCTEONTX_SMI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_PCI_ARID=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index 9a34b97ddb0f..ca9d25a34bff 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -103,7 +103,6 @@ CONFIG_OCTEONTX_SMI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_PCI_ARID=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index a63310c18a02..c93298ddf60f 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -105,7 +105,6 @@ CONFIG_OCTEONTX_SMI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_PCI_ARID=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index 07c0d3f873a0..53baf527d7ca 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -102,7 +102,6 @@ CONFIG_OCTEONTX_SMI=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SRIOV=y
CONFIG_PCI_ARID=y
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index c7f4404bbacb..3cbfb50da2cd 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -39,7 +39,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig
index 0ca1fdf381db..b08d2c37a800 100644
--- a/configs/p2771-0000-000_defconfig
+++ b/configs/p2771-0000-000_defconfig
@@ -32,7 +32,6 @@ CONFIG_E1000=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_POWER_DOMAIN=y
CONFIG_TEGRA186_POWER_DOMAIN=y
diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig
index ca340f1bd7dd..8235c775f365 100644
--- a/configs/p2771-0000-500_defconfig
+++ b/configs/p2771-0000-500_defconfig
@@ -32,7 +32,6 @@ CONFIG_E1000=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_POWER_DOMAIN=y
CONFIG_TEGRA186_POWER_DOMAIN=y
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index 6e6a8133b4d4..ee071838aafc 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -41,7 +41,6 @@ CONFIG_RTL8169=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA114_SPI=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 9a373bab6fe3..523b07e05c4e 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -157,7 +157,6 @@ CONFIG_DM_ETH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index bdbf714e2bd9..11cddd690671 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -190,7 +190,6 @@ CONFIG_DM_ETH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 853c9440ea02..758a9c116ccd 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -133,7 +133,6 @@ CONFIG_DM_ETH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index c7fc98b5569a..e66a03bdf3f6 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -153,7 +153,6 @@ CONFIG_DM_ETH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 87223a54d873..d784e91d055a 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -155,7 +155,6 @@ CONFIG_DM_ETH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_SANDBOX=y
CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 6c62197dfd3d..84a12c119cdd 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SFLASH=y
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 7ca95142149b..d73d0d678e20 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -46,7 +46,6 @@ CONFIG_SMC911X=y
CONFIG_SMC911X_32_BIT=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 890c94b5c1fe..a6056d32ff9c 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PCI=y
-CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* [PATCH 27/27] pci: Require DM_PCI
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (24 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 26/27] configs: Remove unnecessary CONFIG_DM_PCI_COMPAT=y Tom Rini
@ 2021-05-15 1:34 ` Tom Rini
2021-07-19 12:25 ` Tom Rini
2021-07-08 2:51 ` [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
26 siblings, 1 reply; 71+ messages in thread
From: Tom Rini @ 2021-05-15 1:34 UTC (permalink / raw)
To: u-boot
As the migration deadline has passed, require that DM_PCI be used.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
.azure-pipelines.yml | 16 -
.gitlab-ci.yml | 28 --
Makefile | 1 -
drivers/pci/Kconfig | 9 +-
drivers/pci/Makefile | 4 -
drivers/pci/pci.c | 588 -------------------------------------
drivers/pci/pci_auto_old.c | 387 ------------------------
7 files changed, 5 insertions(+), 1028 deletions(-)
delete mode 100644 drivers/pci/pci.c
delete mode 100644 drivers/pci/pci_auto_old.c
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 8a567832ddac..438139660219 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -217,22 +217,6 @@ jobs:
qemu_mips64el:
TEST_PY_BD: "qemu_mips64el"
TEST_PY_TEST_SPEC: "not sleep"
- qemu_malta:
- TEST_PY_BD: "malta"
- TEST_PY_ID: "--id qemu"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- qemu_maltael:
- TEST_PY_BD: "maltael"
- TEST_PY_ID: "--id qemu"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- qemu_malta64:
- TEST_PY_BD: "malta64"
- TEST_PY_ID: "--id qemu"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- qemu_malta64el:
- TEST_PY_BD: "malta64el"
- TEST_PY_ID: "--id qemu"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_ppce500:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index bff487404f30..5bf6f151b4fc 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -249,34 +249,6 @@ qemu_mips64el test.py:
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
-qemu_malta test.py:
- variables:
- TEST_PY_BD: "malta"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- TEST_PY_ID: "--id qemu"
- <<: *buildman_and_testpy_dfn
-
-qemu_maltael test.py:
- variables:
- TEST_PY_BD: "maltael"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- TEST_PY_ID: "--id qemu"
- <<: *buildman_and_testpy_dfn
-
-qemu_malta64 test.py:
- variables:
- TEST_PY_BD: "malta64"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- TEST_PY_ID: "--id qemu"
- <<: *buildman_and_testpy_dfn
-
-qemu_malta64el test.py:
- variables:
- TEST_PY_BD: "malta64el"
- TEST_PY_TEST_SPEC: "not sleep and not efi"
- TEST_PY_ID: "--id qemu"
- <<: *buildman_and_testpy_dfn
-
qemu-ppce500 test.py:
variables:
TEST_PY_BD: "qemu-ppce500"
diff --git a/Makefile b/Makefile
index 559594fe1d8f..fea578a639d7 100644
--- a/Makefile
+++ b/Makefile
@@ -1088,7 +1088,6 @@ ifneq ($(CONFIG_DM),y)
endif
$(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
USB,v2019.07,$(CONFIG_USB))
- $(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
$(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\
$(CONFIG_LCD)$(CONFIG_VIDEO))
$(call deprecated,CONFIG_DM_SPI_FLASH,SPI flash,v2019.07,\
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index d5b6018b3d41..7286d31438ff 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,22 +1,23 @@
menuconfig PCI
bool "PCI support"
+ depends on DM
default y if PPC
+ select DM_PCI
help
Enable support for PCI (Peripheral Interconnect Bus), a type of bus
used on some devices to allow the CPU to communicate with its
peripherals.
-if PCI
-
config DM_PCI
- bool "Enable driver model for PCI"
- depends on DM
+ bool
help
Use driver model for PCI. Driver model is the new method for
orgnising devices in U-Boot. For PCI, driver model keeps track of
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
+if PCI
+
config DM_PCI_COMPAT
bool "Enable compatible functions for PCI"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 1f741786a07a..b04d420f996c 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -3,16 +3,12 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_DM_VIDEO) += pci_rom.o
obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o pci_rom.o
-else
-obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
-endif
obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
deleted file mode 100644
index d8f9239523cd..000000000000
--- a/drivers/pci/pci.c
+++ /dev/null
@@ -1,588 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * (C) Copyright 2002, 2003
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-/*
- * Old PCI routines
- *
- * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
- * and change pci-uclass.c.
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <command.h>
-#include <env.h>
-#include <errno.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PCI_HOSE_OP(rw, size, type) \
-int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, \
- int offset, type value) \
-{ \
- return hose->rw##_##size(hose, dev, offset, value); \
-}
-
-PCI_HOSE_OP(read, byte, u8 *)
-PCI_HOSE_OP(read, word, u16 *)
-PCI_HOSE_OP(read, dword, u32 *)
-PCI_HOSE_OP(write, byte, u8)
-PCI_HOSE_OP(write, word, u16)
-PCI_HOSE_OP(write, dword, u32)
-
-#define PCI_OP(rw, size, type, error_code) \
-int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
-{ \
- struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
- \
- if (!hose) \
- { \
- error_code; \
- return -1; \
- } \
- \
- return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
-}
-
-PCI_OP(read, byte, u8 *, *value = 0xff)
-PCI_OP(read, word, u16 *, *value = 0xffff)
-PCI_OP(read, dword, u32 *, *value = 0xffffffff)
-PCI_OP(write, byte, u8, )
-PCI_OP(write, word, u16, )
-PCI_OP(write, dword, u32, )
-
-#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
-int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
- pci_dev_t dev, \
- int offset, type val) \
-{ \
- u32 val32; \
- \
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
- *val = -1; \
- return -1; \
- } \
- \
- *val = (val32 >> ((offset & (int)off_mask) * 8)); \
- \
- return 0; \
-}
-
-#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
-int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
- pci_dev_t dev, \
- int offset, type val) \
-{ \
- u32 val32, mask, ldata, shift; \
- \
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
- return -1; \
- \
- shift = ((offset & (int)off_mask) * 8); \
- ldata = (((unsigned long)val) & val_mask) << shift; \
- mask = val_mask << shift; \
- val32 = (val32 & ~mask) | ldata; \
- \
- if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
- return -1; \
- \
- return 0; \
-}
-
-PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
-PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
-PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
-PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
-
-/*
- *
- */
-
-static struct pci_controller* hose_head;
-
-struct pci_controller *pci_get_hose_head(void)
-{
- if (gd->hose)
- return gd->hose;
-
- return hose_head;
-}
-
-void pci_register_hose(struct pci_controller* hose)
-{
- struct pci_controller **phose = &hose_head;
-
- while(*phose)
- phose = &(*phose)->next;
-
- hose->next = NULL;
-
- *phose = hose;
-}
-
-struct pci_controller *pci_bus_to_hose(int bus)
-{
- struct pci_controller *hose;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- if (bus >= hose->first_busno && bus <= hose->last_busno)
- return hose;
- }
-
- printf("pci_bus_to_hose() failed\n");
- return NULL;
-}
-
-struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
-{
- struct pci_controller *hose;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- if (hose->cfg_addr == cfg_addr)
- return hose;
- }
-
- return NULL;
-}
-
-int pci_last_busno(void)
-{
- struct pci_controller *hose = pci_get_hose_head();
-
- if (!hose)
- return -1;
-
- while (hose->next)
- hose = hose->next;
-
- return hose->last_busno;
-}
-
-pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
-{
- struct pci_controller * hose;
- pci_dev_t bdf;
- int bus;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
- bdf = pci_hose_find_devices(hose, bus, ids, &index);
- if (bdf != -1)
- return bdf;
- }
- }
-
- return -1;
-}
-
-static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
- ulong io, pci_addr_t mem, ulong command)
-{
- u32 bar_response;
- unsigned int old_command;
- pci_addr_t bar_value;
- pci_size_t bar_size;
- unsigned char pin;
- int bar, found_mem64;
-
- debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
- (u64)mem, command);
-
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
-
- for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- if (!bar_response)
- continue;
-
- found_mem64 = 0;
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
- /* round up region base address to a multiple of size */
- io = ((io - 1) | (bar_size - 1)) + 1;
- bar_value = io;
- /* compute new region base address */
- io = io + bar_size;
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- found_mem64 = 1;
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
-
- /* round up region base address to multiple of size */
- mem = ((mem - 1) | (bar_size - 1)) + 1;
- bar_value = mem;
- /* compute new region base address */
- mem = mem + bar_size;
- }
-
- /* Write it out and update our limit */
- pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar,
- (u32)(bar_value >> 32));
-#else
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
- }
-
- /* Configure Cache Line Size Register */
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /* Configure Latency Timer */
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-
- /* Disable interrupt line, if device says it wants to use interrupts */
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
- if (pin != 0) {
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- PCI_INTERRUPT_LINE_DISABLE);
- }
-
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
- (old_command & 0xffff0000) | command);
-
- return 0;
-}
-
-/*
- *
- */
-
-struct pci_config_table *pci_find_config(struct pci_controller *hose,
- unsigned short class,
- unsigned int vendor,
- unsigned int device,
- unsigned int bus,
- unsigned int dev,
- unsigned int func)
-{
- struct pci_config_table *table;
-
- for (table = hose->config_table; table && table->vendor; table++) {
- if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
- (table->device == PCI_ANY_ID || table->device == device) &&
- (table->class == PCI_ANY_ID || table->class == class) &&
- (table->bus == PCI_ANY_ID || table->bus == bus) &&
- (table->dev == PCI_ANY_ID || table->dev == dev) &&
- (table->func == PCI_ANY_ID || table->func == func)) {
- return table;
- }
- }
-
- return NULL;
-}
-
-void pci_cfgfunc_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- struct pci_config_table *entry)
-{
- pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
- entry->priv[2]);
-}
-
-void pci_cfgfunc_do_nothing(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
-}
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
-{
- if (dev == PCI_BDF(hose->first_busno, 0, 0))
- return 0;
-
- return 1;
-}
-#endif /* CONFIG_PCI_SCAN_SHOW */
-
-int pci_hose_scan_bus(struct pci_controller *hose, int bus)
-{
- unsigned int sub_bus, found_multi = 0;
- unsigned short vendor, device, class;
- unsigned char header_type;
-#ifndef CONFIG_PCI_PNP
- struct pci_config_table *cfg;
-#endif
- pci_dev_t dev;
-#ifdef CONFIG_PCI_SCAN_SHOW
- static int indent = 0;
-#endif
-
- sub_bus = bus;
-
- for (dev = PCI_BDF(bus,0,0);
- dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
- dev += PCI_BDF(0, 0, 1)) {
-
- if (pci_skip_dev(hose, dev))
- continue;
-
- if (PCI_FUNC(dev) && !found_multi)
- continue;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
-
- pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
-
- if (vendor == 0xffff || vendor == 0x0000)
- continue;
-
- if (!PCI_FUNC(dev))
- found_multi = header_type & 0x80;
-
- debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
-
- pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
-#ifdef CONFIG_PCI_FIXUP_DEV
- board_pci_fixup_dev(hose, dev, vendor, device, class);
-#endif
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- indent++;
-
- /* Print leading space, including bus indentation */
- printf("%*c", indent + 1, ' ');
-
- if (pci_print_dev(hose, dev)) {
- printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
- PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
- vendor, device, pci_class_str(class >> 8));
- }
-#endif
-
-#ifdef CONFIG_PCI_PNP
- sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
- sub_bus);
-#else
- cfg = pci_find_config(hose, class, vendor, device,
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
- if (cfg) {
- cfg->config_device(hose, dev, cfg);
- sub_bus = max(sub_bus,
- (unsigned int)hose->current_busno);
- }
-#endif
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- indent--;
-#endif
-
- if (hose->fixup_irq)
- hose->fixup_irq(hose, dev);
- }
-
- return sub_bus;
-}
-
-int pci_hose_scan(struct pci_controller *hose)
-{
-#if defined(CONFIG_PCI_BOOTDELAY)
- char *s;
- int i;
-
- if (!gd->pcidelay_done) {
- /* wait "pcidelay" ms (if defined)... */
- s = env_get("pcidelay");
- if (s) {
- int val = simple_strtoul(s, NULL, 10);
- for (i = 0; i < val; i++)
- udelay(1000);
- }
- gd->pcidelay_done = 1;
- }
-#endif /* CONFIG_PCI_BOOTDELAY */
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- puts("PCI:\n");
-#endif
-
- /*
- * Start scan at current_busno.
- * PCIe will start scan at first_busno+1.
- */
- /* For legacy support, ensure current >= first */
- if (hose->first_busno > hose->current_busno)
- hose->current_busno = hose->first_busno;
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(hose);
-#endif
- return pci_hose_scan_bus(hose, hose->current_busno);
-}
-
-int pci_init(void)
-{
- hose_head = NULL;
-
- /* allow env to disable pci init/enum */
- if (env_get("pcidisable") != NULL)
- return 0;
-
- /* now call board specific pci_init()... */
- pci_init_board();
-
- return 0;
-}
-
-/* Returns the address of the requested capability structure within the
- * device's PCI configuration space or 0 in case the device does not
- * support it.
- * */
-int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
- int cap)
-{
- int pos;
- u8 hdr_type;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
-
- pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
-
- if (pos)
- pos = pci_find_cap(hose, dev, pos, cap);
-
- return pos;
-}
-
-/* Find the header pointer to the Capabilities*/
-int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
- u8 hdr_type)
-{
- u16 status;
-
- pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
-
- if (!(status & PCI_STATUS_CAP_LIST))
- return 0;
-
- switch (hdr_type) {
- case PCI_HEADER_TYPE_NORMAL:
- case PCI_HEADER_TYPE_BRIDGE:
- return PCI_CAPABILITY_LIST;
- case PCI_HEADER_TYPE_CARDBUS:
- return PCI_CB_CAPABILITY_LIST;
- default:
- return 0;
- }
-}
-
-int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
-{
- int ttl = PCI_FIND_CAP_TTL;
- u8 id;
- u8 next_pos;
-
- while (ttl--) {
- pci_hose_read_config_byte(hose, dev, pos, &next_pos);
- if (next_pos < CAP_START_POS)
- break;
- next_pos &= ~3;
- pos = (int) next_pos;
- pci_hose_read_config_byte(hose, dev,
- pos + PCI_CAP_LIST_ID, &id);
- if (id == 0xff)
- break;
- if (id == cap)
- return pos;
- pos += PCI_CAP_LIST_NEXT;
- }
- return 0;
-}
-
-/**
- * pci_find_next_ext_capability - Find an extended capability
- *
- * Returns the address of the next matching extended capability structure
- * within the device's PCI configuration space or 0 if the device does
- * not support it. Some capabilities can occur several times, e.g., the
- * vendor-specific capability, and this provides a way to find them all.
- */
-int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
- int start, int cap)
-{
- u32 header;
- int ttl, pos = PCI_CFG_SPACE_SIZE;
-
- /* minimum 8 bytes per capability */
- ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
- if (start)
- pos = start;
-
- pci_hose_read_config_dword(hose, dev, pos, &header);
- if (header == 0xffffffff || header == 0)
- return 0;
-
- while (ttl-- > 0) {
- if (PCI_EXT_CAP_ID(header) == cap && pos != start)
- return pos;
-
- pos = PCI_EXT_CAP_NEXT(header);
- if (pos < PCI_CFG_SPACE_SIZE)
- break;
-
- pci_hose_read_config_dword(hose, dev, pos, &header);
- if (header == 0xffffffff || header == 0)
- break;
- }
-
- return 0;
-}
-
-/**
- * pci_hose_find_ext_capability - Find an extended capability
- *
- * Returns the address of the requested extended capability structure
- * within the device's PCI configuration space or 0 if the device does
- * not support it.
- */
-int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
- int cap)
-{
- return pci_find_next_ext_capability(hose, dev, 0, cap);
-}
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
deleted file mode 100644
index c56ff53c4f9f..000000000000
--- a/drivers/pci/pci_auto_old.c
+++ /dev/null
@@ -1,387 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PCI autoconfiguration library (legacy version, do not change)
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * Copyright 2000 MontaVista Software Inc.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <log.h>
-#include <pci.h>
-
-/*
- * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
- * and change pci_auto.c.
- */
-
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
-#endif
-
-/*
- *
- */
-
-void pciauto_setup_device(struct pci_controller *hose,
- pci_dev_t dev, int bars_num,
- struct pci_region *mem,
- struct pci_region *prefetch,
- struct pci_region *io)
-{
- u32 bar_response;
- pci_size_t bar_size;
- u16 cmdstat = 0;
- int bar, bar_nr = 0;
- u8 header_type;
- int rom_addr;
- pci_addr_t bar_value;
- struct pci_region *bar_res;
- int found_mem64 = 0;
- u16 class;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
-
- for (bar = PCI_BASE_ADDRESS_0;
- bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
- /* Tickle the BAR and get the response */
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- /* If BAR is not implemented go to the next BAR */
- if (!bar_response)
- continue;
-
- found_mem64 = 0;
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
- & 0xffff) + 1;
- bar_res = io;
-
- debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
- bar_nr, (unsigned long long)bar_size);
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
-
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- found_mem64 = 1;
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
- if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
- bar_res = prefetch;
- else
- bar_res = mem;
-
- debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
- bar_nr, bar_res == prefetch ? "Prf" : "Mem",
- (unsigned long long)bar_size);
- }
-
- if (pciauto_region_allocate(bar_res, bar_size,
- &bar_value, found_mem64) == 0) {
- /* Write it out and update our limit */
- pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
-#else
- /*
- * If we are a 64-bit decoder then increment to the
- * upper 32 bits of the bar and force it to locate
- * in the lower 4GB of memory.
- */
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
-
- }
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
-
- debug("\n");
-
- bar_nr++;
- }
-
- /* Configure the expansion ROM address */
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
- header_type &= 0x7f;
- if (header_type != PCI_HEADER_TYPE_CARDBUS) {
- rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
- PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
- pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
- pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
- if (bar_response) {
- bar_size = -(bar_response & ~1);
- debug("PCI Autoconfig: ROM, size=%#x, ",
- (unsigned int)bar_size);
- if (pciauto_region_allocate(mem, bar_size,
- &bar_value, false) == 0) {
- pci_hose_write_config_dword(hose, dev, rom_addr,
- bar_value);
- }
- cmdstat |= PCI_COMMAND_MEMORY;
- debug("\n");
- }
- }
-
- /* PCI_COMMAND_IO must be set for VGA device */
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- if (class == PCI_CLASS_DISPLAY_VGA)
- cmdstat |= PCI_COMMAND_IO;
-
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
- CONFIG_SYS_PCI_CACHE_LINE_SIZE);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-}
-
-void pciauto_prescan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- u16 cmdstat, prefechable_64;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Configure bus number registers */
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
- PCI_BUS(dev) - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
- sub_bus - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
-
- cmdstat |= PCI_COMMAND_MEMORY;
- }
-
- if (pci_prefetch) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- pci_prefetch->bus_lower >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- 0x0);
-#endif
-
- cmdstat |= PCI_COMMAND_MEMORY;
- } else {
- /* We don't support prefetchable memory for now, so disable */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
- pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
- pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
- }
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
- (pci_io->bus_lower & 0xffff0000) >> 16);
-
- cmdstat |= PCI_COMMAND_IO;
- }
-
- /* Enable memory and I/O accesses, enable bus master */
- pci_hose_write_config_word(hose, dev, PCI_COMMAND,
- cmdstat | PCI_COMMAND_MASTER);
-}
-
-void pciauto_postscan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- /* Configure bus number registers */
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
- sub_bus - hose->first_busno);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
- }
-
- if (pci_prefetch) {
- u16 prefechable_64;
-
- pci_hose_read_config_word(hose, dev,
- PCI_PREF_MEMORY_LIMIT,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- (pci_prefetch->bus_lower - 1) >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- 0x0);
-#endif
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
- ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
- }
-}
-
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- unsigned int sub_bus = PCI_BUS(dev);
- unsigned short class;
- int n;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
- switch (class) {
- case PCI_CLASS_BRIDGE_PCI:
- debug("PCI Autoconfig: Found P2P bridge, device %d\n",
- PCI_DEV(dev));
-
- pciauto_setup_device(hose, dev, 2, pci_mem,
- pci_prefetch, pci_io);
-
- /* Passing in current_busno allows for sibling P2P bridges */
- hose->current_busno++;
- pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- /*
- * need to figure out if this is a subordinate bridge on the bus
- * to be able to properly set the pri/sec/sub bridge registers.
- */
- n = pci_hose_scan_bus(hose, hose->current_busno);
-
- /* figure out the deepest we've gone for this leg */
- sub_bus = max((unsigned int)n, sub_bus);
- pciauto_postscan_setup_bridge(hose, dev, sub_bus);
-
- sub_bus = hose->current_busno;
- break;
-
- case PCI_CLASS_BRIDGE_CARDBUS:
- /*
- * just do a minimal setup of the bridge,
- * let the OS take care of the rest
- */
- pciauto_setup_device(hose, dev, 0, pci_mem,
- pci_prefetch, pci_io);
-
- debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
- PCI_DEV(dev));
-
- hose->current_busno++;
- break;
-
-#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
- case PCI_CLASS_BRIDGE_OTHER:
- debug("PCI Autoconfig: Skipping bridge device %d\n",
- PCI_DEV(dev));
- break;
-#endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
- !defined(CONFIG_TARGET_CADDY2)
- case PCI_CLASS_BRIDGE_OTHER:
- /*
- * The host/PCI bridge 1 seems broken in 8349 - it presents
- * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
- * device claiming resources io/mem/irq.. we only allow for
- * the PIMMR window to be allocated (BAR0 - 1MB size)
- */
- debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-#endif
-
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- debug("PCI AutoConfig: Found PowerPC device\n");
-
- default:
- pciauto_setup_device(hose, dev, 6, pci_mem,
- pci_prefetch, pci_io);
- break;
- }
-
- return sub_bus;
-}
--
2.17.1
^ permalink raw reply related [flat|nested] 71+ messages in thread* Re: [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration
2021-05-15 1:34 [PATCH 01/27] pci: Remove non-DM board_pci_fixup_dev() declaration Tom Rini
` (25 preceding siblings ...)
2021-05-15 1:34 ` [PATCH 27/27] pci: Require DM_PCI Tom Rini
@ 2021-07-08 2:51 ` Tom Rini
26 siblings, 0 replies; 71+ messages in thread
From: Tom Rini @ 2021-07-08 2:51 UTC (permalink / raw)
To: u-boot; +Cc: Stefano Babic
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On Fri, May 14, 2021 at 09:34:06PM -0400, Tom Rini wrote:
> With the ventana boards migrated to DM_PCI and DM_ETH, we can remove
> this prototype.
>
> Cc: Stefano Babic <sbabic@denx.de>
> Signed-off-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 71+ messages in thread