* [PATCH v3 01/29] armv8: ls1028a: add IOMMU stream ID to vivante node
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-16 9:53 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 02/29] arm: dts: ls1028a: remove /memory node Michael Walle
` (28 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
The fixup is done for the "fsl,ls1028a-gpu" which isn't any official
device tree binding. Don't break it, but instead add a fixup for another
compatible "vivante,gc" which is the offical one for the GPU on the
LS1028A.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
index 49df8b3790..d93a793f39 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
@@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
+ SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 01/29] armv8: ls1028a: add IOMMU stream ID to vivante node
2021-09-02 16:45 ` [PATCH v3 01/29] armv8: ls1028a: add IOMMU stream ID to vivante node Michael Walle
@ 2021-09-16 9:53 ` Vladimir Oltean
2021-09-16 10:15 ` Michael Walle
0 siblings, 1 reply; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-16 9:53 UTC (permalink / raw)
To: Michael Walle, Andy Tang
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:30PM +0200, Michael Walle wrote:
> The fixup is done for the "fsl,ls1028a-gpu" which isn't any official
> device tree binding. Don't break it, but instead add a fixup for another
> compatible "vivante,gc" which is the offical one for the GPU on the
> LS1028A.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> index 49df8b3790..d93a793f39 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
> @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
> SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
> SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
> SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
> + SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID),
> SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
> SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
> #ifdef CONFIG_FSL_CAAM
> --
> 2.30.2
>
So I have zero tangency with the LS1028A GPU (I've just ordered a
DisplayPort to HDMI adapter so I can test it from now on with my HDMI
capture card), but I think that you know that the "fsl,ls1028a-gpu"
compatible string is for this driver:
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/tree/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx.c?h=LSDK-21.08
which yes, has no upstream equivalent, and will probably never be upstream.
And by the way, every time I boot an upstream kernel with upstream
U-Boot, I get this warning due to the attempted fixup, which is really annoying:
WARNING could not find node fsl,ls1028a-gpu: FDT_ERR_NOTFOUND.
So I personally would not mind if we would just delete anything having
to do with "fsl,ls1028a-gpu" from mainline U-Boot (at least until
something meaningful gets added to Linux which is specific to the
LS1028A) :)
Let me add Andy Tang to the discussion just to make sure that he's aware
of what you're up to:
https://www.spinics.net/lists/kernel/msg4060045.html
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [PATCH v3 01/29] armv8: ls1028a: add IOMMU stream ID to vivante node
2021-09-16 9:53 ` Vladimir Oltean
@ 2021-09-16 10:15 ` Michael Walle
0 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-16 10:15 UTC (permalink / raw)
To: Vladimir Oltean, Andy Tang
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
Am 16. September 2021 11:53:23 MESZ schrieb Vladimir Oltean <vladimir.oltean@nxp.com>:
>On Thu, Sep 02, 2021 at 06:45:30PM +0200, Michael Walle wrote:
>> The fixup is done for the "fsl,ls1028a-gpu" which isn't any official
>> device tree binding. Don't break it, but instead add a fixup for another
>> compatible "vivante,gc" which is the offical one for the GPU on the
>> LS1028A.
>>
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>> arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>> index 49df8b3790..d93a793f39 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
>> @@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
>> SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
>> SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
>> SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
>> + SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID),
>> SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
>> SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
>> #ifdef CONFIG_FSL_CAAM
>> --
>> 2.30.2
>>
>
>So I have zero tangency with the LS1028A GPU (I've just ordered a
>DisplayPort to HDMI adapter so I can test it from now on with my HDMI
>capture card), but I think that you know that the "fsl,ls1028a-gpu"
>compatible string is for this driver:
>https://source.codeaurora.org/external/qoriq/qoriq-components/linux/tree/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx.c?h=LSDK-21.08
>which yes, has no upstream equivalent, and will probably never be upstream.
yes. and for which there is no official binding. that being said i wouldn't want to break things. but i'm fine with (and prefer to) remove that compatible string, too.
>And by the way, every time I boot an upstream kernel with upstream
>U-Boot, I get this warning due to the attempted fixup, which is really annoying:
>
>WARNING could not find node fsl,ls1028a-gpu: FDT_ERR_NOTFOUND.
yep.. and unless we remove this warning, there will be an additional one. and both are not there at the same time..
>
>So I personally would not mind if we would just delete anything having
>to do with "fsl,ls1028a-gpu" from mainline U-Boot (at least until
>something meaningful gets added to Linux which is specific to the
>LS1028A) :)
which is already the case with the etnaviv. theres also a fixup for the LS1027A in u-boot btw (which removes the gpu node)
-michael
>Let me add Andy Tang to the discussion just to make sure that he's aware
>of what you're up to:
>https://www.spinics.net/lists/kernel/msg4060045.html
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 02/29] arm: dts: ls1028a: remove /memory node
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
2021-09-02 16:45 ` [PATCH v3 01/29] armv8: ls1028a: add IOMMU stream ID to vivante node Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-02 16:45 ` [PATCH v3 03/29] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property Michael Walle
` (27 subsequent siblings)
29 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
This node is some hodgepodge between the ddr controller node at SoC
offset 0x1080000 and some static memory size of 2GiB. Remove this bogus
node because it doesn't seem to be used at all.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
arch/arm/dts/fsl-ls1028a.dtsi | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 53b052ed32..48f70c10d9 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -28,12 +28,6 @@
clocks = <&sysclk>;
};
- memory@01080000 {
- device_type = "memory";
- reg = <0x00000000 0x01080000 0 0x80000000>;
- /* DRAM space - 1, size : 2 GB DRAM */
- };
-
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 03/29] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
2021-09-02 16:45 ` [PATCH v3 01/29] armv8: ls1028a: add IOMMU stream ID to vivante node Michael Walle
2021-09-02 16:45 ` [PATCH v3 02/29] arm: dts: ls1028a: remove /memory node Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:43 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 04/29] arm: dts: ls1028a: add an empty /soc Michael Walle
` (26 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
Nowadays, both boards boot using the TF-A BL1/BL2 and SPL isn't used at
all. The property is not needed, remove it.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a-qds.dtsi | 1 -
arch/arm/dts/fsl-ls1028a-rdb.dts | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi
index 69632fa796..335d7b1e4c 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -130,7 +130,6 @@
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
fpga@66 {
#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 82a8c0a0cd..708182f65c 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -61,7 +61,6 @@
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
i2c-mux@77 {
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 03/29] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property
2021-09-02 16:45 ` [PATCH v3 03/29] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property Michael Walle
@ 2021-09-14 23:43 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:43 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:32PM +0200, Michael Walle wrote:
> Nowadays, both boards boot using the TF-A BL1/BL2 and SPL isn't used at
> all. The property is not needed, remove it.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 04/29] arm: dts: ls1028a: add an empty /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (2 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 03/29] arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:43 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 05/29] arm: dts: ls1028a: move the clockgen node into /soc Michael Walle
` (25 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
To keep the device tree similar to the linux kernel one, we need to move
all CCSR related devices into the /soc node. To keep the patches easy to
review, we initially add an empty /soc node and populate it piece by
piece.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 ++++
arch/arm/dts/fsl-ls1028a.dtsi | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
index b3861ed98c..fa4c05212a 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -266,6 +266,10 @@
u-boot,dm-pre-reloc;
};
+&soc {
+ u-boot,dm-pre-reloc;
+};
+
&sysclk {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 48f70c10d9..1f562cfdad 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -478,4 +478,11 @@
compatible = "arm,sp805-wdt";
reg = <0x0 0xc000000 0x0 0x1000>;
};
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ };
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 04/29] arm: dts: ls1028a: add an empty /soc
2021-09-02 16:45 ` [PATCH v3 04/29] arm: dts: ls1028a: add an empty /soc Michael Walle
@ 2021-09-14 23:43 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:43 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:33PM +0200, Michael Walle wrote:
> To keep the device tree similar to the linux kernel one, we need to move
> all CCSR related devices into the /soc node. To keep the patches easy to
> review, we initially add an empty /soc node and populate it piece by
> piece.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 05/29] arm: dts: ls1028a: move the clockgen node into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (3 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 04/29] arm: dts: ls1028a: add an empty /soc Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:44 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 06/29] arm: dts: ls1028a: move I2C controller nodes " Michael Walle
` (24 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
Populate the /soc node with the first device node.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 1f562cfdad..54f97014be 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -21,13 +21,6 @@
clock-output-names = "sysclk";
};
- clockgen: clocking@1300000 {
- compatible = "fsl,ls1028a-clockgen";
- reg = <0x0 0x1300000 0x0 0xa0000>;
- #clock-cells = <2>;
- clocks = <&sysclk>;
- };
-
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
@@ -484,5 +477,12 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+
+ clockgen: clocking@1300000 {
+ compatible = "fsl,ls1028a-clockgen";
+ reg = <0x0 0x1300000 0x0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 06/29] arm: dts: ls1028a: move I2C controller nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (4 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 05/29] arm: dts: ls1028a: move the clockgen node into /soc Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:47 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 07/29] arm: dts: ls1028a: move the FlexSPI controller node Michael Walle
` (23 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
.../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 +-
.../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 +-
.../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 2 +-
.../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 8 +-
.../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 8 +-
.../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 8 +-
.../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 8 +-
.../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +-
arch/arm/dts/fsl-ls1028a.dtsi | 176 +++++++++---------
12 files changed, 115 insertions(+), 115 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
index 23816da8ee..181fd2ddcb 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
@@ -16,5 +16,5 @@
&enetc0 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
index c6558ae2e0..67b68f1b3d 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
@@ -15,5 +15,5 @@
&enetc0 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
index 5a0f060c16..433731df0e 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -31,25 +31,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
index 39a83e10c4..cb74c8b371 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -20,13 +20,13 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
index 7d4702e4ff..979c0ddd48 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
@@ -15,5 +15,5 @@
&enetc0 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
index 021fe3fbc6..f74c1433af 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -45,25 +45,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
index b6704d8089..4edc428b27 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -30,25 +30,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
index 8c10897e56..7fefb4c99f 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -30,25 +30,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "usxgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
index 1d800dacef..223145756a 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -24,25 +24,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "qsgmii";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
index 1fb2cdf0c2..1834418ae2 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -20,7 +20,7 @@
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
index 2333f74e5a..2ee11bcacb 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -20,7 +20,7 @@
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
- phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
+ phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};
&mscc_felix_port4 {
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 54f97014be..de85fdd045 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -203,94 +203,6 @@
};
};
- i2c0: i2c@2000000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c1: i2c@2010000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2010000 0x0 0x10000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c2: i2c@2020000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2020000 0x0 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c3: i2c@2030000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2030000 0x0 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c4: i2c@2040000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2040000 0x0 0x10000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c5: i2c@2050000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2050000 0x0 0x10000>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c6: i2c@2060000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2060000 0x0 0x10000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
- i2c7: i2c@2070000 {
- compatible = "fsl,vf610-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2070000 0x0 0x10000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
- status = "disabled";
- };
-
lpuart0: serial@2260000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
@@ -484,5 +396,93 @@
#clock-cells = <2>;
clocks = <&sysclk>;
};
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 0>;
+ status = "disabled";
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 06/29] arm: dts: ls1028a: move I2C controller nodes into /soc
2021-09-02 16:45 ` [PATCH v3 06/29] arm: dts: ls1028a: move I2C controller nodes " Michael Walle
@ 2021-09-14 23:47 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:47 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:35PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 07/29] arm: dts: ls1028a: move the FlexSPI controller node
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (5 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 06/29] arm: dts: ls1028a: move I2C controller nodes " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:47 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 08/29] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc Michael Walle
` (22 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting it into the new location, keep it sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index de85fdd045..6d80b32816 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -43,19 +43,6 @@
IRQ_TYPE_LEVEL_LOW)>;
};
- fspi: flexspi@20c0000 {
- compatible = "nxp,lx2160a-fspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x20c0000 0x0 0x10000>,
- <0x0 0x20000000 0x0 0x10000000>;
- reg-names = "fspi_base", "fspi_mmap";
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
- clock-names = "fspi_en", "fspi";
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
@@ -484,5 +471,18 @@
clocks = <&clockgen 4 0>;
status = "disabled";
};
+
+ fspi: flexspi@20c0000 {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "fspi_en", "fspi";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 07/29] arm: dts: ls1028a: move the FlexSPI controller node
2021-09-02 16:45 ` [PATCH v3 07/29] arm: dts: ls1028a: move the FlexSPI controller node Michael Walle
@ 2021-09-14 23:47 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:47 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:36PM +0200, Michael Walle wrote:
> While inserting it into the new location, keep it sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 08/29] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (6 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 07/29] arm: dts: ls1028a: move the FlexSPI controller node Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:48 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 09/29] arm: dts: ls1028a: move the UART " Michael Walle
` (21 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 116 +++++++++++++++++-----------------
1 file changed, 58 insertions(+), 58 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 6d80b32816..ecafa67d08 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -266,64 +266,6 @@
status = "disabled";
};
- dspi0: dspi@2100000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2100000 0x0 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- num-cs = <5>;
- litte-endian;
- status = "disabled";
- };
-
- dspi1: dspi@2110000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2110000 0x0 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- num-cs = <5>;
- little-endian;
- status = "disabled";
- };
-
- dspi2: dspi@2120000 {
- compatible = "fsl,vf610-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x2120000 0x0 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- num-cs = <5>;
- little-endian;
- status = "disabled";
- };
-
- esdhc0: esdhc@2140000 {
- compatible = "fsl,esdhc";
- reg = <0x0 0x2140000 0x0 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
- bus-width = <4>;
- status = "disabled";
- };
-
- esdhc1: esdhc@2150000 {
- compatible = "fsl,esdhc";
- reg = <0x0 0x2150000 0x0 0x10000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
- non-removable;
- bus-width = <4>;
- status = "disabled";
- };
-
gpio0: gpio@2300000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
@@ -484,5 +426,63 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ dspi0: dspi@2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <5>;
+ litte-endian;
+ status = "disabled";
+ };
+
+ dspi1: dspi@2110000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <5>;
+ little-endian;
+ status = "disabled";
+ };
+
+ dspi2: dspi@2120000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dspi";
+ clocks = <&clockgen 4 0>;
+ num-cs = <5>;
+ little-endian;
+ status = "disabled";
+ };
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ non-removable;
+ bus-width = <4>;
+ status = "disabled";
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 08/29] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc
2021-09-02 16:45 ` [PATCH v3 08/29] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc Michael Walle
@ 2021-09-14 23:48 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:48 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:37PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 09/29] arm: dts: ls1028a: move the UART controller nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (7 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 08/29] arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:49 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 10/29] arm: dts: ls1028a: move the low-power UART " Michael Walle
` (20 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index ecafa67d08..07aeb380ef 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -43,22 +43,6 @@
IRQ_TYPE_LEVEL_LOW)>;
};
- serial0: serial@21c0500 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- serial1: serial@21c0600 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000
@@ -484,5 +468,21 @@
bus-width = <4>;
status = "disabled";
};
+
+ serial0: serial@21c0500 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ serial1: serial@21c0600 {
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 09/29] arm: dts: ls1028a: move the UART controller nodes into /soc
2021-09-02 16:45 ` [PATCH v3 09/29] arm: dts: ls1028a: move the UART " Michael Walle
@ 2021-09-14 23:49 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:49 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:38PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 10/29] arm: dts: ls1028a: move the low-power UART nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (8 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 09/29] arm: dts: ls1028a: move the UART " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:50 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 11/29] arm: dts: ls1028a: move the GPIO controller " Michael Walle
` (19 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 120 +++++++++++++++++-----------------
1 file changed, 60 insertions(+), 60 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 07aeb380ef..349c4bf862 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -174,66 +174,6 @@
};
};
- lpuart0: serial@2260000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2260000 0x0 0x1000>;
- interrupts = <0 232 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
-
- lpuart1: serial@2270000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2270000 0x0 0x1000>;
- interrupts = <0 233 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
-
- lpuart2: serial@2280000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2280000 0x0 0x1000>;
- interrupts = <0 234 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
-
- lpuart3: serial@2290000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x2290000 0x0 0x1000>;
- interrupts = <0 235 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
-
- lpuart4: serial@22a0000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x22a0000 0x0 0x1000>;
- interrupts = <0 236 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
-
- lpuart5: serial@22b0000 {
- compatible = "fsl,ls1021a-lpuart";
- reg = <0x0 0x22b0000 0x0 0x1000>;
- interrupts = <0 237 0x4>;
- clocks = <&sysclk>;
- clock-names = "ipg";
- little-endian;
- status = "disabled";
- };
-
usb1: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
@@ -484,5 +424,65 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ lpuart0: serial@2260000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2260000 0x0 0x1000>;
+ interrupts = <0 232 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart1: serial@2270000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2270000 0x0 0x1000>;
+ interrupts = <0 233 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart2: serial@2280000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2280000 0x0 0x1000>;
+ interrupts = <0 234 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart3: serial@2290000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x2290000 0x0 0x1000>;
+ interrupts = <0 235 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart4: serial@22a0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x22a0000 0x0 0x1000>;
+ interrupts = <0 236 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
+
+ lpuart5: serial@22b0000 {
+ compatible = "fsl,ls1021a-lpuart";
+ reg = <0x0 0x22b0000 0x0 0x1000>;
+ interrupts = <0 237 0x4>;
+ clocks = <&sysclk>;
+ clock-names = "ipg";
+ little-endian;
+ status = "disabled";
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 10/29] arm: dts: ls1028a: move the low-power UART nodes into /soc
2021-09-02 16:45 ` [PATCH v3 10/29] arm: dts: ls1028a: move the low-power UART " Michael Walle
@ 2021-09-14 23:50 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:50 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:39PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 11/29] arm: dts: ls1028a: move the GPIO controller nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (9 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 10/29] arm: dts: ls1028a: move the low-power UART " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:51 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 12/29] arm: dts: ls1028a: move SATA and USB " Michael Walle
` (18 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 66 +++++++++++++++++------------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 349c4bf862..9f466554e9 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -190,39 +190,6 @@
status = "disabled";
};
- gpio0: gpio@2300000 {
- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
- reg = <0x0 0x2300000 0x0 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
- };
-
- gpio1: gpio@2310000 {
- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
- reg = <0x0 0x2310000 0x0 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
- };
-
- gpio2: gpio@2320000 {
- compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
- reg = <0x0 0x2320000 0x0 0x10000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- little-endian;
- };
-
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
@@ -484,5 +451,38 @@
little-endian;
status = "disabled";
};
+
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 11/29] arm: dts: ls1028a: move the GPIO controller nodes into /soc
2021-09-02 16:45 ` [PATCH v3 11/29] arm: dts: ls1028a: move the GPIO controller " Michael Walle
@ 2021-09-14 23:51 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:51 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:40PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 12/29] arm: dts: ls1028a: move SATA and USB controller nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (10 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 11/29] arm: dts: ls1028a: move the GPIO controller " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:52 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 13/29] arm: dts: ls1028a: move the PCIe " Michael Walle
` (17 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 50 +++++++++++++++++------------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 9f466554e9..7d18085615 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -174,31 +174,6 @@
};
};
- usb1: usb3@3100000 {
- compatible = "fsl,layerscape-dwc3";
- reg = <0x0 0x3100000 0x0 0x10000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- status = "disabled";
- };
-
- usb2: usb3@3110000 {
- compatible = "fsl,layerscape-dwc3";
- reg = <0x0 0x3110000 0x0 0x10000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- status = "disabled";
- };
-
- sata: sata@3200000 {
- compatible = "fsl,ls1028a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
- 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt";
reg = <0x0 0xc000000 0x0 0x1000>;
@@ -484,5 +459,30 @@
#interrupt-cells = <2>;
little-endian;
};
+
+ usb1: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ usb2: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1028a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
+ reg-names = "sata-base", "ecc-addr";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 12/29] arm: dts: ls1028a: move SATA and USB controller nodes into /soc
2021-09-02 16:45 ` [PATCH v3 12/29] arm: dts: ls1028a: move SATA and USB " Michael Walle
@ 2021-09-14 23:52 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:52 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:41PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 13/29] arm: dts: ls1028a: move the PCIe controller nodes into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (11 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 12/29] arm: dts: ls1028a: move SATA and USB " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:53 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 14/29] arm: dts: ls1028a: move the watchdog node " Michael Walle
` (16 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
While at it fix the indentation.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 64 +++++++++++++++++------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 7d18085615..d0f90941b9 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -43,38 +43,6 @@
IRQ_TYPE_LEVEL_LOW)>;
};
- pcie1: pcie@3400000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03400000 0x0 0x80000
- 0x00 0x03480000 0x0 0x40000 /* lut registers */
- 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
- 0x80 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- };
-
- pcie2: pcie@3500000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03500000 0x0 0x80000
- 0x00 0x03580000 0x0 0x40000 /* lut registers */
- 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
- 0x88 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <4>;
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
- 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
- };
-
pcie@1f0000000 {
compatible = "pci-host-ecam-generic";
/* ECAM bus 0, HW has more space reserved but not populated */
@@ -484,5 +452,37 @@
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ pcie1: pcie@3400000 {
+ compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000
+ 0x00 0x03480000 0x0 0x40000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x80 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie2: pcie@3500000 {
+ compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000
+ 0x00 0x03580000 0x0 0x40000 /* lut registers */
+ 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
+ 0x88 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 13/29] arm: dts: ls1028a: move the PCIe controller nodes into /soc
2021-09-02 16:45 ` [PATCH v3 13/29] arm: dts: ls1028a: move the PCIe " Michael Walle
@ 2021-09-14 23:53 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:53 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:42PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> While at it fix the indentation.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/dts/fsl-ls1028a.dtsi | 64 +++++++++++++++++------------------
> 1 file changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
> index 7d18085615..d0f90941b9 100644
> --- a/arch/arm/dts/fsl-ls1028a.dtsi
> +++ b/arch/arm/dts/fsl-ls1028a.dtsi
> @@ -43,38 +43,6 @@
> IRQ_TYPE_LEVEL_LOW)>;
> };
>
> - pcie1: pcie@3400000 {
> - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
> - reg = <0x00 0x03400000 0x0 0x80000
> - 0x00 0x03480000 0x0 0x40000 /* lut registers */
> - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
> - 0x80 0x00000000 0x0 0x20000>; /* configuration space */
> - reg-names = "dbi", "lut", "ctrl", "config";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - num-lanes = <4>;
> - bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
> - 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> - };
> -
> - pcie2: pcie@3500000 {
> - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
> - reg = <0x00 0x03500000 0x0 0x80000
> - 0x00 0x03580000 0x0 0x40000 /* lut registers */
> - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
> - 0x88 0x00000000 0x0 0x20000>; /* configuration space */
> - reg-names = "dbi", "lut", "ctrl", "config";
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - num-lanes = <4>;
> - bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
> - 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> - };
Impossible for me to understand how somebody could have gotten it that wrong.
> -
> pcie@1f0000000 {
> compatible = "pci-host-ecam-generic";
> /* ECAM bus 0, HW has more space reserved but not populated */
> @@ -484,5 +452,37 @@
> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
> +
> + pcie1: pcie@3400000 {
> + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03400000 0x0 0x80000
> + 0x00 0x03480000 0x0 0x40000 /* lut registers */
> + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
> + 0x80 0x00000000 0x0 0x20000>; /* configuration space */
> + reg-names = "dbi", "lut", "ctrl", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + };
> +
> + pcie2: pcie@3500000 {
> + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
> + reg = <0x00 0x03500000 0x0 0x80000
> + 0x00 0x03580000 0x0 0x40000 /* lut registers */
> + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
> + 0x88 0x00000000 0x0 0x20000>; /* configuration space */
> + reg-names = "dbi", "lut", "ctrl", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
> + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> + };
> };
> };
> --
> 2.30.2
>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 14/29] arm: dts: ls1028a: move the watchdog node into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (12 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 13/29] arm: dts: ls1028a: move the PCIe " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:54 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 15/29] arm: dts: ls1028a: move the iRC node and its devices " Michael Walle
` (15 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting it into the new location, keep it sorted by the
register base offset just like in the linux kernel device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index d0f90941b9..c289009ca1 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -142,11 +142,6 @@
};
};
- cluster1_core0_watchdog: wdt@c000000 {
- compatible = "arm,sp805-wdt";
- reg = <0x0 0xc000000 0x0 0x1000>;
- };
-
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -484,5 +479,10 @@
ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
+
+ cluster1_core0_watchdog: wdt@c000000 {
+ compatible = "arm,sp805-wdt";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 14/29] arm: dts: ls1028a: move the watchdog node into /soc
2021-09-02 16:45 ` [PATCH v3 14/29] arm: dts: ls1028a: move the watchdog node " Michael Walle
@ 2021-09-14 23:54 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:54 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:43PM +0200, Michael Walle wrote:
> While inserting it into the new location, keep it sorted by the
> register base offset just like in the linux kernel device tree.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 15/29] arm: dts: ls1028a: move the iRC node and its devices into /soc
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (13 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 14/29] arm: dts: ls1028a: move the watchdog node " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-14 23:56 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 16/29] arm: dts: ls1028a: update the labels Michael Walle
` (14 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.
While at it fix the indentation.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 202 +++++++++++++++++-----------------
1 file changed, 103 insertions(+), 99 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index c289009ca1..ca593c7218 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -43,105 +43,6 @@
IRQ_TYPE_LEVEL_LOW)>;
};
- pcie@1f0000000 {
- compatible = "pci-host-ecam-generic";
- /* ECAM bus 0, HW has more space reserved but not populated */
- bus-range = <0x0 0x0>;
- reg = <0x01 0xf0000000 0x0 0x100000>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
- enetc0: pci@0,0 {
- reg = <0x000000 0 0 0 0>;
- status = "disabled";
- };
- enetc1: pci@0,1 {
- reg = <0x000100 0 0 0 0>;
- status = "disabled";
- };
- enetc2: pci@0,2 {
- reg = <0x000200 0 0 0 0>;
- status = "disabled";
- phy-mode = "internal";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
- };
- mdio0: pci@0,3 {
- #address-cells=<0>;
- #size-cells=<1>;
- reg = <0x000300 0 0 0 0>;
- status = "disabled";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- mscc_felix: pci@0,5 {
- reg = <0x000500 0 0 0 0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mscc_felix_port0: port@0 {
- reg = <0>;
- status = "disabled";
- };
-
- mscc_felix_port1: port@1 {
- reg = <1>;
- status = "disabled";
- };
-
- mscc_felix_port2: port@2 {
- reg = <2>;
- status = "disabled";
- };
-
- mscc_felix_port3: port@3 {
- reg = <3>;
- status = "disabled";
- };
-
- mscc_felix_port4: port@4 {
- reg = <4>;
- phy-mode = "internal";
- status = "disabled";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
- };
-
- mscc_felix_port5: port@5 {
- reg = <5>;
- phy-mode = "internal";
- status = "disabled";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-
- };
- };
- };
-
- enetc6: pci@0,6 {
- reg = <0x000600 0 0 0 0>;
- status = "disabled";
- phy-mode = "internal";
- };
- };
-
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -484,5 +385,108 @@
compatible = "arm,sp805-wdt";
reg = <0x0 0xc000000 0x0 0x1000>;
};
+
+ pcie@1f0000000 {
+ compatible = "pci-host-ecam-generic";
+ /* ECAM bus 0, HW has more space reserved but not populated */
+ bus-range = <0x0 0x0>;
+ reg = <0x01 0xf0000000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
+
+ enetc0: pci@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ status = "disabled";
+ };
+
+ enetc1: pci@0,1 {
+ reg = <0x000100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ enetc2: pci@0,2 {
+ reg = <0x000200 0 0 0 0>;
+ status = "disabled";
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ mdio0: pci@0,3 {
+ #address-cells=<0>;
+ #size-cells=<1>;
+ reg = <0x000300 0 0 0 0>;
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ mscc_felix: pci@0,5 {
+ reg = <0x000500 0 0 0 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mscc_felix_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ mscc_felix_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ mscc_felix_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ mscc_felix_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ mscc_felix_port4: port@4 {
+ reg = <4>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ mscc_felix_port5: port@5 {
+ reg = <5>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+ };
+ };
+
+ enetc6: pci@0,6 {
+ reg = <0x000600 0 0 0 0>;
+ status = "disabled";
+ phy-mode = "internal";
+ };
+ };
};
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 15/29] arm: dts: ls1028a: move the iRC node and its devices into /soc
2021-09-02 16:45 ` [PATCH v3 15/29] arm: dts: ls1028a: move the iRC node and its devices " Michael Walle
@ 2021-09-14 23:56 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-14 23:56 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:44PM +0200, Michael Walle wrote:
> While inserting them into the new location, keep them sorted by the
> register base offset just like in the linux kernel device tree.
>
> While at it fix the indentation.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 16/29] arm: dts: ls1028a: update the labels
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (14 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 15/29] arm: dts: ls1028a: move the iRC node and its devices " Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:02 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 17/29] watchdog: sp805_wdt: use correct compatible string Michael Walle
` (13 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
Update the labels of the nodes to match the kernel ones.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Vladimir, this has changed due to the sorted nodes now. It should be the
same, but maybe you should retest it.
.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 10 +++----
.../fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi | 2 +-
.../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 6 ++---
.../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 8 +++---
.../fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi | 2 +-
.../fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi | 4 +--
.../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 4 +--
arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 22 ++++++++--------
.../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 4 +--
.../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 +--
.../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 2 +-
.../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 4 +--
.../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 4 +--
arch/arm/dts/fsl-ls1028a-qds-duart.dts | 2 +-
.../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 4 +--
.../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 4 +--
.../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 4 +--
.../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 4 +--
arch/arm/dts/fsl-ls1028a-qds.dtsi | 16 ++++++------
arch/arm/dts/fsl-ls1028a-rdb.dts | 22 ++++++++--------
arch/arm/dts/fsl-ls1028a.dtsi | 26 +++++++++----------
23 files changed, 81 insertions(+), 81 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
index fa4c05212a..42bd3138b2 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -5,13 +5,13 @@
/ {
aliases {
mmc0 = &esdhc1;
- mmc1 = &esdhc0;
+ mmc1 = &esdhc;
i2c0 = &i2c0;
i2c1 = &i2c3;
i2c2 = &i2c4;
rtc0 = &rtc;
- ethernet2 = &enetc2;
- ethernet3 = &enetc6;
+ ethernet2 = &enetc_port2;
+ ethernet3 = &enetc_port3;
};
binman: binman {
@@ -250,7 +250,7 @@
u-boot,dm-pre-reloc;
};
-&esdhc0 {
+&esdhc {
u-boot,dm-pre-reloc;
};
@@ -262,7 +262,7 @@
u-boot,dm-pre-reloc;
};
-&serial0 {
+&duart0 {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi
index 98e8939369..a46e07dc6b 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi
@@ -3,6 +3,6 @@
/ {
aliases {
- ethernet0 = &enetc1;
+ ethernet0 = &enetc_port1;
};
};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
index 33d85ed83a..ba2e4de96d 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
@@ -21,19 +21,19 @@
compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};
-&enetc0 {
+&enetc_port0 {
status = "disabled";
/delete-property/ phy-handle;
};
-&enetc1 {
+&enetc_port1 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
/delete-node/ &phy0;
-&mdio0 {
+&enetc_mdio_pf3 {
phy0: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
index 7a3aa21408..db80874f4e 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
@@ -17,12 +17,12 @@
compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
};
-&enetc0 {
+&enetc_port0 {
status = "disabled";
/delete-property/ phy-handle;
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -45,12 +45,12 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
/delete-node/ &phy0;
-&mdio0 {
+&enetc_mdio_pf3 {
phy0: ethernet-phy@5 {
reg = <0x5>;
eee-broken-1000t;
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
index 879a76415b..3d6bf5a0bd 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var3-u-boot.dtsi
@@ -3,6 +3,6 @@
/ {
aliases {
- ethernet0 = &enetc0;
+ ethernet0 = &enetc_port0;
};
};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
index fce4694682..5d82973bba 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4-u-boot.dtsi
@@ -3,7 +3,7 @@
/ {
aliases {
- ethernet0 = &enetc0;
- ethernet1 = &enetc1;
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port1;
};
};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
index b95e082b70..54d12ab992 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
@@ -18,13 +18,13 @@
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};
-&enetc1 {
+&enetc_port1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};
-&mdio0 {
+&enetc_mdio_pf3 {
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
index 7f237c39ec..9ae70ba541 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
@@ -14,8 +14,8 @@
compatible = "kontron,sl28", "fsl,ls1028a";
aliases {
- serial0 = &serial0;
- serial1 = &serial1;
+ serial0 = &duart0;
+ serial1 = &duart1;
serial2 = &lpuart1;
spi0 = &fspi;
spi1 = &dspi2;
@@ -30,21 +30,21 @@
status = "okay";
};
-&enetc0 {
+&enetc_port0 {
phy-handle = <&phy0>;
phy-mode = "sgmii";
status = "okay";
};
-&enetc2 {
+&enetc_port2 {
status = "disabled";
};
-&enetc6 {
+&enetc_port3 {
status = "disabled";
};
-&esdhc0 {
+&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
@@ -108,7 +108,7 @@
status = "okay";
};
-&mdio0 {
+&enetc_mdio_pf3 {
status = "okay";
phy0: ethernet-phy@5 {
reg = <0x5>;
@@ -121,18 +121,18 @@
status = "okay";
};
-&serial0 {
+&duart0 {
status = "okay";
};
-&serial1 {
+&duart1 {
status = "okay";
};
-&usb1 {
+&usb0 {
status = "okay";
};
-&usb2 {
+&usb1 {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
index 181fd2ddcb..68e048966f 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
@@ -13,7 +13,7 @@
#include "fsl-sch-30842.dtsi"
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
index 67b68f1b3d..297ffa8878 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
@@ -12,7 +12,7 @@
#include "fsl-sch-30842.dtsi"
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
index 433731df0e..4b935412cd 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -20,7 +20,7 @@
#include "fsl-sch-30841.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -53,6 +53,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
index cb74c8b371..2c0012bcb4 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -9,7 +9,7 @@
#include "fsl-sch-30841.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -30,6 +30,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
index 979c0ddd48..5e4b359205 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
@@ -12,7 +12,7 @@
#include "fsl-sch-24801.dtsi"
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
index f74c1433af..ce35f3567a 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -34,7 +34,7 @@
#include "fsl-sch-24801.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -67,6 +67,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
index 4edc428b27..cd8c9a34a0 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -19,7 +19,7 @@
#include "fsl-sch-24801.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -52,6 +52,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-duart.dts b/arch/arm/dts/fsl-ls1028a-qds-duart.dts
index 83264e0f54..81db21a947 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-duart.dts
+++ b/arch/arm/dts/fsl-ls1028a-qds-duart.dts
@@ -10,6 +10,6 @@
/ {
chosen {
- stdout-path = &serial0;
+ stdout-path = &duart0;
};
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
index 7fefb4c99f..6d089a401c 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -19,7 +19,7 @@
#include "fsl-sch-30841.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -52,6 +52,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
index 223145756a..2675901fca 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -13,7 +13,7 @@
#include "fsl-sch-28021.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -46,6 +46,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
index 1834418ae2..23e2a298bb 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -9,7 +9,7 @@
#include "fsl-sch-30842.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -24,6 +24,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
index 2ee11bcacb..a61058446d 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -9,7 +9,7 @@
#include "fsl-sch-30842.dtsi"
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -24,6 +24,6 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi
index 335d7b1e4c..babd8445ee 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -105,7 +105,7 @@
};
};
-&esdhc0 {
+&esdhc {
status = "okay";
};
@@ -144,7 +144,7 @@
reg = <0x54>;
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf0>;
- mdio-parent-bus = <&mdio0>;
+ mdio-parent-bus = <&enetc_mdio_pf3>;
/* on-board MDIO with a single RGMII PHY */
mdio@00 {
@@ -232,29 +232,29 @@
status = "okay";
};
-&serial0 {
+&duart0 {
status = "okay";
};
-&serial1 {
+&duart1 {
status = "okay";
};
-&usb1 {
+&usb0 {
status = "okay";
};
-&usb2 {
+&usb1 {
status = "okay";
};
-&enetc1 {
+&enetc_port1 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&qds_phy0>;
};
-&mdio0 {
+&enetc_mdio_pf3 {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 708182f65c..18ee363d75 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -15,8 +15,8 @@
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
aliases {
spi0 = &fspi;
- ethernet0 = &enetc0;
- ethernet1 = &enetc2;
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port2;
ethernet2 = &mscc_felix_port0;
ethernet3 = &mscc_felix_port1;
ethernet4 = &mscc_felix_port2;
@@ -36,7 +36,7 @@
status = "okay";
};
-&esdhc0 {
+&esdhc {
status = "okay";
};
@@ -114,29 +114,29 @@
status = "okay";
};
-&serial0 {
+&duart0 {
status = "okay";
};
-&serial1 {
+&duart1 {
status = "okay";
};
-&usb1 {
+&usb0 {
status = "okay";
};
-&usb2 {
+&usb1 {
status = "okay";
};
-&enetc0 {
+&enetc_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&rdb_phy0>;
};
-&enetc2 {
+&enetc_port2 {
status = "okay";
};
@@ -173,11 +173,11 @@
};
&mscc_felix_port4 {
- ethernet = <&enetc2>;
+ ethernet = <&enetc_port2>;
status = "okay";
};
-&mdio0 {
+&enetc_mdio_pf3 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index ca593c7218..e5b5a0dc9f 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -196,7 +196,7 @@
status = "disabled";
};
- esdhc0: esdhc@2140000 {
+ esdhc: esdhc@2140000 {
compatible = "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -215,7 +215,7 @@
status = "disabled";
};
- serial0: serial@21c0500 {
+ duart0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
@@ -223,7 +223,7 @@
status = "disabled";
};
- serial1: serial@21c0600 {
+ duart1: serial@21c0600 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
@@ -291,7 +291,7 @@
status = "disabled";
};
- gpio0: gpio@2300000 {
+ gpio1: gpio@2300000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -302,7 +302,7 @@
little-endian;
};
- gpio1: gpio@2310000 {
+ gpio2: gpio@2310000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2310000 0x0 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -313,7 +313,7 @@
little-endian;
};
- gpio2: gpio@2320000 {
+ gpio3: gpio@2320000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -324,7 +324,7 @@
little-endian;
};
- usb1: usb3@3100000 {
+ usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
@@ -332,7 +332,7 @@
status = "disabled";
};
- usb2: usb3@3110000 {
+ usb1: usb3@3110000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -396,17 +396,17 @@
device_type = "pci";
ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
- enetc0: pci@0,0 {
+ enetc_port0: pci@0,0 {
reg = <0x000000 0 0 0 0>;
status = "disabled";
};
- enetc1: pci@0,1 {
+ enetc_port1: pci@0,1 {
reg = <0x000100 0 0 0 0>;
status = "disabled";
};
- enetc2: pci@0,2 {
+ enetc_port2: pci@0,2 {
reg = <0x000200 0 0 0 0>;
status = "disabled";
phy-mode = "internal";
@@ -417,7 +417,7 @@
};
};
- mdio0: pci@0,3 {
+ enetc_mdio_pf3: pci@0,3 {
#address-cells=<0>;
#size-cells=<1>;
reg = <0x000300 0 0 0 0>;
@@ -482,7 +482,7 @@
};
};
- enetc6: pci@0,6 {
+ enetc_port3: pci@0,6 {
reg = <0x000600 0 0 0 0>;
status = "disabled";
phy-mode = "internal";
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 16/29] arm: dts: ls1028a: update the labels
2021-09-02 16:45 ` [PATCH v3 16/29] arm: dts: ls1028a: update the labels Michael Walle
@ 2021-09-15 0:02 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:02 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:45PM +0200, Michael Walle wrote:
> Update the labels of the nodes to match the kernel ones.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> - gpio0: gpio@2300000 {
> + gpio1: gpio@2300000 {
For better or for worse. It seems that in Linux our GPIO controller
labels are not zero-based. Whatever.
I maintain my Reviewed-by and Tested-by tags.
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 17/29] watchdog: sp805_wdt: use correct compatible string
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (15 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 16/29] arm: dts: ls1028a: update the labels Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-02 16:45 ` [PATCH v3 18/29] spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi Michael Walle
` (12 subsequent siblings)
29 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
According to the linux device tree specification the compatible string
is:
compatible = "arm,sp805", "arm,primecell";
Fix all users in u-boot.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 2 +-
arch/arm/dts/hi3660.dtsi | 4 ++--
drivers/watchdog/sp805_wdt.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index e5b5a0dc9f..cbdddccaea 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -382,7 +382,7 @@
};
cluster1_core0_watchdog: wdt@c000000 {
- compatible = "arm,sp805-wdt";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
};
diff --git a/arch/arm/dts/hi3660.dtsi b/arch/arm/dts/hi3660.dtsi
index 65a45b0e80..028f4db60d 100644
--- a/arch/arm/dts/hi3660.dtsi
+++ b/arch/arm/dts/hi3660.dtsi
@@ -1087,7 +1087,7 @@
};
watchdog0: watchdog@e8a06000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xe8a06000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>;
@@ -1095,7 +1095,7 @@
};
watchdog1: watchdog@e8a07000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
+ compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xe8a07000 0x0 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_OSC32K>;
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index bec8827ceb..0d6fb12065 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -134,7 +134,7 @@ static const struct wdt_ops sp805_wdt_ops = {
};
static const struct udevice_id sp805_wdt_ids[] = {
- { .compatible = "arm,sp805-wdt" },
+ { .compatible = "arm,sp805" },
{}
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 18/29] spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (16 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 17/29] watchdog: sp805_wdt: use correct compatible string Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-02 16:45 ` [PATCH v3 19/29] spi: fsl_dspi: rename num-cs to spi-num-chipselects Michael Walle
` (11 subsequent siblings)
29 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Add the missing compatible to the driver and update the device tree.
We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness
is determined by the little-endian property and not by the compatible
string itself. Further, we won't need and specific details on the DMA
configuration (which is different on the LS1021A). If it's ever needed,
we can later add the more specific "fsl,ls1028a-dspi" compatible to the
driver.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
drivers/spi/fsl_dspi.c | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index cbdddccaea..6158a1362a 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -158,7 +158,7 @@
};
dspi0: dspi@2100000 {
- compatible = "fsl,vf610-dspi";
+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
@@ -171,7 +171,7 @@
};
dspi1: dspi@2110000 {
- compatible = "fsl,vf610-dspi";
+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
@@ -184,7 +184,7 @@
};
dspi2: dspi@2120000 {
- compatible = "fsl,vf610-dspi";
+ compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 8fe3508c64..23d812f476 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -654,6 +654,7 @@ static const struct dm_spi_ops fsl_dspi_ops = {
static const struct udevice_id fsl_dspi_ids[] = {
{ .compatible = "fsl,vf610-dspi" },
+ { .compatible = "fsl,ls1021a-v1.0-dspi" },
{ }
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 19/29] spi: fsl_dspi: rename num-cs to spi-num-chipselects
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (17 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 18/29] spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:05 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 20/29] serial: lpuart: add new compatible fsl, ls1028a-lpuart Michael Walle
` (10 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
The official devicetree bindings specifies spi-num-chipselects as the
name. Use it.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
arch/arm/dts/fsl-ls1043a.dtsi | 4 ++--
arch/arm/dts/fsl-ls1046a.dtsi | 4 ++--
arch/arm/dts/fsl-ls1088a.dtsi | 2 +-
arch/arm/dts/fsl-ls2080a.dtsi | 2 +-
arch/arm/dts/fsl-lx2160a.dtsi | 6 +++---
arch/arm/dts/ls1021a.dtsi | 4 ++--
arch/arm/dts/vf.dtsi | 4 ++--
drivers/spi/fsl_dspi.c | 5 +++--
10 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2894842cf2..dcdcd444b3 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -49,7 +49,7 @@
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 6158a1362a..7da32561a4 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -165,7 +165,7 @@
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
litte-endian;
status = "disabled";
};
@@ -178,7 +178,7 @@
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
little-endian;
status = "disabled";
};
@@ -191,7 +191,7 @@
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
little-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index d8171bd03b..3aaec8b6af 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -53,7 +53,7 @@
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
@@ -66,7 +66,7 @@
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 9df419a87d..6a205cd3df 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -52,7 +52,7 @@
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
@@ -65,7 +65,7 @@
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 3a5a50fb83..9e48a3ab94 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -89,7 +89,7 @@
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
qspi: quadspi@1550000 {
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 278daeeb6e..72ba52594a 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -93,7 +93,7 @@
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
qspi: quadspi@1550000 {
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 3b5f0d119e..52e4d7205a 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -172,7 +172,7 @@
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
dspi1: dspi@2110000 {
@@ -181,7 +181,7 @@
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <0 26 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
dspi2: dspi@2120000 {
@@ -190,7 +190,7 @@
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <0 241 0x4>; /* Level high type */
- num-cs = <6>;
+ spi-num-chipselects = <6>;
};
gpio0: gpio@2300000 {
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 7ba2dd2269..8aefc82f87 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -190,7 +190,7 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
@@ -203,7 +203,7 @@
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
- num-cs = <6>;
+ spi-num-chipselects = <6>;
big-endian;
status = "disabled";
};
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi
index 5f69d0fd6e..0d512d111e 100644
--- a/arch/arm/dts/vf.dtsi
+++ b/arch/arm/dts/vf.dtsi
@@ -70,7 +70,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002c000 0x1000>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
status = "disabled";
};
@@ -79,7 +79,7 @@
#size-cells = <0>;
compatible = "fsl,vf610-dspi";
reg = <0x4002d000 0x1000>;
- num-cs = <5>;
+ spi-num-chipselects = <5>;
status = "disabled";
};
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 23d812f476..62444e408a 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -586,8 +586,9 @@ static int fsl_dspi_of_to_plat(struct udevice *bus)
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
- plat->num_chipselect =
- fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
+ plat->num_chipselect = fdtdec_get_int(blob, node,
+ "spi-num-chipselects",
+ FSL_DSPI_MAX_CHIPSELECT);
addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE) {
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 20/29] serial: lpuart: add new compatible fsl, ls1028a-lpuart
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (18 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 19/29] spi: fsl_dspi: rename num-cs to spi-num-chipselects Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-02 16:45 ` [PATCH v3 21/29] scsi: ceva: rename the resource name to match the linux kernel one Michael Walle
` (9 subsequent siblings)
29 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-lpuart";
Add the missing compatible to the driver and update the device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
arch/arm/dts/fsl-ls1028a.dtsi | 18 ++++++------------
drivers/serial/serial_lpuart.c | 2 ++
2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 7da32561a4..cf381a0856 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -232,62 +232,56 @@
};
lpuart0: serial@2260000 {
- compatible = "fsl,ls1021a-lpuart";
+ compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
interrupts = <0 232 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
- little-endian;
status = "disabled";
};
lpuart1: serial@2270000 {
- compatible = "fsl,ls1021a-lpuart";
+ compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2270000 0x0 0x1000>;
interrupts = <0 233 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
- little-endian;
status = "disabled";
};
lpuart2: serial@2280000 {
- compatible = "fsl,ls1021a-lpuart";
+ compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2280000 0x0 0x1000>;
interrupts = <0 234 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
- little-endian;
status = "disabled";
};
lpuart3: serial@2290000 {
- compatible = "fsl,ls1021a-lpuart";
+ compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2290000 0x0 0x1000>;
interrupts = <0 235 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
- little-endian;
status = "disabled";
};
lpuart4: serial@22a0000 {
- compatible = "fsl,ls1021a-lpuart";
+ compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22a0000 0x0 0x1000>;
interrupts = <0 236 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
- little-endian;
status = "disabled";
};
lpuart5: serial@22b0000 {
- compatible = "fsl,ls1021a-lpuart";
+ compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22b0000 0x0 0x1000>;
interrupts = <0 237 0x4>;
clocks = <&sysclk>;
clock-names = "ipg";
- little-endian;
status = "disabled";
};
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 2b473d70f6..3c9a69598a 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -553,6 +553,8 @@ static const struct dm_serial_ops lpuart_serial_ops = {
static const struct udevice_id lpuart_serial_ids[] = {
{ .compatible = "fsl,ls1021a-lpuart", .data =
LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
+ { .compatible = "fsl,ls1028a-lpuart",
+ .data = LPUART_FLAG_REGMAP_32BIT_REG },
{ .compatible = "fsl,imx7ulp-lpuart",
.data = LPUART_FLAG_REGMAP_32BIT_REG },
{ .compatible = "fsl,vf610-lpuart"},
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 21/29] scsi: ceva: rename the resource name to match the linux kernel one
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (19 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 20/29] serial: lpuart: add new compatible fsl, ls1028a-lpuart Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:10 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 22/29] usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3 Michael Walle
` (8 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle,
Michal Simek
The driver will look for a named resource "ecc-addr", but this isn't the
official binding. In fact, the official device tree binding
documentation doesn't mention any resource names at all. But it is safe
to assume that it's the linux ones we have to use if we want to be
compatible with the linux device tree. Thus rename "ecc-addr" to
"sata-ecc" and convert all the users in u-boot.
While at it, also rename "sata-base" to "ahci" although its not used at
all.
This change doesn't affect the SATA controller on the ZynqMP.
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
arch/arm/dts/fsl-ls1028a.dtsi | 2 +-
arch/arm/dts/fsl-ls1043a.dtsi | 2 +-
arch/arm/dts/fsl-ls1046a.dtsi | 2 +-
arch/arm/dts/fsl-ls1088a.dtsi | 2 +-
arch/arm/dts/ls1021a.dtsi | 2 +-
drivers/ata/sata_ceva.c | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index dcdcd444b3..0ea899c7d7 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -157,7 +157,7 @@
compatible = "fsl,ls1012a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index cf381a0856..34aad526fe 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -338,7 +338,7 @@
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 3aaec8b6af..52dc5a9638 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -331,7 +331,7 @@
compatible = "fsl,ls1043a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 6a205cd3df..a60cbf11fc 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -367,7 +367,7 @@
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 69 4>;
clocks = <&clockgen 4 1>;
status = "disabled";
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 9e48a3ab94..ee0e3b367d 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -226,7 +226,7 @@
compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 133 4>;
status = "disabled";
};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 8aefc82f87..86192cbb7f 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -469,7 +469,7 @@
sata: sata@3200000 {
compatible = "fsl,ls1021a-ahci";
reg = <0x3200000 0x10000 0x20220520 0x4>;
- reg-names = "sata-base", "ecc-addr";
+ reg-names = "ahci", "sata-ecc";
interrupts = <0 101 4>;
status = "disabled";
};
diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c
index 87e6a90f74..b71f10223d 100644
--- a/drivers/ata/sata_ceva.c
+++ b/drivers/ata/sata_ceva.c
@@ -212,7 +212,7 @@ static int sata_ceva_of_to_plat(struct udevice *dev)
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
- ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
+ ret = dev_read_resource_byname(dev, "sata-ecc", &res_regs);
if (ret)
priv->ecc_base = 0;
else
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 21/29] scsi: ceva: rename the resource name to match the linux kernel one
2021-09-02 16:45 ` [PATCH v3 21/29] scsi: ceva: rename the resource name to match the linux kernel one Michael Walle
@ 2021-09-15 0:10 ` Vladimir Oltean
2021-09-15 7:26 ` Michael Walle
0 siblings, 1 reply; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:10 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam, Michal Simek
On Thu, Sep 02, 2021 at 06:45:50PM +0200, Michael Walle wrote:
> The driver will look for a named resource "ecc-addr", but this isn't the
> official binding. In fact, the official device tree binding
> documentation doesn't mention any resource names at all. But it is safe
> to assume that it's the linux ones we have to use if we want to be
> compatible with the linux device tree. Thus rename "ecc-addr" to
> "sata-ecc" and convert all the users in u-boot.
>
> While at it, also rename "sata-base" to "ahci" although its not used at
> all.
>
> This change doesn't affect the SATA controller on the ZynqMP.
Because the "ceva,ahci-1v84" device doesn't have an ECC region, right.
>
> Cc: Michal Simek <monstr@monstr.eu>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v3 21/29] scsi: ceva: rename the resource name to match the linux kernel one
2021-09-15 0:10 ` Vladimir Oltean
@ 2021-09-15 7:26 ` Michael Walle
0 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-15 7:26 UTC (permalink / raw)
To: Vladimir Oltean
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam, Michal Simek
Am 2021-09-15 02:10, schrieb Vladimir Oltean:
> On Thu, Sep 02, 2021 at 06:45:50PM +0200, Michael Walle wrote:
>> The driver will look for a named resource "ecc-addr", but this isn't
>> the
>> official binding. In fact, the official device tree binding
>> documentation doesn't mention any resource names at all. But it is
>> safe
>> to assume that it's the linux ones we have to use if we want to be
>> compatible with the linux device tree. Thus rename "ecc-addr" to
>> "sata-ecc" and convert all the users in u-boot.
>>
>> While at it, also rename "sata-base" to "ahci" although its not used
>> at
>> all.
>>
>> This change doesn't affect the SATA controller on the ZynqMP.
>
> Because the "ceva,ahci-1v84" device doesn't have an ECC region, right.
I don't know if it doesn't have any. But it's not used in the
driver nor is it described in the device tree (binding).
>> Cc: Michal Simek <monstr@monstr.eu>
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>
> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 22/29] usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (20 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 21/29] scsi: ceva: rename the resource name to match the linux kernel one Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-03 23:51 ` [PATCH v3 22/29] usb: xhci: fsl: add new compatible fsl, ls1028a-dwc3 Bin Meng
2021-09-02 16:45 ` [PATCH v3 23/29] pci: layerscape: add official ls1028a binding support Michael Walle
` (7 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle, Bin Meng,
Marek Vasut
The official ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
Change the ls1028a device tree and add this new compatible to the fsl
specific xhci driver, otherwise the generic dwc3 driver will be used
with the compatibles above.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 4 ++--
drivers/usb/host/xhci-fsl.c | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 34aad526fe..cc055e65e5 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -319,7 +319,7 @@
};
usb0: usb3@3100000 {
- compatible = "fsl,layerscape-dwc3";
+ compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
@@ -327,7 +327,7 @@
};
usb1: usb3@3110000 {
- compatible = "fsl,layerscape-dwc3";
+ compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index f062f12ade..80871908dc 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -159,6 +159,7 @@ static int xhci_fsl_remove(struct udevice *dev)
static const struct udevice_id xhci_usb_ids[] = {
{ .compatible = "fsl,layerscape-dwc3", },
+ { .compatible = "fsl,ls1028a-dwc3", },
{ }
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 22/29] usb: xhci: fsl: add new compatible fsl, ls1028a-dwc3
2021-09-02 16:45 ` [PATCH v3 22/29] usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3 Michael Walle
@ 2021-09-03 23:51 ` Bin Meng
0 siblings, 0 replies; 61+ messages in thread
From: Bin Meng @ 2021-09-03 23:51 UTC (permalink / raw)
To: Michael Walle
Cc: U-Boot Mailing List, Jagan Teki, Priyanka Jain, Vladimir Oltean,
Tom Rini, Peter Griffin, Manivannan Sadhasivam, Marek Vasut
On Fri, Sep 3, 2021 at 12:46 AM Michael Walle <michael@walle.cc> wrote:
>
> The official ls1028a binding of the driver uses the following as
> compatibles:
> compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
>
> Change the ls1028a device tree and add this new compatible to the fsl
> specific xhci driver, otherwise the generic dwc3 driver will be used
> with the compatibles above.
>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Marek Vasut <marex@denx.de>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/dts/fsl-ls1028a.dtsi | 4 ++--
> drivers/usb/host/xhci-fsl.c | 1 +
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 23/29] pci: layerscape: add official ls1028a binding support
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (21 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 22/29] usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3 Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-02 16:45 ` [PATCH v3 24/29] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes Michael Walle
` (6 subsequent siblings)
29 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
The official bindind of the PCIe controller of the ls1028a has the
following compatible string:
compatible = "fsl,ls1028a-pcie";
Additionally, the resource names and count are different. Update the
driver to support this binding and change the entry in the ls1028a
device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 20 +++++------
drivers/pci/pcie_layerscape_rc.c | 61 +++++++++++++++++++++++---------
2 files changed, 53 insertions(+), 28 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index cc055e65e5..435b965d00 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -344,12 +344,10 @@
};
pcie1: pcie@3400000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03400000 0x0 0x80000
- 0x00 0x03480000 0x0 0x40000 /* lut registers */
- 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
- 0x80 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -360,12 +358,10 @@
};
pcie2: pcie@3500000 {
- compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
- reg = <0x00 0x03500000 0x0 0x80000
- 0x00 0x03580000 0x0 0x40000 /* lut registers */
- 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
- 0x88 0x00000000 0x0 0x20000>; /* configuration space */
- reg-names = "dbi", "lut", "ctrl", "config";
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index bd2c19f7f0..c9fd68524d 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -21,6 +21,12 @@
DECLARE_GLOBAL_DATA_PTR;
+struct ls_pcie_drvdata {
+ u32 lut_offset;
+ u32 ctrl_offset;
+ bool big_endian;
+};
+
static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
{
struct ls_pcie *pcie = pcie_rc->pcie;
@@ -243,6 +249,7 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
static int ls_pcie_probe(struct udevice *dev)
{
+ const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev);
struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
@@ -260,8 +267,12 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->pcie = pcie;
+ /* try resource name of the official binding first */
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "dbi", &pcie_rc->dbi_res);
+ "regs", &pcie_rc->dbi_res);
+ if (ret)
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie_rc->dbi_res);
if (ret) {
printf("ls-pcie: resource \"dbi\" not found\n");
return ret;
@@ -287,21 +298,29 @@ static int ls_pcie_probe(struct udevice *dev)
if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
return 0;
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "lut", &pcie_rc->lut_res);
- if (!ret)
- pcie->lut = map_physmem(pcie_rc->lut_res.start,
- fdt_resource_size(&pcie_rc->lut_res),
- MAP_NOCACHE);
+ if (drvdata) {
+ pcie->lut = pcie->dbi + drvdata->lut_offset;
+ } else {
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie_rc->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie_rc->lut_res.start,
+ fdt_resource_size(&pcie_rc->lut_res),
+ MAP_NOCACHE);
+ }
- ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
- "ctrl", &pcie_rc->ctrl_res);
- if (!ret)
- pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
- fdt_resource_size(&pcie_rc->ctrl_res),
- MAP_NOCACHE);
- if (!pcie->ctrl)
- pcie->ctrl = pcie->lut;
+ if (drvdata) {
+ pcie->ctrl = pcie->lut + drvdata->ctrl_offset;
+ } else {
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie_rc->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
+ fdt_resource_size(&pcie_rc->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+ }
if (!pcie->ctrl) {
printf("%s: NOT find CTRL\n", dev->name);
@@ -343,7 +362,10 @@ static int ls_pcie_probe(struct udevice *dev)
pcie_rc->cfg1 = pcie_rc->cfg0 +
fdt_resource_size(&pcie_rc->cfg_res) / 2;
- pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
+ if (drvdata)
+ pcie->big_endian = drvdata->big_endian;
+ else
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
@@ -373,8 +395,15 @@ static const struct dm_pci_ops ls_pcie_ops = {
.write_config = ls_pcie_write_config,
};
+static const struct ls_pcie_drvdata ls1028a_drvdata = {
+ .lut_offset = 0x80000,
+ .ctrl_offset = 0x40000,
+ .big_endian = false,
+};
+
static const struct udevice_id ls_pcie_ids[] = {
{ .compatible = "fsl,ls-pcie" },
+ { .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
{ }
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v3 24/29] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (22 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 23/29] pci: layerscape: add official ls1028a binding support Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:12 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window to match Michael Walle
` (5 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
This property is unused in the layerscape PCIe controller driver and not
present in the linux device tree. Remove it to be similarly.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 435b965d00..3ef710bb3d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -351,7 +351,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -365,7 +364,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 24/29] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes
2021-09-02 16:45 ` [PATCH v3 24/29] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes Michael Walle
@ 2021-09-15 0:12 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:12 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:53PM +0200, Michael Walle wrote:
> This property is unused in the layerscape PCIe controller driver and not
> present in the linux device tree. Remove it to be similarly.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Looks pretty much unused, indeed.
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window to match
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (23 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 24/29] arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:13 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 26/29] arm: dts: ls1028a: disable the PCIe controller by default Michael Walle
` (4 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
To make the synchronization of the u-boot device tree with the one from
linux easier, move the I/O window to the one which is specified in the
linux device tree. The actual value shouldn't matter as long as it
mapped to the corresponding memory window of the PCIe controller which
is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h
(second controller).
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 3ef710bb3d..f11e75032b 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -352,7 +352,7 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
@@ -365,7 +365,7 @@
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window to match
2021-09-02 16:45 ` [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window to match Michael Walle
@ 2021-09-15 0:13 ` Vladimir Oltean
2021-09-16 4:03 ` Z.Q. Hou
0 siblings, 1 reply; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:13 UTC (permalink / raw)
To: Michael Walle, Z.Q. Hou
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:54PM +0200, Michael Walle wrote:
> To make the synchronization of the u-boot device tree with the one from
> linux easier, move the I/O window to the one which is specified in the
> linux device tree. The actual value shouldn't matter as long as it
> mapped to the corresponding memory window of the PCIe controller which
> is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h
> (second controller).
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/dts/fsl-ls1028a.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
> index 3ef710bb3d..f11e75032b 100644
> --- a/arch/arm/dts/fsl-ls1028a.dtsi
> +++ b/arch/arm/dts/fsl-ls1028a.dtsi
> @@ -352,7 +352,7 @@
> #size-cells = <2>;
> device_type = "pci";
> bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
> + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
> 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> };
>
> @@ -365,7 +365,7 @@
> #size-cells = <2>;
> device_type = "pci";
> bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
> + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
> 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
> };
>
> --
> 2.30.2
>
Zhiqiang, can you please review this patch?
^ permalink raw reply [flat|nested] 61+ messages in thread
* RE: [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window to match
2021-09-15 0:13 ` Vladimir Oltean
@ 2021-09-16 4:03 ` Z.Q. Hou
0 siblings, 0 replies; 61+ messages in thread
From: Z.Q. Hou @ 2021-09-16 4:03 UTC (permalink / raw)
To: Vladimir Oltean, Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
> -----Original Message-----
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> Sent: 2021年9月15日 8:13
> To: Michael Walle <michael@walle.cc>; Z.Q. Hou <zhiqiang.hou@nxp.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <jagan@amarulasolutions.com>;
> Priyanka Jain <priyanka.jain@nxp.com>; Tom Rini <trini@konsulko.com>;
> Peter Griffin <peter.griffin@linaro.org>; Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org>
> Subject: Re: [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window
> to match
>
> On Thu, Sep 02, 2021 at 06:45:54PM +0200, Michael Walle wrote:
> > To make the synchronization of the u-boot device tree with the one
> > from linux easier, move the I/O window to the one which is specified
> > in the linux device tree. The actual value shouldn't matter as long as
> > it mapped to the corresponding memory window of the PCIe controller
> > which is a 32GiB window at 80_0000_0000h (first controller) or
> > 88_0000_0000h (second controller).
> >
> > Signed-off-by: Michael Walle <michael@walle.cc>
> > ---
> > arch/arm/dts/fsl-ls1028a.dtsi | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/dts/fsl-ls1028a.dtsi
> > b/arch/arm/dts/fsl-ls1028a.dtsi index 3ef710bb3d..f11e75032b 100644
> > --- a/arch/arm/dts/fsl-ls1028a.dtsi
> > +++ b/arch/arm/dts/fsl-ls1028a.dtsi
> > @@ -352,7 +352,7 @@
> > #size-cells = <2>;
> > device_type = "pci";
> > bus-range = <0x0 0xff>;
> > - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0
> 0x00010000 /* downstream I/O */
> > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > };
> >
> > @@ -365,7 +365,7 @@
> > #size-cells = <2>;
> > device_type = "pci";
> > bus-range = <0x0 0xff>;
> > - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0
> 0x00010000 /* downstream I/O */
> > + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0
> 0x00010000 /* downstream I/O */
> > 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > };
> >
> > --
> > 2.30.2
> >
>
> Zhiqiang, can you please review this patch?
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 26/29] arm: dts: ls1028a: disable the PCIe controller by default
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (24 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 25/29] arm: dts: ls1028a: move the PCI I/O window to match Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:14 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node Michael Walle
` (3 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
Disable the PCIe controllers by default, just like in the linux device
tree. But there is one catch, for linux they are enabled in-place by the
bootloader. Obviously, this doesn't work for the bootloader. Thus we
explicitly enable the controllers in the -u-boot.dtsi files.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 13 +++++++++++++
arch/arm/dts/fsl-ls1028a-qds.dtsi | 8 ++++++++
arch/arm/dts/fsl-ls1028a-rdb.dts | 8 ++++++++
arch/arm/dts/fsl-ls1028a.dtsi | 2 ++
4 files changed, 31 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
index 42bd3138b2..25aa274765 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -266,6 +266,19 @@
u-boot,dm-pre-reloc;
};
+/*
+ * u-boot will enable the device in the linux device tree in place. Because
+ * we are using the linux device tree, we have to enable the PCI controller
+ * ourselves.
+ */
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
+
&soc {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi
index babd8445ee..0da0a7bc5d 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -240,6 +240,14 @@
status = "okay";
};
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
+
&usb0 {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 18ee363d75..537ebbc697 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -122,6 +122,14 @@
status = "okay";
};
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
+
&usb0 {
status = "okay";
};
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index f11e75032b..d2f558d208 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -354,6 +354,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ status = "disabled";
};
pcie2: pcie@3500000 {
@@ -367,6 +368,7 @@
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ status = "disabled";
};
cluster1_core0_watchdog: wdt@c000000 {
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 26/29] arm: dts: ls1028a: disable the PCIe controller by default
2021-09-02 16:45 ` [PATCH v3 26/29] arm: dts: ls1028a: disable the PCIe controller by default Michael Walle
@ 2021-09-15 0:14 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:14 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:55PM +0200, Michael Walle wrote:
> Disable the PCIe controllers by default, just like in the linux device
> tree. But there is one catch, for linux they are enabled in-place by the
> bootloader. Obviously, this doesn't work for the bootloader. Thus we
> explicitly enable the controllers in the -u-boot.dtsi files.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (25 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 26/29] arm: dts: ls1028a: disable the PCIe controller by default Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:17 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 28/29] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux Michael Walle
` (2 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
The linux device tree hasn't set this property. To be similarly we remove
it from the u-boot device tree, too. The second controller of the
LS1028A has indeed no card detect pin. The present state register of the
second controller will always report the card as present. Thus, there
should be no functional change otherwise than one more register access
to read the present state. The property should still be introduced in
the linux device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index d2f558d208..af6dabe847 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -210,7 +210,6 @@
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
- non-removable;
bus-width = <4>;
status = "disabled";
};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node
2021-09-02 16:45 ` [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node Michael Walle
@ 2021-09-15 0:17 ` Vladimir Oltean
2021-09-15 8:09 ` Michael Walle
0 siblings, 1 reply; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:17 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:56PM +0200, Michael Walle wrote:
> The linux device tree hasn't set this property. To be similarly we remove
s/similarly/similar/
> it from the u-boot device tree, too. The second controller of the
> LS1028A has indeed no card detect pin.
Because it is an eMMC controller.
> The present state register of the
> second controller will always report the card as present. Thus, there
> should be no functional change otherwise than one more register access
> to read the present state.
Tested?
> The property should still be introduced in
> the linux device tree.
How do you feel about dropping this patch?
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
> arch/arm/dts/fsl-ls1028a.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
> index d2f558d208..af6dabe847 100644
> --- a/arch/arm/dts/fsl-ls1028a.dtsi
> +++ b/arch/arm/dts/fsl-ls1028a.dtsi
> @@ -210,7 +210,6 @@
> reg = <0x0 0x2150000 0x0 0x10000>;
> interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> big-endian;
> - non-removable;
> bus-width = <4>;
> status = "disabled";
> };
> --
> 2.30.2
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node
2021-09-15 0:17 ` Vladimir Oltean
@ 2021-09-15 8:09 ` Michael Walle
2021-09-15 10:36 ` Vladimir Oltean
0 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-15 8:09 UTC (permalink / raw)
To: Vladimir Oltean
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
Am 2021-09-15 02:17, schrieb Vladimir Oltean:
> On Thu, Sep 02, 2021 at 06:45:56PM +0200, Michael Walle wrote:
>> The linux device tree hasn't set this property. To be similarly we
>> remove
>
> s/similarly/similar/
>
>> it from the u-boot device tree, too. The second controller of the
>> LS1028A has indeed no card detect pin.
>
> Because it is an eMMC controller.
>
>> The present state register of the
>> second controller will always report the card as present. Thus, there
>> should be no functional change otherwise than one more register access
>> to read the present state.
>
> Tested?
Yes, I've tested the eMMC (and actually using it this way). I also
manually read out the register value and made sure the card detect
bit is set.
>> The property should still be introduced in
>> the linux device tree.
>
> How do you feel about dropping this patch?
If I drop this patch, I'll either have to (1) keep this property
the device tree sync patch too or (2) it will be removed without a
comment in that patch.
I presume you prefer (1), but as I said, I'd keep the device trees
between linux and u-boot the same and keep it simple by just copying
the files. So yes, I'd like to keep this patch as the point of this
patch is to give an explanation why this property is removed (until
it might or might not be introduced in the kernel device tree; in
fact I thought I had send a patch to the LKML but I must have
forgotten it).
I was thinking of putting it into the -u-boot.dtsi, but as there
is no breakage, I didn't.
Thanks for reviewing the patches!
-michael
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>> arch/arm/dts/fsl-ls1028a.dtsi | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/fsl-ls1028a.dtsi
>> b/arch/arm/dts/fsl-ls1028a.dtsi
>> index d2f558d208..af6dabe847 100644
>> --- a/arch/arm/dts/fsl-ls1028a.dtsi
>> +++ b/arch/arm/dts/fsl-ls1028a.dtsi
>> @@ -210,7 +210,6 @@
>> reg = <0x0 0x2150000 0x0 0x10000>;
>> interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
>> big-endian;
>> - non-removable;
>> bus-width = <4>;
>> status = "disabled";
>> };
>> --
>> 2.30.2
>>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node
2021-09-15 8:09 ` Michael Walle
@ 2021-09-15 10:36 ` Vladimir Oltean
2021-10-05 7:57 ` Michael Walle
0 siblings, 1 reply; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 10:36 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Wed, Sep 15, 2021 at 10:09:45AM +0200, Michael Walle wrote:
> Am 2021-09-15 02:17, schrieb Vladimir Oltean:
> > On Thu, Sep 02, 2021 at 06:45:56PM +0200, Michael Walle wrote:
> > > The linux device tree hasn't set this property. To be similarly we
> > > remove
> >
> > s/similarly/similar/
> >
> > > it from the u-boot device tree, too. The second controller of the
> > > LS1028A has indeed no card detect pin.
> >
> > Because it is an eMMC controller.
> >
> > > The present state register of the
> > > second controller will always report the card as present. Thus, there
> > > should be no functional change otherwise than one more register access
> > > to read the present state.
> >
> > Tested?
>
> Yes, I've tested the eMMC (and actually using it this way). I also
> manually read out the register value and made sure the card detect
> bit is set.
>
> > > The property should still be introduced in
> > > the linux device tree.
> >
> > How do you feel about dropping this patch?
>
> If I drop this patch, I'll either have to (1) keep this property
> the device tree sync patch too or (2) it will be removed without a
> comment in that patch.
>
> I presume you prefer (1), but as I said, I'd keep the device trees
> between linux and u-boot the same and keep it simple by just copying
> the files. So yes, I'd like to keep this patch as the point of this
> patch is to give an explanation why this property is removed (until
> it might or might not be introduced in the kernel device tree; in
> fact I thought I had send a patch to the LKML but I must have
> forgotten it).
>
> I was thinking of putting it into the -u-boot.dtsi, but as there
> is no breakage, I didn't.
Ok, but we should still put "non-removable" in the Linux dtsi soon then.
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node
2021-09-15 10:36 ` Vladimir Oltean
@ 2021-10-05 7:57 ` Michael Walle
0 siblings, 0 replies; 61+ messages in thread
From: Michael Walle @ 2021-10-05 7:57 UTC (permalink / raw)
To: Vladimir Oltean
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
Am 2021-09-15 12:36, schrieb Vladimir Oltean:
> On Wed, Sep 15, 2021 at 10:09:45AM +0200, Michael Walle wrote:
>> I was thinking of putting it into the -u-boot.dtsi, but as there
>> is no breakage, I didn't.
>
> Ok, but we should still put "non-removable" in the Linux dtsi soon
> then.
Just for the reference:
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/commit/?h=for-next&id=8b94aa318aa746fbbc668d6b9b3ad812c835230c
-michael
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 28/29] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (26 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 27/29] arm: dts: ls1028a: drop non-removable property from esdhc controller node Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:24 ` Vladimir Oltean
2021-09-02 16:45 ` [PATCH v3 29/29] arm: dts: sl28: sync dtbs Michael Walle
2021-10-05 0:39 ` [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Vladimir Oltean
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
linux kernel v5.14.
Notable changes:
- second watchdog added
- the number of chip selects of the SPI controller is now correct and
reflects what the hardware offers
- the LPUARTs have the correct clock parent
- USB controllers are enabled by default, which was already the case
before this sync because all board enabled all the USB controller
nodes. A linux patch to fix this is pending.
- the eSDHC controller changes from big-endian to little-endian, but
that property seems to be not used at all.
Signed-off-by: Michael Walle <michael@walle.cc>
---
arch/arm/dts/fsl-ls1028a.dtsi | 861 ++++++++++++++++--
.../dt-bindings/clock/fsl,qoriq-clockgen.h | 15 +
2 files changed, 786 insertions(+), 90 deletions(-)
create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index af6dabe847..343ecf0e89 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -1,12 +1,16 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * NXP ls1028a SOC common device tree source
+ * Device Tree Include file for NXP Layerscape-1028A family SoC.
*
- * Copyright 2019-2020 NXP
+ * Copyright 2018-2020 NXP
+ *
+ * Harninder Rai <harninder.rai@nxp.com>
*
*/
+#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1028a";
@@ -14,6 +18,54 @@
#address-cells = <2>;
#size-cells = <2>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0>;
+ enable-method = "psci";
+ clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PW20>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x1>;
+ enable-method = "psci";
+ clocks = <&clockgen QORIQ_CLK_CMUX 0>;
+ next-level-cache = <&l2>;
+ cpu-idle-states = <&CPU_PW20>;
+ #cooling-cells = <2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ idle-states {
+ /*
+ * PSCI node is not added default, U-boot will add missing
+ * parts if it determines to use PSCI.
+ */
+ entry-method = "psci";
+
+ CPU_PW20: cpu-pw20 {
+ compatible = "arm,idle-state";
+ idle-state-name = "PW20";
+ arm,psci-suspend-param = <0x0>;
+ entry-latency-us = <2000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6000>;
+ };
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -21,14 +73,33 @@
clock-output-names = "sysclk";
};
- gic: interrupt-controller@6000000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
- <0x0 0x06040000 0 0x40000>;
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
- IRQ_TYPE_LEVEL_LOW)>;
+ osc_27m: clock-osc-27m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "phy_27m";
+ };
+
+ dpclk: clock-controller@f1f0000 {
+ compatible = "fsl,ls1028a-plldig";
+ reg = <0x0 0xf1f0000 0x0 0xffff>;
+ #clock-cells = <0>;
+ clocks = <&osc_27m>;
+ };
+
+ firmware {
+ optee: optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ status = "disabled";
+ };
+ };
+
+ reboot {
+ compatible ="syscon-reboot";
+ regmap = <&rst>;
+ offset = <0>;
+ mask = <0x02>;
};
timer {
@@ -43,13 +114,123 @@
IRQ_TYPE_LEVEL_LOW)>;
};
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible= "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
+ <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
+ #interrupt-cells= <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ its: gic-its@6020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
+ };
+ };
+
+ thermal-zones {
+ ddr-controller {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ ddr-ctrler-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ ddr-ctrler-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ core-cluster {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+
+ trips {
+ core_cluster_alert: core-cluster-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core_cluster_crit: core-cluster-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clockgen: clocking@1300000 {
+ ddr: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ };
+
+ dcfg: syscon@1e00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
+ reg = <0x0 0x1e00000 0x0 0x10000>;
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
+ little-endian;
+
+ fspi_clk: clock-controller@900 {
+ compatible = "fsl,ls1028a-flexspi-clk";
+ reg = <0x900 0x4>;
+ #clock-cells = <0>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
+ clock-output-names = "fspi_clk";
+ };
+ };
+
+ rst: syscon@1e60000 {
+ compatible = "syscon";
+ reg = <0x0 0x1e60000 0x0 0x10000>;
+ little-endian;
+ };
+
+ scfg: syscon@1fc0000 {
+ compatible = "fsl,ls1028a-scfg", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x10000>;
+ big-endian;
+ };
+
+ clockgen: clock-controller@1300000 {
compatible = "fsl,ls1028a-clockgen";
reg = <0x0 0x1300000 0x0 0xa0000>;
#clock-cells = <2>;
@@ -62,8 +243,8 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -73,8 +254,8 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -84,8 +265,8 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -95,8 +276,8 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -106,8 +287,8 @@
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -117,8 +298,8 @@
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -128,8 +309,8 @@
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
@@ -139,151 +320,237 @@
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "i2c";
- clocks = <&clockgen 4 0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
- fspi: flexspi@20c0000 {
+ fspi: spi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
- clock-names = "fspi_en", "fspi";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fspi_clk>, <&fspi_clk>;
+ clock-names = "fspi_en", "fspi";
status = "disabled";
};
- dspi0: dspi@2100000 {
+ dspi0: spi@2100000 {
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- spi-num-chipselects = <5>;
- litte-endian;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ dmas = <&edma0 0 62>, <&edma0 0 60>;
+ dma-names = "tx", "rx";
+ spi-num-chipselects = <4>;
+ little-endian;
status = "disabled";
};
- dspi1: dspi@2110000 {
+ dspi1: spi@2110000 {
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- spi-num-chipselects = <5>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ dmas = <&edma0 0 58>, <&edma0 0 56>;
+ dma-names = "tx", "rx";
+ spi-num-chipselects = <4>;
little-endian;
status = "disabled";
};
- dspi2: dspi@2120000 {
+ dspi2: spi@2120000 {
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
- clocks = <&clockgen 4 0>;
- spi-num-chipselects = <5>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ dmas = <&edma0 0 54>, <&edma0 0 2>;
+ dma-names = "tx", "rx";
+ spi-num-chipselects = <3>;
little-endian;
status = "disabled";
};
- esdhc: esdhc@2140000 {
- compatible = "fsl,esdhc";
+ esdhc: mmc@2140000 {
+ compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
+ clock-frequency = <0>; /* fixed up by bootloader */
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
bus-width = <4>;
status = "disabled";
};
- esdhc1: esdhc@2150000 {
- compatible = "fsl,esdhc";
+ esdhc1: mmc@2150000 {
+ compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- big-endian;
+ clock-frequency = <0>; /* fixed up by bootloader */
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ broken-cd;
+ little-endian;
bus-width = <4>;
status = "disabled";
};
+ can0: can@2180000 {
+ compatible = "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2180000 0x0 0x10000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can1: can@2190000 {
+ compatible = "fsl,lx2160ar1-flexcan";
+ reg = <0x0 0x2190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
duart0: serial@21c0500 {
- device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
+ reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
duart1: serial@21c0600 {
- device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
+ reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
+
lpuart0: serial@2260000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
- interrupts = <0 232 0x4>;
- clocks = <&sysclk>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 32>,
+ <&edma0 1 33>;
status = "disabled";
};
lpuart1: serial@2270000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2270000 0x0 0x1000>;
- interrupts = <0 233 0x4>;
- clocks = <&sysclk>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 30>,
+ <&edma0 1 31>;
status = "disabled";
};
lpuart2: serial@2280000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2280000 0x0 0x1000>;
- interrupts = <0 234 0x4>;
- clocks = <&sysclk>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 28>,
+ <&edma0 1 29>;
status = "disabled";
};
lpuart3: serial@2290000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2290000 0x0 0x1000>;
- interrupts = <0 235 0x4>;
- clocks = <&sysclk>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 26>,
+ <&edma0 1 27>;
status = "disabled";
};
lpuart4: serial@22a0000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22a0000 0x0 0x1000>;
- interrupts = <0 236 0x4>;
- clocks = <&sysclk>;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 24>,
+ <&edma0 1 25>;
status = "disabled";
};
lpuart5: serial@22b0000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22b0000 0x0 0x1000>;
- interrupts = <0 237 0x4>;
- clocks = <&sysclk>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
+ dma-names = "rx","tx";
+ dmas = <&edma0 1 22>,
+ <&edma0 1 23>;
status = "disabled";
};
+ edma0: dma-controller@22c0000 {
+ #dma-cells = <2>;
+ compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
+ reg = <0x0 0x22c0000 0x0 0x10000>,
+ <0x0 0x22d0000 0x0 0x10000>,
+ <0x0 0x22e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma-tx", "edma-err";
+ dma-channels = <32>;
+ clock-names = "dmamux0", "dmamux1";
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ };
+
gpio1: gpio@2300000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
@@ -317,28 +584,34 @@
little-endian;
};
- usb0: usb3@3100000 {
+ usb0: usb@3100000 {
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
- status = "disabled";
+ snps,dis_rxdet_inp3_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
- usb1: usb3@3110000 {
+ usb1: usb@3110000 {
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
- status = "disabled";
+ snps,dis_rxdet_inp3_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
- reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
- 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
+ reg = <0x0 0x3200000 0x0 0x10000>,
+ <0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
@@ -347,12 +620,25 @@
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ dma-coherent;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
@@ -361,44 +647,380 @@
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ dma-coherent;
+ num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
- cluster1_core0_watchdog: wdt@c000000 {
+ smmu: iommu@5000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #global-interrupts = <8>;
+ #iommu-cells = <1>;
+ stream-match-mask = <0x7c00>;
+ /* global secure fault */
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ /* combined secure interrupt */
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ /* global non-secure fault */
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ /* combined non-secure interrupt */
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ /* performance counter interrupts 0-7 */
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ /* per context interrupt, 64 interrupts */
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ qdma: dma-controller@8380000 {
+ compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
+ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
+ <0x0 0x8390000 0x0 0x10000>, /* Status regs */
+ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "qdma-error", "qdma-queue0",
+ "qdma-queue1", "qdma-queue2", "qdma-queue3";
+ dma-channels = <8>;
+ block-number = <1>;
+ block-offset = <0x10000>;
+ fsl,dma-queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ };
+
+ cluster1_core0_watchdog: watchdog@c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>;
+ clock-names = "wdog_clk", "apb_pclk";
+ };
+
+ cluster1_core1_watchdog: watchdog@c010000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(16)>;
+ clock-names = "wdog_clk", "apb_pclk";
+ };
+
+ sai1: audio-controller@f100000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 4>,
+ <&edma0 1 3>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
+
+ sai2: audio-controller@f110000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 6>,
+ <&edma0 1 5>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
+
+ sai3: audio-controller@f120000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf120000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 8>,
+ <&edma0 1 7>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
+
+ sai4: audio-controller@f130000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf130000 0x0 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 10>,
+ <&edma0 1 9>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
+
+ sai5: audio-controller@f140000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf140000 0x0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 12>,
+ <&edma0 1 11>;
+ fsl,sai-asynchronous;
+ status = "disabled";
+ };
+
+ sai6: audio-controller@f150000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,vf610-sai";
+ reg = <0x0 0xf150000 0x0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL
+ QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 1 14>,
+ <&edma0 1 13>;
+ fsl,sai-asynchronous;
+ status = "disabled";
};
- pcie@1f0000000 {
+ tmu: tmu@1f80000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f80000 0x0 0x10000>;
+ interrupts = <0 23 0x4>;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000024
+ 0x00000001 0x0000002b
+ 0x00000002 0x00000031
+ 0x00000003 0x00000038
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000045
+ 0x00000006 0x0000004c
+ 0x00000007 0x00000053
+ 0x00000008 0x00000059
+ 0x00000009 0x00000060
+ 0x0000000a 0x00000066
+ 0x0000000b 0x0000006d
+
+ 0x00010000 0x0000001c
+ 0x00010001 0x00000024
+ 0x00010002 0x0000002c
+ 0x00010003 0x00000035
+ 0x00010004 0x0000003d
+ 0x00010005 0x00000045
+ 0x00010006 0x0000004d
+ 0x00010007 0x00000055
+ 0x00010008 0x0000005e
+ 0x00010009 0x00000066
+ 0x0001000a 0x0000006e
+
+ 0x00020000 0x00000018
+ 0x00020001 0x00000022
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000038
+ 0x00020004 0x00000043
+ 0x00020005 0x0000004d
+ 0x00020006 0x00000058
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006e
+
+ 0x00030000 0x00000010
+ 0x00030001 0x0000001c
+ 0x00030002 0x00000029
+ 0x00030003 0x00000036
+ 0x00030004 0x00000042
+ 0x00030005 0x0000004f
+ 0x00030006 0x0000005b
+ 0x00030007 0x00000068>;
+ little-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
- /* ECAM bus 0, HW has more space reserved but not populated */
- bus-range = <0x0 0x0>;
reg = <0x01 0xf0000000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
+ msi-parent = <&its>;
device_type = "pci";
- ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
+ bus-range = <0x0 0x0>;
+ dma-coherent;
+ msi-map = <0 &its 0x17 0xe>;
+ iommu-map = <0 &smmu 0x17 0xe>;
+ /* PF0-6 BAR0 - non-prefetchable memory */
+ ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
+ /* PF0-6 BAR2 - prefetchable memory */
+ 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
+ /* PF0: VF0-1 BAR0 - non-prefetchable memory */
+ 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
+ /* PF0: VF0-1 BAR2 - prefetchable memory */
+ 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
+ /* PF1: VF0-1 BAR0 - non-prefetchable memory */
+ 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
+ /* PF1: VF0-1 BAR2 - prefetchable memory */
+ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
+ /* BAR4 (PF5) - non-prefetchable memory */
+ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
- enetc_port0: pci@0,0 {
+ enetc_port0: ethernet@0,0 {
+ compatible = "fsl,enetc";
reg = <0x000000 0 0 0 0>;
status = "disabled";
};
- enetc_port1: pci@0,1 {
+ enetc_port1: ethernet@0,1 {
+ compatible = "fsl,enetc";
reg = <0x000100 0 0 0 0>;
status = "disabled";
};
- enetc_port2: pci@0,2 {
+ enetc_port2: ethernet@0,2 {
+ compatible = "fsl,enetc";
reg = <0x000200 0 0 0 0>;
- status = "disabled";
phy-mode = "internal";
+ status = "disabled";
fixed-link {
speed = <2500>;
@@ -406,26 +1028,32 @@
};
};
- enetc_mdio_pf3: pci@0,3 {
- #address-cells=<0>;
- #size-cells=<1>;
+ enetc_mdio_pf3: mdio@0,3 {
+ compatible = "fsl,enetc-mdio";
reg = <0x000300 0 0 0 0>;
- status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
+ ethernet@0,4 {
+ compatible = "fsl,enetc-ptp";
+ reg = <0x000400 0 0 0 0>;
+ clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
+ little-endian;
+ fsl,extts-fifo;
};
- mscc_felix: pci@0,5 {
+ mscc_felix: ethernet-switch@0,5 {
reg = <0x000500 0 0 0 0>;
+ /* IEP INT_B */
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
+ /* External ports */
mscc_felix_port0: port@0 {
reg = <0>;
status = "disabled";
@@ -446,6 +1074,7 @@
status = "disabled";
};
+ /* Internal ports */
mscc_felix_port4: port@4 {
reg = <4>;
phy-mode = "internal";
@@ -466,15 +1095,67 @@
speed = <1000>;
full-duplex;
};
-
};
};
};
- enetc_port3: pci@0,6 {
+ enetc_port3: ethernet@0,6 {
+ compatible = "fsl,enetc";
reg = <0x000600 0 0 0 0>;
- status = "disabled";
phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ rcec@1f,0 {
+ reg = <0x00f800 0 0 0 0>;
+ /* IEP INT_A */
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ /* Integrated Endpoint Register Block */
+ ierb@1f0800000 {
+ compatible = "fsl,ls1028a-enetc-ierb";
+ reg = <0x01 0xf0800000 0x0 0x10000>;
+ };
+
+ rcpm: power-controller@1e34040 {
+ compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ malidp0: display@f080000 {
+ compatible = "arm,mali-dp500";
+ reg = <0x0 0xf080000 0x0 0x10000>;
+ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "DE", "SE";
+ clocks = <&dpclk>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ arm,malidp-arqos-value = <0xd000d000>;
+
+ port {
+ dp0_out: endpoint {
+
};
};
};
diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
new file mode 100644
index 0000000000..ddec7d0bdc
--- /dev/null
+++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK 0
+#define QORIQ_CLK_CMUX 1
+#define QORIQ_CLK_HWACCEL 2
+#define QORIQ_CLK_FMAN 3
+#define QORIQ_CLK_PLATFORM_PLL 4
+#define QORIQ_CLK_CORECLK 5
+
+#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 28/29] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux
2021-09-02 16:45 ` [PATCH v3 28/29] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux Michael Walle
@ 2021-09-15 0:24 ` Vladimir Oltean
0 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-09-15 0:24 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:57PM +0200, Michael Walle wrote:
> Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
> linux kernel v5.14.
>
> Notable changes:
> - second watchdog added
> - the number of chip selects of the SPI controller is now correct and
> reflects what the hardware offers
> - the LPUARTs have the correct clock parent
> - USB controllers are enabled by default, which was already the case
> before this sync because all board enabled all the USB controller
> nodes. A linux patch to fix this is pending.
> - the eSDHC controller changes from big-endian to little-endian, but
> that property seems to be not used at all.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v3 29/29] arm: dts: sl28: sync dtbs
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (27 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 28/29] arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux Michael Walle
@ 2021-09-02 16:45 ` Michael Walle
2021-09-15 0:27 ` Vladimir Oltean
2021-10-05 0:39 ` [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Vladimir Oltean
29 siblings, 1 reply; 61+ messages in thread
From: Michael Walle @ 2021-09-02 16:45 UTC (permalink / raw)
To: u-boot
Cc: Jagan Teki, Priyanka Jain, Vladimir Oltean, Tom Rini,
Peter Griffin, Manivannan Sadhasivam, Michael Walle
Copy the board device tree files from linux v5.14. On top of the v5.14
dtbs the changes of these two patches are included here which are needed
for u-boot:
https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-michael@walle.cc/
https://lore.kernel.org/linux-devicetree/20210831134013.1625527-8-michael@walle.cc/
At the time of this writing the patches are still pending but already
have Reviewed-by tags.
Signed-off-by: Michael Walle <michael@walle.cc>
---
.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 12 +-
.../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 31 +--
.../fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 8 +
.../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 40 +--
.../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 16 +-
arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 250 +++++++++++++++---
6 files changed, 265 insertions(+), 92 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
index 25aa274765..8538ce7984 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -4,12 +4,9 @@
/ {
aliases {
- mmc0 = &esdhc1;
- mmc1 = &esdhc;
i2c0 = &i2c0;
i2c1 = &i2c3;
i2c2 = &i2c4;
- rtc0 = &rtc;
ethernet2 = &enetc_port2;
ethernet3 = &enetc_port3;
};
@@ -234,11 +231,6 @@
};
#endif
-&i2c0 {
- rtc: rtc@32 {
- };
-};
-
&fspi {
u-boot,dm-pre-reloc;
flash@0 {
@@ -279,6 +271,10 @@
status = "okay";
};
+&sata {
+ status = "okay";
+};
+
&soc {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
index ba2e4de96d..7cd29ab970 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts
@@ -8,7 +8,7 @@
* None of the four SerDes lanes are used by the module, instead they are
* all led out to the carrier for customer use.
*
- * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@@ -21,28 +21,17 @@
compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};
-&enetc_port0 {
- status = "disabled";
- /delete-property/ phy-handle;
-};
-
-&enetc_port1 {
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
- status = "okay";
-};
-
-/delete-node/ &phy0;
&enetc_mdio_pf3 {
+ /* Delete unused phy node */
+ /delete-node/ ethernet-phy@5;
+
phy0: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
-
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
-
vddio-supply = <&vddio>;
vddio: vddio-regulator {
@@ -56,3 +45,15 @@
};
};
};
+
+&enetc_port0 {
+ status = "disabled";
+ /* Delete the phy-handle to the old phy0 label */
+ /delete-property/ phy-handle;
+};
+
+&enetc_port1 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi
index 4e0ce3f77d..c010ea0dc7 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi
@@ -7,3 +7,11 @@
ethernet1 = &mscc_felix_port1;
};
};
+
+&mscc_felix_port0 {
+ label = "gbe0";
+};
+
+&mscc_felix_port1 {
+ label = "gbe1";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
index db80874f4e..330e34f933 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts
@@ -2,10 +2,10 @@
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
- * This is for the network variant 2 which has no ethernet support in the
- * bootloader.
+ * This is for the network variant 2 which has two ethernet ports. These
+ * ports are connected to the internal switch.
*
- * Copyright (C) 2020 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@@ -17,8 +17,21 @@
compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
};
+&enetc_mdio_pf3 {
+ phy1: ethernet-phy@4 {
+ reg = <0x4>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
+};
+
&enetc_port0 {
status = "disabled";
+ /*
+ * In the base device tree the PHY at address 5 was assigned for
+ * this port. On this module this PHY is connected to a switch
+ * port instead. Therefore, delete the phy-handle property here.
+ */
/delete-property/ phy-handle;
};
@@ -31,14 +44,16 @@
};
&mscc_felix_port0 {
- label = "gbe0";
+ label = "swp0";
+ managed = "in-band-status";
phy-handle = <&phy0>;
phy-mode = "sgmii";
status = "okay";
};
&mscc_felix_port1 {
- label = "gbe1";
+ label = "swp1";
+ managed = "in-band-status";
phy-handle = <&phy1>;
phy-mode = "sgmii";
status = "okay";
@@ -48,18 +63,3 @@
ethernet = <&enetc_port2>;
status = "okay";
};
-
-/delete-node/ &phy0;
-&enetc_mdio_pf3 {
- phy0: ethernet-phy@5 {
- reg = <0x5>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-
- phy1: ethernet-phy@4 {
- reg = <0x4>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
index 54d12ab992..9b5e92fb75 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts
@@ -5,7 +5,7 @@
* This is for the network variant 4 which has two ethernet ports. It
* extends the base and provides one more port connected via RGMII.
*
- * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@@ -18,22 +18,14 @@
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};
-&enetc_port1 {
- phy-handle = <&phy1>;
- phy-mode = "rgmii-id";
- status = "okay";
-};
-
&enetc_mdio_pf3 {
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
-
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
-
vddio-supply = <&vddio>;
vddio: vddio-regulator {
@@ -47,3 +39,9 @@
};
};
};
+
+&enetc_port1 {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
index 9ae70ba541..ab713b4949 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts
@@ -2,23 +2,61 @@
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
- * Copyright (C) 2019 Michael Walle <michael@walle.cc>
+ * Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Kontron SMARC-sAL28";
compatible = "kontron,sl28", "fsl,ls1028a";
aliases {
+ crypto = &crypto;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &lpuart1;
spi0 = &fspi;
spi1 = &dspi2;
+ mmc0 = &esdhc1;
+ mmc1 = &esdhc;
+ rtc0 = &rtc;
+ rtc1 = &ftm_alarm0;
+ };
+
+ buttons0 {
+ compatible = "gpio-keys";
+
+ power-button {
+ interrupts-extended = <&sl28cpld_intc
+ 4 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ label = "Power";
+ };
+
+ sleep-button {
+ interrupts-extended = <&sl28cpld_intc
+ 5 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_SLEEP>;
+ label = "Sleep";
+ };
+ };
+
+ buttons1 {
+ compatible = "gpio-keys-polled";
+ poll-interval = <200>;
+
+ lid-switch {
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>;
+ label = "Lid";
+ };
};
chosen {
@@ -26,22 +64,35 @@
};
};
+&can0 {
+ status = "okay";
+};
+
&dspi2 {
status = "okay";
};
-&enetc_port0 {
- phy-handle = <&phy0>;
- phy-mode = "sgmii";
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
status = "okay";
};
-&enetc_port2 {
- status = "disabled";
+&enetc_mdio_pf3 {
+ phy0: ethernet-phy@5 {
+ reg = <0x5>;
+ eee-broken-1000t;
+ eee-broken-100tx;
+ };
};
-&enetc_port3 {
- status = "disabled";
+&enetc_port0 {
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
};
&esdhc {
@@ -63,8 +114,6 @@
status = "okay";
flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
compatible = "jedec,spi-nor";
m25p,fast-read;
spi-max-frequency = <133000000>;
@@ -72,17 +121,167 @@
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x000000 0x010000>;
+ label = "rcw";
+ read-only;
+ };
+
+ partition@10000 {
+ reg = <0x010000 0x1d0000>;
+ label = "failsafe bootloader";
+ read-only;
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x010000>;
+ label = "configuration store";
+ };
+
+ partition@210000 {
+ reg = <0x210000 0x1d0000>;
+ label = "bootloader";
+ };
+
+ partition@3e0000 {
+ reg = <0x3e0000 0x020000>;
+ label = "bootloader environment";
+ };
+ };
};
};
+&gpio1 {
+ gpio-line-names =
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "TDO", "TCK",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "", "", "", "", "", "", "TMS", "TDI",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
&i2c0 {
status = "okay";
- rtc@32 {
+ rtc: rtc@32 {
compatible = "microcrystal,rv8803";
reg = <0x32>;
};
+ sl28cpld@4a {
+ compatible = "kontron,sl28cpld";
+ reg = <0x4a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ watchdog@4 {
+ compatible = "kontron,sl28cpld-wdt";
+ reg = <0x4>;
+ kontron,assert-wdt-timeout-pin;
+ };
+
+ hwmon@b {
+ compatible = "kontron,sl28cpld-fan";
+ reg = <0xb>;
+ };
+
+ sl28cpld_pwm0: pwm@c {
+ compatible = "kontron,sl28cpld-pwm";
+ reg = <0xc>;
+ #pwm-cells = <2>;
+ };
+
+ sl28cpld_pwm1: pwm@e {
+ compatible = "kontron,sl28cpld-pwm";
+ reg = <0xe>;
+ #pwm-cells = <2>;
+ };
+
+ sl28cpld_gpio0: gpio@10 {
+ compatible = "kontron,sl28cpld-gpio";
+ reg = <0x10>;
+ interrupts-extended = <&gpio2 6
+ IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N",
+ "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N",
+ "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT",
+ "GPIO6_TACHIN", "GPIO7";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sl28cpld_gpio1: gpio@15 {
+ compatible = "kontron,sl28cpld-gpio";
+ reg = <0x15>;
+ interrupts-extended = <&gpio2 6
+ IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "GPIO8", "GPIO9", "GPIO10", "GPIO11",
+ "", "", "", "";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sl28cpld_gpio2: gpio@1a {
+ compatible = "kontron,sl28cpld-gpo";
+ reg = <0x1a>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "LCD0 voltage enable",
+ "LCD0 backlight enable",
+ "eMMC reset", "LVDS bridge reset",
+ "LVDS bridge power-down",
+ "SDIO power enable",
+ "", "";
+ };
+
+ sl28cpld_gpio3: gpio@1b {
+ compatible = "kontron,sl28cpld-gpi";
+ reg = <0x1b>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "Power button", "Force recovery", "Sleep",
+ "Battery low", "Lid state", "Charging",
+ "Charger present", "";
+ };
+
+ sl28cpld_intc: interrupt-controller@1c {
+ compatible = "kontron,sl28cpld-intc";
+ reg = <0x1c>;
+ interrupts-extended = <&gpio2 6
+ IRQ_TYPE_EDGE_FALLING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
@@ -107,32 +306,3 @@
&lpuart1 {
status = "okay";
};
-
-&enetc_mdio_pf3 {
- status = "okay";
- phy0: ethernet-phy@5 {
- reg = <0x5>;
- eee-broken-1000t;
- eee-broken-100tx;
- };
-};
-
-&sata {
- status = "okay";
-};
-
-&duart0 {
- status = "okay";
-};
-
-&duart1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
--
2.30.2
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux
2021-09-02 16:45 [PATCH v3 00/29] arm: dts: ls1028a: sync device tree with linux Michael Walle
` (28 preceding siblings ...)
2021-09-02 16:45 ` [PATCH v3 29/29] arm: dts: sl28: sync dtbs Michael Walle
@ 2021-10-05 0:39 ` Vladimir Oltean
29 siblings, 0 replies; 61+ messages in thread
From: Vladimir Oltean @ 2021-10-05 0:39 UTC (permalink / raw)
To: Michael Walle
Cc: u-boot, Jagan Teki, Priyanka Jain, Tom Rini, Peter Griffin,
Manivannan Sadhasivam
On Thu, Sep 02, 2021 at 06:45:29PM +0200, Michael Walle wrote:
> This series sync the device tree of the LS1028A SoC with the linux one.
> To ease future debugging and reviewing, we first clean up the existing one,
> removing bogus nodes, moving all CCSR related nodes in /soc and update the
> drivers to accept the offical compatible strings.
>
> This was tested on a sl28 board, but the ls1028a.dtsi sync also affects the
> LS1028A-RDB and -QDS. It would be nice if someone could actually test it on
> such a board.
>
> I didn't sync the device trees for the NXP boards because u-boot related
> things aren't split into its own -u-boot.dtsi file. So I'll leave that task
> to NXP :)
>
> The following patch is a prerequisite for this series:
> https://patchwork.ozlabs.org/project/uboot/patch/20210825210510.24766-1-trini@konsulko.com/
>
> changes since v2:
> - move the device tree nodes piece by piece and sort them to ease
> reviewing
> - fix PCI driver (bindings)
> - fix SATA driver (bindings)
> - fix USB driver (bindings)
> - split most changes which are caused by the sync of the linux
> device tree to own patches, eg. pcie io window, spi chip selects
>
> The final diff for the sync is much nicer now ;)
>
> changes since v1:
> - remove u-boot,dm-pre-reloc from rdb and qds boards
> - fix enetc0 and enetc2 labels
These patches no longer apply, can you please resend?
^ permalink raw reply [flat|nested] 61+ messages in thread